Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1861	1			T3	3		T10	10		T17	2
all_values[1]	1932	1			T10	12		T17	2		T19	3
all_values[2]	1911	1			T3	5		T10	20		T17	4
all_values[3]	1907	1			T10	14		T17	4		T19	4
all_values[4]	1960	1			T3	1		T10	13		T17	4
all_values[5]	1920	1			T3	2		T10	13		T17	3
all_values[6]	1846	1			T3	2		T10	18		T17	1
all_values[7]	1902	1			T3	3		T10	15		T17	3
all_values[8]	1975	1			T3	2		T10	19		T17	2
all_values[9]	1924	1			T3	1		T10	14		T17	5
all_values[10]	1897	1			T3	2		T10	11		T19	6
all_values[11]	1986	1			T3	3		T10	16		T17	3
all_values[12]	1904	1			T10	14		T17	4		T19	8
all_values[13]	1899	1			T3	3		T10	19		T17	2
all_values[14]	1912	1			T3	3		T10	13		T17	1
all_values[15]	1952	1			T10	24		T17	1		T19	10
all_values[16]	1954	1			T10	12		T17	3		T19	5
all_values[17]	1921	1			T10	15		T17	2		T19	5
all_values[18]	1903	1			T3	2		T10	17		T17	1
all_values[19]	1942	1			T3	1		T10	14		T17	2
all_values[20]	1942	1			T3	2		T10	17		T17	1
all_values[21]	1928	1			T3	1		T10	13		T17	2
all_values[22]	1901	1			T3	1		T10	17		T17	4
all_values[23]	2002	1			T3	4		T10	15		T19	3
all_values[24]	1902	1			T10	5		T17	1		T19	1
all_values[25]	1904	1			T3	2		T10	16		T17	6
all_values[26]	1948	1			T3	3		T10	15		T17	4
all_values[27]	1964	1			T10	12		T17	4		T19	3
all_values[28]	1893	1			T3	2		T10	18		T17	5
all_values[29]	1992	1			T3	3		T10	8		T17	1
all_values[30]	1969	1			T3	3		T10	9		T17	2
all_values[31]	1922	1			T3	5		T10	14		T17	2
all_values[32]	1994	1			T3	1		T10	21		T17	5
all_values[33]	1922	1			T3	2		T10	11		T17	4
all_values[34]	1930	1			T3	1		T10	16		T17	3
all_values[35]	1950	1			T3	3		T10	15		T17	2
all_values[36]	1996	1			T3	2		T10	16		T17	6
all_values[37]	1904	1			T3	3		T10	23		T19	6
all_values[38]	1891	1			T3	1		T10	15		T17	2
all_values[39]	1920	1			T3	3		T10	15		T17	1
all_values[40]	2003	1			T3	2		T10	12		T17	4
all_values[41]	1942	1			T3	2		T10	15		T17	4
all_values[42]	1975	1			T3	4		T10	15		T17	2
all_values[43]	1994	1			T10	20		T17	3		T19	5
all_values[44]	1948	1			T3	2		T10	11		T17	2
all_values[45]	1868	1			T3	2		T10	11		T17	3
all_values[46]	1941	1			T3	2		T10	16		T17	1
all_values[47]	1907	1			T3	2		T10	12		T17	3
all_values[48]	1958	1			T10	5		T17	4		T19	6
all_values[49]	1995	1			T3	1		T10	9		T17	2
all_values[50]	1877	1			T3	1		T10	20		T17	2
all_values[51]	1936	1			T3	1		T10	5		T19	8
all_values[52]	1912	1			T3	1		T10	11		T17	3
all_values[53]	2026	1			T3	1		T10	22		T17	1
all_values[54]	1885	1			T3	2		T10	12		T17	1
all_values[55]	1864	1			T3	1		T10	18		T17	5
all_values[56]	1909	1			T3	1		T10	14		T17	1
all_values[57]	1929	1			T3	2		T10	9		T17	4
all_values[58]	1878	1			T10	9		T17	5		T19	5
all_values[59]	1886	1			T3	1		T10	21		T17	3
all_values[60]	1924	1			T3	2		T10	13		T17	2
all_values[61]	1928	1			T3	2		T10	17		T17	2
all_values[62]	2017	1			T10	16		T17	3		T19	2
all_values[63]	1918	1			T3	3		T10	14		T17	3