Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1800	1			T7	6		T11	12		T14	16
all_values[1]	1821	1			T7	4		T11	12		T14	16
all_values[2]	1773	1			T7	2		T11	8		T14	13
all_values[3]	1772	1			T7	2		T11	10		T14	15
all_values[4]	1765	1			T7	3		T11	9		T14	17
all_values[5]	1766	1			T7	2		T11	6		T14	13
all_values[6]	1808	1			T7	11		T11	9		T14	18
all_values[7]	1757	1			T7	3		T11	9		T14	17
all_values[8]	1680	1			T7	5		T11	7		T14	19
all_values[9]	1810	1			T7	1		T11	11		T14	19
all_values[10]	1747	1			T7	5		T11	11		T14	20
all_values[11]	1793	1			T7	7		T11	16		T14	14
all_values[12]	1780	1			T7	1		T11	9		T14	17
all_values[13]	1796	1			T7	3		T11	18		T14	16
all_values[14]	1725	1			T7	7		T11	14		T14	13
all_values[15]	1823	1			T7	5		T11	15		T14	15
all_values[16]	1810	1			T7	10		T11	15		T14	19
all_values[17]	1822	1			T7	3		T11	10		T14	5
all_values[18]	1769	1			T7	9		T11	2		T14	17
all_values[19]	1816	1			T7	4		T11	13		T14	20
all_values[20]	1761	1			T7	9		T11	11		T14	13
all_values[21]	1830	1			T7	8		T11	12		T14	7
all_values[22]	1789	1			T7	4		T11	7		T14	8
all_values[23]	1848	1			T7	5		T11	6		T14	11
all_values[24]	1790	1			T7	5		T11	13		T14	16
all_values[25]	1795	1			T7	5		T11	20		T14	10
all_values[26]	1857	1			T7	5		T11	11		T14	22
all_values[27]	1930	1			T7	6		T11	14		T14	14
all_values[28]	1853	1			T7	5		T11	11		T14	12
all_values[29]	1791	1			T7	4		T11	15		T14	13
all_values[30]	1768	1			T7	6		T11	10		T14	9
all_values[31]	1816	1			T7	9		T11	10		T14	16
all_values[32]	1847	1			T7	7		T11	12		T14	17
all_values[33]	1867	1			T7	3		T11	15		T14	17
all_values[34]	1794	1			T7	4		T11	4		T14	13
all_values[35]	1782	1			T7	4		T11	8		T14	19
all_values[36]	1717	1			T7	2		T11	10		T14	5
all_values[37]	1789	1			T7	7		T11	15		T14	13
all_values[38]	1918	1			T7	4		T11	7		T14	14
all_values[39]	1773	1			T7	4		T11	12		T14	12
all_values[40]	1761	1			T7	5		T11	10		T14	9
all_values[41]	1798	1			T7	6		T11	8		T14	17
all_values[42]	1725	1			T7	6		T11	10		T14	18
all_values[43]	1873	1			T7	8		T11	14		T14	19
all_values[44]	1742	1			T7	3		T11	17		T14	9
all_values[45]	1803	1			T7	4		T11	9		T14	11
all_values[46]	1773	1			T7	8		T11	11		T14	18
all_values[47]	1862	1			T7	8		T11	8		T14	16
all_values[48]	1752	1			T7	5		T11	15		T14	13
all_values[49]	1834	1			T7	2		T11	10		T14	21
all_values[50]	1759	1			T7	8		T11	12		T14	18
all_values[51]	1769	1			T7	6		T11	10		T14	11
all_values[52]	1795	1			T7	3		T11	10		T14	10
all_values[53]	1776	1			T7	4		T11	10		T14	18
all_values[54]	1762	1			T7	4		T11	11		T14	15
all_values[55]	1812	1			T7	4		T11	15		T14	10
all_values[56]	1791	1			T7	3		T11	14		T14	10
all_values[57]	1793	1			T7	1		T11	15		T14	9
all_values[58]	1852	1			T7	3		T11	5		T14	15
all_values[59]	1763	1			T7	7		T11	9		T14	10
all_values[60]	1804	1			T7	4		T11	5		T14	17
all_values[61]	1767	1			T7	4		T11	13		T14	14
all_values[62]	1753	1			T7	4		T11	14		T14	12
all_values[63]	1790	1			T7	2		T11	15		T14	14