Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1814	1			T6	3		T12	13		T15	1
all_values[1]	1811	1			T6	4		T12	18		T15	3
all_values[2]	1824	1			T6	1		T12	21		T13	4
all_values[3]	1833	1			T12	11		T13	5		T15	4
all_values[4]	1793	1			T6	5		T12	14		T13	2
all_values[5]	1789	1			T6	4		T12	11		T13	1
all_values[6]	1838	1			T6	5		T12	18		T13	2
all_values[7]	1791	1			T6	1		T12	12		T13	1
all_values[8]	1804	1			T6	2		T12	12		T13	3
all_values[9]	1759	1			T6	1		T12	14		T13	1
all_values[10]	1887	1			T6	5		T12	11		T13	4
all_values[11]	1697	1			T6	1		T12	13		T13	3
all_values[12]	1840	1			T6	3		T12	17		T13	3
all_values[13]	1830	1			T6	3		T12	21		T13	2
all_values[14]	1774	1			T6	3		T12	16		T13	2
all_values[15]	1850	1			T6	1		T12	17		T13	2
all_values[16]	1830	1			T6	1		T12	14		T13	1
all_values[17]	1850	1			T6	5		T12	22		T13	2
all_values[18]	1783	1			T6	2		T12	15		T13	1
all_values[19]	1862	1			T6	2		T12	16		T13	1
all_values[20]	1832	1			T6	2		T12	15		T13	3
all_values[21]	1740	1			T6	1		T12	14		T13	1
all_values[22]	1886	1			T6	3		T12	20		T13	1
all_values[23]	1821	1			T6	6		T12	16		T13	2
all_values[24]	1798	1			T6	6		T12	20		T100	1
all_values[25]	1839	1			T6	2		T12	22		T13	4
all_values[26]	1795	1			T6	3		T12	19		T13	2
all_values[27]	1844	1			T6	1		T12	17		T13	3
all_values[28]	1873	1			T6	3		T12	18		T13	2
all_values[29]	1826	1			T6	3		T12	21		T15	2
all_values[30]	1837	1			T12	23		T13	1		T15	1
all_values[31]	1773	1			T6	1		T12	24		T13	1
all_values[32]	1804	1			T6	1		T12	12		T13	2
all_values[33]	1926	1			T6	4		T12	15		T13	4
all_values[34]	1837	1			T6	2		T12	19		T13	4
all_values[35]	1793	1			T12	10		T13	1		T15	2
all_values[36]	1838	1			T6	3		T12	30		T13	3
all_values[37]	1827	1			T6	6		T12	19		T13	2
all_values[38]	1764	1			T6	1		T12	18		T13	3
all_values[39]	1798	1			T12	17		T13	1		T15	4
all_values[40]	1851	1			T6	2		T12	19		T13	4
all_values[41]	1806	1			T6	2		T12	18		T15	2
all_values[42]	1865	1			T6	3		T12	7		T13	1
all_values[43]	1829	1			T6	2		T12	15		T13	2
all_values[44]	1877	1			T6	5		T12	21		T13	2
all_values[45]	1881	1			T6	4		T12	15		T13	2
all_values[46]	1827	1			T6	4		T12	20		T13	1
all_values[47]	1855	1			T6	1		T12	14		T13	2
all_values[48]	1773	1			T6	1		T12	11		T13	5
all_values[49]	1698	1			T6	3		T12	18		T13	3
all_values[50]	1797	1			T6	4		T12	15		T13	1
all_values[51]	1888	1			T6	1		T12	17		T13	2
all_values[52]	1857	1			T6	5		T12	16		T13	4
all_values[53]	1824	1			T6	2		T12	22		T13	1
all_values[54]	1815	1			T6	1		T12	18		T13	1
all_values[55]	1825	1			T6	2		T12	17		T15	4
all_values[56]	1866	1			T6	2		T12	16		T13	4
all_values[57]	1779	1			T6	3		T12	14		T13	5
all_values[58]	1768	1			T6	3		T12	12		T13	2
all_values[59]	1754	1			T6	3		T12	20		T13	3
all_values[60]	1780	1			T6	2		T12	15		T13	3
all_values[61]	1778	1			T6	5		T12	14		T13	2
all_values[62]	1857	1			T6	1		T12	19		T13	4
all_values[63]	1783	1			T6	2		T12	14		T13	1