Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 488 1 T8 1 T24 2 T44 2
all_values[1] 530 1 T12 1 T24 3 T44 1
all_values[2] 494 1 T12 1 T24 4 T44 1
all_values[3] 496 1 T8 1 T24 1 T44 2
all_values[4] 524 1 T23 1 T24 6 T20 1
all_values[5] 469 1 T24 2 T44 4 T162 1
all_values[6] 529 1 T8 1 T12 1 T24 5
all_values[7] 524 1 T8 3 T24 6 T69 1
all_values[8] 514 1 T8 2 T24 3 T69 1
all_values[9] 460 1 T8 1 T12 1 T24 1
all_values[10] 531 1 T12 1 T24 2 T44 5
all_values[11] 483 1 T2 1 T12 1 T24 1
all_values[12] 490 1 T2 1 T12 2 T24 5
all_values[13] 474 1 T8 1 T12 2 T24 3
all_values[14] 480 1 T23 1 T24 2 T44 1
all_values[15] 492 1 T8 1 T12 1 T24 4
all_values[16] 480 1 T8 1 T23 1 T24 7
all_values[17] 508 1 T8 1 T12 2 T23 1
all_values[18] 523 1 T8 1 T12 2 T24 2
all_values[19] 490 1 T8 2 T24 5 T20 2
all_values[20] 497 1 T8 1 T12 1 T24 4
all_values[21] 492 1 T12 2 T23 1 T24 4
all_values[22] 478 1 T8 1 T12 1 T24 5
all_values[23] 510 1 T8 2 T24 4 T44 1

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