Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1830	1			T3	2		T9	2		T12	3
all_values[1]	1862	1			T3	2		T9	4		T12	4
all_values[2]	1737	1			T3	2		T9	3		T12	3
all_values[3]	1846	1			T3	1		T9	2		T12	1
all_values[4]	1810	1			T9	1		T12	2		T24	28
all_values[5]	1856	1			T3	7		T9	3		T12	3
all_values[6]	1877	1			T3	1		T9	5		T12	7
all_values[7]	1762	1			T3	2		T9	2		T12	1
all_values[8]	1815	1			T3	1		T12	2		T24	20
all_values[9]	1859	1			T3	1		T9	3		T12	5
all_values[10]	1840	1			T3	3		T9	3		T12	3
all_values[11]	1714	1			T3	2		T9	4		T12	4
all_values[12]	1814	1			T3	1		T9	4		T12	6
all_values[13]	1816	1			T3	1		T12	2		T24	21
all_values[14]	1772	1			T3	5		T9	4		T12	3
all_values[15]	1738	1			T3	1		T9	4		T12	3
all_values[16]	1783	1			T3	1		T9	5		T12	3
all_values[17]	1770	1			T3	1		T9	2		T12	4
all_values[18]	1883	1			T3	3		T9	2		T12	4
all_values[19]	1917	1			T3	3		T9	5		T24	32
all_values[20]	1835	1			T9	2		T12	4		T24	21
all_values[21]	1780	1			T3	2		T9	2		T12	3
all_values[22]	1846	1			T3	4		T9	2		T12	7
all_values[23]	1794	1			T3	4		T9	1		T12	3
all_values[24]	1818	1			T3	3		T9	4		T24	21
all_values[25]	1867	1			T3	3		T9	3		T12	3
all_values[26]	1742	1			T3	2		T9	2		T12	2
all_values[27]	1874	1			T3	3		T9	2		T24	34
all_values[28]	1778	1			T3	3		T9	2		T24	14
all_values[29]	1818	1			T3	2		T9	1		T12	2
all_values[30]	1792	1			T3	2		T9	4		T12	2
all_values[31]	1864	1			T9	1		T12	5		T24	30
all_values[32]	1749	1			T3	1		T9	1		T12	5
all_values[33]	1897	1			T9	3		T12	3		T24	25
all_values[34]	1826	1			T3	1		T9	5		T12	4
all_values[35]	1785	1			T3	1		T9	2		T12	3
all_values[36]	1825	1			T3	2		T9	4		T12	5
all_values[37]	1879	1			T3	2		T9	2		T12	2
all_values[38]	1826	1			T3	2		T9	3		T12	4
all_values[39]	1826	1			T3	1		T9	5		T12	3
all_values[40]	1755	1			T3	2		T9	1		T12	1
all_values[41]	1849	1			T3	2		T9	4		T12	3
all_values[42]	1788	1			T3	2		T9	4		T12	3
all_values[43]	1828	1			T3	4		T9	3		T12	2
all_values[44]	1889	1			T3	4		T9	1		T12	7
all_values[45]	1834	1			T12	4		T24	33		T42	3
all_values[46]	1930	1			T9	1		T12	1		T24	29
all_values[47]	1806	1			T3	4		T9	3		T12	2
all_values[48]	1791	1			T3	2		T12	4		T24	25
all_values[49]	1736	1			T3	2		T9	1		T12	5
all_values[50]	1858	1			T3	4		T9	3		T24	29
all_values[51]	1765	1			T9	2		T12	5		T24	16
all_values[52]	1802	1			T3	4		T9	5		T12	2
all_values[53]	1821	1			T3	4		T9	4		T12	3
all_values[54]	1791	1			T3	1		T9	3		T12	4
all_values[55]	1826	1			T3	4		T9	4		T12	3
all_values[56]	1781	1			T3	5		T9	4		T12	2
all_values[57]	1878	1			T3	3		T9	4		T12	3
all_values[58]	1872	1			T3	2		T12	4		T24	28
all_values[59]	1865	1			T3	4		T9	5		T12	3
all_values[60]	1905	1			T3	1		T9	4		T12	2
all_values[61]	1827	1			T3	5		T9	3		T12	4
all_values[62]	1817	1			T3	3		T9	7		T12	5
all_values[63]	1947	1			T3	3		T9	2		T12	3