Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.02 99.26 88.92 98.80 95.88 99.26 100.00


Total test records in report: 900
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T766 /workspace/coverage/xbar_build_mode/31.xbar_same_source.3457043680 Jul 26 04:25:13 PM PDT 24 Jul 26 04:25:24 PM PDT 24 313511691 ps
T767 /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.3673243847 Jul 26 04:20:49 PM PDT 24 Jul 26 04:22:29 PM PDT 24 7254656593 ps
T768 /workspace/coverage/xbar_build_mode/14.xbar_same_source.1064425019 Jul 26 04:23:38 PM PDT 24 Jul 26 04:23:56 PM PDT 24 992843625 ps
T769 /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.3312112527 Jul 26 04:26:03 PM PDT 24 Jul 26 04:26:19 PM PDT 24 1021113428 ps
T770 /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2906406884 Jul 26 04:19:54 PM PDT 24 Jul 26 04:24:12 PM PDT 24 53228991882 ps
T771 /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.437096565 Jul 26 04:21:10 PM PDT 24 Jul 26 04:31:06 PM PDT 24 95102873217 ps
T161 /workspace/coverage/xbar_build_mode/43.xbar_smoke.3086967655 Jul 26 04:26:08 PM PDT 24 Jul 26 04:26:12 PM PDT 24 153184085 ps
T772 /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2284013034 Jul 26 04:26:03 PM PDT 24 Jul 26 04:26:18 PM PDT 24 103510109 ps
T773 /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.829581909 Jul 26 04:26:12 PM PDT 24 Jul 26 04:26:32 PM PDT 24 160247753 ps
T774 /workspace/coverage/xbar_build_mode/45.xbar_stress_all.2349073620 Jul 26 04:26:08 PM PDT 24 Jul 26 04:27:07 PM PDT 24 1701756083 ps
T775 /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1361798922 Jul 26 04:20:54 PM PDT 24 Jul 26 04:21:28 PM PDT 24 10008811917 ps
T67 /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.500301389 Jul 26 04:24:25 PM PDT 24 Jul 26 04:26:13 PM PDT 24 40079730655 ps
T776 /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3759862754 Jul 26 04:25:55 PM PDT 24 Jul 26 04:27:27 PM PDT 24 246716295 ps
T777 /workspace/coverage/xbar_build_mode/40.xbar_error_random.2208398444 Jul 26 04:25:42 PM PDT 24 Jul 26 04:26:00 PM PDT 24 199873732 ps
T778 /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.1794586044 Jul 26 04:22:32 PM PDT 24 Jul 26 04:22:35 PM PDT 24 29910851 ps
T779 /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2929649293 Jul 26 04:25:15 PM PDT 24 Jul 26 04:25:18 PM PDT 24 44154742 ps
T780 /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.2872380832 Jul 26 04:25:16 PM PDT 24 Jul 26 04:26:35 PM PDT 24 2659278111 ps
T781 /workspace/coverage/xbar_build_mode/37.xbar_error_random.3047331596 Jul 26 04:25:30 PM PDT 24 Jul 26 04:25:56 PM PDT 24 1415466482 ps
T782 /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.129513810 Jul 26 04:26:09 PM PDT 24 Jul 26 04:26:27 PM PDT 24 45053620 ps
T783 /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.667893201 Jul 26 04:25:17 PM PDT 24 Jul 26 04:25:48 PM PDT 24 8710530098 ps
T784 /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.1043227227 Jul 26 04:24:44 PM PDT 24 Jul 26 04:25:21 PM PDT 24 11528482057 ps
T785 /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.312264396 Jul 26 04:25:23 PM PDT 24 Jul 26 04:28:50 PM PDT 24 719763930 ps
T786 /workspace/coverage/xbar_build_mode/34.xbar_random.959965098 Jul 26 04:25:18 PM PDT 24 Jul 26 04:25:33 PM PDT 24 648636880 ps
T787 /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2531808639 Jul 26 04:25:04 PM PDT 24 Jul 26 04:26:24 PM PDT 24 2881789041 ps
T281 /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.717014369 Jul 26 04:24:27 PM PDT 24 Jul 26 04:26:47 PM PDT 24 3051523103 ps
T214 /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.2329112889 Jul 26 04:24:30 PM PDT 24 Jul 26 04:28:50 PM PDT 24 37703086207 ps
T788 /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.378827167 Jul 26 04:22:38 PM PDT 24 Jul 26 04:25:01 PM PDT 24 112334473301 ps
T789 /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.1667849153 Jul 26 04:25:03 PM PDT 24 Jul 26 04:26:32 PM PDT 24 5078467936 ps
T790 /workspace/coverage/xbar_build_mode/33.xbar_smoke.1150255465 Jul 26 04:25:17 PM PDT 24 Jul 26 04:25:20 PM PDT 24 579282533 ps
T791 /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.472257526 Jul 26 04:25:57 PM PDT 24 Jul 26 04:26:32 PM PDT 24 5641371997 ps
T792 /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.2732936147 Jul 26 04:25:05 PM PDT 24 Jul 26 04:25:14 PM PDT 24 130387573 ps
T293 /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.2604877248 Jul 26 04:25:18 PM PDT 24 Jul 26 04:34:21 PM PDT 24 11543535898 ps
T793 /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.1344809585 Jul 26 04:26:21 PM PDT 24 Jul 26 04:29:06 PM PDT 24 41021476482 ps
T794 /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.3054801213 Jul 26 04:24:28 PM PDT 24 Jul 26 04:26:09 PM PDT 24 23905939556 ps
T795 /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.2436514771 Jul 26 04:25:17 PM PDT 24 Jul 26 04:28:38 PM PDT 24 54069749386 ps
T796 /workspace/coverage/xbar_build_mode/4.xbar_stress_all.4265500852 Jul 26 04:24:42 PM PDT 24 Jul 26 04:25:33 PM PDT 24 715963706 ps
T797 /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.3962156734 Jul 26 04:25:48 PM PDT 24 Jul 26 04:28:04 PM PDT 24 36610974985 ps
T798 /workspace/coverage/xbar_build_mode/0.xbar_same_source.1186642504 Jul 26 04:20:55 PM PDT 24 Jul 26 04:21:09 PM PDT 24 2149574241 ps
T799 /workspace/coverage/xbar_build_mode/15.xbar_same_source.2681418946 Jul 26 04:25:30 PM PDT 24 Jul 26 04:25:50 PM PDT 24 1028682894 ps
T800 /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.4035558353 Jul 26 04:26:30 PM PDT 24 Jul 26 04:26:33 PM PDT 24 40759360 ps
T36 /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.4221558597 Jul 26 04:25:20 PM PDT 24 Jul 26 04:32:26 PM PDT 24 8941136238 ps
T801 /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.1083112797 Jul 26 04:25:27 PM PDT 24 Jul 26 04:25:30 PM PDT 24 15490342 ps
T802 /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3005092647 Jul 26 04:26:31 PM PDT 24 Jul 26 04:26:40 PM PDT 24 132151877 ps
T803 /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.2300106805 Jul 26 04:25:11 PM PDT 24 Jul 26 04:28:39 PM PDT 24 4968314215 ps
T804 /workspace/coverage/xbar_build_mode/34.xbar_error_random.30318718 Jul 26 04:25:28 PM PDT 24 Jul 26 04:25:59 PM PDT 24 2548601119 ps
T805 /workspace/coverage/xbar_build_mode/32.xbar_same_source.25063163 Jul 26 04:25:18 PM PDT 24 Jul 26 04:25:27 PM PDT 24 104113277 ps
T806 /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.2303561668 Jul 26 04:25:21 PM PDT 24 Jul 26 04:25:33 PM PDT 24 341693974 ps
T807 /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3175790869 Jul 26 04:25:34 PM PDT 24 Jul 26 04:25:59 PM PDT 24 3825239737 ps
T123 /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2112397878 Jul 26 04:25:27 PM PDT 24 Jul 26 04:31:58 PM PDT 24 96987903243 ps
T808 /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.2793701998 Jul 26 04:25:20 PM PDT 24 Jul 26 04:25:41 PM PDT 24 121408176 ps
T809 /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.3297560302 Jul 26 04:25:15 PM PDT 24 Jul 26 04:25:40 PM PDT 24 7044176652 ps
T810 /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1536289395 Jul 26 04:26:00 PM PDT 24 Jul 26 04:26:37 PM PDT 24 4707830104 ps
T811 /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.2331616709 Jul 26 04:26:12 PM PDT 24 Jul 26 04:26:26 PM PDT 24 149197502 ps
T812 /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2021530301 Jul 26 04:26:08 PM PDT 24 Jul 26 04:26:45 PM PDT 24 11502278545 ps
T124 /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3758344706 Jul 26 04:25:17 PM PDT 24 Jul 26 04:30:11 PM PDT 24 43581778974 ps
T813 /workspace/coverage/xbar_build_mode/44.xbar_random.3983671976 Jul 26 04:26:06 PM PDT 24 Jul 26 04:26:09 PM PDT 24 80548747 ps
T814 /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.1840012688 Jul 26 04:26:26 PM PDT 24 Jul 26 04:26:37 PM PDT 24 131394331 ps
T815 /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.3601500315 Jul 26 04:25:06 PM PDT 24 Jul 26 04:28:00 PM PDT 24 1057537904 ps
T816 /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1207032991 Jul 26 04:26:55 PM PDT 24 Jul 26 04:26:57 PM PDT 24 70955993 ps
T817 /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.2938725452 Jul 26 04:21:11 PM PDT 24 Jul 26 04:21:18 PM PDT 24 297876285 ps
T818 /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3834970147 Jul 26 04:25:08 PM PDT 24 Jul 26 04:31:51 PM PDT 24 3577206017 ps
T819 /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.338070666 Jul 26 04:25:23 PM PDT 24 Jul 26 04:29:21 PM PDT 24 711407446 ps
T820 /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.3894936817 Jul 26 04:25:05 PM PDT 24 Jul 26 04:27:41 PM PDT 24 70500100826 ps
T821 /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2726014533 Jul 26 04:25:15 PM PDT 24 Jul 26 04:26:56 PM PDT 24 1205440706 ps
T822 /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.441049039 Jul 26 04:24:29 PM PDT 24 Jul 26 04:24:58 PM PDT 24 3438308463 ps
T823 /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.4162883077 Jul 26 04:24:54 PM PDT 24 Jul 26 04:26:31 PM PDT 24 16871279806 ps
T267 /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.2012761655 Jul 26 04:25:19 PM PDT 24 Jul 26 04:25:51 PM PDT 24 9702435847 ps
T824 /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.3501131079 Jul 26 04:22:55 PM PDT 24 Jul 26 04:23:17 PM PDT 24 2443081869 ps
T825 /workspace/coverage/xbar_build_mode/8.xbar_smoke.135147538 Jul 26 04:26:09 PM PDT 24 Jul 26 04:26:13 PM PDT 24 214344955 ps
T282 /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.1643406450 Jul 26 04:26:25 PM PDT 24 Jul 26 04:27:49 PM PDT 24 57385437850 ps
T826 /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.638716973 Jul 26 04:25:43 PM PDT 24 Jul 26 04:26:08 PM PDT 24 1022995074 ps
T827 /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.1744182345 Jul 26 04:26:10 PM PDT 24 Jul 26 04:28:24 PM PDT 24 19731902673 ps
T828 /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1656508293 Jul 26 04:26:16 PM PDT 24 Jul 26 04:26:18 PM PDT 24 95028252 ps
T125 /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.417203458 Jul 26 04:24:40 PM PDT 24 Jul 26 04:24:59 PM PDT 24 793992580 ps
T829 /workspace/coverage/xbar_build_mode/1.xbar_same_source.4134196673 Jul 26 04:20:55 PM PDT 24 Jul 26 04:21:15 PM PDT 24 240788556 ps
T830 /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3257785367 Jul 26 04:25:29 PM PDT 24 Jul 26 04:28:20 PM PDT 24 21093398764 ps
T831 /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.72440473 Jul 26 04:25:28 PM PDT 24 Jul 26 04:25:32 PM PDT 24 53010183 ps
T832 /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3423124361 Jul 26 04:23:08 PM PDT 24 Jul 26 04:23:10 PM PDT 24 26474213 ps
T833 /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.3807954860 Jul 26 04:25:14 PM PDT 24 Jul 26 04:25:22 PM PDT 24 88557481 ps
T834 /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3888378810 Jul 26 04:26:01 PM PDT 24 Jul 26 04:26:35 PM PDT 24 10519865298 ps
T835 /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.996779013 Jul 26 04:25:32 PM PDT 24 Jul 26 04:26:08 PM PDT 24 902758067 ps
T836 /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3751153582 Jul 26 04:26:42 PM PDT 24 Jul 26 04:26:58 PM PDT 24 56281183 ps
T837 /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3077349462 Jul 26 04:25:26 PM PDT 24 Jul 26 04:25:29 PM PDT 24 79843359 ps
T838 /workspace/coverage/xbar_build_mode/29.xbar_same_source.3285449659 Jul 26 04:24:32 PM PDT 24 Jul 26 04:24:47 PM PDT 24 1754404810 ps
T839 /workspace/coverage/xbar_build_mode/43.xbar_random.4170587652 Jul 26 04:26:04 PM PDT 24 Jul 26 04:26:07 PM PDT 24 76116982 ps
T840 /workspace/coverage/xbar_build_mode/27.xbar_random.3500301448 Jul 26 04:25:10 PM PDT 24 Jul 26 04:25:29 PM PDT 24 141020972 ps
T841 /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1695245660 Jul 26 04:25:00 PM PDT 24 Jul 26 04:34:25 PM PDT 24 72243643493 ps
T842 /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.65990831 Jul 26 04:24:23 PM PDT 24 Jul 26 04:24:37 PM PDT 24 367489985 ps
T843 /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1507920984 Jul 26 04:25:13 PM PDT 24 Jul 26 04:26:08 PM PDT 24 3584306299 ps
T274 /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.1329825298 Jul 26 04:26:06 PM PDT 24 Jul 26 04:26:36 PM PDT 24 3597760934 ps
T844 /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.115552898 Jul 26 04:20:47 PM PDT 24 Jul 26 04:25:25 PM PDT 24 771087104 ps
T845 /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1193594433 Jul 26 04:23:10 PM PDT 24 Jul 26 04:23:34 PM PDT 24 564628405 ps
T846 /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.263289757 Jul 26 04:24:48 PM PDT 24 Jul 26 04:24:56 PM PDT 24 58840911 ps
T847 /workspace/coverage/xbar_build_mode/27.xbar_error_random.1539062954 Jul 26 04:24:04 PM PDT 24 Jul 26 04:24:26 PM PDT 24 331789741 ps
T848 /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2346131231 Jul 26 04:25:43 PM PDT 24 Jul 26 04:26:26 PM PDT 24 458228429 ps
T849 /workspace/coverage/xbar_build_mode/4.xbar_random.95113119 Jul 26 04:24:29 PM PDT 24 Jul 26 04:24:55 PM PDT 24 874684541 ps
T850 /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.1017681666 Jul 26 04:25:15 PM PDT 24 Jul 26 04:27:40 PM PDT 24 44319020720 ps
T851 /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.619693002 Jul 26 04:25:29 PM PDT 24 Jul 26 04:25:48 PM PDT 24 825410574 ps
T852 /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.866745372 Jul 26 04:24:08 PM PDT 24 Jul 26 04:24:10 PM PDT 24 27978327 ps
T853 /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.2129685437 Jul 26 04:26:14 PM PDT 24 Jul 26 04:26:38 PM PDT 24 346993348 ps
T854 /workspace/coverage/xbar_build_mode/20.xbar_same_source.922297667 Jul 26 04:24:41 PM PDT 24 Jul 26 04:24:45 PM PDT 24 70206910 ps
T855 /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.2274554099 Jul 26 04:23:29 PM PDT 24 Jul 26 04:23:49 PM PDT 24 146149179 ps
T856 /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.3221894981 Jul 26 04:24:40 PM PDT 24 Jul 26 04:25:19 PM PDT 24 1136227359 ps
T857 /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2984427123 Jul 26 04:24:44 PM PDT 24 Jul 26 04:25:03 PM PDT 24 682529221 ps
T858 /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.789722927 Jul 26 04:25:30 PM PDT 24 Jul 26 04:25:48 PM PDT 24 163004362 ps
T859 /workspace/coverage/xbar_build_mode/26.xbar_smoke.2555425831 Jul 26 04:24:38 PM PDT 24 Jul 26 04:24:41 PM PDT 24 210807467 ps
T860 /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1706147030 Jul 26 04:26:19 PM PDT 24 Jul 26 04:27:29 PM PDT 24 178716685 ps
T268 /workspace/coverage/xbar_build_mode/24.xbar_random.2414123678 Jul 26 04:25:15 PM PDT 24 Jul 26 04:25:36 PM PDT 24 680294840 ps
T861 /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.1295227202 Jul 26 04:20:56 PM PDT 24 Jul 26 04:21:43 PM PDT 24 34249804741 ps
T862 /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.2958361188 Jul 26 04:26:04 PM PDT 24 Jul 26 04:29:54 PM PDT 24 44509071107 ps
T863 /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.108451920 Jul 26 04:25:14 PM PDT 24 Jul 26 04:25:52 PM PDT 24 7458198478 ps
T864 /workspace/coverage/xbar_build_mode/21.xbar_error_random.3457635716 Jul 26 04:22:47 PM PDT 24 Jul 26 04:23:03 PM PDT 24 550227636 ps
T865 /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.1402115223 Jul 26 04:19:53 PM PDT 24 Jul 26 04:22:41 PM PDT 24 43413482051 ps
T866 /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.1934200276 Jul 26 04:24:25 PM PDT 24 Jul 26 04:24:27 PM PDT 24 37662493 ps
T867 /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3369681343 Jul 26 04:25:23 PM PDT 24 Jul 26 04:25:45 PM PDT 24 6178265870 ps
T126 /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1502626194 Jul 26 04:20:50 PM PDT 24 Jul 26 04:21:20 PM PDT 24 1291786587 ps
T868 /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.2428061053 Jul 26 04:25:15 PM PDT 24 Jul 26 04:25:43 PM PDT 24 1674748069 ps
T869 /workspace/coverage/xbar_build_mode/11.xbar_error_random.3619533663 Jul 26 04:22:22 PM PDT 24 Jul 26 04:22:25 PM PDT 24 28171918 ps
T870 /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.1049578221 Jul 26 04:25:30 PM PDT 24 Jul 26 04:25:42 PM PDT 24 3145782156 ps
T871 /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.3085208395 Jul 26 04:26:25 PM PDT 24 Jul 26 04:26:44 PM PDT 24 122967537 ps
T872 /workspace/coverage/xbar_build_mode/34.xbar_stress_all.3558470945 Jul 26 04:25:32 PM PDT 24 Jul 26 04:29:59 PM PDT 24 16873267892 ps
T873 /workspace/coverage/xbar_build_mode/20.xbar_stress_all.3720492516 Jul 26 04:24:42 PM PDT 24 Jul 26 04:27:00 PM PDT 24 1907611312 ps
T874 /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1065540176 Jul 26 04:26:05 PM PDT 24 Jul 26 04:27:13 PM PDT 24 466467907 ps
T875 /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3402075057 Jul 26 04:24:40 PM PDT 24 Jul 26 04:25:01 PM PDT 24 4792488828 ps
T876 /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2615479476 Jul 26 04:25:58 PM PDT 24 Jul 26 04:32:06 PM PDT 24 826000043 ps
T877 /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.4251483658 Jul 26 04:23:30 PM PDT 24 Jul 26 04:26:00 PM PDT 24 24582202361 ps
T187 /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.749113537 Jul 26 04:25:10 PM PDT 24 Jul 26 04:28:39 PM PDT 24 23171913077 ps
T878 /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.41411758 Jul 26 04:25:16 PM PDT 24 Jul 26 04:26:29 PM PDT 24 15119378725 ps
T879 /workspace/coverage/xbar_build_mode/14.xbar_smoke.2416859116 Jul 26 04:21:33 PM PDT 24 Jul 26 04:21:35 PM PDT 24 68008045 ps
T880 /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.1029919641 Jul 26 04:26:26 PM PDT 24 Jul 26 04:27:20 PM PDT 24 15030416221 ps
T881 /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.3300406394 Jul 26 04:25:14 PM PDT 24 Jul 26 04:27:07 PM PDT 24 74946692095 ps
T882 /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3242230706 Jul 26 04:24:33 PM PDT 24 Jul 26 04:27:13 PM PDT 24 7589497039 ps
T883 /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.2909655963 Jul 26 04:26:25 PM PDT 24 Jul 26 04:29:34 PM PDT 24 89589925500 ps
T884 /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.502189185 Jul 26 04:26:10 PM PDT 24 Jul 26 04:29:01 PM PDT 24 4047044138 ps
T885 /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.3756014633 Jul 26 04:24:29 PM PDT 24 Jul 26 04:30:59 PM PDT 24 8959566005 ps
T886 /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.1541165963 Jul 26 04:26:05 PM PDT 24 Jul 26 04:26:14 PM PDT 24 84782657 ps
T887 /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.4157209437 Jul 26 04:21:41 PM PDT 24 Jul 26 04:23:14 PM PDT 24 361895634 ps
T888 /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.160956415 Jul 26 04:24:40 PM PDT 24 Jul 26 04:28:13 PM PDT 24 3466357219 ps
T889 /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.443831202 Jul 26 04:25:52 PM PDT 24 Jul 26 04:26:56 PM PDT 24 1953741564 ps
T890 /workspace/coverage/xbar_build_mode/3.xbar_stress_all.83734259 Jul 26 04:25:13 PM PDT 24 Jul 26 04:26:47 PM PDT 24 683461015 ps
T891 /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.1504688710 Jul 26 04:22:11 PM PDT 24 Jul 26 04:23:50 PM PDT 24 531501721 ps
T892 /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.3217517337 Jul 26 04:26:11 PM PDT 24 Jul 26 04:26:42 PM PDT 24 4056490007 ps
T893 /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.2777505704 Jul 26 04:24:37 PM PDT 24 Jul 26 04:24:41 PM PDT 24 542565807 ps
T894 /workspace/coverage/xbar_build_mode/4.xbar_same_source.425483189 Jul 26 04:25:25 PM PDT 24 Jul 26 04:25:31 PM PDT 24 67055933 ps
T895 /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.3346116228 Jul 26 04:25:39 PM PDT 24 Jul 26 04:25:54 PM PDT 24 257583432 ps
T896 /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.1093407566 Jul 26 04:23:11 PM PDT 24 Jul 26 04:23:36 PM PDT 24 276107438 ps
T897 /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.1440524996 Jul 26 04:24:50 PM PDT 24 Jul 26 04:27:38 PM PDT 24 85382239068 ps
T898 /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.3541366200 Jul 26 04:23:36 PM PDT 24 Jul 26 04:24:32 PM PDT 24 8195410771 ps
T899 /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1094275639 Jul 26 04:25:24 PM PDT 24 Jul 26 04:26:00 PM PDT 24 15042822431 ps
T900 /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2206751925 Jul 26 04:24:33 PM PDT 24 Jul 26 04:32:59 PM PDT 24 84492157841 ps

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.1474318436
Short name T3
Test name
Test status
Simulation time 8568277316 ps
CPU time 45.5 seconds
Started Jul 26 04:26:05 PM PDT 24
Finished Jul 26 04:26:50 PM PDT 24
Peak memory 204056 kb
Host smart-214fbfef-a5e5-401c-b189-a1730c2a7c4e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1474318436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1474318436
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3310223021
Short name T29
Test name
Test status
Simulation time 251925325572 ps
CPU time 731.41 seconds
Started Jul 26 04:25:29 PM PDT 24
Finished Jul 26 04:37:40 PM PDT 24
Peak memory 207312 kb
Host smart-791f2100-8620-4f7b-96fd-642173efaad4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3310223021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo
w_rsp.3310223021
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2474034682
Short name T90
Test name
Test status
Simulation time 167839614984 ps
CPU time 528.62 seconds
Started Jul 26 04:24:14 PM PDT 24
Finished Jul 26 04:33:03 PM PDT 24
Peak memory 211580 kb
Host smart-7994360f-def9-42e7-94a3-9086338bd336
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2474034682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl
ow_rsp.2474034682
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.1949506986
Short name T8
Test name
Test status
Simulation time 3221920757 ps
CPU time 64.23 seconds
Started Jul 26 04:26:33 PM PDT 24
Finished Jul 26 04:27:37 PM PDT 24
Peak memory 205376 kb
Host smart-aab530a1-b42f-43b7-8aa6-f81e674e2d43
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1949506986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.1949506986
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.2936538246
Short name T127
Test name
Test status
Simulation time 86070196221 ps
CPU time 545.84 seconds
Started Jul 26 04:25:39 PM PDT 24
Finished Jul 26 04:34:45 PM PDT 24
Peak memory 206984 kb
Host smart-cbe8f16c-aff9-4509-862e-d57f6a60b389
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2936538246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl
ow_rsp.2936538246
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.3207200855
Short name T4
Test name
Test status
Simulation time 305106428 ps
CPU time 12.07 seconds
Started Jul 26 04:25:32 PM PDT 24
Finished Jul 26 04:25:44 PM PDT 24
Peak memory 203312 kb
Host smart-da2b0feb-3a8a-4261-92f7-59dae0812fe6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3207200855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.3207200855
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.2309686845
Short name T15
Test name
Test status
Simulation time 50389172 ps
CPU time 6.14 seconds
Started Jul 26 04:26:13 PM PDT 24
Finished Jul 26 04:26:19 PM PDT 24
Peak memory 211424 kb
Host smart-14f6ea74-0c48-408b-8b40-61b84bcb91e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2309686845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2309686845
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.3533841419
Short name T25
Test name
Test status
Simulation time 11325273299 ps
CPU time 452.47 seconds
Started Jul 26 04:25:30 PM PDT 24
Finished Jul 26 04:33:03 PM PDT 24
Peak memory 208028 kb
Host smart-b89fd5d2-2f92-4556-a7b2-51fb521bd665
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3533841419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand
_reset.3533841419
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.102985976
Short name T173
Test name
Test status
Simulation time 59121440505 ps
CPU time 255.02 seconds
Started Jul 26 04:24:29 PM PDT 24
Finished Jul 26 04:28:44 PM PDT 24
Peak memory 211964 kb
Host smart-b8d74cca-a56c-4da3-86e9-50f412b49c36
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=102985976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.102985976
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.1568703044
Short name T24
Test name
Test status
Simulation time 657365366 ps
CPU time 158.87 seconds
Started Jul 26 04:26:09 PM PDT 24
Finished Jul 26 04:28:49 PM PDT 24
Peak memory 209788 kb
Host smart-1593b806-fad1-4527-befd-8c34d538e57a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1568703044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res
et_error.1568703044
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.1766946020
Short name T81
Test name
Test status
Simulation time 1533726669 ps
CPU time 352.75 seconds
Started Jul 26 04:24:31 PM PDT 24
Finished Jul 26 04:30:24 PM PDT 24
Peak memory 210220 kb
Host smart-46c24322-db6f-4319-9cd5-aa77d95704c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1766946020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran
d_reset.1766946020
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2972040504
Short name T114
Test name
Test status
Simulation time 8775523820 ps
CPU time 317.48 seconds
Started Jul 26 04:24:17 PM PDT 24
Finished Jul 26 04:29:35 PM PDT 24
Peak memory 211472 kb
Host smart-a48bd583-3c9b-43d9-823e-814c98914c98
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2972040504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran
d_reset.2972040504
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3005205983
Short name T34
Test name
Test status
Simulation time 783791238 ps
CPU time 222.72 seconds
Started Jul 26 04:23:17 PM PDT 24
Finished Jul 26 04:27:00 PM PDT 24
Peak memory 208328 kb
Host smart-64600b19-b92e-4f9f-9ebd-077aa30ff0bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3005205983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran
d_reset.3005205983
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.1238697463
Short name T113
Test name
Test status
Simulation time 9388294727 ps
CPU time 109.02 seconds
Started Jul 26 04:25:30 PM PDT 24
Finished Jul 26 04:27:19 PM PDT 24
Peak memory 208500 kb
Host smart-f0ecfd86-aa23-4e5a-af5d-c5415075236a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1238697463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1238697463
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.606757112
Short name T27
Test name
Test status
Simulation time 2140827717 ps
CPU time 379.37 seconds
Started Jul 26 04:21:38 PM PDT 24
Finished Jul 26 04:27:57 PM PDT 24
Peak memory 219684 kb
Host smart-a6f40ccc-d5e9-491d-96cc-10003eeb9054
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=606757112 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_res
et_error.606757112
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.4121154590
Short name T33
Test name
Test status
Simulation time 21510916658 ps
CPU time 309.77 seconds
Started Jul 26 04:26:10 PM PDT 24
Finished Jul 26 04:31:20 PM PDT 24
Peak memory 219516 kb
Host smart-afefe7a0-b72b-44a3-8ae8-ff10b57e77ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4121154590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res
et_error.4121154590
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.907248638
Short name T31
Test name
Test status
Simulation time 526049885 ps
CPU time 14.99 seconds
Started Jul 26 04:26:16 PM PDT 24
Finished Jul 26 04:26:31 PM PDT 24
Peak memory 211396 kb
Host smart-64941e02-2a63-4d89-9d4a-4b9936cd11bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=907248638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.907248638
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.2399011212
Short name T761
Test name
Test status
Simulation time 250908274 ps
CPU time 16.12 seconds
Started Jul 26 04:19:54 PM PDT 24
Finished Jul 26 04:20:11 PM PDT 24
Peak memory 204132 kb
Host smart-ad7346b2-13a9-4074-a274-3d54f6ce8133
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2399011212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2399011212
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.437096565
Short name T771
Test name
Test status
Simulation time 95102873217 ps
CPU time 596.2 seconds
Started Jul 26 04:21:10 PM PDT 24
Finished Jul 26 04:31:06 PM PDT 24
Peak memory 211552 kb
Host smart-ffdd7fd8-3d3e-4909-97a6-f2b436f537f5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=437096565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow
_rsp.437096565
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.583955758
Short name T595
Test name
Test status
Simulation time 111348825 ps
CPU time 3.66 seconds
Started Jul 26 04:19:42 PM PDT 24
Finished Jul 26 04:19:46 PM PDT 24
Peak memory 203664 kb
Host smart-0e33cc32-c658-4201-8376-dd68fe71dc4e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=583955758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.583955758
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.2930543486
Short name T322
Test name
Test status
Simulation time 422244552 ps
CPU time 14.58 seconds
Started Jul 26 04:19:53 PM PDT 24
Finished Jul 26 04:20:08 PM PDT 24
Peak memory 203104 kb
Host smart-fe5d293f-4b9f-4b39-92cb-4b7b50ffaf2e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2930543486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2930543486
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.2612390909
Short name T740
Test name
Test status
Simulation time 134835801 ps
CPU time 4.58 seconds
Started Jul 26 04:19:54 PM PDT 24
Finished Jul 26 04:19:59 PM PDT 24
Peak memory 210936 kb
Host smart-a0017547-4868-44f3-863b-a972209ebcf8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2612390909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.2612390909
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.1402115223
Short name T865
Test name
Test status
Simulation time 43413482051 ps
CPU time 167.29 seconds
Started Jul 26 04:19:53 PM PDT 24
Finished Jul 26 04:22:41 PM PDT 24
Peak memory 204292 kb
Host smart-cf2ad846-d096-46b5-97fc-842ef9e4b1cf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402115223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1402115223
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1676453521
Short name T119
Test name
Test status
Simulation time 47776125175 ps
CPU time 171.68 seconds
Started Jul 26 04:19:53 PM PDT 24
Finished Jul 26 04:22:45 PM PDT 24
Peak memory 205288 kb
Host smart-bbebe469-2a5c-4bff-a9a7-816460ed9288
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1676453521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1676453521
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.441383017
Short name T743
Test name
Test status
Simulation time 231826890 ps
CPU time 22.45 seconds
Started Jul 26 04:19:53 PM PDT 24
Finished Jul 26 04:20:16 PM PDT 24
Peak memory 210596 kb
Host smart-098551a0-15df-43a5-bae7-50505fa93f9f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441383017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.441383017
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.1186642504
Short name T798
Test name
Test status
Simulation time 2149574241 ps
CPU time 13 seconds
Started Jul 26 04:20:55 PM PDT 24
Finished Jul 26 04:21:09 PM PDT 24
Peak memory 202528 kb
Host smart-d1c5a29a-edad-48a2-b701-40b4efa51682
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1186642504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1186642504
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.2394302136
Short name T336
Test name
Test status
Simulation time 26011811 ps
CPU time 2.13 seconds
Started Jul 26 04:19:44 PM PDT 24
Finished Jul 26 04:19:46 PM PDT 24
Peak memory 202932 kb
Host smart-f1018d25-4d09-4d83-afe5-e6fd2f4060f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2394302136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2394302136
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.1941532488
Short name T536
Test name
Test status
Simulation time 5544284282 ps
CPU time 25.34 seconds
Started Jul 26 04:20:55 PM PDT 24
Finished Jul 26 04:21:20 PM PDT 24
Peak memory 203080 kb
Host smart-f34b2c8f-6035-48cc-bbd8-ed499115ee08
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941532488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1941532488
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.3671141663
Short name T538
Test name
Test status
Simulation time 5669188378 ps
CPU time 24.04 seconds
Started Jul 26 04:19:53 PM PDT 24
Finished Jul 26 04:20:17 PM PDT 24
Peak memory 203400 kb
Host smart-4f1207b2-c78d-4628-8665-5d977c142aaa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3671141663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3671141663
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.2986823361
Short name T764
Test name
Test status
Simulation time 40039937 ps
CPU time 2.17 seconds
Started Jul 26 04:20:55 PM PDT 24
Finished Jul 26 04:20:58 PM PDT 24
Peak memory 202108 kb
Host smart-fef675e0-5aee-49d4-9483-5b5a14cbc421
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986823361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.2986823361
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.3972457809
Short name T167
Test name
Test status
Simulation time 300236074 ps
CPU time 32.67 seconds
Started Jul 26 04:19:53 PM PDT 24
Finished Jul 26 04:20:26 PM PDT 24
Peak memory 205308 kb
Host smart-09251fc1-115e-4976-8c03-e155cd880e68
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3972457809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3972457809
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1540208173
Short name T296
Test name
Test status
Simulation time 7413368328 ps
CPU time 208.84 seconds
Started Jul 26 04:19:43 PM PDT 24
Finished Jul 26 04:23:13 PM PDT 24
Peak memory 208444 kb
Host smart-6d5e0367-29d2-4b0a-b83f-f6ec64b0d769
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1540208173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1540208173
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.4235419809
Short name T765
Test name
Test status
Simulation time 424907071 ps
CPU time 215.49 seconds
Started Jul 26 04:19:56 PM PDT 24
Finished Jul 26 04:23:31 PM PDT 24
Peak memory 210544 kb
Host smart-b356ec93-43a9-4565-b3b5-231d9201c72f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4235419809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand
_reset.4235419809
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.2098742865
Short name T574
Test name
Test status
Simulation time 596550716 ps
CPU time 19.4 seconds
Started Jul 26 04:19:52 PM PDT 24
Finished Jul 26 04:20:11 PM PDT 24
Peak memory 210456 kb
Host smart-8ee73f72-679a-4337-86bc-1beef5739e04
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2098742865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2098742865
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.2938725452
Short name T817
Test name
Test status
Simulation time 297876285 ps
CPU time 7.21 seconds
Started Jul 26 04:21:11 PM PDT 24
Finished Jul 26 04:21:18 PM PDT 24
Peak memory 203328 kb
Host smart-2e93f45c-ba19-41ec-8398-a89eb01ab6f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2938725452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2938725452
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.3026998176
Short name T128
Test name
Test status
Simulation time 518480897632 ps
CPU time 907.69 seconds
Started Jul 26 04:21:11 PM PDT 24
Finished Jul 26 04:36:19 PM PDT 24
Peak memory 211552 kb
Host smart-3839badd-b6b4-4858-99c9-04780fd80ef4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3026998176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo
w_rsp.3026998176
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1248292474
Short name T532
Test name
Test status
Simulation time 192863605 ps
CPU time 2.21 seconds
Started Jul 26 04:19:52 PM PDT 24
Finished Jul 26 04:19:55 PM PDT 24
Peak memory 203416 kb
Host smart-b7e23224-143a-435a-a696-a60be08f272e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1248292474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1248292474
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.2526555553
Short name T413
Test name
Test status
Simulation time 1116166011 ps
CPU time 17.87 seconds
Started Jul 26 04:19:52 PM PDT 24
Finished Jul 26 04:20:11 PM PDT 24
Peak memory 203148 kb
Host smart-6a34776e-eae8-4368-be4a-5279983d3fd8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2526555553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2526555553
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.1431540193
Short name T411
Test name
Test status
Simulation time 421006619 ps
CPU time 11.58 seconds
Started Jul 26 04:20:54 PM PDT 24
Finished Jul 26 04:21:06 PM PDT 24
Peak memory 210744 kb
Host smart-c724fa7d-bd4b-4427-9596-0c614cd9767c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1431540193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.1431540193
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.1295227202
Short name T861
Test name
Test status
Simulation time 34249804741 ps
CPU time 47.24 seconds
Started Jul 26 04:20:56 PM PDT 24
Finished Jul 26 04:21:43 PM PDT 24
Peak memory 211176 kb
Host smart-50d4e709-0212-4a5f-b4a8-4e00e9404de6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295227202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.1295227202
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2906406884
Short name T770
Test name
Test status
Simulation time 53228991882 ps
CPU time 257.77 seconds
Started Jul 26 04:19:54 PM PDT 24
Finished Jul 26 04:24:12 PM PDT 24
Peak memory 211216 kb
Host smart-69d820b3-a2b9-4a66-b933-71208a38988d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2906406884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2906406884
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.2318896822
Short name T756
Test name
Test status
Simulation time 224316539 ps
CPU time 23.67 seconds
Started Jul 26 04:19:43 PM PDT 24
Finished Jul 26 04:20:07 PM PDT 24
Peak memory 210720 kb
Host smart-0e3013f2-58de-44b8-b057-3847388bd5ca
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318896822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.2318896822
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.4134196673
Short name T829
Test name
Test status
Simulation time 240788556 ps
CPU time 19.95 seconds
Started Jul 26 04:20:55 PM PDT 24
Finished Jul 26 04:21:15 PM PDT 24
Peak memory 202712 kb
Host smart-01c41895-4fff-4416-aa6f-7d442dbca24a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4134196673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.4134196673
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.3087079845
Short name T571
Test name
Test status
Simulation time 328495885 ps
CPU time 3 seconds
Started Jul 26 04:19:52 PM PDT 24
Finished Jul 26 04:19:55 PM PDT 24
Peak memory 202568 kb
Host smart-e712e5a5-eefb-4044-a5dd-4621913042b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3087079845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3087079845
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.2603385387
Short name T212
Test name
Test status
Simulation time 6793759537 ps
CPU time 26.95 seconds
Started Jul 26 04:19:52 PM PDT 24
Finished Jul 26 04:20:19 PM PDT 24
Peak memory 203048 kb
Host smart-02c312c9-1276-4341-ab95-c2334f0309d4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603385387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2603385387
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1361798922
Short name T775
Test name
Test status
Simulation time 10008811917 ps
CPU time 33.81 seconds
Started Jul 26 04:20:54 PM PDT 24
Finished Jul 26 04:21:28 PM PDT 24
Peak memory 202560 kb
Host smart-68556630-18ca-4c1b-9a73-a468c60ecbcf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1361798922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1361798922
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1332681087
Short name T526
Test name
Test status
Simulation time 39262415 ps
CPU time 2.28 seconds
Started Jul 26 04:19:52 PM PDT 24
Finished Jul 26 04:19:55 PM PDT 24
Peak memory 202708 kb
Host smart-1077662b-3c7f-46c5-8c3c-f86b81255c74
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332681087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1332681087
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.72951122
Short name T634
Test name
Test status
Simulation time 297386658 ps
CPU time 33.05 seconds
Started Jul 26 04:19:54 PM PDT 24
Finished Jul 26 04:20:27 PM PDT 24
Peak memory 206540 kb
Host smart-a963948a-e2ef-4a11-b487-6cc4bd6439f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=72951122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.72951122
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.1320383862
Short name T567
Test name
Test status
Simulation time 896311771 ps
CPU time 84.43 seconds
Started Jul 26 04:19:56 PM PDT 24
Finished Jul 26 04:21:21 PM PDT 24
Peak memory 207816 kb
Host smart-a9b2fcbc-e758-43cd-b569-e5b7f4381289
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1320383862 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1320383862
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.3729699555
Short name T523
Test name
Test status
Simulation time 4667829449 ps
CPU time 221.67 seconds
Started Jul 26 04:20:55 PM PDT 24
Finished Jul 26 04:24:37 PM PDT 24
Peak memory 208940 kb
Host smart-76911850-80a4-4001-93c7-d68334cfa9c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3729699555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand
_reset.3729699555
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.161798776
Short name T295
Test name
Test status
Simulation time 7674224869 ps
CPU time 297.41 seconds
Started Jul 26 04:19:52 PM PDT 24
Finished Jul 26 04:24:50 PM PDT 24
Peak memory 209540 kb
Host smart-0d151cc8-9d07-4e07-8399-cc656c79a02d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=161798776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rese
t_error.161798776
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.1209137154
Short name T279
Test name
Test status
Simulation time 443891093 ps
CPU time 13.91 seconds
Started Jul 26 04:19:44 PM PDT 24
Finished Jul 26 04:19:58 PM PDT 24
Peak memory 210748 kb
Host smart-436f7c7b-6553-4e9d-a29e-9ac009f290c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1209137154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1209137154
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.1800239351
Short name T332
Test name
Test status
Simulation time 115663859 ps
CPU time 4.73 seconds
Started Jul 26 04:25:34 PM PDT 24
Finished Jul 26 04:25:39 PM PDT 24
Peak memory 203236 kb
Host smart-ee3811a1-1bfc-493a-8a64-75a6dc0ad058
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1800239351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1800239351
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1695245660
Short name T841
Test name
Test status
Simulation time 72243643493 ps
CPU time 564.11 seconds
Started Jul 26 04:25:00 PM PDT 24
Finished Jul 26 04:34:25 PM PDT 24
Peak memory 210256 kb
Host smart-3b10d43b-5150-4f86-b23a-a4bb6f6868a0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1695245660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl
ow_rsp.1695245660
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.759461733
Short name T648
Test name
Test status
Simulation time 138534719 ps
CPU time 19.95 seconds
Started Jul 26 04:23:25 PM PDT 24
Finished Jul 26 04:23:45 PM PDT 24
Peak memory 203860 kb
Host smart-5adc520f-5c78-4f09-93c2-7adfc1268716
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=759461733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.759461733
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.2076687776
Short name T583
Test name
Test status
Simulation time 101487814 ps
CPU time 10.13 seconds
Started Jul 26 04:25:34 PM PDT 24
Finished Jul 26 04:25:44 PM PDT 24
Peak memory 203076 kb
Host smart-31d1e691-e422-461b-b8a3-6f57268ccb7e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2076687776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2076687776
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.2846906526
Short name T448
Test name
Test status
Simulation time 241494849 ps
CPU time 18.37 seconds
Started Jul 26 04:20:45 PM PDT 24
Finished Jul 26 04:21:03 PM PDT 24
Peak memory 211516 kb
Host smart-cc2b16a6-4ecd-432c-9e60-88ce46273138
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2846906526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.2846906526
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.2909292246
Short name T269
Test name
Test status
Simulation time 43668496208 ps
CPU time 236.78 seconds
Started Jul 26 04:25:55 PM PDT 24
Finished Jul 26 04:29:52 PM PDT 24
Peak memory 210780 kb
Host smart-348c68ca-e47b-4f0f-b236-daf79db2c1fd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909292246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2909292246
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.580496838
Short name T545
Test name
Test status
Simulation time 26290979927 ps
CPU time 162.3 seconds
Started Jul 26 04:26:05 PM PDT 24
Finished Jul 26 04:28:48 PM PDT 24
Peak memory 211288 kb
Host smart-10a4e417-4146-4079-a093-e64fcb381ec0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=580496838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.580496838
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.3639742806
Short name T325
Test name
Test status
Simulation time 168320397 ps
CPU time 25.92 seconds
Started Jul 26 04:25:24 PM PDT 24
Finished Jul 26 04:25:50 PM PDT 24
Peak memory 210684 kb
Host smart-05fe5324-b8b7-4627-b468-35e68b8e2f0f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639742806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3639742806
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.2490693135
Short name T432
Test name
Test status
Simulation time 554365155 ps
CPU time 13.35 seconds
Started Jul 26 04:26:06 PM PDT 24
Finished Jul 26 04:26:20 PM PDT 24
Peak memory 203064 kb
Host smart-c0f9fbb7-3a4a-49df-93bc-39649d835ada
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2490693135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2490693135
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.1356925669
Short name T675
Test name
Test status
Simulation time 1157640844 ps
CPU time 4.7 seconds
Started Jul 26 04:21:26 PM PDT 24
Finished Jul 26 04:21:31 PM PDT 24
Peak memory 203332 kb
Host smart-af6483b0-9a11-431e-a290-b92af830930a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1356925669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1356925669
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.2951561095
Short name T64
Test name
Test status
Simulation time 8990013429 ps
CPU time 30.99 seconds
Started Jul 26 04:20:45 PM PDT 24
Finished Jul 26 04:21:16 PM PDT 24
Peak memory 203412 kb
Host smart-c1d046cf-ed7f-4ca4-a9d3-86bb57795176
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951561095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2951561095
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.339592560
Short name T713
Test name
Test status
Simulation time 4804737257 ps
CPU time 33.73 seconds
Started Jul 26 04:20:45 PM PDT 24
Finished Jul 26 04:21:19 PM PDT 24
Peak memory 203420 kb
Host smart-2a9e8aa9-b35a-4ca9-b158-fc16fb2ca9f3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=339592560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.339592560
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3097387216
Short name T96
Test name
Test status
Simulation time 40651099 ps
CPU time 2.42 seconds
Started Jul 26 04:20:40 PM PDT 24
Finished Jul 26 04:20:43 PM PDT 24
Peak memory 203332 kb
Host smart-66b0aaa2-79a7-426a-96f1-531fbbd74793
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097387216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3097387216
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.2831225773
Short name T278
Test name
Test status
Simulation time 716845020 ps
CPU time 19.57 seconds
Started Jul 26 04:21:01 PM PDT 24
Finished Jul 26 04:21:20 PM PDT 24
Peak memory 205628 kb
Host smart-1e353ae0-417c-4444-8270-8b1ec3817695
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2831225773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2831225773
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.2415565932
Short name T12
Test name
Test status
Simulation time 743942891 ps
CPU time 77.88 seconds
Started Jul 26 04:25:34 PM PDT 24
Finished Jul 26 04:26:52 PM PDT 24
Peak memory 204716 kb
Host smart-270046df-ee28-4f68-9e38-102f3130cd1c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2415565932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2415565932
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3262782508
Short name T112
Test name
Test status
Simulation time 7823230409 ps
CPU time 186.22 seconds
Started Jul 26 04:25:35 PM PDT 24
Finished Jul 26 04:28:41 PM PDT 24
Peak memory 209160 kb
Host smart-d25d44bd-2baa-4ab0-a023-d6e055e5fbfd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3262782508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran
d_reset.3262782508
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1365448971
Short name T680
Test name
Test status
Simulation time 5099955295 ps
CPU time 674.37 seconds
Started Jul 26 04:25:34 PM PDT 24
Finished Jul 26 04:36:49 PM PDT 24
Peak memory 227700 kb
Host smart-377ffd31-38dd-4336-abf6-b4ab9ff31525
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1365448971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re
set_error.1365448971
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.2826058124
Short name T461
Test name
Test status
Simulation time 738504868 ps
CPU time 13.95 seconds
Started Jul 26 04:26:05 PM PDT 24
Finished Jul 26 04:26:19 PM PDT 24
Peak memory 211212 kb
Host smart-2541fe76-11b7-4678-8c08-f42e8836e9b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2826058124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2826058124
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.1652688434
Short name T69
Test name
Test status
Simulation time 165354049 ps
CPU time 9.24 seconds
Started Jul 26 04:25:16 PM PDT 24
Finished Jul 26 04:25:26 PM PDT 24
Peak memory 203824 kb
Host smart-575c28a7-4164-4bf8-887e-0ec0154ff8f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1652688434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.1652688434
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.2420000139
Short name T445
Test name
Test status
Simulation time 121154817998 ps
CPU time 500.96 seconds
Started Jul 26 04:24:30 PM PDT 24
Finished Jul 26 04:32:51 PM PDT 24
Peak memory 210504 kb
Host smart-425d31e9-3d59-44d2-8326-073aa2b2a357
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2420000139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl
ow_rsp.2420000139
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2431570767
Short name T310
Test name
Test status
Simulation time 3990326643 ps
CPU time 25.32 seconds
Started Jul 26 04:20:44 PM PDT 24
Finished Jul 26 04:21:09 PM PDT 24
Peak memory 203404 kb
Host smart-d1bee1e9-5872-44be-a33c-0c7bc032c56c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2431570767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2431570767
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.3619533663
Short name T869
Test name
Test status
Simulation time 28171918 ps
CPU time 2.96 seconds
Started Jul 26 04:22:22 PM PDT 24
Finished Jul 26 04:22:25 PM PDT 24
Peak memory 203280 kb
Host smart-76a9a7c9-9c10-43f4-80df-5cb1c0c9bfdf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3619533663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3619533663
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.3907104551
Short name T225
Test name
Test status
Simulation time 150665658 ps
CPU time 17.49 seconds
Started Jul 26 04:26:06 PM PDT 24
Finished Jul 26 04:26:24 PM PDT 24
Peak memory 211228 kb
Host smart-2b3bda21-defb-46ed-9de1-b0d74dbf5544
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3907104551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3907104551
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.1017681666
Short name T850
Test name
Test status
Simulation time 44319020720 ps
CPU time 144.51 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:27:40 PM PDT 24
Peak memory 204748 kb
Host smart-ca888f90-87a7-42e1-b90e-573ada822f79
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017681666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1017681666
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.2329112889
Short name T214
Test name
Test status
Simulation time 37703086207 ps
CPU time 259.71 seconds
Started Jul 26 04:24:30 PM PDT 24
Finished Jul 26 04:28:50 PM PDT 24
Peak memory 210480 kb
Host smart-82f51800-828b-482c-be16-76a28ea521bb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2329112889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2329112889
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.995973138
Short name T244
Test name
Test status
Simulation time 35924383 ps
CPU time 3.25 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:25:19 PM PDT 24
Peak memory 202052 kb
Host smart-1cdf33b4-e4fd-414e-a9fc-a247efee29f8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995973138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.995973138
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.3014762019
Short name T493
Test name
Test status
Simulation time 328113445 ps
CPU time 11.41 seconds
Started Jul 26 04:23:23 PM PDT 24
Finished Jul 26 04:23:35 PM PDT 24
Peak memory 203316 kb
Host smart-6667efc0-f0b4-42c9-aceb-69dc90ee1c6c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3014762019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3014762019
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.477539361
Short name T47
Test name
Test status
Simulation time 254018048 ps
CPU time 2.9 seconds
Started Jul 26 04:20:37 PM PDT 24
Finished Jul 26 04:20:40 PM PDT 24
Peak memory 203708 kb
Host smart-c3267d20-2e5e-4c82-a290-1f89d6421be6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=477539361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.477539361
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.394100376
Short name T737
Test name
Test status
Simulation time 12573538082 ps
CPU time 31.11 seconds
Started Jul 26 04:23:20 PM PDT 24
Finished Jul 26 04:23:51 PM PDT 24
Peak memory 203416 kb
Host smart-3aa87ab4-9c47-4fa6-837f-972108b41d9a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=394100376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.394100376
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3768636369
Short name T10
Test name
Test status
Simulation time 6672161496 ps
CPU time 33.73 seconds
Started Jul 26 04:24:44 PM PDT 24
Finished Jul 26 04:25:18 PM PDT 24
Peak memory 203152 kb
Host smart-74baffea-18d4-4374-a973-9a5baee2f7ac
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3768636369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3768636369
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2630039566
Short name T188
Test name
Test status
Simulation time 30206124 ps
CPU time 2.57 seconds
Started Jul 26 04:21:15 PM PDT 24
Finished Jul 26 04:21:17 PM PDT 24
Peak memory 203300 kb
Host smart-409f6ac3-8242-48f3-aaf9-9e1f5352484c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630039566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2630039566
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.4272523635
Short name T338
Test name
Test status
Simulation time 4560248616 ps
CPU time 128.17 seconds
Started Jul 26 04:24:44 PM PDT 24
Finished Jul 26 04:26:52 PM PDT 24
Peak memory 205928 kb
Host smart-7f01df0f-9428-457f-976b-6b02c814d657
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4272523635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.4272523635
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2910428513
Short name T436
Test name
Test status
Simulation time 2318233893 ps
CPU time 49.97 seconds
Started Jul 26 04:21:29 PM PDT 24
Finished Jul 26 04:22:19 PM PDT 24
Peak memory 206268 kb
Host smart-c08ed203-cc6b-42e3-b079-78d526c67531
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2910428513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2910428513
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.2857086226
Short name T44
Test name
Test status
Simulation time 186752915 ps
CPU time 55.22 seconds
Started Jul 26 04:22:55 PM PDT 24
Finished Jul 26 04:23:51 PM PDT 24
Peak memory 206620 kb
Host smart-a5ecc590-afac-4587-bf9b-5b6bff00534f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2857086226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran
d_reset.2857086226
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.2974377915
Short name T443
Test name
Test status
Simulation time 4071149939 ps
CPU time 221.33 seconds
Started Jul 26 04:20:45 PM PDT 24
Finished Jul 26 04:24:26 PM PDT 24
Peak memory 211580 kb
Host smart-78385f7a-ea61-421f-a994-bc0e7b7aca38
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2974377915 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re
set_error.2974377915
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.126637676
Short name T277
Test name
Test status
Simulation time 184069905 ps
CPU time 21.88 seconds
Started Jul 26 04:26:06 PM PDT 24
Finished Jul 26 04:26:28 PM PDT 24
Peak memory 211228 kb
Host smart-a708e067-27bd-4262-8cb5-9892e8ee4333
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=126637676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.126637676
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.1594068242
Short name T157
Test name
Test status
Simulation time 1467407045 ps
CPU time 63.07 seconds
Started Jul 26 04:25:11 PM PDT 24
Finished Jul 26 04:26:14 PM PDT 24
Peak memory 211532 kb
Host smart-156d1fcf-c93b-4c51-ac17-b50fcab1c968
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1594068242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1594068242
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.3809560130
Short name T171
Test name
Test status
Simulation time 74298443743 ps
CPU time 304.73 seconds
Started Jul 26 04:24:57 PM PDT 24
Finished Jul 26 04:30:02 PM PDT 24
Peak memory 211360 kb
Host smart-29550ba4-2895-429c-b064-20b7f815866b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3809560130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl
ow_rsp.3809560130
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.2628898056
Short name T165
Test name
Test status
Simulation time 1015668215 ps
CPU time 22.62 seconds
Started Jul 26 04:24:40 PM PDT 24
Finished Jul 26 04:25:03 PM PDT 24
Peak memory 203808 kb
Host smart-1b46cf2d-a61e-449d-901c-e0410664d8cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2628898056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.2628898056
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.3315431055
Short name T316
Test name
Test status
Simulation time 358119801 ps
CPU time 2.79 seconds
Started Jul 26 04:24:57 PM PDT 24
Finished Jul 26 04:25:00 PM PDT 24
Peak memory 203084 kb
Host smart-98720ddf-bd99-4242-aa51-1457548c194d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3315431055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.3315431055
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.622104454
Short name T105
Test name
Test status
Simulation time 492558962 ps
CPU time 15.87 seconds
Started Jul 26 04:25:05 PM PDT 24
Finished Jul 26 04:25:21 PM PDT 24
Peak memory 204432 kb
Host smart-d26eccfb-1d06-4ac9-b809-db537003ec10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=622104454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.622104454
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.295997510
Short name T393
Test name
Test status
Simulation time 180242670612 ps
CPU time 273.29 seconds
Started Jul 26 04:25:04 PM PDT 24
Finished Jul 26 04:29:38 PM PDT 24
Peak memory 209760 kb
Host smart-287d3164-521b-4723-9484-dc0afb091a5c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=295997510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.295997510
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.2274639837
Short name T135
Test name
Test status
Simulation time 52847377184 ps
CPU time 98.15 seconds
Started Jul 26 04:21:42 PM PDT 24
Finished Jul 26 04:23:20 PM PDT 24
Peak memory 211556 kb
Host smart-4c2bc901-7b4e-4f2e-9121-38cc2b663e63
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2274639837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2274639837
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.1103872209
Short name T619
Test name
Test status
Simulation time 79277443 ps
CPU time 10.98 seconds
Started Jul 26 04:20:48 PM PDT 24
Finished Jul 26 04:20:59 PM PDT 24
Peak memory 211476 kb
Host smart-5d86981c-58a4-45ec-9e81-570a45fc1664
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103872209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.1103872209
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.3424631663
Short name T349
Test name
Test status
Simulation time 139887143 ps
CPU time 13.16 seconds
Started Jul 26 04:20:53 PM PDT 24
Finished Jul 26 04:21:06 PM PDT 24
Peak memory 203908 kb
Host smart-88dfb06a-2bca-48bf-936e-150008af559d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3424631663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3424631663
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.981170945
Short name T169
Test name
Test status
Simulation time 104165378 ps
CPU time 2.94 seconds
Started Jul 26 04:21:40 PM PDT 24
Finished Jul 26 04:21:43 PM PDT 24
Peak memory 203308 kb
Host smart-a329bc6f-409d-44bf-b1cf-6df1b8876b43
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=981170945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.981170945
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3685582691
Short name T239
Test name
Test status
Simulation time 4406311169 ps
CPU time 26.23 seconds
Started Jul 26 04:20:43 PM PDT 24
Finished Jul 26 04:21:10 PM PDT 24
Peak memory 203732 kb
Host smart-9064de4a-b490-4a43-ac72-25ccee1d9837
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685582691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3685582691
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.3089055080
Short name T720
Test name
Test status
Simulation time 6492682264 ps
CPU time 36.48 seconds
Started Jul 26 04:24:56 PM PDT 24
Finished Jul 26 04:25:34 PM PDT 24
Peak memory 202572 kb
Host smart-8fae52ed-6683-4bcc-80e4-7284e073e7be
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3089055080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3089055080
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.1551818191
Short name T490
Test name
Test status
Simulation time 83154736 ps
CPU time 2 seconds
Started Jul 26 04:25:13 PM PDT 24
Finished Jul 26 04:25:15 PM PDT 24
Peak memory 203056 kb
Host smart-2854bfe1-a394-48d3-836e-fbc40fec8643
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551818191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.1551818191
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.1141941025
Short name T406
Test name
Test status
Simulation time 410277323 ps
CPU time 18.22 seconds
Started Jul 26 04:25:13 PM PDT 24
Finished Jul 26 04:25:31 PM PDT 24
Peak memory 204732 kb
Host smart-2e2b7d8a-27c4-494d-a3b5-b04da3b1b689
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1141941025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1141941025
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2531808639
Short name T787
Test name
Test status
Simulation time 2881789041 ps
CPU time 79.63 seconds
Started Jul 26 04:25:04 PM PDT 24
Finished Jul 26 04:26:24 PM PDT 24
Peak memory 205520 kb
Host smart-d3032e23-1b75-4f20-8443-7e8fd0efc9a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2531808639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2531808639
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2133791012
Short name T134
Test name
Test status
Simulation time 2066628411 ps
CPU time 82.5 seconds
Started Jul 26 04:24:27 PM PDT 24
Finished Jul 26 04:25:50 PM PDT 24
Peak memory 206012 kb
Host smart-4a0b2235-d2ce-4c1a-b3e6-993462eef8e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2133791012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran
d_reset.2133791012
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3887359435
Short name T276
Test name
Test status
Simulation time 9591244506 ps
CPU time 133.43 seconds
Started Jul 26 04:24:27 PM PDT 24
Finished Jul 26 04:26:41 PM PDT 24
Peak memory 208020 kb
Host smart-bf8a4e05-0351-40bd-82f8-f1a812e1a560
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3887359435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re
set_error.3887359435
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1821653112
Short name T471
Test name
Test status
Simulation time 501206549 ps
CPU time 18.09 seconds
Started Jul 26 04:20:53 PM PDT 24
Finished Jul 26 04:21:11 PM PDT 24
Peak memory 204688 kb
Host smart-57e75b80-27ba-4f10-9862-d40539bb6389
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1821653112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1821653112
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.2120309163
Short name T101
Test name
Test status
Simulation time 605323629 ps
CPU time 27.89 seconds
Started Jul 26 04:21:53 PM PDT 24
Finished Jul 26 04:22:21 PM PDT 24
Peak memory 204648 kb
Host smart-27abdca0-2fb2-42df-9436-105d46a2e4d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2120309163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2120309163
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.2360908146
Short name T298
Test name
Test status
Simulation time 56677309402 ps
CPU time 240.23 seconds
Started Jul 26 04:24:54 PM PDT 24
Finished Jul 26 04:28:55 PM PDT 24
Peak memory 204512 kb
Host smart-bbab0a84-7c4a-490f-955d-3d4f58a3c979
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2360908146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl
ow_rsp.2360908146
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.785138068
Short name T240
Test name
Test status
Simulation time 131206300 ps
CPU time 5.07 seconds
Started Jul 26 04:21:23 PM PDT 24
Finished Jul 26 04:21:28 PM PDT 24
Peak memory 203328 kb
Host smart-454e87e6-01a5-49f2-894b-cd6ebb00b159
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=785138068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.785138068
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.4147211109
Short name T752
Test name
Test status
Simulation time 370019546 ps
CPU time 7.31 seconds
Started Jul 26 04:25:08 PM PDT 24
Finished Jul 26 04:25:16 PM PDT 24
Peak memory 203256 kb
Host smart-a1ed43bb-4d3a-42ba-912b-282729198d5f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4147211109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.4147211109
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.844135470
Short name T696
Test name
Test status
Simulation time 36024756 ps
CPU time 4.68 seconds
Started Jul 26 04:21:53 PM PDT 24
Finished Jul 26 04:21:58 PM PDT 24
Peak memory 211476 kb
Host smart-4de2d74e-4125-43ee-874b-969cd24e1070
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=844135470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.844135470
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.568151803
Short name T468
Test name
Test status
Simulation time 60439595324 ps
CPU time 245.78 seconds
Started Jul 26 04:25:04 PM PDT 24
Finished Jul 26 04:29:10 PM PDT 24
Peak memory 209540 kb
Host smart-7c1d1861-6606-460f-b830-e67c206deda3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=568151803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.568151803
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.4162883077
Short name T823
Test name
Test status
Simulation time 16871279806 ps
CPU time 96.22 seconds
Started Jul 26 04:24:54 PM PDT 24
Finished Jul 26 04:26:31 PM PDT 24
Peak memory 210292 kb
Host smart-ebcf57b1-2a15-4d69-95c2-38292a2d15b6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4162883077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.4162883077
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.1093407566
Short name T896
Test name
Test status
Simulation time 276107438 ps
CPU time 25.42 seconds
Started Jul 26 04:23:11 PM PDT 24
Finished Jul 26 04:23:36 PM PDT 24
Peak memory 204884 kb
Host smart-9e6b79f8-0972-438d-b257-e129576979a4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093407566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1093407566
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.525250144
Short name T288
Test name
Test status
Simulation time 97122519 ps
CPU time 5.94 seconds
Started Jul 26 04:22:26 PM PDT 24
Finished Jul 26 04:22:32 PM PDT 24
Peak memory 203904 kb
Host smart-7f42c205-6ef2-4e48-a589-74bd15230b4a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=525250144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.525250144
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.3672198351
Short name T614
Test name
Test status
Simulation time 28654137 ps
CPU time 2.06 seconds
Started Jul 26 04:23:08 PM PDT 24
Finished Jul 26 04:23:11 PM PDT 24
Peak memory 203208 kb
Host smart-b9bd6573-5d4b-4625-9074-95f30b9550f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3672198351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.3672198351
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.3617265533
Short name T372
Test name
Test status
Simulation time 16708426459 ps
CPU time 38.7 seconds
Started Jul 26 04:22:27 PM PDT 24
Finished Jul 26 04:23:06 PM PDT 24
Peak memory 203344 kb
Host smart-eba90704-f9b2-43d4-acba-dad130a5fea3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617265533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3617265533
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.3501131079
Short name T824
Test name
Test status
Simulation time 2443081869 ps
CPU time 21.63 seconds
Started Jul 26 04:22:55 PM PDT 24
Finished Jul 26 04:23:17 PM PDT 24
Peak memory 203264 kb
Host smart-d26296f0-c4ff-47dc-86f5-14c2a313126b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3501131079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3501131079
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.4255605873
Short name T433
Test name
Test status
Simulation time 41999416 ps
CPU time 2.49 seconds
Started Jul 26 04:25:09 PM PDT 24
Finished Jul 26 04:25:11 PM PDT 24
Peak memory 203236 kb
Host smart-89da5fda-6fe1-43de-9785-ed977525ecbe
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255605873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.4255605873
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.2590245803
Short name T215
Test name
Test status
Simulation time 2506576413 ps
CPU time 169.07 seconds
Started Jul 26 04:24:32 PM PDT 24
Finished Jul 26 04:27:22 PM PDT 24
Peak memory 206632 kb
Host smart-6537bd44-23b4-4d88-87ca-7cdf5fba4194
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2590245803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2590245803
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3008258177
Short name T340
Test name
Test status
Simulation time 9411536734 ps
CPU time 122.87 seconds
Started Jul 26 04:24:27 PM PDT 24
Finished Jul 26 04:26:30 PM PDT 24
Peak memory 205952 kb
Host smart-6dc7e47c-ea29-48b6-9470-d381a7982b29
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3008258177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3008258177
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.673211719
Short name T656
Test name
Test status
Simulation time 1547976875 ps
CPU time 305.4 seconds
Started Jul 26 04:22:34 PM PDT 24
Finished Jul 26 04:27:39 PM PDT 24
Peak memory 210076 kb
Host smart-693549a8-25c5-4259-9d3f-3787df2244b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=673211719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand
_reset.673211719
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.773456301
Short name T626
Test name
Test status
Simulation time 1449920666 ps
CPU time 188.29 seconds
Started Jul 26 04:21:26 PM PDT 24
Finished Jul 26 04:24:35 PM PDT 24
Peak memory 208336 kb
Host smart-c3e4d01b-b6d2-4f1f-8cfb-657d3a0124c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=773456301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_res
et_error.773456301
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.3028005139
Short name T430
Test name
Test status
Simulation time 694437999 ps
CPU time 26.57 seconds
Started Jul 26 04:21:31 PM PDT 24
Finished Jul 26 04:21:57 PM PDT 24
Peak memory 204956 kb
Host smart-c3b213b5-fed2-4bf2-b4ed-7f955d979958
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3028005139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3028005139
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.88995074
Short name T256
Test name
Test status
Simulation time 843104995 ps
CPU time 28.02 seconds
Started Jul 26 04:23:49 PM PDT 24
Finished Jul 26 04:24:17 PM PDT 24
Peak memory 211532 kb
Host smart-fbdf76ec-29d4-4e7f-a4c6-ba50246d9391
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=88995074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.88995074
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.702551359
Short name T437
Test name
Test status
Simulation time 54139773706 ps
CPU time 428.48 seconds
Started Jul 26 04:26:07 PM PDT 24
Finished Jul 26 04:33:15 PM PDT 24
Peak memory 211328 kb
Host smart-ed8deacb-ea99-4e48-9044-cab603b15ed6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=702551359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slo
w_rsp.702551359
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.1546468279
Short name T370
Test name
Test status
Simulation time 274003318 ps
CPU time 9.34 seconds
Started Jul 26 04:21:39 PM PDT 24
Finished Jul 26 04:21:49 PM PDT 24
Peak memory 203264 kb
Host smart-f59c4d76-35d8-4795-84e4-f29cfc2d05b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1546468279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.1546468279
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.3869101328
Short name T729
Test name
Test status
Simulation time 472664288 ps
CPU time 16.98 seconds
Started Jul 26 04:21:55 PM PDT 24
Finished Jul 26 04:22:12 PM PDT 24
Peak memory 203412 kb
Host smart-e8240193-23b4-4599-9636-00ea8be3ba9b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3869101328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3869101328
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.1416849829
Short name T476
Test name
Test status
Simulation time 648546971 ps
CPU time 18.1 seconds
Started Jul 26 04:26:08 PM PDT 24
Finished Jul 26 04:26:27 PM PDT 24
Peak memory 211256 kb
Host smart-e45ff2cf-e267-4114-9c64-54f4bb8b88fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1416849829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1416849829
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.2097587405
Short name T683
Test name
Test status
Simulation time 41601829657 ps
CPU time 133.77 seconds
Started Jul 26 04:26:08 PM PDT 24
Finished Jul 26 04:28:22 PM PDT 24
Peak memory 204764 kb
Host smart-c6eddd30-e279-4ff2-b0df-a8fa80a8a267
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097587405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2097587405
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3850433061
Short name T11
Test name
Test status
Simulation time 40962747911 ps
CPU time 225.84 seconds
Started Jul 26 04:26:08 PM PDT 24
Finished Jul 26 04:29:54 PM PDT 24
Peak memory 211352 kb
Host smart-3e23c00b-a3a4-4c50-9cd5-61627d1520f2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3850433061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3850433061
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.449666958
Short name T220
Test name
Test status
Simulation time 155386368 ps
CPU time 26.88 seconds
Started Jul 26 04:23:51 PM PDT 24
Finished Jul 26 04:24:18 PM PDT 24
Peak memory 205016 kb
Host smart-2704dadb-053b-4658-9272-8e0b8a75bacc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449666958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.449666958
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.1064425019
Short name T768
Test name
Test status
Simulation time 992843625 ps
CPU time 17.76 seconds
Started Jul 26 04:23:38 PM PDT 24
Finished Jul 26 04:23:56 PM PDT 24
Peak memory 203784 kb
Host smart-b4f6c881-4786-4b29-9857-82c6ad4c68bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1064425019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1064425019
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke.2416859116
Short name T879
Test name
Test status
Simulation time 68008045 ps
CPU time 2.28 seconds
Started Jul 26 04:21:33 PM PDT 24
Finished Jul 26 04:21:35 PM PDT 24
Peak memory 203472 kb
Host smart-f3a858d2-88b9-46a7-9b0d-b6fd9951c9b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2416859116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2416859116
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.476842767
Short name T1
Test name
Test status
Simulation time 5183263794 ps
CPU time 30.29 seconds
Started Jul 26 04:21:27 PM PDT 24
Finished Jul 26 04:21:57 PM PDT 24
Peak memory 203772 kb
Host smart-6ed2c2b1-553c-46aa-965a-bbf895b73de8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=476842767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.476842767
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2136718710
Short name T72
Test name
Test status
Simulation time 3612943638 ps
CPU time 29.37 seconds
Started Jul 26 04:21:25 PM PDT 24
Finished Jul 26 04:21:54 PM PDT 24
Peak memory 203396 kb
Host smart-f2249552-fb18-4dc7-bac4-01d0e8112b24
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2136718710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2136718710
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.2776662157
Short name T421
Test name
Test status
Simulation time 20741427 ps
CPU time 1.87 seconds
Started Jul 26 04:25:08 PM PDT 24
Finished Jul 26 04:25:10 PM PDT 24
Peak memory 202448 kb
Host smart-738d9c04-2e98-480a-a704-548b0e0c7c8f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776662157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.2776662157
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.940347654
Short name T405
Test name
Test status
Simulation time 5181771336 ps
CPU time 153.97 seconds
Started Jul 26 04:23:41 PM PDT 24
Finished Jul 26 04:26:15 PM PDT 24
Peak memory 206528 kb
Host smart-e144e762-d50b-4a0e-9ea0-0e6cfbc47131
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=940347654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.940347654
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1305652923
Short name T620
Test name
Test status
Simulation time 256483234 ps
CPU time 15.52 seconds
Started Jul 26 04:25:03 PM PDT 24
Finished Jul 26 04:25:19 PM PDT 24
Peak memory 202460 kb
Host smart-b6d8b7b7-cb0c-4118-914c-bba1d29b940c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1305652923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1305652923
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.957761936
Short name T190
Test name
Test status
Simulation time 1581844591 ps
CPU time 314.68 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:30:32 PM PDT 24
Peak memory 208280 kb
Host smart-f29bb085-0704-4014-a422-d40b6a913aa8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=957761936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand
_reset.957761936
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.2274554099
Short name T855
Test name
Test status
Simulation time 146149179 ps
CPU time 19.92 seconds
Started Jul 26 04:23:29 PM PDT 24
Finished Jul 26 04:23:49 PM PDT 24
Peak memory 211476 kb
Host smart-80398182-0949-46e5-bb59-593dd6a4fe32
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2274554099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2274554099
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.698704685
Short name T166
Test name
Test status
Simulation time 476704422 ps
CPU time 28.15 seconds
Started Jul 26 04:25:19 PM PDT 24
Finished Jul 26 04:25:48 PM PDT 24
Peak memory 208712 kb
Host smart-b73c6cbb-51db-4ba2-bd8a-3540cda767d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=698704685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.698704685
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.2432818994
Short name T435
Test name
Test status
Simulation time 203097922859 ps
CPU time 671.87 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:36:29 PM PDT 24
Peak memory 211296 kb
Host smart-e6821ac6-13ea-49d5-bbca-c8250225dde4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2432818994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl
ow_rsp.2432818994
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.3346116228
Short name T895
Test name
Test status
Simulation time 257583432 ps
CPU time 14.8 seconds
Started Jul 26 04:25:39 PM PDT 24
Finished Jul 26 04:25:54 PM PDT 24
Peak memory 203040 kb
Host smart-fd7ca314-0ca6-4462-b1f2-401de9ef2751
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3346116228 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.3346116228
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.3413419639
Short name T611
Test name
Test status
Simulation time 915293739 ps
CPU time 31.24 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:25:49 PM PDT 24
Peak memory 203080 kb
Host smart-ecfe326d-8046-4d22-a8f3-faed7d8391b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3413419639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3413419639
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.4282862708
Short name T151
Test name
Test status
Simulation time 5202325992 ps
CPU time 32.72 seconds
Started Jul 26 04:26:08 PM PDT 24
Finished Jul 26 04:26:41 PM PDT 24
Peak memory 211336 kb
Host smart-6674d881-c656-4a1d-90d9-89cb05c0d1fc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4282862708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.4282862708
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.1575721748
Short name T528
Test name
Test status
Simulation time 23466518180 ps
CPU time 112.55 seconds
Started Jul 26 04:21:48 PM PDT 24
Finished Jul 26 04:23:40 PM PDT 24
Peak memory 211396 kb
Host smart-c1a3a276-77d1-44c2-ba8c-8891b57b6be5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575721748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1575721748
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1716756270
Short name T250
Test name
Test status
Simulation time 13038313965 ps
CPU time 39.15 seconds
Started Jul 26 04:25:30 PM PDT 24
Finished Jul 26 04:26:10 PM PDT 24
Peak memory 202560 kb
Host smart-9c995e8c-13d5-4c5d-9d59-88f2ec3377b4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1716756270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1716756270
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.919040613
Short name T566
Test name
Test status
Simulation time 143103957 ps
CPU time 5.89 seconds
Started Jul 26 04:23:51 PM PDT 24
Finished Jul 26 04:23:57 PM PDT 24
Peak memory 204456 kb
Host smart-6b3dc19c-6d66-4ca2-ac42-8066d62d6b5e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919040613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.919040613
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.2681418946
Short name T799
Test name
Test status
Simulation time 1028682894 ps
CPU time 19.7 seconds
Started Jul 26 04:25:30 PM PDT 24
Finished Jul 26 04:25:50 PM PDT 24
Peak memory 209720 kb
Host smart-c930c3f8-e37b-42bb-9749-e3cb52cf5009
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2681418946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2681418946
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.3706456358
Short name T347
Test name
Test status
Simulation time 130523856 ps
CPU time 2.77 seconds
Started Jul 26 04:24:52 PM PDT 24
Finished Jul 26 04:24:55 PM PDT 24
Peak memory 201912 kb
Host smart-66e739fa-b947-49fa-a486-0e846f8db0da
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3706456358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3706456358
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2021530301
Short name T812
Test name
Test status
Simulation time 11502278545 ps
CPU time 36.19 seconds
Started Jul 26 04:26:08 PM PDT 24
Finished Jul 26 04:26:45 PM PDT 24
Peak memory 203152 kb
Host smart-c0100d2a-7039-4f03-8be0-342e97b9e917
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021530301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2021530301
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.1690932298
Short name T377
Test name
Test status
Simulation time 4635436874 ps
CPU time 28.45 seconds
Started Jul 26 04:21:39 PM PDT 24
Finished Jul 26 04:22:08 PM PDT 24
Peak memory 203120 kb
Host smart-ea69a802-a7cb-4531-a148-c3dc3ad9aeb3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1690932298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1690932298
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.404678042
Short name T407
Test name
Test status
Simulation time 37953961 ps
CPU time 2.35 seconds
Started Jul 26 04:25:04 PM PDT 24
Finished Jul 26 04:25:06 PM PDT 24
Peak memory 202808 kb
Host smart-ce0bb7cc-4c89-4561-becc-98c6ab338b10
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404678042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.404678042
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.174015754
Short name T346
Test name
Test status
Simulation time 10388376496 ps
CPU time 231.33 seconds
Started Jul 26 04:25:34 PM PDT 24
Finished Jul 26 04:29:25 PM PDT 24
Peak memory 210504 kb
Host smart-f27af837-cc65-4e7c-8b4f-ba41a88ffca8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=174015754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.174015754
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.2872380832
Short name T780
Test name
Test status
Simulation time 2659278111 ps
CPU time 79.29 seconds
Started Jul 26 04:25:16 PM PDT 24
Finished Jul 26 04:26:35 PM PDT 24
Peak memory 204620 kb
Host smart-8168d1ec-d2be-4822-8ae8-751b48b5bc74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2872380832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2872380832
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.1821249762
Short name T568
Test name
Test status
Simulation time 473399779 ps
CPU time 127.72 seconds
Started Jul 26 04:21:49 PM PDT 24
Finished Jul 26 04:23:56 PM PDT 24
Peak memory 208176 kb
Host smart-04fc8f15-bbe5-4f3b-ab86-1f289dd0ecf2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1821249762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran
d_reset.1821249762
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.3273636397
Short name T195
Test name
Test status
Simulation time 462537510 ps
CPU time 173.74 seconds
Started Jul 26 04:23:22 PM PDT 24
Finished Jul 26 04:26:16 PM PDT 24
Peak memory 211464 kb
Host smart-ff080750-0aa9-4435-b16a-46540e25fb18
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3273636397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re
set_error.3273636397
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.3286478769
Short name T313
Test name
Test status
Simulation time 104576466 ps
CPU time 12.11 seconds
Started Jul 26 04:25:19 PM PDT 24
Finished Jul 26 04:25:32 PM PDT 24
Peak memory 209096 kb
Host smart-3dd978ca-d0c5-4dd6-b61e-80a485ca1300
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3286478769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3286478769
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.794318697
Short name T111
Test name
Test status
Simulation time 1378159704 ps
CPU time 28.99 seconds
Started Jul 26 04:25:38 PM PDT 24
Finished Jul 26 04:26:07 PM PDT 24
Peak memory 211224 kb
Host smart-3c42ed5d-1f12-4a60-9caa-4a10c17471ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=794318697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.794318697
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.789722927
Short name T858
Test name
Test status
Simulation time 163004362 ps
CPU time 17.37 seconds
Started Jul 26 04:25:30 PM PDT 24
Finished Jul 26 04:25:48 PM PDT 24
Peak memory 201468 kb
Host smart-cf4510fb-0dce-4443-9cf2-4a4a42d7e768
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=789722927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.789722927
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_random.3988229555
Short name T478
Test name
Test status
Simulation time 120599706 ps
CPU time 9.98 seconds
Started Jul 26 04:25:19 PM PDT 24
Finished Jul 26 04:25:29 PM PDT 24
Peak memory 203264 kb
Host smart-03f19535-5fdd-4687-a205-90474bb80304
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3988229555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3988229555
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.1916208825
Short name T709
Test name
Test status
Simulation time 4522616541 ps
CPU time 34.8 seconds
Started Jul 26 04:25:19 PM PDT 24
Finished Jul 26 04:25:55 PM PDT 24
Peak memory 209456 kb
Host smart-b9874093-0dc1-4110-a089-1170eca04ec2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1916208825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1916208825
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.1594651
Short name T681
Test name
Test status
Simulation time 71972770946 ps
CPU time 127.23 seconds
Started Jul 26 04:25:30 PM PDT 24
Finished Jul 26 04:27:38 PM PDT 24
Peak memory 202896 kb
Host smart-2114e60c-78a5-4c10-9127-6a7838aeba03
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1594651
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.958684353
Short name T58
Test name
Test status
Simulation time 115171929362 ps
CPU time 306.89 seconds
Started Jul 26 04:21:48 PM PDT 24
Finished Jul 26 04:26:55 PM PDT 24
Peak memory 211728 kb
Host smart-558b2152-529a-4415-b061-abb91b0b7059
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=958684353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.958684353
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.4176404370
Short name T156
Test name
Test status
Simulation time 165877510 ps
CPU time 18.27 seconds
Started Jul 26 04:25:16 PM PDT 24
Finished Jul 26 04:25:34 PM PDT 24
Peak memory 211188 kb
Host smart-46d1c47c-cf7c-4c13-beeb-59fc941c3ff8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176404370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.4176404370
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.2986304440
Short name T326
Test name
Test status
Simulation time 372623058 ps
CPU time 6.29 seconds
Started Jul 26 04:25:19 PM PDT 24
Finished Jul 26 04:25:26 PM PDT 24
Peak memory 201364 kb
Host smart-6e14b11e-f5f3-4ca3-9449-9a291b27e780
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2986304440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2986304440
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.2550856472
Short name T629
Test name
Test status
Simulation time 39830039 ps
CPU time 2.47 seconds
Started Jul 26 04:21:45 PM PDT 24
Finished Jul 26 04:21:48 PM PDT 24
Peak memory 203332 kb
Host smart-1b5e1924-d7fe-41db-8a4f-a01e39b606a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2550856472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2550856472
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3519377678
Short name T131
Test name
Test status
Simulation time 10159097159 ps
CPU time 30.07 seconds
Started Jul 26 04:21:49 PM PDT 24
Finished Jul 26 04:22:19 PM PDT 24
Peak memory 203372 kb
Host smart-1da0085a-16b6-4810-b2f1-f20df3ef8af7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519377678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3519377678
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2943910522
Short name T380
Test name
Test status
Simulation time 14857267366 ps
CPU time 47.65 seconds
Started Jul 26 04:25:30 PM PDT 24
Finished Jul 26 04:26:18 PM PDT 24
Peak memory 201688 kb
Host smart-718ca7b7-32a2-4a56-93d6-ac6152c538ec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2943910522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2943910522
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2607174685
Short name T625
Test name
Test status
Simulation time 30685873 ps
CPU time 2.21 seconds
Started Jul 26 04:24:52 PM PDT 24
Finished Jul 26 04:24:54 PM PDT 24
Peak memory 201924 kb
Host smart-7ba19ab5-5cec-4f03-b6b3-e9d2e30245c1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607174685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2607174685
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.3583815660
Short name T496
Test name
Test status
Simulation time 624547437 ps
CPU time 65.37 seconds
Started Jul 26 04:21:47 PM PDT 24
Finished Jul 26 04:22:52 PM PDT 24
Peak memory 205504 kb
Host smart-7e331aa1-b749-4220-b6ac-e26b8c7e9145
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3583815660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3583815660
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.873260320
Short name T730
Test name
Test status
Simulation time 19443740727 ps
CPU time 116.32 seconds
Started Jul 26 04:24:03 PM PDT 24
Finished Jul 26 04:26:00 PM PDT 24
Peak memory 206432 kb
Host smart-b70620d1-2374-4aac-bc04-35124c0895d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=873260320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.873260320
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.1653183069
Short name T592
Test name
Test status
Simulation time 13680894613 ps
CPU time 294.13 seconds
Started Jul 26 04:25:13 PM PDT 24
Finished Jul 26 04:30:07 PM PDT 24
Peak memory 219516 kb
Host smart-018c9588-8e26-4a7b-aa19-bc4a292b5769
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1653183069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re
set_error.1653183069
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.310760565
Short name T345
Test name
Test status
Simulation time 791222678 ps
CPU time 20.41 seconds
Started Jul 26 04:25:20 PM PDT 24
Finished Jul 26 04:25:41 PM PDT 24
Peak memory 211136 kb
Host smart-686f1469-e4bf-4d71-816a-9e5716e27b65
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=310760565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.310760565
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.413044217
Short name T364
Test name
Test status
Simulation time 505549109 ps
CPU time 20.13 seconds
Started Jul 26 04:25:34 PM PDT 24
Finished Jul 26 04:25:54 PM PDT 24
Peak memory 211344 kb
Host smart-390ea65b-60b4-4bd5-ae40-8589159d3cfc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=413044217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.413044217
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3758344706
Short name T124
Test name
Test status
Simulation time 43581778974 ps
CPU time 293.65 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:30:11 PM PDT 24
Peak memory 211520 kb
Host smart-01828cfd-004b-4e6e-9351-2a377b3627f3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3758344706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl
ow_rsp.3758344706
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.4144478626
Short name T198
Test name
Test status
Simulation time 15613322 ps
CPU time 1.84 seconds
Started Jul 26 04:25:14 PM PDT 24
Finished Jul 26 04:25:16 PM PDT 24
Peak memory 202368 kb
Host smart-c02059bf-412b-419f-9a98-78fa7638723a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4144478626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.4144478626
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.1005392464
Short name T553
Test name
Test status
Simulation time 174275579 ps
CPU time 5.57 seconds
Started Jul 26 04:25:20 PM PDT 24
Finished Jul 26 04:25:26 PM PDT 24
Peak memory 202968 kb
Host smart-dee07e0a-e85a-4850-8443-9a56138edd9e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1005392464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1005392464
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.3902732403
Short name T189
Test name
Test status
Simulation time 355315150 ps
CPU time 9.89 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:25:27 PM PDT 24
Peak memory 211468 kb
Host smart-631d7811-50d3-4e60-a79b-e2acb0acd92b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3902732403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.3902732403
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.108451920
Short name T863
Test name
Test status
Simulation time 7458198478 ps
CPU time 37.59 seconds
Started Jul 26 04:25:14 PM PDT 24
Finished Jul 26 04:25:52 PM PDT 24
Peak memory 204332 kb
Host smart-d2ef8ab1-c9d1-4103-9de2-79082d46574d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=108451920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.108451920
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2600832011
Short name T547
Test name
Test status
Simulation time 58886688261 ps
CPU time 245.73 seconds
Started Jul 26 04:25:30 PM PDT 24
Finished Jul 26 04:29:35 PM PDT 24
Peak memory 211528 kb
Host smart-21b30976-0f0a-4d7c-8e16-66b2bd2a8b50
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2600832011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2600832011
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.164130584
Short name T315
Test name
Test status
Simulation time 154308310 ps
CPU time 18.51 seconds
Started Jul 26 04:21:57 PM PDT 24
Finished Jul 26 04:22:15 PM PDT 24
Peak memory 204736 kb
Host smart-16d02344-3fe9-4643-bb41-e90fe1c967ff
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164130584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.164130584
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.2120490498
Short name T291
Test name
Test status
Simulation time 487650980 ps
CPU time 9.08 seconds
Started Jul 26 04:21:55 PM PDT 24
Finished Jul 26 04:22:04 PM PDT 24
Peak memory 203312 kb
Host smart-52e14cf7-bbae-4c48-a1eb-9aa7aaf4e5f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2120490498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2120490498
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.215039136
Short name T51
Test name
Test status
Simulation time 168562033 ps
CPU time 3.08 seconds
Started Jul 26 04:25:04 PM PDT 24
Finished Jul 26 04:25:07 PM PDT 24
Peak memory 203012 kb
Host smart-e5d2149a-aede-4c1b-8c0a-b9800900892f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=215039136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.215039136
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.711024969
Short name T196
Test name
Test status
Simulation time 7106626971 ps
CPU time 26 seconds
Started Jul 26 04:25:33 PM PDT 24
Finished Jul 26 04:25:59 PM PDT 24
Peak memory 203212 kb
Host smart-4dc9eb41-3330-4c1d-a2c0-6d6389ccfba5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=711024969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.711024969
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3623149990
Short name T690
Test name
Test status
Simulation time 4807488035 ps
CPU time 24.8 seconds
Started Jul 26 04:22:38 PM PDT 24
Finished Jul 26 04:23:03 PM PDT 24
Peak memory 203384 kb
Host smart-3872e2e3-5bab-46cf-8b38-e081ceadbc94
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3623149990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3623149990
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3441182807
Short name T601
Test name
Test status
Simulation time 31815385 ps
CPU time 2.06 seconds
Started Jul 26 04:25:14 PM PDT 24
Finished Jul 26 04:25:16 PM PDT 24
Peak memory 202500 kb
Host smart-da4d23f5-9d51-4a73-a002-d7ce8543f569
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441182807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3441182807
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.3310123545
Short name T191
Test name
Test status
Simulation time 800531800 ps
CPU time 55.02 seconds
Started Jul 26 04:25:04 PM PDT 24
Finished Jul 26 04:25:59 PM PDT 24
Peak memory 206816 kb
Host smart-fc2de1eb-f365-4f31-84e0-461e395cc2b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3310123545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3310123545
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.1667849153
Short name T789
Test name
Test status
Simulation time 5078467936 ps
CPU time 88.33 seconds
Started Jul 26 04:25:03 PM PDT 24
Finished Jul 26 04:26:32 PM PDT 24
Peak memory 210372 kb
Host smart-713a2542-054d-45d3-b951-3c8335759e8d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1667849153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1667849153
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.2604877248
Short name T293
Test name
Test status
Simulation time 11543535898 ps
CPU time 542.22 seconds
Started Jul 26 04:25:18 PM PDT 24
Finished Jul 26 04:34:21 PM PDT 24
Peak memory 221916 kb
Host smart-55fe0ad9-db7d-4985-ab6d-fd630b52aa7a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2604877248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran
d_reset.2604877248
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.471137336
Short name T146
Test name
Test status
Simulation time 592426571 ps
CPU time 152.68 seconds
Started Jul 26 04:21:56 PM PDT 24
Finished Jul 26 04:24:29 PM PDT 24
Peak memory 211020 kb
Host smart-a15ee298-eaaf-4f12-8a91-4746f6ffaadd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=471137336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_res
et_error.471137336
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.2036440882
Short name T717
Test name
Test status
Simulation time 1335204217 ps
CPU time 19.53 seconds
Started Jul 26 04:23:02 PM PDT 24
Finished Jul 26 04:23:22 PM PDT 24
Peak memory 211456 kb
Host smart-256d3d5b-2574-4cd4-ae8a-a7cccc17e080
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2036440882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2036440882
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1602120669
Short name T121
Test name
Test status
Simulation time 2043463899 ps
CPU time 53.53 seconds
Started Jul 26 04:22:07 PM PDT 24
Finished Jul 26 04:23:01 PM PDT 24
Peak memory 205244 kb
Host smart-87d6574a-eec4-42e0-b7d2-700c24725744
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1602120669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1602120669
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.50749374
Short name T573
Test name
Test status
Simulation time 241762173942 ps
CPU time 448.1 seconds
Started Jul 26 04:25:11 PM PDT 24
Finished Jul 26 04:32:40 PM PDT 24
Peak memory 209328 kb
Host smart-51788b06-dc25-44a9-8112-4673c931e6ed
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=50749374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow
_rsp.50749374
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.1201371435
Short name T585
Test name
Test status
Simulation time 122505854 ps
CPU time 3.15 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:25:21 PM PDT 24
Peak memory 203100 kb
Host smart-97ccab79-4524-46da-88b6-80e8152288f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1201371435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.1201371435
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.831570972
Short name T482
Test name
Test status
Simulation time 317425095 ps
CPU time 7.89 seconds
Started Jul 26 04:22:35 PM PDT 24
Finished Jul 26 04:22:43 PM PDT 24
Peak memory 203284 kb
Host smart-20f44df7-41bd-49a0-ba43-3c3a447ac61b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=831570972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.831570972
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.1646314247
Short name T228
Test name
Test status
Simulation time 5377769023 ps
CPU time 34.73 seconds
Started Jul 26 04:22:59 PM PDT 24
Finished Jul 26 04:23:34 PM PDT 24
Peak memory 204544 kb
Host smart-428b9c94-4443-4f03-bfaa-0089b791dc65
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1646314247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.1646314247
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.1956339661
Short name T569
Test name
Test status
Simulation time 21949627107 ps
CPU time 115.11 seconds
Started Jul 26 04:25:04 PM PDT 24
Finished Jul 26 04:26:59 PM PDT 24
Peak memory 204124 kb
Host smart-17b9f55f-9c22-46d0-ad14-a0b6d4e44228
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956339661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1956339661
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.153280736
Short name T207
Test name
Test status
Simulation time 5960195742 ps
CPU time 21.1 seconds
Started Jul 26 04:24:00 PM PDT 24
Finished Jul 26 04:24:21 PM PDT 24
Peak memory 203384 kb
Host smart-5c02ae0c-364d-45b9-818f-e97ecf1828ab
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=153280736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.153280736
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.3390547399
Short name T563
Test name
Test status
Simulation time 104593787 ps
CPU time 13.33 seconds
Started Jul 26 04:25:30 PM PDT 24
Finished Jul 26 04:25:43 PM PDT 24
Peak memory 211468 kb
Host smart-5964a38b-aae6-463e-9b7c-77c4fd6009fc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390547399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3390547399
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.2563915877
Short name T371
Test name
Test status
Simulation time 50247758 ps
CPU time 4.08 seconds
Started Jul 26 04:25:11 PM PDT 24
Finished Jul 26 04:25:16 PM PDT 24
Peak memory 201068 kb
Host smart-328d11cc-5a5c-4248-9049-3c14e1499eaf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2563915877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2563915877
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.3063674568
Short name T378
Test name
Test status
Simulation time 35247551 ps
CPU time 2.21 seconds
Started Jul 26 04:25:19 PM PDT 24
Finished Jul 26 04:25:22 PM PDT 24
Peak memory 201124 kb
Host smart-72a47633-f330-4f4d-9f55-328a8bbe477e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3063674568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3063674568
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.2634054626
Short name T224
Test name
Test status
Simulation time 19234998851 ps
CPU time 37.15 seconds
Started Jul 26 04:23:33 PM PDT 24
Finished Jul 26 04:24:11 PM PDT 24
Peak memory 203380 kb
Host smart-6984bfd5-7d2b-4d2e-8aaf-d64869553754
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634054626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2634054626
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.543018850
Short name T579
Test name
Test status
Simulation time 10231342064 ps
CPU time 29.86 seconds
Started Jul 26 04:21:57 PM PDT 24
Finished Jul 26 04:22:27 PM PDT 24
Peak memory 203396 kb
Host smart-cc39ce1e-a5eb-44fb-a787-0466ec3caf0d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=543018850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.543018850
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.617847670
Short name T560
Test name
Test status
Simulation time 147945741 ps
CPU time 2.56 seconds
Started Jul 26 04:22:47 PM PDT 24
Finished Jul 26 04:22:50 PM PDT 24
Peak memory 203260 kb
Host smart-b5925135-d2dc-4a62-9e71-2b4f5e73be16
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617847670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.617847670
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.1426000733
Short name T686
Test name
Test status
Simulation time 1541291675 ps
CPU time 160.14 seconds
Started Jul 26 04:22:06 PM PDT 24
Finished Jul 26 04:24:46 PM PDT 24
Peak memory 206908 kb
Host smart-43d7b629-a49c-420e-86ff-d5e43ce98846
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1426000733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1426000733
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3800459553
Short name T28
Test name
Test status
Simulation time 1318599399 ps
CPU time 19.88 seconds
Started Jul 26 04:24:29 PM PDT 24
Finished Jul 26 04:24:49 PM PDT 24
Peak memory 203864 kb
Host smart-d4f79284-d005-43a9-9976-37b15a4f0632
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3800459553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3800459553
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.1240564211
Short name T728
Test name
Test status
Simulation time 4673810752 ps
CPU time 330.66 seconds
Started Jul 26 04:23:16 PM PDT 24
Finished Jul 26 04:28:47 PM PDT 24
Peak memory 211688 kb
Host smart-cd5a0a41-2652-4410-9cf3-fc376767c1bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1240564211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran
d_reset.1240564211
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.1504688710
Short name T891
Test name
Test status
Simulation time 531501721 ps
CPU time 98.68 seconds
Started Jul 26 04:22:11 PM PDT 24
Finished Jul 26 04:23:50 PM PDT 24
Peak memory 209384 kb
Host smart-389c8b2f-b86e-4a92-aa4a-5445da27cda4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1504688710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re
set_error.1504688710
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.4111146642
Short name T270
Test name
Test status
Simulation time 642755601 ps
CPU time 26.07 seconds
Started Jul 26 04:25:11 PM PDT 24
Finished Jul 26 04:25:38 PM PDT 24
Peak memory 203680 kb
Host smart-addc0bf7-9785-4788-89b2-e27143df0bee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4111146642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.4111146642
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.3193539692
Short name T77
Test name
Test status
Simulation time 2824806879 ps
CPU time 51.08 seconds
Started Jul 26 04:24:28 PM PDT 24
Finished Jul 26 04:25:20 PM PDT 24
Peak memory 211200 kb
Host smart-46b3fd9f-c406-47e2-ba38-97b2bfedb013
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3193539692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.3193539692
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.658192989
Short name T91
Test name
Test status
Simulation time 15110874203 ps
CPU time 92.66 seconds
Started Jul 26 04:22:15 PM PDT 24
Finished Jul 26 04:23:48 PM PDT 24
Peak memory 204884 kb
Host smart-cb86df02-2ff6-4acb-b131-cc2e6228ec7f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=658192989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slo
w_rsp.658192989
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.3454863725
Short name T513
Test name
Test status
Simulation time 523187370 ps
CPU time 5.02 seconds
Started Jul 26 04:22:19 PM PDT 24
Finished Jul 26 04:22:24 PM PDT 24
Peak memory 203468 kb
Host smart-c4226c1b-187e-43a5-9c9b-5e04f1b55ca2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3454863725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3454863725
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.519418511
Short name T331
Test name
Test status
Simulation time 896071018 ps
CPU time 14.36 seconds
Started Jul 26 04:24:27 PM PDT 24
Finished Jul 26 04:24:42 PM PDT 24
Peak memory 201044 kb
Host smart-eb9374ff-e9ec-4ef2-9fcc-9ac36b7e661c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=519418511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.519418511
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.627801746
Short name T181
Test name
Test status
Simulation time 181227464 ps
CPU time 23.53 seconds
Started Jul 26 04:25:27 PM PDT 24
Finished Jul 26 04:25:50 PM PDT 24
Peak memory 204360 kb
Host smart-0f88b5bc-84de-479d-a4d1-7f1ddb7705e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=627801746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.627801746
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.1085369904
Short name T260
Test name
Test status
Simulation time 30330612018 ps
CPU time 166.14 seconds
Started Jul 26 04:25:11 PM PDT 24
Finished Jul 26 04:27:58 PM PDT 24
Peak memory 209888 kb
Host smart-1883cf7b-9648-4750-a29b-8481603f077a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085369904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1085369904
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.2013779906
Short name T383
Test name
Test status
Simulation time 47084200901 ps
CPU time 90.82 seconds
Started Jul 26 04:25:12 PM PDT 24
Finished Jul 26 04:26:43 PM PDT 24
Peak memory 204336 kb
Host smart-ee29018c-1d7d-4f26-8653-bd10a26780d5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2013779906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2013779906
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.2769888239
Short name T392
Test name
Test status
Simulation time 496806900 ps
CPU time 28.8 seconds
Started Jul 26 04:23:59 PM PDT 24
Finished Jul 26 04:24:28 PM PDT 24
Peak memory 211520 kb
Host smart-62e58116-4259-478f-9a13-357884ed1a1c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769888239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.2769888239
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.3916162650
Short name T154
Test name
Test status
Simulation time 326035936 ps
CPU time 20.22 seconds
Started Jul 26 04:24:27 PM PDT 24
Finished Jul 26 04:24:48 PM PDT 24
Peak memory 201772 kb
Host smart-b66c1151-f19d-4838-ab50-082ffee93fa5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3916162650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3916162650
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.1331170762
Short name T149
Test name
Test status
Simulation time 32452034 ps
CPU time 2.19 seconds
Started Jul 26 04:25:12 PM PDT 24
Finished Jul 26 04:25:14 PM PDT 24
Peak memory 202964 kb
Host smart-ede60f11-2498-4725-94ae-2c73f0da1ba3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1331170762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1331170762
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.2012761655
Short name T267
Test name
Test status
Simulation time 9702435847 ps
CPU time 32.25 seconds
Started Jul 26 04:25:19 PM PDT 24
Finished Jul 26 04:25:51 PM PDT 24
Peak memory 203148 kb
Host smart-6425aade-8517-4cc0-b654-3b0752c4a78e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012761655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2012761655
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.3243899464
Short name T497
Test name
Test status
Simulation time 36146526491 ps
CPU time 68.76 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:26:26 PM PDT 24
Peak memory 203136 kb
Host smart-8a254958-2524-447d-a5ad-6c48b83d1154
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3243899464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3243899464
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3312558847
Short name T755
Test name
Test status
Simulation time 34686488 ps
CPU time 1.95 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:25:20 PM PDT 24
Peak memory 203036 kb
Host smart-d37ad466-cba4-4a0f-a7b5-323a1db23d1f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312558847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3312558847
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.1155839863
Short name T365
Test name
Test status
Simulation time 657088691 ps
CPU time 50.78 seconds
Started Jul 26 04:24:27 PM PDT 24
Finished Jul 26 04:25:19 PM PDT 24
Peak memory 204208 kb
Host smart-5e571826-a20f-4dde-ae11-7642821e2178
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1155839863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1155839863
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.2922293033
Short name T294
Test name
Test status
Simulation time 6133634317 ps
CPU time 141.15 seconds
Started Jul 26 04:25:11 PM PDT 24
Finished Jul 26 04:27:33 PM PDT 24
Peak memory 204588 kb
Host smart-edb4723f-0f10-4428-bb8c-c27ef5ec57bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2922293033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2922293033
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.717014369
Short name T281
Test name
Test status
Simulation time 3051523103 ps
CPU time 139.67 seconds
Started Jul 26 04:24:27 PM PDT 24
Finished Jul 26 04:26:47 PM PDT 24
Peak memory 206444 kb
Host smart-121ad0c7-61ca-42a4-b592-6ff85da0e848
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=717014369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand
_reset.717014369
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.2300106805
Short name T803
Test name
Test status
Simulation time 4968314215 ps
CPU time 207.79 seconds
Started Jul 26 04:25:11 PM PDT 24
Finished Jul 26 04:28:39 PM PDT 24
Peak memory 217532 kb
Host smart-79dd987c-fda7-4703-94fc-24c02555168e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2300106805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re
set_error.2300106805
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.417203458
Short name T125
Test name
Test status
Simulation time 793992580 ps
CPU time 18.82 seconds
Started Jul 26 04:24:40 PM PDT 24
Finished Jul 26 04:24:59 PM PDT 24
Peak memory 211364 kb
Host smart-17dcdcee-804f-4b88-949f-9a208d8028d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=417203458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.417203458
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.2804747836
Short name T467
Test name
Test status
Simulation time 17810372 ps
CPU time 2.87 seconds
Started Jul 26 04:19:42 PM PDT 24
Finished Jul 26 04:19:45 PM PDT 24
Peak memory 203668 kb
Host smart-28f69ac5-c87a-4515-b666-9b9c89510ba2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2804747836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2804747836
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.2890899475
Short name T300
Test name
Test status
Simulation time 103266110306 ps
CPU time 232.45 seconds
Started Jul 26 04:19:52 PM PDT 24
Finished Jul 26 04:23:45 PM PDT 24
Peak memory 206008 kb
Host smart-28771873-b947-4aea-b6d7-056d034f0f96
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2890899475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo
w_rsp.2890899475
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.1873842582
Short name T672
Test name
Test status
Simulation time 2096067830 ps
CPU time 26.35 seconds
Started Jul 26 04:19:52 PM PDT 24
Finished Jul 26 04:20:19 PM PDT 24
Peak memory 203436 kb
Host smart-7d94e5f3-4bd7-4f92-afc4-5cfdc41dec20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1873842582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.1873842582
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.406052046
Short name T525
Test name
Test status
Simulation time 187734081 ps
CPU time 8.61 seconds
Started Jul 26 04:19:55 PM PDT 24
Finished Jul 26 04:20:04 PM PDT 24
Peak memory 203708 kb
Host smart-2f346b0c-ef87-415d-a049-450a267fd5d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=406052046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.406052046
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.189534993
Short name T391
Test name
Test status
Simulation time 123136914 ps
CPU time 8.86 seconds
Started Jul 26 04:19:52 PM PDT 24
Finished Jul 26 04:20:01 PM PDT 24
Peak memory 210484 kb
Host smart-1fd422a2-4d7c-41b7-bf74-96f834a1ee61
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=189534993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.189534993
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.3068232723
Short name T508
Test name
Test status
Simulation time 49526371743 ps
CPU time 187.45 seconds
Started Jul 26 04:19:42 PM PDT 24
Finished Jul 26 04:22:50 PM PDT 24
Peak memory 204088 kb
Host smart-80262af4-9e91-4a4d-b62b-9fd7f541f736
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068232723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3068232723
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.1309811339
Short name T691
Test name
Test status
Simulation time 1885538160 ps
CPU time 8.24 seconds
Started Jul 26 04:19:53 PM PDT 24
Finished Jul 26 04:20:02 PM PDT 24
Peak memory 203356 kb
Host smart-9b244e7c-c51d-4984-b98f-594e4351c5b4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1309811339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1309811339
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.2307253196
Short name T561
Test name
Test status
Simulation time 352531886 ps
CPU time 24.26 seconds
Started Jul 26 04:19:42 PM PDT 24
Finished Jul 26 04:20:06 PM PDT 24
Peak memory 211840 kb
Host smart-9b4a3cd4-6d04-4afa-b90f-595613d3e408
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307253196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.2307253196
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.916202184
Short name T174
Test name
Test status
Simulation time 462791917 ps
CPU time 4.58 seconds
Started Jul 26 04:19:53 PM PDT 24
Finished Jul 26 04:19:58 PM PDT 24
Peak memory 202552 kb
Host smart-c21bbb78-624e-497d-96bb-9289162167f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=916202184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.916202184
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.3611190505
Short name T627
Test name
Test status
Simulation time 73328398 ps
CPU time 1.9 seconds
Started Jul 26 04:19:45 PM PDT 24
Finished Jul 26 04:19:47 PM PDT 24
Peak memory 203280 kb
Host smart-dca1e9f0-8890-4e20-8304-d8d9da9b9bed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3611190505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3611190505
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.2189870097
Short name T498
Test name
Test status
Simulation time 24841957101 ps
CPU time 36.42 seconds
Started Jul 26 04:20:54 PM PDT 24
Finished Jul 26 04:21:31 PM PDT 24
Peak memory 202972 kb
Host smart-86913167-bd5d-4d15-aae1-88dcff61a0db
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189870097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2189870097
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.3088990506
Short name T718
Test name
Test status
Simulation time 4252413572 ps
CPU time 24.97 seconds
Started Jul 26 04:19:52 PM PDT 24
Finished Jul 26 04:20:17 PM PDT 24
Peak memory 203480 kb
Host smart-b5fdd684-f7f4-47e5-9d64-93b94b3b3dad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3088990506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3088990506
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.856336702
Short name T716
Test name
Test status
Simulation time 64014181 ps
CPU time 2.3 seconds
Started Jul 26 04:19:52 PM PDT 24
Finished Jul 26 04:19:55 PM PDT 24
Peak memory 203420 kb
Host smart-48ada5b1-77c5-4b96-9b44-b7fae0703244
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856336702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.856336702
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.4175210174
Short name T185
Test name
Test status
Simulation time 9482332354 ps
CPU time 199.62 seconds
Started Jul 26 04:19:54 PM PDT 24
Finished Jul 26 04:23:14 PM PDT 24
Peak memory 210792 kb
Host smart-edc15f69-c2fd-4675-bfca-8c25a8a67d7d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4175210174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.4175210174
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.1002650420
Short name T722
Test name
Test status
Simulation time 5114527452 ps
CPU time 105.56 seconds
Started Jul 26 04:24:27 PM PDT 24
Finished Jul 26 04:26:13 PM PDT 24
Peak memory 205316 kb
Host smart-e4ab05ea-2334-4b58-8f2c-badf938163b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1002650420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1002650420
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1962647973
Short name T616
Test name
Test status
Simulation time 3763767984 ps
CPU time 203.82 seconds
Started Jul 26 04:20:22 PM PDT 24
Finished Jul 26 04:23:46 PM PDT 24
Peak memory 208060 kb
Host smart-aeca5b33-90e8-4b9f-aa9f-e1f8c9639db8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1962647973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand
_reset.1962647973
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.4157209437
Short name T887
Test name
Test status
Simulation time 361895634 ps
CPU time 92.55 seconds
Started Jul 26 04:21:41 PM PDT 24
Finished Jul 26 04:23:14 PM PDT 24
Peak memory 209144 kb
Host smart-68c6f9cc-ebe2-4075-8a0d-1cbddc93315f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4157209437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res
et_error.4157209437
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.1952835937
Short name T668
Test name
Test status
Simulation time 130596678 ps
CPU time 10.38 seconds
Started Jul 26 04:19:54 PM PDT 24
Finished Jul 26 04:20:05 PM PDT 24
Peak memory 211172 kb
Host smart-cc33d931-3b22-462c-8a2a-272f12a173f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1952835937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1952835937
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.1766081558
Short name T581
Test name
Test status
Simulation time 1190067909 ps
CPU time 38.53 seconds
Started Jul 26 04:24:42 PM PDT 24
Finished Jul 26 04:25:20 PM PDT 24
Peak memory 211508 kb
Host smart-0cc434f7-1ec3-44a9-935c-ba1242276500
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1766081558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.1766081558
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3402564266
Short name T688
Test name
Test status
Simulation time 30195576174 ps
CPU time 258.56 seconds
Started Jul 26 04:24:41 PM PDT 24
Finished Jul 26 04:29:00 PM PDT 24
Peak memory 211548 kb
Host smart-d695ce0a-0a83-4357-98f6-f42f96b09ee7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3402564266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl
ow_rsp.3402564266
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1934015711
Short name T283
Test name
Test status
Simulation time 43997203 ps
CPU time 6.37 seconds
Started Jul 26 04:24:41 PM PDT 24
Finished Jul 26 04:24:48 PM PDT 24
Peak memory 203324 kb
Host smart-918d5660-9e13-48dc-b738-f5c93cc7f5ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1934015711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1934015711
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.3907325412
Short name T697
Test name
Test status
Simulation time 885687958 ps
CPU time 20.59 seconds
Started Jul 26 04:24:41 PM PDT 24
Finished Jul 26 04:25:02 PM PDT 24
Peak memory 203376 kb
Host smart-159033f0-49bf-4864-963f-70773af94177
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3907325412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3907325412
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.1983675181
Short name T689
Test name
Test status
Simulation time 257304537 ps
CPU time 21.5 seconds
Started Jul 26 04:22:24 PM PDT 24
Finished Jul 26 04:22:46 PM PDT 24
Peak memory 211472 kb
Host smart-9135b051-65fb-483f-862b-46d491f66ed9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1983675181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.1983675181
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.3581450078
Short name T60
Test name
Test status
Simulation time 39912265082 ps
CPU time 168.48 seconds
Started Jul 26 04:24:41 PM PDT 24
Finished Jul 26 04:27:29 PM PDT 24
Peak memory 204492 kb
Host smart-105932a2-3a3a-4286-9fa6-2c4f200795f7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581450078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3581450078
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.4034363598
Short name T80
Test name
Test status
Simulation time 37577243988 ps
CPU time 187.69 seconds
Started Jul 26 04:24:41 PM PDT 24
Finished Jul 26 04:27:49 PM PDT 24
Peak memory 211576 kb
Host smart-bad17e96-d5dd-4874-9ebb-3204be087073
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4034363598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.4034363598
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.2966538726
Short name T438
Test name
Test status
Simulation time 208101301 ps
CPU time 25 seconds
Started Jul 26 04:24:42 PM PDT 24
Finished Jul 26 04:25:07 PM PDT 24
Peak memory 211492 kb
Host smart-0a59df51-a848-44a6-975f-e6673483e241
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966538726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2966538726
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.922297667
Short name T854
Test name
Test status
Simulation time 70206910 ps
CPU time 3.69 seconds
Started Jul 26 04:24:41 PM PDT 24
Finished Jul 26 04:24:45 PM PDT 24
Peak memory 203272 kb
Host smart-32ad7677-c5a4-4c4d-a73c-bd4258405eaa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=922297667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.922297667
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.2853971210
Short name T183
Test name
Test status
Simulation time 200337021 ps
CPU time 3.36 seconds
Started Jul 26 04:24:28 PM PDT 24
Finished Jul 26 04:24:32 PM PDT 24
Peak memory 202968 kb
Host smart-ca685a1d-dc57-4cb3-becd-813bf3dc99ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2853971210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2853971210
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.2418363075
Short name T576
Test name
Test status
Simulation time 5725026389 ps
CPU time 34.18 seconds
Started Jul 26 04:24:42 PM PDT 24
Finished Jul 26 04:25:16 PM PDT 24
Peak memory 203372 kb
Host smart-8f6ce047-3ab9-4bcb-8f45-860b8433c0c9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418363075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2418363075
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.232154533
Short name T204
Test name
Test status
Simulation time 6815698364 ps
CPU time 32.35 seconds
Started Jul 26 04:24:42 PM PDT 24
Finished Jul 26 04:25:14 PM PDT 24
Peak memory 203384 kb
Host smart-54ce3218-9ff6-4c92-9b93-8f3305f733e9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=232154533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.232154533
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.3418587750
Short name T591
Test name
Test status
Simulation time 160142270 ps
CPU time 2.34 seconds
Started Jul 26 04:23:19 PM PDT 24
Finished Jul 26 04:23:21 PM PDT 24
Peak memory 203264 kb
Host smart-71b1b57e-6a33-439c-b3b8-c3877eebb2eb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418587750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3418587750
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.3720492516
Short name T873
Test name
Test status
Simulation time 1907611312 ps
CPU time 138.15 seconds
Started Jul 26 04:24:42 PM PDT 24
Finished Jul 26 04:27:00 PM PDT 24
Peak memory 208364 kb
Host smart-a4652ad0-73ac-4d22-99e4-e71107836e15
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3720492516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3720492516
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.1357046558
Short name T410
Test name
Test status
Simulation time 25159371990 ps
CPU time 164.09 seconds
Started Jul 26 04:24:43 PM PDT 24
Finished Jul 26 04:27:27 PM PDT 24
Peak memory 205728 kb
Host smart-4285aca6-8581-4530-82b1-c0795431c3ca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1357046558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1357046558
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.160956415
Short name T888
Test name
Test status
Simulation time 3466357219 ps
CPU time 213.33 seconds
Started Jul 26 04:24:40 PM PDT 24
Finished Jul 26 04:28:13 PM PDT 24
Peak memory 209024 kb
Host smart-c30db6c0-adbb-4550-a8a3-d831aa8dbec4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=160956415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand
_reset.160956415
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.2258585485
Short name T5
Test name
Test status
Simulation time 3811412549 ps
CPU time 169.96 seconds
Started Jul 26 04:22:36 PM PDT 24
Finished Jul 26 04:25:26 PM PDT 24
Peak memory 210460 kb
Host smart-a38309cd-747f-4a87-b2e3-1a4a08de88d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2258585485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re
set_error.2258585485
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.1794586044
Short name T778
Test name
Test status
Simulation time 29910851 ps
CPU time 2.52 seconds
Started Jul 26 04:22:32 PM PDT 24
Finished Jul 26 04:22:35 PM PDT 24
Peak memory 211460 kb
Host smart-2962b9d8-3f59-4616-b110-776c5298dece
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1794586044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1794586044
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.2428061053
Short name T868
Test name
Test status
Simulation time 1674748069 ps
CPU time 26.97 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:25:43 PM PDT 24
Peak memory 211284 kb
Host smart-1d43005d-d8fb-491e-8988-93cb7db564de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2428061053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.2428061053
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1878580311
Short name T139
Test name
Test status
Simulation time 25760896348 ps
CPU time 82.95 seconds
Started Jul 26 04:24:43 PM PDT 24
Finished Jul 26 04:26:06 PM PDT 24
Peak memory 211568 kb
Host smart-d10c4042-4733-4435-9787-ec3e8917e0b6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1878580311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl
ow_rsp.1878580311
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2537190564
Short name T646
Test name
Test status
Simulation time 87971793 ps
CPU time 3.56 seconds
Started Jul 26 04:24:40 PM PDT 24
Finished Jul 26 04:24:44 PM PDT 24
Peak memory 203072 kb
Host smart-91e2b87d-cbc9-4d12-aa8a-6b29cdbf09f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2537190564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.2537190564
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.3457635716
Short name T864
Test name
Test status
Simulation time 550227636 ps
CPU time 16.43 seconds
Started Jul 26 04:22:47 PM PDT 24
Finished Jul 26 04:23:03 PM PDT 24
Peak memory 203296 kb
Host smart-15fa8c94-30e7-4487-a47c-6c98a0425311
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3457635716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3457635716
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.3958746219
Short name T427
Test name
Test status
Simulation time 313082409 ps
CPU time 10.93 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:25:27 PM PDT 24
Peak memory 204208 kb
Host smart-6aaa0106-1d01-446c-8a1b-3c3e7bbe4ca4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3958746219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.3958746219
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.378827167
Short name T788
Test name
Test status
Simulation time 112334473301 ps
CPU time 143.04 seconds
Started Jul 26 04:22:38 PM PDT 24
Finished Jul 26 04:25:01 PM PDT 24
Peak memory 204536 kb
Host smart-1a61b3d2-ddf3-4c13-a7e5-bd79e704c77a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=378827167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.378827167
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.338918884
Short name T649
Test name
Test status
Simulation time 35728475933 ps
CPU time 164.28 seconds
Started Jul 26 04:24:41 PM PDT 24
Finished Jul 26 04:27:25 PM PDT 24
Peak memory 211556 kb
Host smart-223ca47a-2b0d-4eda-bbf5-b9a6199c3045
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=338918884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.338918884
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.318517139
Short name T494
Test name
Test status
Simulation time 379944021 ps
CPU time 14.56 seconds
Started Jul 26 04:24:27 PM PDT 24
Finished Jul 26 04:24:41 PM PDT 24
Peak memory 203788 kb
Host smart-8925910c-3588-41db-9b13-16a229728c32
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318517139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.318517139
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.3776536772
Short name T557
Test name
Test status
Simulation time 124044979 ps
CPU time 2.79 seconds
Started Jul 26 04:24:40 PM PDT 24
Finished Jul 26 04:24:43 PM PDT 24
Peak memory 203392 kb
Host smart-f4b07ad4-3152-4c24-b461-fec253974a99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3776536772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3776536772
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.3345654509
Short name T522
Test name
Test status
Simulation time 38485482 ps
CPU time 1.79 seconds
Started Jul 26 04:24:40 PM PDT 24
Finished Jul 26 04:24:42 PM PDT 24
Peak memory 203308 kb
Host smart-f92cd4dd-a485-4fe4-b984-2683c16837c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3345654509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.3345654509
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.3297560302
Short name T809
Test name
Test status
Simulation time 7044176652 ps
CPU time 24.29 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:25:40 PM PDT 24
Peak memory 203148 kb
Host smart-8d688aab-f74b-4985-812c-137382fe644a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297560302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3297560302
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.1674000365
Short name T389
Test name
Test status
Simulation time 5361557876 ps
CPU time 29.78 seconds
Started Jul 26 04:22:39 PM PDT 24
Finished Jul 26 04:23:09 PM PDT 24
Peak memory 203384 kb
Host smart-6003f5a5-2bc2-40e2-8c1a-eda9a3823e32
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1674000365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.1674000365
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3840288711
Short name T712
Test name
Test status
Simulation time 56798204 ps
CPU time 2.3 seconds
Started Jul 26 04:22:36 PM PDT 24
Finished Jul 26 04:22:38 PM PDT 24
Peak memory 203260 kb
Host smart-c1f14d01-496f-46e2-a480-0ad2c3f29eb3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840288711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3840288711
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.2301069588
Short name T32
Test name
Test status
Simulation time 19968783722 ps
CPU time 174.88 seconds
Started Jul 26 04:24:43 PM PDT 24
Finished Jul 26 04:27:38 PM PDT 24
Peak memory 208328 kb
Host smart-24d53445-14b5-473a-afb6-a9304aa68966
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2301069588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.2301069588
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3504492210
Short name T217
Test name
Test status
Simulation time 2761905856 ps
CPU time 180.03 seconds
Started Jul 26 04:25:06 PM PDT 24
Finished Jul 26 04:28:06 PM PDT 24
Peak memory 206836 kb
Host smart-d9d227e2-8249-4306-8604-5a63afad8a83
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3504492210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3504492210
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.1856025304
Short name T202
Test name
Test status
Simulation time 3209721010 ps
CPU time 600.13 seconds
Started Jul 26 04:22:48 PM PDT 24
Finished Jul 26 04:32:48 PM PDT 24
Peak memory 219732 kb
Host smart-c1d70348-27e6-4845-83ac-4d646270ee74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1856025304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran
d_reset.1856025304
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.2715777120
Short name T763
Test name
Test status
Simulation time 1676218263 ps
CPU time 137.51 seconds
Started Jul 26 04:25:04 PM PDT 24
Finished Jul 26 04:27:22 PM PDT 24
Peak memory 209488 kb
Host smart-9642cb3a-db94-4306-8dd5-36fd6c9898cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2715777120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re
set_error.2715777120
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.7681852
Short name T517
Test name
Test status
Simulation time 47391103 ps
CPU time 6.66 seconds
Started Jul 26 04:22:35 PM PDT 24
Finished Jul 26 04:22:42 PM PDT 24
Peak memory 211528 kb
Host smart-5d01ce02-c143-476c-af62-c2389ed8e946
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=7681852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.7681852
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.1426238532
Short name T384
Test name
Test status
Simulation time 16654405 ps
CPU time 2.94 seconds
Started Jul 26 04:24:26 PM PDT 24
Finished Jul 26 04:24:29 PM PDT 24
Peak memory 202212 kb
Host smart-07b1bda2-14ce-4c87-b8fb-ede25105b091
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1426238532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1426238532
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3421738270
Short name T102
Test name
Test status
Simulation time 156753212568 ps
CPU time 616.35 seconds
Started Jul 26 04:24:40 PM PDT 24
Finished Jul 26 04:34:57 PM PDT 24
Peak memory 211560 kb
Host smart-4c601400-e70e-4e4f-b553-c0164545c1b3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3421738270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl
ow_rsp.3421738270
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.456699814
Short name T16
Test name
Test status
Simulation time 2356203225 ps
CPU time 17.68 seconds
Started Jul 26 04:25:10 PM PDT 24
Finished Jul 26 04:25:28 PM PDT 24
Peak memory 203172 kb
Host smart-b409b950-743b-449d-8376-612a1824ef2c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=456699814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.456699814
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.500545372
Short name T13
Test name
Test status
Simulation time 167508591 ps
CPU time 17.84 seconds
Started Jul 26 04:25:09 PM PDT 24
Finished Jul 26 04:25:27 PM PDT 24
Peak memory 202072 kb
Host smart-4661c488-89a3-482b-b999-104d7ecd2aa1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=500545372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.500545372
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.3730976380
Short name T655
Test name
Test status
Simulation time 400091739 ps
CPU time 11.37 seconds
Started Jul 26 04:24:42 PM PDT 24
Finished Jul 26 04:24:53 PM PDT 24
Peak memory 211428 kb
Host smart-2561b6a5-97ec-4035-b242-de70d97fa394
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3730976380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.3730976380
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.2932525130
Short name T177
Test name
Test status
Simulation time 60233299263 ps
CPU time 70.13 seconds
Started Jul 26 04:25:04 PM PDT 24
Finished Jul 26 04:26:14 PM PDT 24
Peak memory 211260 kb
Host smart-981ddc1f-fcdc-4de7-bce7-7f634c3d3798
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932525130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2932525130
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3700865328
Short name T622
Test name
Test status
Simulation time 10942621547 ps
CPU time 86.54 seconds
Started Jul 26 04:24:41 PM PDT 24
Finished Jul 26 04:26:08 PM PDT 24
Peak memory 211504 kb
Host smart-843b4c56-897f-49d3-83af-7ed2cd1993fb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3700865328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3700865328
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.1578279082
Short name T319
Test name
Test status
Simulation time 159835625 ps
CPU time 6.57 seconds
Started Jul 26 04:23:57 PM PDT 24
Finished Jul 26 04:24:04 PM PDT 24
Peak memory 211488 kb
Host smart-f0a6ad84-9e7d-4ba0-bf2a-6451fc40bbf2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578279082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.1578279082
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.861519134
Short name T211
Test name
Test status
Simulation time 129594372 ps
CPU time 3.06 seconds
Started Jul 26 04:24:26 PM PDT 24
Finished Jul 26 04:24:29 PM PDT 24
Peak memory 202708 kb
Host smart-c888a404-9f77-4f92-a56c-3f014c31eebf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=861519134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.861519134
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.181633669
Short name T236
Test name
Test status
Simulation time 51137394 ps
CPU time 2.37 seconds
Started Jul 26 04:24:40 PM PDT 24
Finished Jul 26 04:24:42 PM PDT 24
Peak memory 203236 kb
Host smart-56f04380-20ce-4a8e-a6bd-a0650cc0044a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=181633669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.181633669
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.3494846507
Short name T133
Test name
Test status
Simulation time 6898994112 ps
CPU time 30.68 seconds
Started Jul 26 04:23:28 PM PDT 24
Finished Jul 26 04:23:59 PM PDT 24
Peak memory 203344 kb
Host smart-1e114e5c-d07d-458f-b583-34db7eccced7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494846507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.3494846507
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.2828233167
Short name T168
Test name
Test status
Simulation time 8330377288 ps
CPU time 30.23 seconds
Started Jul 26 04:25:04 PM PDT 24
Finished Jul 26 04:25:35 PM PDT 24
Peak memory 203156 kb
Host smart-c4e91c73-97a9-48e6-b874-eb82b5a54dd5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2828233167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2828233167
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.421246822
Short name T735
Test name
Test status
Simulation time 27655780 ps
CPU time 2.1 seconds
Started Jul 26 04:24:27 PM PDT 24
Finished Jul 26 04:24:29 PM PDT 24
Peak memory 203012 kb
Host smart-0bbfad2a-5b27-4913-83a9-917899a9fd1f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421246822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.421246822
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.2121154429
Short name T460
Test name
Test status
Simulation time 200518119 ps
CPU time 19.72 seconds
Started Jul 26 04:22:50 PM PDT 24
Finished Jul 26 04:23:10 PM PDT 24
Peak memory 205128 kb
Host smart-8a56f9e5-84a5-4e70-a5e2-93ee247d61e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2121154429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2121154429
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.902336703
Short name T109
Test name
Test status
Simulation time 5084609754 ps
CPU time 109.08 seconds
Started Jul 26 04:25:33 PM PDT 24
Finished Jul 26 04:27:23 PM PDT 24
Peak memory 205280 kb
Host smart-d4ee0f5c-37b1-4214-a5fd-23dec874510c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=902336703 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.902336703
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.3879865279
Short name T254
Test name
Test status
Simulation time 652267747 ps
CPU time 187.88 seconds
Started Jul 26 04:23:24 PM PDT 24
Finished Jul 26 04:26:32 PM PDT 24
Peak memory 208924 kb
Host smart-f9ffb0e2-d7d8-4e05-86aa-da4f3fd30f1c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3879865279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran
d_reset.3879865279
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.634838902
Short name T552
Test name
Test status
Simulation time 1316164776 ps
CPU time 143.29 seconds
Started Jul 26 04:23:18 PM PDT 24
Finished Jul 26 04:25:42 PM PDT 24
Peak memory 209220 kb
Host smart-dbb81413-5ad2-467a-b41c-92d60f6a55d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=634838902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_res
et_error.634838902
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.227298096
Short name T723
Test name
Test status
Simulation time 2186148167 ps
CPU time 23.16 seconds
Started Jul 26 04:24:49 PM PDT 24
Finished Jul 26 04:25:12 PM PDT 24
Peak memory 204880 kb
Host smart-f8a92522-df9f-43f2-a77e-7ead2eec7069
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=227298096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.227298096
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.3221894981
Short name T856
Test name
Test status
Simulation time 1136227359 ps
CPU time 38.31 seconds
Started Jul 26 04:24:40 PM PDT 24
Finished Jul 26 04:25:19 PM PDT 24
Peak memory 205472 kb
Host smart-f9ab01ce-ba1f-4b16-b5bc-abdfbdb09200
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3221894981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.3221894981
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.749113537
Short name T187
Test name
Test status
Simulation time 23171913077 ps
CPU time 208.86 seconds
Started Jul 26 04:25:10 PM PDT 24
Finished Jul 26 04:28:39 PM PDT 24
Peak memory 206276 kb
Host smart-7805b276-22a1-4628-889a-b5e49228ecd1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=749113537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slo
w_rsp.749113537
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1193594433
Short name T845
Test name
Test status
Simulation time 564628405 ps
CPU time 23.9 seconds
Started Jul 26 04:23:10 PM PDT 24
Finished Jul 26 04:23:34 PM PDT 24
Peak memory 203364 kb
Host smart-3a261ba2-4bd3-425e-b61e-9a0c762553cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1193594433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1193594433
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.1866475600
Short name T369
Test name
Test status
Simulation time 817868625 ps
CPU time 26.61 seconds
Started Jul 26 04:23:12 PM PDT 24
Finished Jul 26 04:23:38 PM PDT 24
Peak memory 203268 kb
Host smart-420dedb4-7d58-4329-8635-936973542374
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1866475600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1866475600
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.3921217905
Short name T238
Test name
Test status
Simulation time 214650461 ps
CPU time 21.22 seconds
Started Jul 26 04:24:30 PM PDT 24
Finished Jul 26 04:24:51 PM PDT 24
Peak memory 210236 kb
Host smart-1e21053a-a955-4602-b158-d50f3126601b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3921217905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3921217905
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.962162209
Short name T289
Test name
Test status
Simulation time 14927068251 ps
CPU time 52.35 seconds
Started Jul 26 04:23:19 PM PDT 24
Finished Jul 26 04:24:11 PM PDT 24
Peak memory 211540 kb
Host smart-5b7db0ee-05bb-48d2-bf52-cc3358240431
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=962162209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.962162209
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.3814277266
Short name T486
Test name
Test status
Simulation time 11919196986 ps
CPU time 79.06 seconds
Started Jul 26 04:24:39 PM PDT 24
Finished Jul 26 04:25:58 PM PDT 24
Peak memory 204940 kb
Host smart-b09fbe0a-00e0-444e-910e-d6ce09529437
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3814277266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3814277266
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.2611573113
Short name T533
Test name
Test status
Simulation time 60547197 ps
CPU time 6.7 seconds
Started Jul 26 04:24:39 PM PDT 24
Finished Jul 26 04:24:46 PM PDT 24
Peak memory 210788 kb
Host smart-215b6a7f-6c5d-4cc1-911e-ddcee7d79d15
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611573113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.2611573113
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.1539763307
Short name T453
Test name
Test status
Simulation time 888050868 ps
CPU time 13.19 seconds
Started Jul 26 04:24:41 PM PDT 24
Finished Jul 26 04:24:54 PM PDT 24
Peak memory 203200 kb
Host smart-08b89d29-4e9e-4008-9ff8-4ef734e5d02d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1539763307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1539763307
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.610183787
Short name T160
Test name
Test status
Simulation time 329796761 ps
CPU time 3.32 seconds
Started Jul 26 04:26:10 PM PDT 24
Finished Jul 26 04:26:13 PM PDT 24
Peak memory 202924 kb
Host smart-2c0139a8-b2b8-451e-97f2-28881d6bfa9e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=610183787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.610183787
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.1799109167
Short name T617
Test name
Test status
Simulation time 4960019284 ps
CPU time 22.57 seconds
Started Jul 26 04:24:39 PM PDT 24
Finished Jul 26 04:25:02 PM PDT 24
Peak memory 202460 kb
Host smart-6ee47061-d062-4769-b24f-bc5f3daa4597
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799109167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1799109167
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.3735827193
Short name T706
Test name
Test status
Simulation time 10435556809 ps
CPU time 33.62 seconds
Started Jul 26 04:26:10 PM PDT 24
Finished Jul 26 04:26:44 PM PDT 24
Peak memory 203152 kb
Host smart-f6596a39-2ebb-492a-a450-7ada09565792
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3735827193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3735827193
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.4092023791
Short name T95
Test name
Test status
Simulation time 133253344 ps
CPU time 2.07 seconds
Started Jul 26 04:24:39 PM PDT 24
Finished Jul 26 04:24:41 PM PDT 24
Peak memory 202996 kb
Host smart-b5a62ae8-9ba8-41b4-af21-d0920c21e885
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092023791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.4092023791
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.949106815
Short name T450
Test name
Test status
Simulation time 15678797153 ps
CPU time 139.54 seconds
Started Jul 26 04:24:39 PM PDT 24
Finished Jul 26 04:26:59 PM PDT 24
Peak memory 211280 kb
Host smart-4d22d2f8-7d32-4213-a177-cde7f42ddcaf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=949106815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.949106815
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.3637319710
Short name T394
Test name
Test status
Simulation time 9529448882 ps
CPU time 158.33 seconds
Started Jul 26 04:23:11 PM PDT 24
Finished Jul 26 04:25:49 PM PDT 24
Peak memory 206876 kb
Host smart-38674493-09ff-4788-bdf3-e7197973c96e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3637319710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3637319710
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.2370184364
Short name T664
Test name
Test status
Simulation time 4293733636 ps
CPU time 356.36 seconds
Started Jul 26 04:23:06 PM PDT 24
Finished Jul 26 04:29:02 PM PDT 24
Peak memory 209484 kb
Host smart-da2d0fe9-50dc-4875-aab6-cd07c870244d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2370184364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran
d_reset.2370184364
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3147356894
Short name T434
Test name
Test status
Simulation time 327915910 ps
CPU time 94.44 seconds
Started Jul 26 04:24:27 PM PDT 24
Finished Jul 26 04:26:02 PM PDT 24
Peak memory 208940 kb
Host smart-881fe14c-2928-4fd9-8989-ec28cfed6529
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3147356894 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re
set_error.3147356894
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.539960165
Short name T633
Test name
Test status
Simulation time 874511489 ps
CPU time 25.86 seconds
Started Jul 26 04:24:49 PM PDT 24
Finished Jul 26 04:25:15 PM PDT 24
Peak memory 204964 kb
Host smart-2ae1dc8b-1b70-4c33-8a26-ce3c4a2e071c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=539960165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.539960165
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.3043058971
Short name T424
Test name
Test status
Simulation time 1833988236 ps
CPU time 32.01 seconds
Started Jul 26 04:25:14 PM PDT 24
Finished Jul 26 04:25:47 PM PDT 24
Peak memory 210348 kb
Host smart-7d1cfe81-e937-433e-810d-383871ae4398
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3043058971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.3043058971
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3257785367
Short name T830
Test name
Test status
Simulation time 21093398764 ps
CPU time 170.73 seconds
Started Jul 26 04:25:29 PM PDT 24
Finished Jul 26 04:28:20 PM PDT 24
Peak memory 211496 kb
Host smart-bcfc590b-ac0e-45a5-a577-31422afbe29e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3257785367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl
ow_rsp.3257785367
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.3739653272
Short name T152
Test name
Test status
Simulation time 14848075 ps
CPU time 1.72 seconds
Started Jul 26 04:24:23 PM PDT 24
Finished Jul 26 04:24:25 PM PDT 24
Peak memory 202476 kb
Host smart-ccd77892-f9aa-40c0-971f-37a01735b643
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3739653272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.3739653272
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.3811942506
Short name T366
Test name
Test status
Simulation time 4105199758 ps
CPU time 26.68 seconds
Started Jul 26 04:24:40 PM PDT 24
Finished Jul 26 04:25:07 PM PDT 24
Peak memory 203384 kb
Host smart-ed265782-ab66-4f90-9017-ebbdcc55850d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3811942506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3811942506
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.2414123678
Short name T268
Test name
Test status
Simulation time 680294840 ps
CPU time 20.4 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:25:36 PM PDT 24
Peak memory 204512 kb
Host smart-df8d5db0-96b9-46a0-b9df-9dce66bdf32d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2414123678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.2414123678
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.2037974947
Short name T62
Test name
Test status
Simulation time 62683749908 ps
CPU time 168.67 seconds
Started Jul 26 04:23:17 PM PDT 24
Finished Jul 26 04:26:06 PM PDT 24
Peak memory 204932 kb
Host smart-d7b161b8-0f39-48be-8c11-322a1f04ea10
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037974947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2037974947
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.4121936610
Short name T176
Test name
Test status
Simulation time 23751814675 ps
CPU time 162.85 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:27:58 PM PDT 24
Peak memory 204620 kb
Host smart-53f2fbda-e7f8-41e3-838f-5373fad399b4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4121936610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.4121936610
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.1405979190
Short name T249
Test name
Test status
Simulation time 230916793 ps
CPU time 22.11 seconds
Started Jul 26 04:24:40 PM PDT 24
Finished Jul 26 04:25:03 PM PDT 24
Peak memory 204440 kb
Host smart-70185517-d6c8-401f-bb40-8327e9bfdf52
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405979190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1405979190
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.1240767040
Short name T504
Test name
Test status
Simulation time 1050820864 ps
CPU time 15.93 seconds
Started Jul 26 04:25:14 PM PDT 24
Finished Jul 26 04:25:31 PM PDT 24
Peak memory 201828 kb
Host smart-9846c486-2652-48fd-be3a-69983d4f8e32
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1240767040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1240767040
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.1132552351
Short name T242
Test name
Test status
Simulation time 1066255744 ps
CPU time 4.09 seconds
Started Jul 26 04:24:39 PM PDT 24
Finished Jul 26 04:24:43 PM PDT 24
Peak memory 203044 kb
Host smart-5676c9d9-3fd4-4780-8883-a15aaa4e6906
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1132552351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1132552351
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3402075057
Short name T875
Test name
Test status
Simulation time 4792488828 ps
CPU time 20.57 seconds
Started Jul 26 04:24:40 PM PDT 24
Finished Jul 26 04:25:01 PM PDT 24
Peak memory 203188 kb
Host smart-5b4a6797-18ee-44ea-88ed-334d3b14472e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402075057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3402075057
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.1121484977
Short name T321
Test name
Test status
Simulation time 5581358668 ps
CPU time 29.86 seconds
Started Jul 26 04:25:13 PM PDT 24
Finished Jul 26 04:25:43 PM PDT 24
Peak memory 203364 kb
Host smart-f4330e4f-b5c8-4678-b7a4-c234ba5a2ea3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1121484977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1121484977
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3423124361
Short name T832
Test name
Test status
Simulation time 26474213 ps
CPU time 2.3 seconds
Started Jul 26 04:23:08 PM PDT 24
Finished Jul 26 04:23:10 PM PDT 24
Peak memory 203300 kb
Host smart-6eef81ab-efd5-4c8a-a16e-8ccce977425f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423124361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3423124361
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.4087660115
Short name T678
Test name
Test status
Simulation time 748145661 ps
CPU time 95.49 seconds
Started Jul 26 04:25:28 PM PDT 24
Finished Jul 26 04:27:04 PM PDT 24
Peak memory 207648 kb
Host smart-39209ac1-d574-4de1-ad94-0629b46c46c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4087660115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.4087660115
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.1778007650
Short name T6
Test name
Test status
Simulation time 1374813454 ps
CPU time 45.55 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:26:01 PM PDT 24
Peak memory 205504 kb
Host smart-bd667724-85aa-4fcc-806a-d624069f228a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1778007650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1778007650
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.884795144
Short name T87
Test name
Test status
Simulation time 5332947777 ps
CPU time 273.33 seconds
Started Jul 26 04:25:14 PM PDT 24
Finished Jul 26 04:29:48 PM PDT 24
Peak memory 208880 kb
Host smart-32b251f2-301c-415e-a33e-860457e5f90c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=884795144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand
_reset.884795144
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.2440573950
Short name T303
Test name
Test status
Simulation time 377094180 ps
CPU time 107.37 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:27:03 PM PDT 24
Peak memory 208052 kb
Host smart-41f94cdf-24f4-4494-888e-4e8a3f01533b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2440573950 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re
set_error.2440573950
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.72440473
Short name T831
Test name
Test status
Simulation time 53010183 ps
CPU time 3.74 seconds
Started Jul 26 04:25:28 PM PDT 24
Finished Jul 26 04:25:32 PM PDT 24
Peak memory 204652 kb
Host smart-9e5316fc-c4b6-4b1a-9060-1ee2f8704a91
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=72440473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.72440473
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.1311027589
Short name T330
Test name
Test status
Simulation time 684292545 ps
CPU time 15.5 seconds
Started Jul 26 04:26:00 PM PDT 24
Finished Jul 26 04:26:15 PM PDT 24
Peak memory 205072 kb
Host smart-2483aa1d-2a0b-46a9-9383-3e0c1df6c32c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1311027589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.1311027589
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.322192994
Short name T658
Test name
Test status
Simulation time 5882868928 ps
CPU time 28.96 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:25:46 PM PDT 24
Peak memory 203304 kb
Host smart-be8b9a1b-ca45-4d7a-bade-816cc7c15afe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=322192994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slo
w_rsp.322192994
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.4088436825
Short name T317
Test name
Test status
Simulation time 116777453 ps
CPU time 3.64 seconds
Started Jul 26 04:26:01 PM PDT 24
Finished Jul 26 04:26:05 PM PDT 24
Peak memory 202960 kb
Host smart-08319794-eeaf-40f4-a28b-3d5a847c7ff3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4088436825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.4088436825
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.491898367
Short name T621
Test name
Test status
Simulation time 200061387 ps
CPU time 23.1 seconds
Started Jul 26 04:25:51 PM PDT 24
Finished Jul 26 04:26:15 PM PDT 24
Peak memory 202652 kb
Host smart-6adc432f-4f0d-431b-af2d-6a674088de72
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=491898367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.491898367
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.972204906
Short name T143
Test name
Test status
Simulation time 191396468 ps
CPU time 30.83 seconds
Started Jul 26 04:25:59 PM PDT 24
Finished Jul 26 04:26:30 PM PDT 24
Peak memory 211204 kb
Host smart-abb85c5f-3d32-4599-b8d0-3a4b55c5b7f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=972204906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.972204906
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.3249676196
Short name T210
Test name
Test status
Simulation time 15146972445 ps
CPU time 35.98 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:25:52 PM PDT 24
Peak memory 211452 kb
Host smart-6d9c5ae0-3fd7-414b-ac25-fdae67c1f8de
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249676196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3249676196
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.2855513100
Short name T379
Test name
Test status
Simulation time 4158914064 ps
CPU time 16.13 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:25:33 PM PDT 24
Peak memory 203300 kb
Host smart-6228b778-28fa-48f8-baa2-a784314508bd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2855513100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2855513100
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.3442648940
Short name T760
Test name
Test status
Simulation time 94774051 ps
CPU time 10.74 seconds
Started Jul 26 04:25:59 PM PDT 24
Finished Jul 26 04:26:10 PM PDT 24
Peak memory 204456 kb
Host smart-c56e2185-b34a-494f-873b-8495112790f4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442648940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.3442648940
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.3788231571
Short name T715
Test name
Test status
Simulation time 2034846559 ps
CPU time 33.52 seconds
Started Jul 26 04:26:01 PM PDT 24
Finished Jul 26 04:26:35 PM PDT 24
Peak memory 211164 kb
Host smart-000beab8-6966-4cce-8cd1-cba419473476
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3788231571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3788231571
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.2109713025
Short name T237
Test name
Test status
Simulation time 326134104 ps
CPU time 3.75 seconds
Started Jul 26 04:25:00 PM PDT 24
Finished Jul 26 04:25:04 PM PDT 24
Peak memory 201976 kb
Host smart-93fcc901-4baa-47e2-a215-76e233d8ea8a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2109713025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2109713025
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2575238029
Short name T554
Test name
Test status
Simulation time 16853987381 ps
CPU time 40.19 seconds
Started Jul 26 04:25:16 PM PDT 24
Finished Jul 26 04:25:56 PM PDT 24
Peak memory 203300 kb
Host smart-6d5bbb9f-b2e1-49a9-b825-8974080ec0ab
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575238029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2575238029
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.302908159
Short name T259
Test name
Test status
Simulation time 7266914476 ps
CPU time 28.07 seconds
Started Jul 26 04:25:16 PM PDT 24
Finished Jul 26 04:25:44 PM PDT 24
Peak memory 203288 kb
Host smart-f083a1c5-c57d-4290-8705-eeb7cf370de3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=302908159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.302908159
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.250599783
Short name T679
Test name
Test status
Simulation time 87672687 ps
CPU time 2.36 seconds
Started Jul 26 04:23:28 PM PDT 24
Finished Jul 26 04:23:31 PM PDT 24
Peak memory 203360 kb
Host smart-1393bea4-a331-4fee-a9e4-603d8dc22201
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250599783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.250599783
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.2079898092
Short name T474
Test name
Test status
Simulation time 1013134254 ps
CPU time 27.57 seconds
Started Jul 26 04:25:16 PM PDT 24
Finished Jul 26 04:25:44 PM PDT 24
Peak memory 205524 kb
Host smart-3cfc7d5e-5e90-4a86-a2f4-0dd5035f5edd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2079898092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2079898092
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1536289395
Short name T810
Test name
Test status
Simulation time 4707830104 ps
CPU time 37.39 seconds
Started Jul 26 04:26:00 PM PDT 24
Finished Jul 26 04:26:37 PM PDT 24
Peak memory 211224 kb
Host smart-5594459c-9e7d-4cc4-a497-46abc8934b72
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1536289395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1536289395
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.2567777679
Short name T492
Test name
Test status
Simulation time 599572716 ps
CPU time 229.11 seconds
Started Jul 26 04:26:01 PM PDT 24
Finished Jul 26 04:29:50 PM PDT 24
Peak memory 208144 kb
Host smart-1e0a5deb-cfa1-45e4-b4cf-c82105ae7047
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2567777679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran
d_reset.2567777679
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.4262072642
Short name T612
Test name
Test status
Simulation time 8043068848 ps
CPU time 240.84 seconds
Started Jul 26 04:24:04 PM PDT 24
Finished Jul 26 04:28:05 PM PDT 24
Peak memory 219912 kb
Host smart-ba22b763-3977-4466-8263-ad39215262c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4262072642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re
set_error.4262072642
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.2806643281
Short name T334
Test name
Test status
Simulation time 137048896 ps
CPU time 15.74 seconds
Started Jul 26 04:25:16 PM PDT 24
Finished Jul 26 04:25:32 PM PDT 24
Peak memory 211384 kb
Host smart-71f277d3-52f4-4e22-89a4-081891f06b58
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2806643281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.2806643281
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.4109408617
Short name T141
Test name
Test status
Simulation time 3131774747 ps
CPU time 29.39 seconds
Started Jul 26 04:25:22 PM PDT 24
Finished Jul 26 04:25:51 PM PDT 24
Peak memory 211288 kb
Host smart-bcb94a96-69c1-4aba-a9e4-0b86ce6ea922
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4109408617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.4109408617
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.2299039805
Short name T205
Test name
Test status
Simulation time 87737984158 ps
CPU time 626.71 seconds
Started Jul 26 04:25:22 PM PDT 24
Finished Jul 26 04:35:49 PM PDT 24
Peak memory 211316 kb
Host smart-e45745cd-0fb3-422d-b62d-493bb730e539
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2299039805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl
ow_rsp.2299039805
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.234166198
Short name T103
Test name
Test status
Simulation time 284784498 ps
CPU time 8.29 seconds
Started Jul 26 04:23:42 PM PDT 24
Finished Jul 26 04:23:51 PM PDT 24
Peak memory 203592 kb
Host smart-60c356cd-ff23-4a4c-8be7-dce5be2f6a3f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=234166198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.234166198
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.1782086123
Short name T447
Test name
Test status
Simulation time 2874315830 ps
CPU time 25.09 seconds
Started Jul 26 04:25:21 PM PDT 24
Finished Jul 26 04:25:47 PM PDT 24
Peak memory 203096 kb
Host smart-6b814fb8-6f95-4b82-a993-7339127a80fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1782086123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1782086123
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.3218093899
Short name T521
Test name
Test status
Simulation time 396078156 ps
CPU time 16.28 seconds
Started Jul 26 04:23:31 PM PDT 24
Finished Jul 26 04:23:47 PM PDT 24
Peak memory 204444 kb
Host smart-18482f89-d31f-47f9-99c2-c0970ce7fc2b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3218093899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3218093899
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.4251483658
Short name T877
Test name
Test status
Simulation time 24582202361 ps
CPU time 149.87 seconds
Started Jul 26 04:23:30 PM PDT 24
Finished Jul 26 04:26:00 PM PDT 24
Peak memory 211536 kb
Host smart-4671967e-9cb0-47a1-a07e-69e6fe8cd466
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251483658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.4251483658
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.3541366200
Short name T898
Test name
Test status
Simulation time 8195410771 ps
CPU time 56.18 seconds
Started Jul 26 04:23:36 PM PDT 24
Finished Jul 26 04:24:32 PM PDT 24
Peak memory 211964 kb
Host smart-d7471e01-0551-4676-984c-ae2bb4785c6c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3541366200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3541366200
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.2732936147
Short name T792
Test name
Test status
Simulation time 130387573 ps
CPU time 8.68 seconds
Started Jul 26 04:25:05 PM PDT 24
Finished Jul 26 04:25:14 PM PDT 24
Peak memory 204432 kb
Host smart-79cb6712-a0fa-4b14-8005-6a055bf5a0c5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732936147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.2732936147
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.2208670615
Short name T30
Test name
Test status
Simulation time 231024436 ps
CPU time 7.77 seconds
Started Jul 26 04:25:21 PM PDT 24
Finished Jul 26 04:25:29 PM PDT 24
Peak memory 203580 kb
Host smart-ea1897eb-4698-4fbe-9950-8c563ba9882a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2208670615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2208670615
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.2555425831
Short name T859
Test name
Test status
Simulation time 210807467 ps
CPU time 3.28 seconds
Started Jul 26 04:24:38 PM PDT 24
Finished Jul 26 04:24:41 PM PDT 24
Peak memory 203312 kb
Host smart-7dae287a-50d1-410c-b616-974fbfd549a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2555425831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2555425831
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2812043545
Short name T73
Test name
Test status
Simulation time 5348070130 ps
CPU time 24.12 seconds
Started Jul 26 04:23:29 PM PDT 24
Finished Jul 26 04:23:54 PM PDT 24
Peak memory 203348 kb
Host smart-9426509f-345e-497c-85ab-b7d8b095d697
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812043545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2812043545
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3199453077
Short name T362
Test name
Test status
Simulation time 3345004406 ps
CPU time 27.66 seconds
Started Jul 26 04:23:42 PM PDT 24
Finished Jul 26 04:24:09 PM PDT 24
Peak memory 203392 kb
Host smart-10c0a754-3b83-4888-be7e-85c225392679
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3199453077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3199453077
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.753841957
Short name T312
Test name
Test status
Simulation time 29422405 ps
CPU time 2.17 seconds
Started Jul 26 04:23:41 PM PDT 24
Finished Jul 26 04:23:44 PM PDT 24
Peak memory 203288 kb
Host smart-8a5c8e7c-3833-4d33-8107-73d5e56352b0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753841957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.753841957
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.147551603
Short name T94
Test name
Test status
Simulation time 7557330041 ps
CPU time 85.36 seconds
Started Jul 26 04:25:13 PM PDT 24
Finished Jul 26 04:26:39 PM PDT 24
Peak memory 206044 kb
Host smart-24bfabb9-c277-4362-a539-ac5ee1b8932a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=147551603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.147551603
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.3999145272
Short name T429
Test name
Test status
Simulation time 8342874667 ps
CPU time 83.47 seconds
Started Jul 26 04:23:48 PM PDT 24
Finished Jul 26 04:25:12 PM PDT 24
Peak memory 206324 kb
Host smart-45e00a99-ae9b-4b41-9c6d-42d670b8c65b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3999145272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3999145272
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1002751705
Short name T179
Test name
Test status
Simulation time 4805823557 ps
CPU time 282.04 seconds
Started Jul 26 04:25:22 PM PDT 24
Finished Jul 26 04:30:05 PM PDT 24
Peak memory 210904 kb
Host smart-5572f336-0920-40bb-83e3-fd591060a6e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1002751705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran
d_reset.1002751705
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.1827856115
Short name T402
Test name
Test status
Simulation time 159253357 ps
CPU time 53.39 seconds
Started Jul 26 04:23:50 PM PDT 24
Finished Jul 26 04:24:43 PM PDT 24
Peak memory 207696 kb
Host smart-d682ee80-c55e-4c27-babf-10c8a81a8c48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1827856115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re
set_error.1827856115
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.661847788
Short name T257
Test name
Test status
Simulation time 542254062 ps
CPU time 16.62 seconds
Started Jul 26 04:23:49 PM PDT 24
Finished Jul 26 04:24:05 PM PDT 24
Peak memory 211384 kb
Host smart-7405dd7f-c671-42da-9d00-ce9527cc48b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=661847788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.661847788
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.2204504276
Short name T201
Test name
Test status
Simulation time 523226518 ps
CPU time 27.35 seconds
Started Jul 26 04:25:23 PM PDT 24
Finished Jul 26 04:25:51 PM PDT 24
Peak memory 211424 kb
Host smart-403d1027-c02c-4726-ad28-8fcfb0865817
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2204504276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.2204504276
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.3204628891
Short name T357
Test name
Test status
Simulation time 30889926892 ps
CPU time 81.71 seconds
Started Jul 26 04:25:24 PM PDT 24
Finished Jul 26 04:26:46 PM PDT 24
Peak memory 204396 kb
Host smart-6e7aa58c-f4a1-4b13-a461-701f4f277925
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3204628891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl
ow_rsp.3204628891
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.2325546245
Short name T335
Test name
Test status
Simulation time 2947270699 ps
CPU time 24.37 seconds
Started Jul 26 04:25:28 PM PDT 24
Finished Jul 26 04:25:53 PM PDT 24
Peak memory 203308 kb
Host smart-3a1d8e8d-ac76-4fc0-8b18-e913d01672d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2325546245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.2325546245
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.1539062954
Short name T847
Test name
Test status
Simulation time 331789741 ps
CPU time 22.22 seconds
Started Jul 26 04:24:04 PM PDT 24
Finished Jul 26 04:24:26 PM PDT 24
Peak memory 203744 kb
Host smart-741106e1-b6c0-4c60-8293-1d53496b5ab5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1539062954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1539062954
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.3500301448
Short name T840
Test name
Test status
Simulation time 141020972 ps
CPU time 18.86 seconds
Started Jul 26 04:25:10 PM PDT 24
Finished Jul 26 04:25:29 PM PDT 24
Peak memory 211276 kb
Host smart-7ff80b61-7114-4387-b676-bd84842a99e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3500301448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.3500301448
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.2836273619
Short name T368
Test name
Test status
Simulation time 80069726400 ps
CPU time 220.12 seconds
Started Jul 26 04:25:24 PM PDT 24
Finished Jul 26 04:29:04 PM PDT 24
Peak memory 211480 kb
Host smart-123c897a-7268-4e44-bad3-619c9c9dec7f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836273619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2836273619
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.833464992
Short name T136
Test name
Test status
Simulation time 62003039131 ps
CPU time 189.5 seconds
Started Jul 26 04:23:54 PM PDT 24
Finished Jul 26 04:27:03 PM PDT 24
Peak memory 204816 kb
Host smart-568db144-170e-4e8c-92ae-321ac8e0aff2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=833464992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.833464992
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.3902437130
Short name T685
Test name
Test status
Simulation time 230206424 ps
CPU time 11.78 seconds
Started Jul 26 04:25:07 PM PDT 24
Finished Jul 26 04:25:19 PM PDT 24
Peak memory 210680 kb
Host smart-b66f6010-cad3-4b9b-a425-2f803ea696a5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902437130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.3902437130
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.782070389
Short name T59
Test name
Test status
Simulation time 8973297679 ps
CPU time 29.82 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:25:47 PM PDT 24
Peak memory 211300 kb
Host smart-1e6e407e-27c6-4941-b02f-acf43a33c888
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=782070389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.782070389
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.1633009494
Short name T726
Test name
Test status
Simulation time 210857283 ps
CPU time 3.61 seconds
Started Jul 26 04:23:50 PM PDT 24
Finished Jul 26 04:23:53 PM PDT 24
Peak memory 203292 kb
Host smart-4fdf54da-6d27-429b-857b-e9bb719ecd51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1633009494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1633009494
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1094275639
Short name T899
Test name
Test status
Simulation time 15042822431 ps
CPU time 35.4 seconds
Started Jul 26 04:25:24 PM PDT 24
Finished Jul 26 04:26:00 PM PDT 24
Peak memory 203368 kb
Host smart-f62da3ba-56f5-4447-a722-757f499d330e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094275639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1094275639
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.2492201840
Short name T333
Test name
Test status
Simulation time 7269074185 ps
CPU time 24.96 seconds
Started Jul 26 04:25:22 PM PDT 24
Finished Jul 26 04:25:47 PM PDT 24
Peak memory 203108 kb
Host smart-27991d91-f0e5-436a-b3f0-5a6f2de20417
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2492201840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2492201840
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1316775086
Short name T98
Test name
Test status
Simulation time 44223293 ps
CPU time 1.99 seconds
Started Jul 26 04:25:09 PM PDT 24
Finished Jul 26 04:25:11 PM PDT 24
Peak memory 202124 kb
Host smart-d0064ba7-e74b-4c3d-a38a-bd4f74276576
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316775086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.1316775086
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.2385505286
Short name T26
Test name
Test status
Simulation time 19739670289 ps
CPU time 234.18 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:29:09 PM PDT 24
Peak memory 209400 kb
Host smart-aa9fb6e2-56db-4e85-a87e-26ec63b04d3c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2385505286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2385505286
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3577927279
Short name T588
Test name
Test status
Simulation time 14174381199 ps
CPU time 181.56 seconds
Started Jul 26 04:25:28 PM PDT 24
Finished Jul 26 04:28:30 PM PDT 24
Peak memory 209144 kb
Host smart-3255b344-c122-4389-9b33-bb352d9d3d3f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3577927279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3577927279
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3940096840
Short name T727
Test name
Test status
Simulation time 523747342 ps
CPU time 224.08 seconds
Started Jul 26 04:25:14 PM PDT 24
Finished Jul 26 04:28:59 PM PDT 24
Peak memory 206380 kb
Host smart-41120dba-3fbb-46e7-8280-f211e74fa521
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3940096840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran
d_reset.3940096840
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.2278991194
Short name T746
Test name
Test status
Simulation time 389407172 ps
CPU time 126.16 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:27:21 PM PDT 24
Peak memory 209272 kb
Host smart-3ad9de5b-01e2-4711-9d9d-4746ba6d668c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2278991194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re
set_error.2278991194
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.3465283219
Short name T43
Test name
Test status
Simulation time 940167563 ps
CPU time 25.17 seconds
Started Jul 26 04:25:14 PM PDT 24
Finished Jul 26 04:25:40 PM PDT 24
Peak memory 203036 kb
Host smart-bb2d1670-e31c-4572-934c-6ce3134deb2a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3465283219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3465283219
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.459588254
Short name T577
Test name
Test status
Simulation time 1337113150 ps
CPU time 20.55 seconds
Started Jul 26 04:25:16 PM PDT 24
Finished Jul 26 04:25:37 PM PDT 24
Peak memory 204312 kb
Host smart-2d6cc7d7-196b-482a-acce-d33eef04f3c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=459588254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.459588254
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.268403528
Short name T597
Test name
Test status
Simulation time 82790239 ps
CPU time 3.73 seconds
Started Jul 26 04:24:24 PM PDT 24
Finished Jul 26 04:24:27 PM PDT 24
Peak memory 203308 kb
Host smart-daa7d0cd-3746-4081-b039-65300c1e2f0b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=268403528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.268403528
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.2471692649
Short name T311
Test name
Test status
Simulation time 60324085 ps
CPU time 4.05 seconds
Started Jul 26 04:24:18 PM PDT 24
Finished Jul 26 04:24:22 PM PDT 24
Peak memory 203268 kb
Host smart-b7d0210d-afc4-4e18-bbe0-fea8ed2b3343
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2471692649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2471692649
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.1846861167
Short name T351
Test name
Test status
Simulation time 156547419 ps
CPU time 14.18 seconds
Started Jul 26 04:24:09 PM PDT 24
Finished Jul 26 04:24:23 PM PDT 24
Peak memory 204428 kb
Host smart-a2d239a5-3844-4cd2-bd67-fe5695f19a04
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1846861167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.1846861167
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.3894936817
Short name T820
Test name
Test status
Simulation time 70500100826 ps
CPU time 154.94 seconds
Started Jul 26 04:25:05 PM PDT 24
Finished Jul 26 04:27:41 PM PDT 24
Peak memory 211696 kb
Host smart-ec8c0630-5c19-41eb-b7e7-49bab95152b4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894936817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3894936817
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.1596305291
Short name T575
Test name
Test status
Simulation time 27296697808 ps
CPU time 247.67 seconds
Started Jul 26 04:24:19 PM PDT 24
Finished Jul 26 04:28:27 PM PDT 24
Peak memory 211536 kb
Host smart-df44a38c-0f84-4bb2-8732-86fa8b881715
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1596305291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.1596305291
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.2997756714
Short name T68
Test name
Test status
Simulation time 316921845 ps
CPU time 24.66 seconds
Started Jul 26 04:24:15 PM PDT 24
Finished Jul 26 04:24:40 PM PDT 24
Peak memory 204392 kb
Host smart-ad62e2d9-6fd8-41c7-9054-c3a7cc77a1aa
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997756714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2997756714
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.4251561858
Short name T670
Test name
Test status
Simulation time 517154056 ps
CPU time 12.44 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:25:29 PM PDT 24
Peak memory 203052 kb
Host smart-7238fdd0-2157-439d-906e-eeaa1c3c3120
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4251561858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.4251561858
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.2088346364
Short name T732
Test name
Test status
Simulation time 179776200 ps
CPU time 4.19 seconds
Started Jul 26 04:24:11 PM PDT 24
Finished Jul 26 04:24:16 PM PDT 24
Peak memory 203692 kb
Host smart-7ff89cc3-b46a-4753-8379-50877ee471c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2088346364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2088346364
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.3569066726
Short name T248
Test name
Test status
Simulation time 15821999951 ps
CPU time 33.1 seconds
Started Jul 26 04:24:11 PM PDT 24
Finished Jul 26 04:24:44 PM PDT 24
Peak memory 203360 kb
Host smart-488bccce-e29b-4182-85af-4939e220f2ea
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569066726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3569066726
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.4282347338
Short name T543
Test name
Test status
Simulation time 29226681681 ps
CPU time 52.97 seconds
Started Jul 26 04:24:08 PM PDT 24
Finished Jul 26 04:25:01 PM PDT 24
Peak memory 203424 kb
Host smart-6afc1dff-2b4a-425d-a862-58fee136c993
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4282347338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.4282347338
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.866745372
Short name T852
Test name
Test status
Simulation time 27978327 ps
CPU time 2.31 seconds
Started Jul 26 04:24:08 PM PDT 24
Finished Jul 26 04:24:10 PM PDT 24
Peak memory 203300 kb
Host smart-50f59dca-6b0d-4d0f-8985-896a74cddfd9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866745372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.866745372
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.1975900546
Short name T246
Test name
Test status
Simulation time 7749812819 ps
CPU time 230.55 seconds
Started Jul 26 04:25:12 PM PDT 24
Finished Jul 26 04:29:03 PM PDT 24
Peak memory 209940 kb
Host smart-810ed152-4f67-496c-bba0-6cbb8ff8cae4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1975900546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1975900546
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.2129872796
Short name T549
Test name
Test status
Simulation time 3873741477 ps
CPU time 113.88 seconds
Started Jul 26 04:24:25 PM PDT 24
Finished Jul 26 04:26:19 PM PDT 24
Peak memory 205484 kb
Host smart-fb86f049-2274-4bef-a280-e5da6897ccad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2129872796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2129872796
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.2448163716
Short name T527
Test name
Test status
Simulation time 16465629108 ps
CPU time 491.04 seconds
Started Jul 26 04:24:23 PM PDT 24
Finished Jul 26 04:32:34 PM PDT 24
Peak memory 219792 kb
Host smart-772ac8dc-44a6-48e1-a867-0d520817ecb7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2448163716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re
set_error.2448163716
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.1444069495
Short name T481
Test name
Test status
Simulation time 436880279 ps
CPU time 16.59 seconds
Started Jul 26 04:25:18 PM PDT 24
Finished Jul 26 04:25:34 PM PDT 24
Peak memory 211240 kb
Host smart-e4f73566-51aa-48a2-aadb-2ee07de00302
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1444069495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1444069495
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.1139809364
Short name T701
Test name
Test status
Simulation time 4052068227 ps
CPU time 45.96 seconds
Started Jul 26 04:24:30 PM PDT 24
Finished Jul 26 04:25:16 PM PDT 24
Peak memory 205904 kb
Host smart-cfa07565-e14e-4f7f-829a-b1bb01457460
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1139809364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1139809364
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2206751925
Short name T900
Test name
Test status
Simulation time 84492157841 ps
CPU time 505.73 seconds
Started Jul 26 04:24:33 PM PDT 24
Finished Jul 26 04:32:59 PM PDT 24
Peak memory 211508 kb
Host smart-6c898542-2ec0-47c6-9dca-084897fe763e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2206751925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl
ow_rsp.2206751925
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1454884895
Short name T747
Test name
Test status
Simulation time 537347956 ps
CPU time 8.91 seconds
Started Jul 26 04:24:30 PM PDT 24
Finished Jul 26 04:24:39 PM PDT 24
Peak memory 203328 kb
Host smart-9975caff-c9d0-45bb-aced-a23a73b80aef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1454884895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1454884895
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.671259544
Short name T744
Test name
Test status
Simulation time 637325497 ps
CPU time 25.08 seconds
Started Jul 26 04:24:29 PM PDT 24
Finished Jul 26 04:24:54 PM PDT 24
Peak memory 203468 kb
Host smart-f58cf02c-ccaa-4129-b7b9-4bbf2e193ba9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=671259544 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.671259544
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.2281362899
Short name T495
Test name
Test status
Simulation time 100145079 ps
CPU time 11.54 seconds
Started Jul 26 04:24:26 PM PDT 24
Finished Jul 26 04:24:37 PM PDT 24
Peak memory 211500 kb
Host smart-5744bdb6-de8f-4f2f-9866-f55c093f8edc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2281362899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2281362899
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.500301389
Short name T67
Test name
Test status
Simulation time 40079730655 ps
CPU time 108.13 seconds
Started Jul 26 04:24:25 PM PDT 24
Finished Jul 26 04:26:13 PM PDT 24
Peak memory 211560 kb
Host smart-66335dc6-64ea-4347-8cb3-6f0bc6ac1159
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=500301389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.500301389
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.65990831
Short name T842
Test name
Test status
Simulation time 367489985 ps
CPU time 14.29 seconds
Started Jul 26 04:24:23 PM PDT 24
Finished Jul 26 04:24:37 PM PDT 24
Peak memory 204508 kb
Host smart-d090c3b7-8eb4-443f-a8a7-a37e4496c86b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65990831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.65990831
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.3285449659
Short name T838
Test name
Test status
Simulation time 1754404810 ps
CPU time 15.49 seconds
Started Jul 26 04:24:32 PM PDT 24
Finished Jul 26 04:24:47 PM PDT 24
Peak memory 203380 kb
Host smart-f01e49f2-79f3-4146-bd86-0e58a617b8f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3285449659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3285449659
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.797243174
Short name T431
Test name
Test status
Simulation time 127711288 ps
CPU time 3.65 seconds
Started Jul 26 04:24:28 PM PDT 24
Finished Jul 26 04:24:32 PM PDT 24
Peak memory 203708 kb
Host smart-ee87a0cd-ee2a-47c4-8167-bdc506c09026
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=797243174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.797243174
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3991742307
Short name T61
Test name
Test status
Simulation time 4068430264 ps
CPU time 24.98 seconds
Started Jul 26 04:24:23 PM PDT 24
Finished Jul 26 04:24:48 PM PDT 24
Peak memory 203372 kb
Host smart-964202ec-1bef-4105-b8dc-6d9a643d098b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991742307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3991742307
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.441049039
Short name T822
Test name
Test status
Simulation time 3438308463 ps
CPU time 29.44 seconds
Started Jul 26 04:24:29 PM PDT 24
Finished Jul 26 04:24:58 PM PDT 24
Peak memory 203760 kb
Host smart-9d01e3c4-71ba-497d-bacd-6566a54e6561
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=441049039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.441049039
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.1934200276
Short name T866
Test name
Test status
Simulation time 37662493 ps
CPU time 2.34 seconds
Started Jul 26 04:24:25 PM PDT 24
Finished Jul 26 04:24:27 PM PDT 24
Peak memory 203280 kb
Host smart-ad095747-4b17-4e60-9a26-35cd3aaa4dcb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934200276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.1934200276
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.3129161574
Short name T483
Test name
Test status
Simulation time 3718644304 ps
CPU time 78.66 seconds
Started Jul 26 04:24:34 PM PDT 24
Finished Jul 26 04:25:53 PM PDT 24
Peak memory 206732 kb
Host smart-cc2b66fd-7f84-4310-ba10-a7a336c72976
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3129161574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3129161574
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3242230706
Short name T882
Test name
Test status
Simulation time 7589497039 ps
CPU time 159.26 seconds
Started Jul 26 04:24:33 PM PDT 24
Finished Jul 26 04:27:13 PM PDT 24
Peak memory 209152 kb
Host smart-e29fd4aa-a118-480f-b4b4-6eafb7f55368
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3242230706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3242230706
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3759862754
Short name T776
Test name
Test status
Simulation time 246716295 ps
CPU time 91.91 seconds
Started Jul 26 04:25:55 PM PDT 24
Finished Jul 26 04:27:27 PM PDT 24
Peak memory 208328 kb
Host smart-18da8066-70bc-4d08-8199-7dd248cf1fe4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3759862754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re
set_error.3759862754
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.3807946226
Short name T479
Test name
Test status
Simulation time 200185149 ps
CPU time 16.95 seconds
Started Jul 26 04:24:34 PM PDT 24
Finished Jul 26 04:24:51 PM PDT 24
Peak memory 211476 kb
Host smart-6495246c-aaed-4388-8d40-0008986023c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3807946226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3807946226
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.2051053318
Short name T323
Test name
Test status
Simulation time 57877373 ps
CPU time 11.23 seconds
Started Jul 26 04:25:27 PM PDT 24
Finished Jul 26 04:25:38 PM PDT 24
Peak memory 211412 kb
Host smart-404c932a-4235-4ace-8634-4009f0a9d768
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2051053318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2051053318
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1250044205
Short name T751
Test name
Test status
Simulation time 50636393116 ps
CPU time 394.33 seconds
Started Jul 26 04:25:24 PM PDT 24
Finished Jul 26 04:31:59 PM PDT 24
Peak memory 211304 kb
Host smart-9caf5657-3ba3-4bd5-9ce0-a1f90b27a987
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1250044205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo
w_rsp.1250044205
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.1873904704
Short name T586
Test name
Test status
Simulation time 470354182 ps
CPU time 14.9 seconds
Started Jul 26 04:24:28 PM PDT 24
Finished Jul 26 04:24:43 PM PDT 24
Peak memory 201552 kb
Host smart-560c87e2-03e9-4332-ac05-76b59b014a51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1873904704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.1873904704
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.2994228442
Short name T219
Test name
Test status
Simulation time 18422211 ps
CPU time 1.57 seconds
Started Jul 26 04:24:26 PM PDT 24
Finished Jul 26 04:24:28 PM PDT 24
Peak memory 202748 kb
Host smart-9e81d91e-cb94-4d6b-b039-2de5bbd6de3f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2994228442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2994228442
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.2449242704
Short name T241
Test name
Test status
Simulation time 64954799 ps
CPU time 7.32 seconds
Started Jul 26 04:20:39 PM PDT 24
Finished Jul 26 04:20:46 PM PDT 24
Peak memory 211500 kb
Host smart-547a878e-12aa-4ca1-b2aa-180e233829e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2449242704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.2449242704
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.3054801213
Short name T794
Test name
Test status
Simulation time 23905939556 ps
CPU time 100.08 seconds
Started Jul 26 04:24:28 PM PDT 24
Finished Jul 26 04:26:09 PM PDT 24
Peak memory 209804 kb
Host smart-a6ae24bc-96ae-4b7d-9de8-e971d46a06e8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054801213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3054801213
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.2700648093
Short name T399
Test name
Test status
Simulation time 22315617425 ps
CPU time 181.63 seconds
Started Jul 26 04:24:28 PM PDT 24
Finished Jul 26 04:27:30 PM PDT 24
Peak memory 211184 kb
Host smart-2bea0894-48db-42f5-a917-7d26e3c327a0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2700648093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.2700648093
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.750025621
Short name T137
Test name
Test status
Simulation time 727974060 ps
CPU time 23.67 seconds
Started Jul 26 04:24:26 PM PDT 24
Finished Jul 26 04:24:50 PM PDT 24
Peak memory 209972 kb
Host smart-29fe4ef5-05ec-447c-8efd-59e9e3368fe2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750025621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.750025621
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.3050333879
Short name T604
Test name
Test status
Simulation time 2273438264 ps
CPU time 23.69 seconds
Started Jul 26 04:24:27 PM PDT 24
Finished Jul 26 04:24:51 PM PDT 24
Peak memory 202208 kb
Host smart-3c406f0c-f328-45d4-9cfc-cbf33b573506
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3050333879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3050333879
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.540501917
Short name T632
Test name
Test status
Simulation time 136462663 ps
CPU time 3.4 seconds
Started Jul 26 04:24:26 PM PDT 24
Finished Jul 26 04:24:30 PM PDT 24
Peak memory 202312 kb
Host smart-c983e4b6-631c-4321-8cd5-78e6d566961f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=540501917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.540501917
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.215825968
Short name T53
Test name
Test status
Simulation time 9657013177 ps
CPU time 32.35 seconds
Started Jul 26 04:25:12 PM PDT 24
Finished Jul 26 04:25:45 PM PDT 24
Peak memory 202156 kb
Host smart-3de71a72-28c3-4969-9956-155a58d38f0e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=215825968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.215825968
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.311251944
Short name T425
Test name
Test status
Simulation time 3152563770 ps
CPU time 24.58 seconds
Started Jul 26 04:25:27 PM PDT 24
Finished Jul 26 04:25:51 PM PDT 24
Peak memory 203308 kb
Host smart-0034fd9b-2536-495d-827e-1d3a408c73e9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=311251944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.311251944
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1989868591
Short name T762
Test name
Test status
Simulation time 29994908 ps
CPU time 1.96 seconds
Started Jul 26 04:22:04 PM PDT 24
Finished Jul 26 04:22:06 PM PDT 24
Peak memory 203276 kb
Host smart-b1a06408-aa74-4e45-82ce-61cb76651af2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989868591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1989868591
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.83734259
Short name T890
Test name
Test status
Simulation time 683461015 ps
CPU time 93.97 seconds
Started Jul 26 04:25:13 PM PDT 24
Finished Jul 26 04:26:47 PM PDT 24
Peak memory 206844 kb
Host smart-2250cc71-a207-4f8a-95bd-eac3f46a5eaf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=83734259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.83734259
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.356727619
Short name T519
Test name
Test status
Simulation time 1901517642 ps
CPU time 24.53 seconds
Started Jul 26 04:22:32 PM PDT 24
Finished Jul 26 04:22:57 PM PDT 24
Peak memory 204468 kb
Host smart-fa7eff1b-e591-4ef0-bcde-c68275fd4fd5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=356727619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.356727619
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3496469990
Short name T122
Test name
Test status
Simulation time 15159870896 ps
CPU time 424.86 seconds
Started Jul 26 04:24:28 PM PDT 24
Finished Jul 26 04:31:34 PM PDT 24
Peak memory 208300 kb
Host smart-2304d4bc-711e-4ad4-92d2-a13310f3fa60
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3496469990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand
_reset.3496469990
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.3756014633
Short name T885
Test name
Test status
Simulation time 8959566005 ps
CPU time 389.58 seconds
Started Jul 26 04:24:29 PM PDT 24
Finished Jul 26 04:30:59 PM PDT 24
Peak memory 225368 kb
Host smart-62724329-4290-40cc-b236-c3b4d424ad9a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3756014633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res
et_error.3756014633
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.992952896
Short name T582
Test name
Test status
Simulation time 865541943 ps
CPU time 10.53 seconds
Started Jul 26 04:25:12 PM PDT 24
Finished Jul 26 04:25:23 PM PDT 24
Peak memory 210396 kb
Host smart-b2f6a483-f1cd-4851-982f-ceeef10f63c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=992952896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.992952896
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.2777505704
Short name T893
Test name
Test status
Simulation time 542565807 ps
CPU time 3.67 seconds
Started Jul 26 04:24:37 PM PDT 24
Finished Jul 26 04:24:41 PM PDT 24
Peak memory 203232 kb
Host smart-e9e240aa-0eaa-4787-8577-c03866910b59
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2777505704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.2777505704
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.2141398490
Short name T711
Test name
Test status
Simulation time 56801102324 ps
CPU time 380.27 seconds
Started Jul 26 04:24:47 PM PDT 24
Finished Jul 26 04:31:07 PM PDT 24
Peak memory 206024 kb
Host smart-ced09645-30bd-47c8-85a4-6eed7fd2dbaa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2141398490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl
ow_rsp.2141398490
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.2974488704
Short name T415
Test name
Test status
Simulation time 106745417 ps
CPU time 12.6 seconds
Started Jul 26 04:24:47 PM PDT 24
Finished Jul 26 04:25:00 PM PDT 24
Peak memory 203340 kb
Host smart-b65c457d-0a47-4d20-be29-35bf1eff40fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2974488704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.2974488704
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.3747262522
Short name T512
Test name
Test status
Simulation time 1890512475 ps
CPU time 20.96 seconds
Started Jul 26 04:24:51 PM PDT 24
Finished Jul 26 04:25:12 PM PDT 24
Peak memory 203368 kb
Host smart-5d070ebd-1f57-4ed6-9d6f-4a7cd77a2ca5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3747262522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3747262522
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.3948451815
Short name T472
Test name
Test status
Simulation time 320661706 ps
CPU time 11.28 seconds
Started Jul 26 04:24:46 PM PDT 24
Finished Jul 26 04:24:57 PM PDT 24
Peak memory 211544 kb
Host smart-f0781970-a2c5-404a-8607-a822a9a43f87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3948451815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.3948451815
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.1440524996
Short name T897
Test name
Test status
Simulation time 85382239068 ps
CPU time 168.21 seconds
Started Jul 26 04:24:50 PM PDT 24
Finished Jul 26 04:27:38 PM PDT 24
Peak memory 204632 kb
Host smart-f43d16d1-f673-454a-b3c5-6a8322189c6a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440524996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1440524996
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3101571611
Short name T50
Test name
Test status
Simulation time 16402192747 ps
CPU time 99.2 seconds
Started Jul 26 04:24:41 PM PDT 24
Finished Jul 26 04:26:20 PM PDT 24
Peak memory 211556 kb
Host smart-f6e813cc-c320-4144-a2f7-bf0ac71764cd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3101571611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3101571611
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.2055031397
Short name T359
Test name
Test status
Simulation time 97404300 ps
CPU time 7.44 seconds
Started Jul 26 04:26:09 PM PDT 24
Finished Jul 26 04:26:16 PM PDT 24
Peak memory 211452 kb
Host smart-2c4353da-7d07-4998-bee1-d196bcd4141b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055031397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.2055031397
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.3740446482
Short name T742
Test name
Test status
Simulation time 273647609 ps
CPU time 7.02 seconds
Started Jul 26 04:24:48 PM PDT 24
Finished Jul 26 04:24:55 PM PDT 24
Peak memory 203720 kb
Host smart-0575b4d7-5810-48b3-979c-e7d2ece04084
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3740446482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3740446482
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.2140709324
Short name T324
Test name
Test status
Simulation time 110260765 ps
CPU time 2.61 seconds
Started Jul 26 04:24:32 PM PDT 24
Finished Jul 26 04:24:35 PM PDT 24
Peak memory 203328 kb
Host smart-ea2e536e-5301-4a2b-9f48-734169f49771
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2140709324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2140709324
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.4153459430
Short name T290
Test name
Test status
Simulation time 7549612607 ps
CPU time 27.33 seconds
Started Jul 26 04:25:56 PM PDT 24
Finished Jul 26 04:26:24 PM PDT 24
Peak memory 203320 kb
Host smart-6691b21f-5952-4cb4-894c-6c612746e10c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153459430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.4153459430
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.1102094369
Short name T426
Test name
Test status
Simulation time 11864581839 ps
CPU time 33.79 seconds
Started Jul 26 04:24:36 PM PDT 24
Finished Jul 26 04:25:10 PM PDT 24
Peak memory 203400 kb
Host smart-0d103b0f-c4e2-4dad-bf57-63484a078da8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1102094369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1102094369
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.1010591266
Short name T41
Test name
Test status
Simulation time 23185614 ps
CPU time 1.99 seconds
Started Jul 26 04:25:59 PM PDT 24
Finished Jul 26 04:26:01 PM PDT 24
Peak memory 203272 kb
Host smart-313b7324-db83-46de-a0da-d88b6d52fdcb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010591266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.1010591266
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all.2290933381
Short name T284
Test name
Test status
Simulation time 1464695658 ps
CPU time 74.71 seconds
Started Jul 26 04:25:02 PM PDT 24
Finished Jul 26 04:26:16 PM PDT 24
Peak memory 205280 kb
Host smart-4dcd9df7-d022-4de6-8e6c-3c9308b4b185
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2290933381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2290933381
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2222179665
Short name T258
Test name
Test status
Simulation time 2832960635 ps
CPU time 110.7 seconds
Started Jul 26 04:25:02 PM PDT 24
Finished Jul 26 04:26:53 PM PDT 24
Peak memory 208180 kb
Host smart-ca14895a-09fd-46db-8b8f-0e9965cb45f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2222179665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2222179665
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.3561774524
Short name T200
Test name
Test status
Simulation time 6423483529 ps
CPU time 655.03 seconds
Started Jul 26 04:24:47 PM PDT 24
Finished Jul 26 04:35:42 PM PDT 24
Peak memory 227956 kb
Host smart-ec310292-00e5-4860-bfd2-816b484f9838
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3561774524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran
d_reset.3561774524
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.3601500315
Short name T815
Test name
Test status
Simulation time 1057537904 ps
CPU time 173.71 seconds
Started Jul 26 04:25:06 PM PDT 24
Finished Jul 26 04:28:00 PM PDT 24
Peak memory 219652 kb
Host smart-94884a3c-43cc-41ce-baaa-3c845e2c1d18
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3601500315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re
set_error.3601500315
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.263289757
Short name T846
Test name
Test status
Simulation time 58840911 ps
CPU time 7.96 seconds
Started Jul 26 04:24:48 PM PDT 24
Finished Jul 26 04:24:56 PM PDT 24
Peak memory 204780 kb
Host smart-4d343604-0c10-4d7e-a451-907f5caae95e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=263289757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.263289757
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.3312112527
Short name T769
Test name
Test status
Simulation time 1021113428 ps
CPU time 16.38 seconds
Started Jul 26 04:26:03 PM PDT 24
Finished Jul 26 04:26:19 PM PDT 24
Peak memory 204124 kb
Host smart-6dcf21a5-0091-4906-ba37-1dcd5fe01b73
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3312112527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3312112527
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1558760551
Short name T297
Test name
Test status
Simulation time 102406678473 ps
CPU time 655.38 seconds
Started Jul 26 04:25:06 PM PDT 24
Finished Jul 26 04:36:02 PM PDT 24
Peak memory 211532 kb
Host smart-acd3e7ea-4cbf-4767-9e62-f41635dc1d05
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1558760551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl
ow_rsp.1558760551
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.2401889424
Short name T341
Test name
Test status
Simulation time 585670331 ps
CPU time 15.76 seconds
Started Jul 26 04:25:07 PM PDT 24
Finished Jul 26 04:25:23 PM PDT 24
Peak memory 204020 kb
Host smart-2c3e6152-9258-4463-9756-9c3e1eaf2b43
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2401889424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2401889424
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.1261821886
Short name T510
Test name
Test status
Simulation time 601805922 ps
CPU time 6.1 seconds
Started Jul 26 04:25:11 PM PDT 24
Finished Jul 26 04:25:17 PM PDT 24
Peak memory 203284 kb
Host smart-4d5942c2-ac4f-4ac9-ad27-95a028c036c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1261821886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1261821886
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.4152388568
Short name T695
Test name
Test status
Simulation time 30194415 ps
CPU time 3.73 seconds
Started Jul 26 04:25:06 PM PDT 24
Finished Jul 26 04:25:09 PM PDT 24
Peak memory 203364 kb
Host smart-e616d9eb-6c6c-422a-a69a-735aac3800d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4152388568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.4152388568
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.2790941371
Short name T88
Test name
Test status
Simulation time 30957924981 ps
CPU time 174.78 seconds
Started Jul 26 04:25:24 PM PDT 24
Finished Jul 26 04:28:19 PM PDT 24
Peak memory 204636 kb
Host smart-010c3441-3908-4ab1-8225-7db1f35b3d3b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790941371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2790941371
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.870534444
Short name T84
Test name
Test status
Simulation time 24412276863 ps
CPU time 211.02 seconds
Started Jul 26 04:25:03 PM PDT 24
Finished Jul 26 04:28:34 PM PDT 24
Peak memory 211444 kb
Host smart-6a04c79b-24ea-4d53-9111-60cab2d2b92b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=870534444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.870534444
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.65265609
Short name T230
Test name
Test status
Simulation time 148035712 ps
CPU time 8.73 seconds
Started Jul 26 04:25:28 PM PDT 24
Finished Jul 26 04:25:38 PM PDT 24
Peak memory 211460 kb
Host smart-814a3e89-862a-4a13-8341-0da0be3e2cf5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65265609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.65265609
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.3457043680
Short name T766
Test name
Test status
Simulation time 313511691 ps
CPU time 10.14 seconds
Started Jul 26 04:25:13 PM PDT 24
Finished Jul 26 04:25:24 PM PDT 24
Peak memory 203316 kb
Host smart-259ada29-bdc7-4f26-a328-fd99268ea115
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3457043680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3457043680
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.1072493700
Short name T275
Test name
Test status
Simulation time 127767197 ps
CPU time 3.23 seconds
Started Jul 26 04:25:07 PM PDT 24
Finished Jul 26 04:25:11 PM PDT 24
Peak memory 203292 kb
Host smart-04ffd8d0-1224-47b7-b885-a8cc4d66d353
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1072493700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1072493700
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.1297959067
Short name T462
Test name
Test status
Simulation time 5573202030 ps
CPU time 26.97 seconds
Started Jul 26 04:27:12 PM PDT 24
Finished Jul 26 04:27:40 PM PDT 24
Peak memory 203360 kb
Host smart-95a3bdc8-e3d5-40df-8d58-3d2e7672bd35
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297959067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1297959067
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.3317291976
Short name T280
Test name
Test status
Simulation time 5095906608 ps
CPU time 29.57 seconds
Started Jul 26 04:24:57 PM PDT 24
Finished Jul 26 04:25:27 PM PDT 24
Peak memory 203384 kb
Host smart-d129c0ae-438e-4868-87bf-e457fdbc848f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3317291976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3317291976
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1491111159
Short name T243
Test name
Test status
Simulation time 29639593 ps
CPU time 2.09 seconds
Started Jul 26 04:25:24 PM PDT 24
Finished Jul 26 04:25:26 PM PDT 24
Peak memory 203292 kb
Host smart-fe74acc8-9132-48c8-8f83-cff1e808c468
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491111159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1491111159
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.1073495881
Short name T373
Test name
Test status
Simulation time 2404118343 ps
CPU time 51.55 seconds
Started Jul 26 04:25:09 PM PDT 24
Finished Jul 26 04:26:01 PM PDT 24
Peak memory 206192 kb
Host smart-52b7129e-2871-47d9-b265-117a2567b2e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1073495881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1073495881
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.406007149
Short name T261
Test name
Test status
Simulation time 8906099750 ps
CPU time 230.35 seconds
Started Jul 26 04:25:11 PM PDT 24
Finished Jul 26 04:29:01 PM PDT 24
Peak memory 211292 kb
Host smart-1b8cd089-0f96-446f-a7ff-d302d3dae9bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=406007149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.406007149
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1110111098
Short name T162
Test name
Test status
Simulation time 44895847 ps
CPU time 16.94 seconds
Started Jul 26 04:25:11 PM PDT 24
Finished Jul 26 04:25:28 PM PDT 24
Peak memory 205788 kb
Host smart-f51c1757-4d0b-4b95-9a27-ad14eae2fdbe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1110111098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran
d_reset.1110111098
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3834970147
Short name T818
Test name
Test status
Simulation time 3577206017 ps
CPU time 403.18 seconds
Started Jul 26 04:25:08 PM PDT 24
Finished Jul 26 04:31:51 PM PDT 24
Peak memory 227908 kb
Host smart-3deefbda-e21d-42eb-84a7-bfeaa5d19011
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3834970147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re
set_error.3834970147
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.163064787
Short name T623
Test name
Test status
Simulation time 57723860 ps
CPU time 2.4 seconds
Started Jul 26 04:26:08 PM PDT 24
Finished Jul 26 04:26:11 PM PDT 24
Peak memory 203276 kb
Host smart-eea654b5-03ff-4fd9-a483-bbf1ef8ae482
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=163064787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.163064787
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.3599844906
Short name T76
Test name
Test status
Simulation time 522132287 ps
CPU time 15.87 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:25:33 PM PDT 24
Peak memory 211476 kb
Host smart-eb448da4-d946-4e2e-93e4-14b9817412f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3599844906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.3599844906
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1059909270
Short name T116
Test name
Test status
Simulation time 129778153442 ps
CPU time 437.51 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:32:35 PM PDT 24
Peak memory 211544 kb
Host smart-8f3dae19-a6b2-4a3a-a3be-42a5ea683637
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1059909270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl
ow_rsp.1059909270
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.1804194665
Short name T651
Test name
Test status
Simulation time 21216655 ps
CPU time 1.6 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:25:19 PM PDT 24
Peak memory 203308 kb
Host smart-c4433e0d-f1c1-481f-98f0-439dbb0e5d52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1804194665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.1804194665
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.2975299016
Short name T164
Test name
Test status
Simulation time 475108522 ps
CPU time 17.22 seconds
Started Jul 26 04:25:12 PM PDT 24
Finished Jul 26 04:25:30 PM PDT 24
Peak memory 203340 kb
Host smart-00f3f8d7-184c-41fb-9511-386036eecb3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2975299016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2975299016
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.4259427676
Short name T148
Test name
Test status
Simulation time 213765241 ps
CPU time 19.56 seconds
Started Jul 26 04:25:14 PM PDT 24
Finished Jul 26 04:25:33 PM PDT 24
Peak memory 204432 kb
Host smart-f30e70e6-2991-4385-a00a-55a6929f5509
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4259427676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.4259427676
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.3300406394
Short name T881
Test name
Test status
Simulation time 74946692095 ps
CPU time 113.26 seconds
Started Jul 26 04:25:14 PM PDT 24
Finished Jul 26 04:27:07 PM PDT 24
Peak memory 204788 kb
Host smart-af8806db-1529-4622-bca7-9a0d4987af2b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300406394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3300406394
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.2022862096
Short name T144
Test name
Test status
Simulation time 10695721490 ps
CPU time 96.51 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:26:53 PM PDT 24
Peak memory 204616 kb
Host smart-36b6274b-6f7b-48e6-babb-e706b01c5df1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2022862096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2022862096
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.231894942
Short name T702
Test name
Test status
Simulation time 68968557 ps
CPU time 5.38 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:25:23 PM PDT 24
Peak memory 211880 kb
Host smart-c4463969-14d6-4616-83b7-258d8d356a68
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231894942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.231894942
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.25063163
Short name T805
Test name
Test status
Simulation time 104113277 ps
CPU time 8.68 seconds
Started Jul 26 04:25:18 PM PDT 24
Finished Jul 26 04:25:27 PM PDT 24
Peak memory 203300 kb
Host smart-f1b2d9a0-aa38-4567-be2a-a9ea80bf3820
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=25063163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.25063163
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.3583352511
Short name T578
Test name
Test status
Simulation time 28977836 ps
CPU time 2.41 seconds
Started Jul 26 04:25:19 PM PDT 24
Finished Jul 26 04:25:22 PM PDT 24
Peak memory 203336 kb
Host smart-00edb1e3-1929-4d45-8607-4fb5530f7f13
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3583352511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3583352511
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.392359715
Short name T511
Test name
Test status
Simulation time 30231753216 ps
CPU time 44.55 seconds
Started Jul 26 04:25:11 PM PDT 24
Finished Jul 26 04:25:56 PM PDT 24
Peak memory 203388 kb
Host smart-d0f41305-4d52-4d34-9bd9-f4b40475656f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=392359715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.392359715
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.1688458714
Short name T318
Test name
Test status
Simulation time 2856489079 ps
CPU time 26.54 seconds
Started Jul 26 04:25:12 PM PDT 24
Finished Jul 26 04:25:39 PM PDT 24
Peak memory 203368 kb
Host smart-4577f990-a6ff-42cc-adf3-ca413bf8c17c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1688458714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1688458714
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.3248553192
Short name T590
Test name
Test status
Simulation time 109444623 ps
CPU time 2.29 seconds
Started Jul 26 04:25:19 PM PDT 24
Finished Jul 26 04:25:22 PM PDT 24
Peak memory 203300 kb
Host smart-55ec27f8-7d9f-4226-8ccc-41fccd20a5d1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248553192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.3248553192
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.1394691359
Short name T676
Test name
Test status
Simulation time 4907109613 ps
CPU time 119.73 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:27:17 PM PDT 24
Peak memory 211544 kb
Host smart-b60a1547-94f8-44f4-a1f3-3d7c7fbe0767
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1394691359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1394691359
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1507920984
Short name T843
Test name
Test status
Simulation time 3584306299 ps
CPU time 54.26 seconds
Started Jul 26 04:25:13 PM PDT 24
Finished Jul 26 04:26:08 PM PDT 24
Peak memory 204684 kb
Host smart-89d6d8f1-2852-4061-98c9-5cdffc021727
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1507920984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1507920984
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.4221558597
Short name T36
Test name
Test status
Simulation time 8941136238 ps
CPU time 426.09 seconds
Started Jul 26 04:25:20 PM PDT 24
Finished Jul 26 04:32:26 PM PDT 24
Peak memory 219732 kb
Host smart-fce1795b-1405-4634-bfdf-1ad550e2036e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4221558597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran
d_reset.4221558597
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.338070666
Short name T819
Test name
Test status
Simulation time 711407446 ps
CPU time 237.43 seconds
Started Jul 26 04:25:23 PM PDT 24
Finished Jul 26 04:29:21 PM PDT 24
Peak memory 219644 kb
Host smart-ad9cb8ed-dd55-40e6-8590-aae2ef560459
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=338070666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_res
et_error.338070666
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.781898050
Short name T603
Test name
Test status
Simulation time 1387971825 ps
CPU time 18.3 seconds
Started Jul 26 04:25:41 PM PDT 24
Finished Jul 26 04:25:59 PM PDT 24
Peak memory 204648 kb
Host smart-9294f79c-2c44-4c56-86c1-d64d8d8d2b12
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=781898050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.781898050
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.527379974
Short name T79
Test name
Test status
Simulation time 8684124603 ps
CPU time 57.12 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:26:13 PM PDT 24
Peak memory 211568 kb
Host smart-828ea655-8bda-4c83-ad99-2eda07e92f1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=527379974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.527379974
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.26266201
Short name T489
Test name
Test status
Simulation time 8290467040 ps
CPU time 47.56 seconds
Started Jul 26 04:25:19 PM PDT 24
Finished Jul 26 04:26:07 PM PDT 24
Peak memory 211540 kb
Host smart-31e87171-cad7-4799-9a48-f50ecbf284cc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=26266201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow
_rsp.26266201
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.1045787225
Short name T537
Test name
Test status
Simulation time 206698728 ps
CPU time 18.04 seconds
Started Jul 26 04:26:55 PM PDT 24
Finished Jul 26 04:27:14 PM PDT 24
Peak memory 203056 kb
Host smart-5135e876-ef10-4e1a-bba4-bb641fff3441
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1045787225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.1045787225
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.3445197315
Short name T707
Test name
Test status
Simulation time 627693663 ps
CPU time 11.53 seconds
Started Jul 26 04:25:23 PM PDT 24
Finished Jul 26 04:25:35 PM PDT 24
Peak memory 203296 kb
Host smart-428b9885-3782-4dfd-94ee-8d6927c9fd3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3445197315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3445197315
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.2495672
Short name T529
Test name
Test status
Simulation time 13361053 ps
CPU time 1.88 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:25:19 PM PDT 24
Peak memory 203696 kb
Host smart-692d3244-68b7-4126-8b9f-255e58dae44e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2495672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2495672
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.2436514771
Short name T795
Test name
Test status
Simulation time 54069749386 ps
CPU time 201.34 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:28:38 PM PDT 24
Peak memory 211544 kb
Host smart-028672e2-a76a-4415-82d3-9319cbe8e9aa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436514771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2436514771
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.41411758
Short name T878
Test name
Test status
Simulation time 15119378725 ps
CPU time 73.66 seconds
Started Jul 26 04:25:16 PM PDT 24
Finished Jul 26 04:26:29 PM PDT 24
Peak memory 211448 kb
Host smart-4c11db4b-224b-48b0-86c8-312d003a6e6e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=41411758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.41411758
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.3807954860
Short name T833
Test name
Test status
Simulation time 88557481 ps
CPU time 7 seconds
Started Jul 26 04:25:14 PM PDT 24
Finished Jul 26 04:25:22 PM PDT 24
Peak memory 211480 kb
Host smart-307c0f83-1e48-4987-98d6-1aa1ea5a7fa8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807954860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.3807954860
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.2109670014
Short name T172
Test name
Test status
Simulation time 5007681970 ps
CPU time 32.81 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:25:48 PM PDT 24
Peak memory 204460 kb
Host smart-948464a1-85c1-4c58-9a8e-06ad2154ed82
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2109670014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2109670014
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.1150255465
Short name T790
Test name
Test status
Simulation time 579282533 ps
CPU time 3.51 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:25:20 PM PDT 24
Peak memory 203300 kb
Host smart-c51145bc-f21c-4108-bff7-37ddcddfc689
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1150255465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1150255465
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.4030459885
Short name T589
Test name
Test status
Simulation time 4792897091 ps
CPU time 26.24 seconds
Started Jul 26 04:25:18 PM PDT 24
Finished Jul 26 04:25:44 PM PDT 24
Peak memory 203372 kb
Host smart-f33b7bd4-a913-4661-b16e-3cb7599aea93
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030459885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.4030459885
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.571041430
Short name T251
Test name
Test status
Simulation time 13305346201 ps
CPU time 44.36 seconds
Started Jul 26 04:25:14 PM PDT 24
Finished Jul 26 04:25:59 PM PDT 24
Peak memory 203368 kb
Host smart-20563c0c-22a6-4413-929d-a657967aa032
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=571041430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.571041430
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.2813376627
Short name T645
Test name
Test status
Simulation time 30115494 ps
CPU time 2.11 seconds
Started Jul 26 04:25:40 PM PDT 24
Finished Jul 26 04:25:42 PM PDT 24
Peak memory 203296 kb
Host smart-c401c75f-7c19-4e1c-9a45-8a9ca7735135
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813376627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.2813376627
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.124305053
Short name T115
Test name
Test status
Simulation time 6501605808 ps
CPU time 166.25 seconds
Started Jul 26 04:25:18 PM PDT 24
Finished Jul 26 04:28:04 PM PDT 24
Peak memory 209324 kb
Host smart-f82e94c8-c820-4a18-8705-d3c49379292e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=124305053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.124305053
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2726014533
Short name T821
Test name
Test status
Simulation time 1205440706 ps
CPU time 100.35 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:26:56 PM PDT 24
Peak memory 207752 kb
Host smart-5acce153-0d6f-4fcc-99ae-9900fe53f9a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2726014533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2726014533
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.2027108699
Short name T524
Test name
Test status
Simulation time 554367252 ps
CPU time 206.92 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:28:42 PM PDT 24
Peak memory 208460 kb
Host smart-1a311c0a-5a84-4ce3-b8e3-4be64e779aeb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2027108699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran
d_reset.2027108699
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.4134988835
Short name T35
Test name
Test status
Simulation time 3558051915 ps
CPU time 187.49 seconds
Started Jul 26 04:26:55 PM PDT 24
Finished Jul 26 04:30:03 PM PDT 24
Peak memory 210736 kb
Host smart-e0a77da5-603b-4c0f-95ab-580101167a8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4134988835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re
set_error.4134988835
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.1992678238
Short name T418
Test name
Test status
Simulation time 17571498 ps
CPU time 2.96 seconds
Started Jul 26 04:25:19 PM PDT 24
Finished Jul 26 04:25:22 PM PDT 24
Peak memory 211504 kb
Host smart-1383414f-dd48-4586-ac1d-0635c177e070
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1992678238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.1992678238
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.2699068959
Short name T140
Test name
Test status
Simulation time 759833939 ps
CPU time 17.85 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:25:33 PM PDT 24
Peak memory 211480 kb
Host smart-31ee6eb3-6af5-4e6e-9073-4146e384176f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2699068959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.2699068959
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1790829044
Short name T367
Test name
Test status
Simulation time 29338945940 ps
CPU time 143.13 seconds
Started Jul 26 04:25:18 PM PDT 24
Finished Jul 26 04:27:41 PM PDT 24
Peak memory 211540 kb
Host smart-a43c393a-fdc1-4db6-a4fc-8f62bc7b9c10
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1790829044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl
ow_rsp.1790829044
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.735801063
Short name T652
Test name
Test status
Simulation time 1297956026 ps
CPU time 12.62 seconds
Started Jul 26 04:25:23 PM PDT 24
Finished Jul 26 04:25:35 PM PDT 24
Peak memory 203332 kb
Host smart-05bb493b-b2e9-42b6-a162-f74bd83a586c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=735801063 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.735801063
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.30318718
Short name T804
Test name
Test status
Simulation time 2548601119 ps
CPU time 30.54 seconds
Started Jul 26 04:25:28 PM PDT 24
Finished Jul 26 04:25:59 PM PDT 24
Peak memory 203380 kb
Host smart-ff55a7c0-e93d-41c4-ba9e-291baa660955
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=30318718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.30318718
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.959965098
Short name T786
Test name
Test status
Simulation time 648636880 ps
CPU time 14.55 seconds
Started Jul 26 04:25:18 PM PDT 24
Finished Jul 26 04:25:33 PM PDT 24
Peak memory 211460 kb
Host smart-186d88b6-74f9-4aba-a512-9f1c420104b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=959965098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.959965098
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.3638692429
Short name T272
Test name
Test status
Simulation time 17762979609 ps
CPU time 80.13 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:26:37 PM PDT 24
Peak memory 211936 kb
Host smart-794fc8e0-deb7-42f6-a262-68b4c6b68591
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638692429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3638692429
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.240429296
Short name T466
Test name
Test status
Simulation time 64490880647 ps
CPU time 235.73 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:29:10 PM PDT 24
Peak memory 211500 kb
Host smart-7d55234d-82da-418f-9501-52833d3a74d4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=240429296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.240429296
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.3210011064
Short name T186
Test name
Test status
Simulation time 235119305 ps
CPU time 11.74 seconds
Started Jul 26 04:25:13 PM PDT 24
Finished Jul 26 04:25:25 PM PDT 24
Peak memory 211476 kb
Host smart-4ad89476-0a27-41d4-9b30-7c5274b1bfff
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210011064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3210011064
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.983443965
Short name T550
Test name
Test status
Simulation time 577787324 ps
CPU time 15.37 seconds
Started Jul 26 04:25:42 PM PDT 24
Finished Jul 26 04:25:58 PM PDT 24
Peak memory 203936 kb
Host smart-e73d91a4-560d-42ca-8d4a-fc210b766a08
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=983443965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.983443965
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.976531441
Short name T456
Test name
Test status
Simulation time 62659412 ps
CPU time 2.85 seconds
Started Jul 26 04:25:24 PM PDT 24
Finished Jul 26 04:25:27 PM PDT 24
Peak memory 203312 kb
Host smart-369d2a9f-1228-4bda-9c0f-34557f12e4cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=976531441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.976531441
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.667893201
Short name T783
Test name
Test status
Simulation time 8710530098 ps
CPU time 30.05 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:25:48 PM PDT 24
Peak memory 203412 kb
Host smart-6d628d73-109e-4f14-abf9-dd866d34d6e5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=667893201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.667893201
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.3352211436
Short name T7
Test name
Test status
Simulation time 10367180889 ps
CPU time 38.97 seconds
Started Jul 26 04:25:24 PM PDT 24
Finished Jul 26 04:26:03 PM PDT 24
Peak memory 203368 kb
Host smart-bb59bfa4-25f3-4986-8f19-466ff754f41e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3352211436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3352211436
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3077349462
Short name T837
Test name
Test status
Simulation time 79843359 ps
CPU time 2.18 seconds
Started Jul 26 04:25:26 PM PDT 24
Finished Jul 26 04:25:29 PM PDT 24
Peak memory 203280 kb
Host smart-069dcdc0-76b8-4b92-909b-8888cfd72521
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077349462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3077349462
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.3558470945
Short name T872
Test name
Test status
Simulation time 16873267892 ps
CPU time 267.16 seconds
Started Jul 26 04:25:32 PM PDT 24
Finished Jul 26 04:29:59 PM PDT 24
Peak memory 207244 kb
Host smart-667ac7c2-1ccd-4f44-995b-4bbcac91c27d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3558470945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3558470945
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.663272953
Short name T605
Test name
Test status
Simulation time 1735926914 ps
CPU time 52.2 seconds
Started Jul 26 04:27:11 PM PDT 24
Finished Jul 26 04:28:03 PM PDT 24
Peak memory 204988 kb
Host smart-ad50eae4-f21d-4c12-80d9-6ee767305af6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=663272953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.663272953
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1000063124
Short name T40
Test name
Test status
Simulation time 5099521183 ps
CPU time 223.75 seconds
Started Jul 26 04:25:22 PM PDT 24
Finished Jul 26 04:29:06 PM PDT 24
Peak memory 210044 kb
Host smart-0678ec7c-6242-4b98-9095-0c152b117658
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1000063124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran
d_reset.1000063124
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.2181884353
Short name T721
Test name
Test status
Simulation time 2175974904 ps
CPU time 230.25 seconds
Started Jul 26 04:25:28 PM PDT 24
Finished Jul 26 04:29:18 PM PDT 24
Peak memory 211540 kb
Host smart-a29ccac2-8ac4-456e-8335-c0f1594c7123
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2181884353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re
set_error.2181884353
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.2303561668
Short name T806
Test name
Test status
Simulation time 341693974 ps
CPU time 11.26 seconds
Started Jul 26 04:25:21 PM PDT 24
Finished Jul 26 04:25:33 PM PDT 24
Peak memory 204664 kb
Host smart-297568fd-c048-4d34-ae6f-1164eafb7e38
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2303561668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2303561668
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.1127172756
Short name T158
Test name
Test status
Simulation time 149003999 ps
CPU time 18.45 seconds
Started Jul 26 04:25:21 PM PDT 24
Finished Jul 26 04:25:40 PM PDT 24
Peak memory 211388 kb
Host smart-0d2aed4a-2112-4cd8-8781-9040e1e0e985
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1127172756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.1127172756
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2112397878
Short name T123
Test name
Test status
Simulation time 96987903243 ps
CPU time 390.62 seconds
Started Jul 26 04:25:27 PM PDT 24
Finished Jul 26 04:31:58 PM PDT 24
Peak memory 211560 kb
Host smart-d583525c-d6ec-4c3b-9770-63ecff413c9b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2112397878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl
ow_rsp.2112397878
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.4244928367
Short name T417
Test name
Test status
Simulation time 1055402781 ps
CPU time 27.06 seconds
Started Jul 26 04:25:27 PM PDT 24
Finished Jul 26 04:25:55 PM PDT 24
Peak memory 203336 kb
Host smart-c37b5ffc-c94a-41f8-8497-b6205b1b0e81
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4244928367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.4244928367
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.2139642873
Short name T520
Test name
Test status
Simulation time 749430700 ps
CPU time 22.03 seconds
Started Jul 26 04:25:31 PM PDT 24
Finished Jul 26 04:25:53 PM PDT 24
Peak memory 211636 kb
Host smart-d67b57d4-207f-48e8-9276-85d82f8e7972
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2139642873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.2139642873
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.3501472549
Short name T653
Test name
Test status
Simulation time 12140880779 ps
CPU time 26.95 seconds
Started Jul 26 04:25:21 PM PDT 24
Finished Jul 26 04:25:49 PM PDT 24
Peak memory 211500 kb
Host smart-cae77329-b68b-488c-ad2f-e2cccdc3d634
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501472549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3501472549
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.714540899
Short name T292
Test name
Test status
Simulation time 1715303534 ps
CPU time 11.51 seconds
Started Jul 26 04:25:23 PM PDT 24
Finished Jul 26 04:25:35 PM PDT 24
Peak memory 203340 kb
Host smart-34766a37-4a8a-47cf-b0a8-74ae9a8d59a6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=714540899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.714540899
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.2590325577
Short name T130
Test name
Test status
Simulation time 305304796 ps
CPU time 15.8 seconds
Started Jul 26 04:25:24 PM PDT 24
Finished Jul 26 04:25:40 PM PDT 24
Peak memory 204416 kb
Host smart-406d914e-644a-4aca-a026-f4bf21deb7ce
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590325577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.2590325577
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.2352237643
Short name T375
Test name
Test status
Simulation time 126295859 ps
CPU time 7.12 seconds
Started Jul 26 04:25:24 PM PDT 24
Finished Jul 26 04:25:32 PM PDT 24
Peak memory 203280 kb
Host smart-f21a33e4-aefa-4b10-ba56-6154afabc6a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2352237643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2352237643
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.532689564
Short name T97
Test name
Test status
Simulation time 115117920 ps
CPU time 2.25 seconds
Started Jul 26 04:27:09 PM PDT 24
Finished Jul 26 04:27:11 PM PDT 24
Peak memory 203252 kb
Host smart-a15431a1-7926-4dcc-bd53-06f9d7ab6450
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=532689564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.532689564
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3369681343
Short name T867
Test name
Test status
Simulation time 6178265870 ps
CPU time 21.94 seconds
Started Jul 26 04:25:23 PM PDT 24
Finished Jul 26 04:25:45 PM PDT 24
Peak memory 203336 kb
Host smart-01d4223d-ff94-4237-91b2-f2b0d7611a69
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369681343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3369681343
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.616752792
Short name T733
Test name
Test status
Simulation time 3006437992 ps
CPU time 24.06 seconds
Started Jul 26 04:26:55 PM PDT 24
Finished Jul 26 04:27:19 PM PDT 24
Peak memory 201548 kb
Host smart-d64d48d4-8f64-4b0d-b37c-584b9184601c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=616752792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.616752792
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.536743182
Short name T534
Test name
Test status
Simulation time 33292332 ps
CPU time 2.43 seconds
Started Jul 26 04:25:23 PM PDT 24
Finished Jul 26 04:25:26 PM PDT 24
Peak memory 203276 kb
Host smart-d8ea5b99-f5fc-4eca-83b7-12a2f4a7d21b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536743182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.536743182
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.636914214
Short name T640
Test name
Test status
Simulation time 4791475181 ps
CPU time 146.72 seconds
Started Jul 26 04:25:39 PM PDT 24
Finished Jul 26 04:28:06 PM PDT 24
Peak memory 207032 kb
Host smart-3399eb10-c01a-42ac-a847-94ad0ca99500
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=636914214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.636914214
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2771560107
Short name T262
Test name
Test status
Simulation time 6789231715 ps
CPU time 199.94 seconds
Started Jul 26 04:25:32 PM PDT 24
Finished Jul 26 04:28:52 PM PDT 24
Peak memory 206828 kb
Host smart-3ae7c445-feb3-47cb-9ad8-8d1aad1f0cb8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2771560107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2771560107
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.312264396
Short name T785
Test name
Test status
Simulation time 719763930 ps
CPU time 207.3 seconds
Started Jul 26 04:25:23 PM PDT 24
Finished Jul 26 04:28:50 PM PDT 24
Peak memory 208024 kb
Host smart-1ba88f2c-3b71-4f03-bccf-530b996f975a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=312264396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand
_reset.312264396
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3994253652
Short name T741
Test name
Test status
Simulation time 302263288 ps
CPU time 50.18 seconds
Started Jul 26 04:25:21 PM PDT 24
Finished Jul 26 04:26:11 PM PDT 24
Peak memory 207648 kb
Host smart-68f569c7-6378-4217-8e28-b9ce76feb7c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3994253652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re
set_error.3994253652
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.2793701998
Short name T808
Test name
Test status
Simulation time 121408176 ps
CPU time 20.3 seconds
Started Jul 26 04:25:20 PM PDT 24
Finished Jul 26 04:25:41 PM PDT 24
Peak memory 205092 kb
Host smart-49541e86-7851-4507-89f2-cb6ad1c5484f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2793701998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2793701998
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.1235459724
Short name T449
Test name
Test status
Simulation time 3013999128 ps
CPU time 22.98 seconds
Started Jul 26 04:25:23 PM PDT 24
Finished Jul 26 04:25:46 PM PDT 24
Peak memory 204076 kb
Host smart-7f8432fc-cb97-44cb-a5d4-cbffa68cd9d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1235459724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.1235459724
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1094828466
Short name T635
Test name
Test status
Simulation time 21787506769 ps
CPU time 162.24 seconds
Started Jul 26 04:25:31 PM PDT 24
Finished Jul 26 04:28:14 PM PDT 24
Peak memory 211548 kb
Host smart-d9d5d9c4-a638-4ed0-abcd-63e71e33e30a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1094828466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl
ow_rsp.1094828466
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2092002263
Short name T754
Test name
Test status
Simulation time 85854110 ps
CPU time 10.46 seconds
Started Jul 26 04:25:29 PM PDT 24
Finished Jul 26 04:25:40 PM PDT 24
Peak memory 203324 kb
Host smart-80cad558-87bb-487d-94c5-4ce157d8afce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2092002263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2092002263
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.1316123685
Short name T542
Test name
Test status
Simulation time 1350388367 ps
CPU time 31.65 seconds
Started Jul 26 04:27:10 PM PDT 24
Finished Jul 26 04:27:42 PM PDT 24
Peak memory 203264 kb
Host smart-435d8749-867f-456c-a4ac-c305eba3e5b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1316123685 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1316123685
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.1464024588
Short name T226
Test name
Test status
Simulation time 123137060 ps
CPU time 4.44 seconds
Started Jul 26 04:25:24 PM PDT 24
Finished Jul 26 04:25:29 PM PDT 24
Peak memory 211384 kb
Host smart-08da9879-1fb5-4bf8-a368-3688c7bf6027
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1464024588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.1464024588
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.733384792
Short name T344
Test name
Test status
Simulation time 65678850920 ps
CPU time 113.31 seconds
Started Jul 26 04:25:22 PM PDT 24
Finished Jul 26 04:27:15 PM PDT 24
Peak memory 211532 kb
Host smart-cf680754-187a-4e74-8548-70a1bc287c09
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=733384792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.733384792
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2938482877
Short name T698
Test name
Test status
Simulation time 46373695085 ps
CPU time 197.27 seconds
Started Jul 26 04:25:27 PM PDT 24
Finished Jul 26 04:28:44 PM PDT 24
Peak memory 211556 kb
Host smart-0cdb2e0b-ad1f-4a44-95e0-5297e3e07974
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2938482877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2938482877
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.1083112797
Short name T801
Test name
Test status
Simulation time 15490342 ps
CPU time 2.13 seconds
Started Jul 26 04:25:27 PM PDT 24
Finished Jul 26 04:25:30 PM PDT 24
Peak memory 203312 kb
Host smart-5e7a8000-7799-4ce3-8618-a4cbea2051fd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083112797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.1083112797
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.3039025203
Short name T71
Test name
Test status
Simulation time 263233047 ps
CPU time 13.19 seconds
Started Jul 26 04:26:55 PM PDT 24
Finished Jul 26 04:27:08 PM PDT 24
Peak memory 201588 kb
Host smart-76f88126-d95d-47cb-8eb1-8c5cf730bae3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3039025203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3039025203
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.4279790031
Short name T642
Test name
Test status
Simulation time 183875242 ps
CPU time 3.67 seconds
Started Jul 26 04:25:23 PM PDT 24
Finished Jul 26 04:25:27 PM PDT 24
Peak memory 203268 kb
Host smart-1fb117b9-3e26-48ce-8f0d-038f8d47f943
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4279790031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.4279790031
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3472415959
Short name T739
Test name
Test status
Simulation time 13519531730 ps
CPU time 34.92 seconds
Started Jul 26 04:25:27 PM PDT 24
Finished Jul 26 04:26:02 PM PDT 24
Peak memory 203388 kb
Host smart-9b69b926-7284-48d7-afb5-79c0f9d4f445
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472415959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3472415959
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.1504103712
Short name T444
Test name
Test status
Simulation time 3826271022 ps
CPU time 30.83 seconds
Started Jul 26 04:25:23 PM PDT 24
Finished Jul 26 04:25:54 PM PDT 24
Peak memory 203352 kb
Host smart-05ab5348-a3b9-4f2a-a44a-9a02dcd4cd2a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1504103712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1504103712
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.3023763239
Short name T159
Test name
Test status
Simulation time 27046641 ps
CPU time 2.19 seconds
Started Jul 26 04:25:27 PM PDT 24
Finished Jul 26 04:25:29 PM PDT 24
Peak memory 203312 kb
Host smart-90f52223-8710-4bd4-99de-f9bd805260a6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023763239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.3023763239
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.4154158101
Short name T184
Test name
Test status
Simulation time 614484064 ps
CPU time 19.47 seconds
Started Jul 26 04:25:38 PM PDT 24
Finished Jul 26 04:25:57 PM PDT 24
Peak memory 205188 kb
Host smart-b4828fc3-5a99-4256-a11b-9137dc0c7ee6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4154158101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.4154158101
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.2848743078
Short name T440
Test name
Test status
Simulation time 7306257791 ps
CPU time 154.1 seconds
Started Jul 26 04:25:29 PM PDT 24
Finished Jul 26 04:28:03 PM PDT 24
Peak memory 207596 kb
Host smart-cede7507-094f-4cc3-b46a-f3c53a51f222
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2848743078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2848743078
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.317199689
Short name T85
Test name
Test status
Simulation time 6953329038 ps
CPU time 273.3 seconds
Started Jul 26 04:25:28 PM PDT 24
Finished Jul 26 04:30:01 PM PDT 24
Peak memory 208112 kb
Host smart-037ebc85-99f3-4f7a-b058-7c9a3239f628
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=317199689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand
_reset.317199689
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.2162653170
Short name T594
Test name
Test status
Simulation time 244960478 ps
CPU time 99.88 seconds
Started Jul 26 04:25:27 PM PDT 24
Finished Jul 26 04:27:07 PM PDT 24
Peak memory 209220 kb
Host smart-961d8a27-83f5-4969-9daa-6305cd2b0158
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2162653170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re
set_error.2162653170
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.3456203314
Short name T255
Test name
Test status
Simulation time 720558075 ps
CPU time 22.6 seconds
Started Jul 26 04:25:37 PM PDT 24
Finished Jul 26 04:26:00 PM PDT 24
Peak memory 211488 kb
Host smart-f0b29262-3a51-416f-8819-cd62a23cc647
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3456203314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.3456203314
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.3172918666
Short name T232
Test name
Test status
Simulation time 218022897 ps
CPU time 6.51 seconds
Started Jul 26 04:25:58 PM PDT 24
Finished Jul 26 04:26:04 PM PDT 24
Peak memory 203460 kb
Host smart-b1f09daf-bd44-498a-99db-e97c5f4bc831
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3172918666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.3172918666
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.2743000546
Short name T264
Test name
Test status
Simulation time 90913213275 ps
CPU time 495.29 seconds
Started Jul 26 04:25:57 PM PDT 24
Finished Jul 26 04:34:12 PM PDT 24
Peak memory 207108 kb
Host smart-56499168-8379-4a55-b726-862f3ee4fda7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2743000546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl
ow_rsp.2743000546
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.4062796881
Short name T361
Test name
Test status
Simulation time 496821135 ps
CPU time 10 seconds
Started Jul 26 04:25:42 PM PDT 24
Finished Jul 26 04:25:53 PM PDT 24
Peak memory 203328 kb
Host smart-2bf9cd63-d70a-4dce-bf43-e65bbf2d5f6f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4062796881 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.4062796881
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.3047331596
Short name T781
Test name
Test status
Simulation time 1415466482 ps
CPU time 25.74 seconds
Started Jul 26 04:25:30 PM PDT 24
Finished Jul 26 04:25:56 PM PDT 24
Peak memory 203332 kb
Host smart-07254ab7-376c-4f41-90f0-020d82f7d1d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3047331596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3047331596
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.2488457577
Short name T74
Test name
Test status
Simulation time 996658153 ps
CPU time 15.77 seconds
Started Jul 26 04:25:30 PM PDT 24
Finished Jul 26 04:25:46 PM PDT 24
Peak memory 204436 kb
Host smart-b977b521-4cf8-4415-a8ab-4c4e5fee4669
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2488457577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.2488457577
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.1617410192
Short name T465
Test name
Test status
Simulation time 35254355932 ps
CPU time 192.69 seconds
Started Jul 26 04:26:10 PM PDT 24
Finished Jul 26 04:29:23 PM PDT 24
Peak memory 211528 kb
Host smart-0a2d5a76-d8c0-444c-b552-434a51948fff
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617410192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.1617410192
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.3215151323
Short name T93
Test name
Test status
Simulation time 30541272816 ps
CPU time 212.58 seconds
Started Jul 26 04:25:27 PM PDT 24
Finished Jul 26 04:29:00 PM PDT 24
Peak memory 211612 kb
Host smart-5f31f5df-6bd5-47a8-8e36-8f684a6ee213
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3215151323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3215151323
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.2960942944
Short name T598
Test name
Test status
Simulation time 108558706 ps
CPU time 12.23 seconds
Started Jul 26 04:25:27 PM PDT 24
Finished Jul 26 04:25:40 PM PDT 24
Peak memory 204388 kb
Host smart-f00b2e42-48c4-4ff6-931e-76e9b5fc59d5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960942944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2960942944
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.2408746656
Short name T360
Test name
Test status
Simulation time 1761015121 ps
CPU time 23.35 seconds
Started Jul 26 04:25:32 PM PDT 24
Finished Jul 26 04:25:56 PM PDT 24
Peak memory 203884 kb
Host smart-b2f95535-5fe5-496a-b9ac-b2281863d8f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2408746656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2408746656
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.377910585
Short name T304
Test name
Test status
Simulation time 101987898 ps
CPU time 3.08 seconds
Started Jul 26 04:25:28 PM PDT 24
Finished Jul 26 04:25:32 PM PDT 24
Peak memory 203304 kb
Host smart-fc21a57d-a67b-42c8-9aac-e6ad30b0289a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=377910585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.377910585
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.1011113419
Short name T673
Test name
Test status
Simulation time 8228926878 ps
CPU time 35.45 seconds
Started Jul 26 04:26:08 PM PDT 24
Finished Jul 26 04:26:44 PM PDT 24
Peak memory 203328 kb
Host smart-e5240029-eee5-4606-acbf-121f426e5132
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011113419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1011113419
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.3217517337
Short name T892
Test name
Test status
Simulation time 4056490007 ps
CPU time 30.42 seconds
Started Jul 26 04:26:11 PM PDT 24
Finished Jul 26 04:26:42 PM PDT 24
Peak memory 203364 kb
Host smart-394a7a33-0865-402a-be15-cf3ba5462e50
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3217517337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3217517337
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3234072159
Short name T180
Test name
Test status
Simulation time 61233880 ps
CPU time 2.36 seconds
Started Jul 26 04:25:33 PM PDT 24
Finished Jul 26 04:25:35 PM PDT 24
Peak memory 203288 kb
Host smart-bb8eb9aa-9124-4698-a1fd-46e7a0ff6cbb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234072159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3234072159
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.996779013
Short name T835
Test name
Test status
Simulation time 902758067 ps
CPU time 35.44 seconds
Started Jul 26 04:25:32 PM PDT 24
Finished Jul 26 04:26:08 PM PDT 24
Peak memory 211408 kb
Host smart-ba3fbdb9-bf2e-4257-8543-4ea542a4b275
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=996779013 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.996779013
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.249905079
Short name T682
Test name
Test status
Simulation time 466212718 ps
CPU time 143.39 seconds
Started Jul 26 04:25:30 PM PDT 24
Finished Jul 26 04:27:54 PM PDT 24
Peak memory 208752 kb
Host smart-533b300d-8740-4f0a-9364-38ab92a895c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=249905079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand
_reset.249905079
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3979884791
Short name T252
Test name
Test status
Simulation time 2862353236 ps
CPU time 160.05 seconds
Started Jul 26 04:26:19 PM PDT 24
Finished Jul 26 04:28:59 PM PDT 24
Peak memory 209428 kb
Host smart-5fff9882-c9fa-41ba-b595-0385c0301bb4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3979884791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re
set_error.3979884791
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.1541165963
Short name T886
Test name
Test status
Simulation time 84782657 ps
CPU time 8.28 seconds
Started Jul 26 04:26:05 PM PDT 24
Finished Jul 26 04:26:14 PM PDT 24
Peak memory 211444 kb
Host smart-2d6351b1-4e61-4ac7-8e7c-34b7e6a8b7d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1541165963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1541165963
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.223417086
Short name T531
Test name
Test status
Simulation time 502923662 ps
CPU time 11.09 seconds
Started Jul 26 04:25:29 PM PDT 24
Finished Jul 26 04:25:41 PM PDT 24
Peak memory 211500 kb
Host smart-5a5f096b-aecd-48af-ac94-8a9eccf05c57
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=223417086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.223417086
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2589170622
Short name T487
Test name
Test status
Simulation time 314327035215 ps
CPU time 777.11 seconds
Started Jul 26 04:25:29 PM PDT 24
Finished Jul 26 04:38:27 PM PDT 24
Peak memory 205860 kb
Host smart-dfa30e02-9918-4a5b-820d-5f68287cbd94
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2589170622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl
ow_rsp.2589170622
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.619693002
Short name T851
Test name
Test status
Simulation time 825410574 ps
CPU time 18.41 seconds
Started Jul 26 04:25:29 PM PDT 24
Finished Jul 26 04:25:48 PM PDT 24
Peak memory 203360 kb
Host smart-62659235-f070-468a-8a9a-4f1b96d38e38
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=619693002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.619693002
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.2205434384
Short name T19
Test name
Test status
Simulation time 236210524 ps
CPU time 5.11 seconds
Started Jul 26 04:26:10 PM PDT 24
Finished Jul 26 04:26:15 PM PDT 24
Peak memory 203292 kb
Host smart-e7fc2906-56ad-4e3b-83af-6a8eb825b944
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2205434384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2205434384
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.538824674
Short name T446
Test name
Test status
Simulation time 385118159 ps
CPU time 13.89 seconds
Started Jul 26 04:25:37 PM PDT 24
Finished Jul 26 04:25:51 PM PDT 24
Peak memory 204572 kb
Host smart-575971ed-ff7f-474d-a15f-d042ec324ab3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=538824674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.538824674
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.430201562
Short name T213
Test name
Test status
Simulation time 13686991884 ps
CPU time 80.45 seconds
Started Jul 26 04:25:28 PM PDT 24
Finished Jul 26 04:26:49 PM PDT 24
Peak memory 211484 kb
Host smart-351ec55e-5b58-46bc-a0da-3723b975db18
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=430201562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.430201562
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2009646150
Short name T395
Test name
Test status
Simulation time 8310048651 ps
CPU time 75.4 seconds
Started Jul 26 04:25:36 PM PDT 24
Finished Jul 26 04:26:51 PM PDT 24
Peak memory 211540 kb
Host smart-c4d8fc44-83df-4bb5-96d2-630486f07ae5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2009646150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2009646150
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.2331616709
Short name T811
Test name
Test status
Simulation time 149197502 ps
CPU time 14.33 seconds
Started Jul 26 04:26:12 PM PDT 24
Finished Jul 26 04:26:26 PM PDT 24
Peak memory 211476 kb
Host smart-2efc1cb8-e3fe-4624-af34-e0e1b19e3481
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331616709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.2331616709
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.1576461652
Short name T608
Test name
Test status
Simulation time 161935595 ps
CPU time 6.51 seconds
Started Jul 26 04:25:36 PM PDT 24
Finished Jul 26 04:25:43 PM PDT 24
Peak memory 203356 kb
Host smart-be1b9d39-d426-42aa-b309-258171f00387
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1576461652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1576461652
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.1683101420
Short name T584
Test name
Test status
Simulation time 346212961 ps
CPU time 3.27 seconds
Started Jul 26 04:25:30 PM PDT 24
Finished Jul 26 04:25:33 PM PDT 24
Peak memory 203332 kb
Host smart-bf6249f6-43a4-4247-953a-8022ef501264
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1683101420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1683101420
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.902996842
Short name T353
Test name
Test status
Simulation time 8759840946 ps
CPU time 32.54 seconds
Started Jul 26 04:25:42 PM PDT 24
Finished Jul 26 04:26:15 PM PDT 24
Peak memory 203412 kb
Host smart-da6795e3-bb11-4299-9c7e-c88ff2daab15
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=902996842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.902996842
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2476815187
Short name T663
Test name
Test status
Simulation time 4007908119 ps
CPU time 31.2 seconds
Started Jul 26 04:26:11 PM PDT 24
Finished Jul 26 04:26:43 PM PDT 24
Peak memory 203312 kb
Host smart-c5042474-bd64-41f1-94e2-98c37425dc4a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2476815187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2476815187
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.4188629457
Short name T480
Test name
Test status
Simulation time 120547645 ps
CPU time 2.23 seconds
Started Jul 26 04:25:31 PM PDT 24
Finished Jul 26 04:25:33 PM PDT 24
Peak memory 203200 kb
Host smart-e00396ef-5203-4e5c-865f-5b3d17ee002a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188629457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.4188629457
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.2395757413
Short name T265
Test name
Test status
Simulation time 868946320 ps
CPU time 27.24 seconds
Started Jul 26 04:25:32 PM PDT 24
Finished Jul 26 04:25:59 PM PDT 24
Peak memory 205764 kb
Host smart-5a0ff5a4-0f79-4993-8287-ac1b8a83bc74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2395757413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2395757413
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.907668202
Short name T509
Test name
Test status
Simulation time 2028169082 ps
CPU time 33.69 seconds
Started Jul 26 04:26:19 PM PDT 24
Finished Jul 26 04:26:53 PM PDT 24
Peak memory 204332 kb
Host smart-9335f9fe-4556-492b-9d3d-0ec6ee91cadf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=907668202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.907668202
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2615479476
Short name T876
Test name
Test status
Simulation time 826000043 ps
CPU time 367.96 seconds
Started Jul 26 04:25:58 PM PDT 24
Finished Jul 26 04:32:06 PM PDT 24
Peak memory 210852 kb
Host smart-10459e5e-26cd-48f6-b110-6dce876faf86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2615479476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran
d_reset.2615479476
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3180967412
Short name T666
Test name
Test status
Simulation time 602311749 ps
CPU time 125.15 seconds
Started Jul 26 04:25:42 PM PDT 24
Finished Jul 26 04:27:48 PM PDT 24
Peak memory 209948 kb
Host smart-338401a9-2aba-48de-a46e-07b17e197d10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3180967412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re
set_error.3180967412
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.2981366377
Short name T110
Test name
Test status
Simulation time 2299213697 ps
CPU time 35.02 seconds
Started Jul 26 04:25:27 PM PDT 24
Finished Jul 26 04:26:02 PM PDT 24
Peak memory 204928 kb
Host smart-bba84384-2464-4aa3-b330-92853c6f5579
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2981366377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.2981366377
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.1840012688
Short name T814
Test name
Test status
Simulation time 131394331 ps
CPU time 11.06 seconds
Started Jul 26 04:26:26 PM PDT 24
Finished Jul 26 04:26:37 PM PDT 24
Peak memory 205364 kb
Host smart-20ac0d4d-823d-414d-9ebc-c145dc29455b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1840012688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.1840012688
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1500721198
Short name T65
Test name
Test status
Simulation time 122048111293 ps
CPU time 641.5 seconds
Started Jul 26 04:25:38 PM PDT 24
Finished Jul 26 04:36:20 PM PDT 24
Peak memory 211584 kb
Host smart-b1d1137b-ce4e-4b38-86dd-e2d5e009eede
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1500721198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl
ow_rsp.1500721198
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.278299673
Short name T451
Test name
Test status
Simulation time 65956567 ps
CPU time 7.86 seconds
Started Jul 26 04:25:37 PM PDT 24
Finished Jul 26 04:25:45 PM PDT 24
Peak memory 203308 kb
Host smart-b8aca62b-738a-4eb6-b0ec-d9fa73c70a33
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=278299673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.278299673
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.1168153437
Short name T193
Test name
Test status
Simulation time 6040121210 ps
CPU time 33.98 seconds
Started Jul 26 04:26:46 PM PDT 24
Finished Jul 26 04:27:21 PM PDT 24
Peak memory 203372 kb
Host smart-299f08c1-7c31-435d-aa4b-f1b04275a7e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1168153437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1168153437
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.1203985183
Short name T654
Test name
Test status
Simulation time 89928259 ps
CPU time 3.05 seconds
Started Jul 26 04:26:05 PM PDT 24
Finished Jul 26 04:26:08 PM PDT 24
Peak memory 203716 kb
Host smart-9b364e6c-a12a-4f49-91d4-aad683abcd30
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1203985183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1203985183
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.489671945
Short name T661
Test name
Test status
Simulation time 36451191660 ps
CPU time 207.53 seconds
Started Jul 26 04:26:28 PM PDT 24
Finished Jul 26 04:29:55 PM PDT 24
Peak memory 211404 kb
Host smart-0083af75-4984-4df6-8ba7-dc30031fa8ad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=489671945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.489671945
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.2239899477
Short name T374
Test name
Test status
Simulation time 194543008017 ps
CPU time 446.12 seconds
Started Jul 26 04:25:35 PM PDT 24
Finished Jul 26 04:33:01 PM PDT 24
Peak memory 211564 kb
Host smart-d158643a-eee9-4ed3-b4f9-d6b1a9af783e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2239899477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2239899477
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.2611312810
Short name T14
Test name
Test status
Simulation time 370725638 ps
CPU time 14.33 seconds
Started Jul 26 04:25:35 PM PDT 24
Finished Jul 26 04:25:49 PM PDT 24
Peak memory 211448 kb
Host smart-eec6f612-fd0c-4594-97ae-37e156a0a29f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611312810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.2611312810
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.1257066193
Short name T18
Test name
Test status
Simulation time 171372722 ps
CPU time 10.55 seconds
Started Jul 26 04:25:35 PM PDT 24
Finished Jul 26 04:25:46 PM PDT 24
Peak memory 203276 kb
Host smart-3b80c5db-c27e-47ab-944a-1b985f419ad0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1257066193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1257066193
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.3987168881
Short name T699
Test name
Test status
Simulation time 146202256 ps
CPU time 2.74 seconds
Started Jul 26 04:26:11 PM PDT 24
Finished Jul 26 04:26:14 PM PDT 24
Peak memory 203240 kb
Host smart-e76e92e9-9064-48bf-9bdd-10b054cf7662
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3987168881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3987168881
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.1643591584
Short name T306
Test name
Test status
Simulation time 12292070417 ps
CPU time 30.15 seconds
Started Jul 26 04:26:14 PM PDT 24
Finished Jul 26 04:26:44 PM PDT 24
Peak memory 203312 kb
Host smart-6409472f-cdf8-410f-a4c9-f1a60834181a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643591584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1643591584
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3175790869
Short name T807
Test name
Test status
Simulation time 3825239737 ps
CPU time 25.33 seconds
Started Jul 26 04:25:34 PM PDT 24
Finished Jul 26 04:25:59 PM PDT 24
Peak memory 203760 kb
Host smart-b0bfd407-9ab5-4cde-a062-c63687153b0d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3175790869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3175790869
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2208007071
Short name T470
Test name
Test status
Simulation time 34875357 ps
CPU time 2.11 seconds
Started Jul 26 04:25:35 PM PDT 24
Finished Jul 26 04:25:38 PM PDT 24
Peak memory 203256 kb
Host smart-d267f07e-d08f-4bfc-a599-13c7db606139
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208007071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2208007071
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.2858992478
Short name T555
Test name
Test status
Simulation time 7895279347 ps
CPU time 80.1 seconds
Started Jul 26 04:26:55 PM PDT 24
Finished Jul 26 04:28:16 PM PDT 24
Peak memory 205956 kb
Host smart-209e328c-a065-4192-a8ab-d5d2a28a9869
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2858992478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.2858992478
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.4278494456
Short name T500
Test name
Test status
Simulation time 2568088466 ps
CPU time 170.36 seconds
Started Jul 26 04:25:34 PM PDT 24
Finished Jul 26 04:28:25 PM PDT 24
Peak memory 211048 kb
Host smart-e69d5928-87c0-4f69-92fe-47b50833b4af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4278494456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.4278494456
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.648907521
Short name T86
Test name
Test status
Simulation time 5607747481 ps
CPU time 398.24 seconds
Started Jul 26 04:26:55 PM PDT 24
Finished Jul 26 04:33:33 PM PDT 24
Peak memory 207708 kb
Host smart-81786f4a-320f-4670-b43f-508d73a4ab5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=648907521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand
_reset.648907521
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.931829752
Short name T704
Test name
Test status
Simulation time 581471633 ps
CPU time 139.93 seconds
Started Jul 26 04:26:37 PM PDT 24
Finished Jul 26 04:28:57 PM PDT 24
Peak memory 210636 kb
Host smart-10fad0fb-8358-40b6-88a2-76ea7d15419f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=931829752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_res
et_error.931829752
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.2020402184
Short name T725
Test name
Test status
Simulation time 157599308 ps
CPU time 12.77 seconds
Started Jul 26 04:26:55 PM PDT 24
Finished Jul 26 04:27:08 PM PDT 24
Peak memory 211172 kb
Host smart-df3eb812-da91-41bd-9cfc-12dc6d3af57f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2020402184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2020402184
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.2261586432
Short name T132
Test name
Test status
Simulation time 97417860 ps
CPU time 4 seconds
Started Jul 26 04:24:28 PM PDT 24
Finished Jul 26 04:24:32 PM PDT 24
Peak memory 201368 kb
Host smart-b0e39686-24e8-4765-9e9b-89307c20ace5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2261586432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.2261586432
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3152869726
Short name T117
Test name
Test status
Simulation time 61665570339 ps
CPU time 343.41 seconds
Started Jul 26 04:25:13 PM PDT 24
Finished Jul 26 04:30:57 PM PDT 24
Peak memory 206092 kb
Host smart-5e2eb723-e575-4cf6-8b35-e5ac208d300e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3152869726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo
w_rsp.3152869726
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3281974152
Short name T99
Test name
Test status
Simulation time 118979135 ps
CPU time 11.09 seconds
Started Jul 26 04:21:43 PM PDT 24
Finished Jul 26 04:21:54 PM PDT 24
Peak memory 203372 kb
Host smart-6951c869-8f1b-4ec8-b1ac-940f85e5b635
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3281974152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3281974152
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.3882159429
Short name T206
Test name
Test status
Simulation time 162217067 ps
CPU time 7.89 seconds
Started Jul 26 04:20:37 PM PDT 24
Finished Jul 26 04:20:45 PM PDT 24
Peak memory 203660 kb
Host smart-280ccc41-6542-4fa8-87ba-b7b6960dda59
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3882159429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3882159429
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.95113119
Short name T849
Test name
Test status
Simulation time 874684541 ps
CPU time 26.37 seconds
Started Jul 26 04:24:29 PM PDT 24
Finished Jul 26 04:24:55 PM PDT 24
Peak memory 211132 kb
Host smart-f1db7b6e-abb9-4598-b4df-d72f172e04e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=95113119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.95113119
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.966209194
Short name T273
Test name
Test status
Simulation time 75098132950 ps
CPU time 184.96 seconds
Started Jul 26 04:25:13 PM PDT 24
Finished Jul 26 04:28:18 PM PDT 24
Peak memory 204332 kb
Host smart-02d9317d-f141-40b0-b0ca-d0ef7d8d89fd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=966209194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.966209194
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.2568562129
Short name T175
Test name
Test status
Simulation time 33267030279 ps
CPU time 235.87 seconds
Started Jul 26 04:24:00 PM PDT 24
Finished Jul 26 04:27:56 PM PDT 24
Peak memory 211576 kb
Host smart-cc48ea8a-5a85-4a63-a934-59148dd06210
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2568562129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2568562129
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.24057161
Short name T570
Test name
Test status
Simulation time 1117899590 ps
CPU time 24.12 seconds
Started Jul 26 04:24:30 PM PDT 24
Finished Jul 26 04:24:54 PM PDT 24
Peak memory 203392 kb
Host smart-48fb5daf-a01d-4b3d-813f-18e0211586c3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24057161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.24057161
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.425483189
Short name T894
Test name
Test status
Simulation time 67055933 ps
CPU time 5.28 seconds
Started Jul 26 04:25:25 PM PDT 24
Finished Jul 26 04:25:31 PM PDT 24
Peak memory 203276 kb
Host smart-e18bef9f-4c4b-45d0-90e2-a64e68ca9f80
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=425483189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.425483189
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.3302693919
Short name T376
Test name
Test status
Simulation time 296962544 ps
CPU time 3.39 seconds
Started Jul 26 04:24:42 PM PDT 24
Finished Jul 26 04:24:45 PM PDT 24
Peak memory 203096 kb
Host smart-3456f846-efd4-4b07-b925-bb2f53577cb5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3302693919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3302693919
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.332039572
Short name T724
Test name
Test status
Simulation time 11539456902 ps
CPU time 34.58 seconds
Started Jul 26 04:24:28 PM PDT 24
Finished Jul 26 04:25:03 PM PDT 24
Peak memory 201620 kb
Host smart-e83cb7f2-268a-4b27-948e-803e700569e0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=332039572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.332039572
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.1754602939
Short name T420
Test name
Test status
Simulation time 4282153122 ps
CPU time 26.09 seconds
Started Jul 26 04:25:25 PM PDT 24
Finished Jul 26 04:25:52 PM PDT 24
Peak memory 203356 kb
Host smart-1b746132-6399-4556-a856-109bb3cf1e81
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1754602939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1754602939
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.736534924
Short name T285
Test name
Test status
Simulation time 66239239 ps
CPU time 2.11 seconds
Started Jul 26 04:25:25 PM PDT 24
Finished Jul 26 04:25:27 PM PDT 24
Peak memory 203128 kb
Host smart-df524611-2319-49c7-bca9-6a28ebe2a094
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736534924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.736534924
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.4265500852
Short name T796
Test name
Test status
Simulation time 715963706 ps
CPU time 50.63 seconds
Started Jul 26 04:24:42 PM PDT 24
Finished Jul 26 04:25:33 PM PDT 24
Peak memory 205308 kb
Host smart-2fb17357-312c-4b90-b937-ac40ea7fdf3f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4265500852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.4265500852
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.3673243847
Short name T767
Test name
Test status
Simulation time 7254656593 ps
CPU time 99.73 seconds
Started Jul 26 04:20:49 PM PDT 24
Finished Jul 26 04:22:29 PM PDT 24
Peak memory 205012 kb
Host smart-926edcc4-11a5-4822-8fd2-0d750e671898
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3673243847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3673243847
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.3066681489
Short name T92
Test name
Test status
Simulation time 9430843627 ps
CPU time 302.95 seconds
Started Jul 26 04:25:13 PM PDT 24
Finished Jul 26 04:30:16 PM PDT 24
Peak memory 208080 kb
Host smart-b6932d64-347e-4e2c-ab17-430fd50f0eb3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3066681489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand
_reset.3066681489
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.1388319627
Short name T39
Test name
Test status
Simulation time 54270876 ps
CPU time 18.57 seconds
Started Jul 26 04:20:26 PM PDT 24
Finished Jul 26 04:20:44 PM PDT 24
Peak memory 205328 kb
Host smart-80800f79-89f8-4b87-8196-6f61d2901043
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1388319627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res
et_error.1388319627
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.1242072435
Short name T657
Test name
Test status
Simulation time 1374013534 ps
CPU time 21.9 seconds
Started Jul 26 04:23:17 PM PDT 24
Finished Jul 26 04:23:39 PM PDT 24
Peak memory 211492 kb
Host smart-1aa6879c-292e-43c5-9f16-f400d9a9203f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1242072435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1242072435
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.443831202
Short name T889
Test name
Test status
Simulation time 1953741564 ps
CPU time 63.84 seconds
Started Jul 26 04:25:52 PM PDT 24
Finished Jul 26 04:26:56 PM PDT 24
Peak memory 211556 kb
Host smart-ed4ea3a9-1b52-436c-8694-7b80f586b8a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=443831202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.443831202
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3848841766
Short name T731
Test name
Test status
Simulation time 11158649247 ps
CPU time 79.03 seconds
Started Jul 26 04:25:47 PM PDT 24
Finished Jul 26 04:27:06 PM PDT 24
Peak memory 211540 kb
Host smart-d52c1778-3f52-48ae-a8b7-c65d5a440f0f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3848841766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl
ow_rsp.3848841766
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.638716973
Short name T826
Test name
Test status
Simulation time 1022995074 ps
CPU time 24.86 seconds
Started Jul 26 04:25:43 PM PDT 24
Finished Jul 26 04:26:08 PM PDT 24
Peak memory 203328 kb
Host smart-06009bd4-1aa1-4898-811f-21e810b7a5de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=638716973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.638716973
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.2208398444
Short name T777
Test name
Test status
Simulation time 199873732 ps
CPU time 17.13 seconds
Started Jul 26 04:25:42 PM PDT 24
Finished Jul 26 04:26:00 PM PDT 24
Peak memory 203268 kb
Host smart-29f93230-6804-4251-98c5-468f9e43ddd2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2208398444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2208398444
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.2080836290
Short name T409
Test name
Test status
Simulation time 786197523 ps
CPU time 20.51 seconds
Started Jul 26 04:25:52 PM PDT 24
Finished Jul 26 04:26:12 PM PDT 24
Peak memory 211484 kb
Host smart-02509e01-8cab-44ae-b616-93add21114b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2080836290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.2080836290
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.2425187218
Short name T343
Test name
Test status
Simulation time 23741661355 ps
CPU time 117.03 seconds
Started Jul 26 04:25:48 PM PDT 24
Finished Jul 26 04:27:45 PM PDT 24
Peak memory 204960 kb
Host smart-988e82f8-9d89-45f8-a693-48b066b8cb4b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425187218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2425187218
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.3962156734
Short name T797
Test name
Test status
Simulation time 36610974985 ps
CPU time 135.72 seconds
Started Jul 26 04:25:48 PM PDT 24
Finished Jul 26 04:28:04 PM PDT 24
Peak memory 204744 kb
Host smart-ddde5cc7-6cda-4a87-b274-09af3c7f138c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3962156734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3962156734
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.2808562254
Short name T687
Test name
Test status
Simulation time 136897110 ps
CPU time 17.84 seconds
Started Jul 26 04:25:41 PM PDT 24
Finished Jul 26 04:25:59 PM PDT 24
Peak memory 204624 kb
Host smart-e2c234ad-3986-4891-bc1c-0cb438ee7ac0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808562254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.2808562254
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.2421915159
Short name T540
Test name
Test status
Simulation time 384389286 ps
CPU time 11.92 seconds
Started Jul 26 04:25:56 PM PDT 24
Finished Jul 26 04:26:08 PM PDT 24
Peak memory 203332 kb
Host smart-573d6bb5-1a6a-4e53-8abe-8b58ce8684a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2421915159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2421915159
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.2884430622
Short name T719
Test name
Test status
Simulation time 143558797 ps
CPU time 3.71 seconds
Started Jul 26 04:26:15 PM PDT 24
Finished Jul 26 04:26:19 PM PDT 24
Peak memory 203268 kb
Host smart-90badbe5-e0c5-456d-ba39-741ce4a7ca3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2884430622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2884430622
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.2091112445
Short name T669
Test name
Test status
Simulation time 7893282852 ps
CPU time 27.34 seconds
Started Jul 26 04:25:51 PM PDT 24
Finished Jul 26 04:26:18 PM PDT 24
Peak memory 203380 kb
Host smart-0165c961-e859-4045-9934-5428d976f5af
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091112445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2091112445
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.3199995218
Short name T48
Test name
Test status
Simulation time 9371395566 ps
CPU time 21.66 seconds
Started Jul 26 04:25:43 PM PDT 24
Finished Jul 26 04:26:05 PM PDT 24
Peak memory 203344 kb
Host smart-b02e044e-4c6a-4042-acd5-5612cf804432
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3199995218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3199995218
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1207032991
Short name T816
Test name
Test status
Simulation time 70955993 ps
CPU time 2.39 seconds
Started Jul 26 04:26:55 PM PDT 24
Finished Jul 26 04:26:57 PM PDT 24
Peak memory 201824 kb
Host smart-63a4d4d9-385c-4a9f-ad9c-a3d3a855a680
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207032991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1207032991
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.1517573921
Short name T624
Test name
Test status
Simulation time 823594334 ps
CPU time 27.7 seconds
Started Jul 26 04:25:41 PM PDT 24
Finished Jul 26 04:26:09 PM PDT 24
Peak memory 205500 kb
Host smart-12db771f-a6de-48ac-b553-502e25552c2e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1517573921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1517573921
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2346131231
Short name T848
Test name
Test status
Simulation time 458228429 ps
CPU time 42.95 seconds
Started Jul 26 04:25:43 PM PDT 24
Finished Jul 26 04:26:26 PM PDT 24
Peak memory 211480 kb
Host smart-a0aed294-f6d5-46be-8e2c-ea2d9ca06833
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2346131231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2346131231
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.301677277
Short name T45
Test name
Test status
Simulation time 936646294 ps
CPU time 289.82 seconds
Started Jul 26 04:25:40 PM PDT 24
Finished Jul 26 04:30:30 PM PDT 24
Peak memory 208384 kb
Host smart-14a716e4-5a5a-4657-9359-e336c345b4de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=301677277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand
_reset.301677277
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3470021452
Short name T37
Test name
Test status
Simulation time 2036099299 ps
CPU time 252.51 seconds
Started Jul 26 04:25:50 PM PDT 24
Finished Jul 26 04:30:03 PM PDT 24
Peak memory 211484 kb
Host smart-e14210f2-9fb7-484a-a4d5-627f46c9d8bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3470021452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re
set_error.3470021452
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.1268424616
Short name T748
Test name
Test status
Simulation time 119735495 ps
CPU time 9.92 seconds
Started Jul 26 04:25:56 PM PDT 24
Finished Jul 26 04:26:06 PM PDT 24
Peak memory 211512 kb
Host smart-672817ca-5c6d-4a87-aad1-c544f7d0290e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1268424616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1268424616
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1416298759
Short name T170
Test name
Test status
Simulation time 169441256 ps
CPU time 21.12 seconds
Started Jul 26 04:25:53 PM PDT 24
Finished Jul 26 04:26:14 PM PDT 24
Peak memory 204376 kb
Host smart-1f0ea465-6f4a-4b1e-b1e6-0f5078b4576e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1416298759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1416298759
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.4005734110
Short name T120
Test name
Test status
Simulation time 143863564947 ps
CPU time 622.86 seconds
Started Jul 26 04:25:53 PM PDT 24
Finished Jul 26 04:36:16 PM PDT 24
Peak memory 205876 kb
Host smart-1af11c69-0c9f-41af-b718-252c8b2bbdb4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4005734110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl
ow_rsp.4005734110
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.1842480181
Short name T457
Test name
Test status
Simulation time 398763932 ps
CPU time 12.8 seconds
Started Jul 26 04:25:55 PM PDT 24
Finished Jul 26 04:26:08 PM PDT 24
Peak memory 203724 kb
Host smart-7e5ed6ed-17a9-48c0-b5bf-442736edbbf2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1842480181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.1842480181
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.3935237194
Short name T422
Test name
Test status
Simulation time 264970974 ps
CPU time 8.3 seconds
Started Jul 26 04:25:56 PM PDT 24
Finished Jul 26 04:26:05 PM PDT 24
Peak memory 203328 kb
Host smart-2826c678-1d46-45d8-bc9f-dc63e155e30d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3935237194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3935237194
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.566809527
Short name T473
Test name
Test status
Simulation time 59187829 ps
CPU time 8.17 seconds
Started Jul 26 04:26:05 PM PDT 24
Finished Jul 26 04:26:14 PM PDT 24
Peak memory 204380 kb
Host smart-5eaf7403-04cf-4ced-8c5f-30403cc0431c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=566809527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.566809527
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.808551681
Short name T562
Test name
Test status
Simulation time 74704457670 ps
CPU time 187.95 seconds
Started Jul 26 04:25:53 PM PDT 24
Finished Jul 26 04:29:01 PM PDT 24
Peak memory 211552 kb
Host smart-001c1e2d-83a9-4c15-bfd1-e9cad85eb729
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=808551681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.808551681
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2671880628
Short name T203
Test name
Test status
Simulation time 8417015553 ps
CPU time 63.55 seconds
Started Jul 26 04:25:52 PM PDT 24
Finished Jul 26 04:26:56 PM PDT 24
Peak memory 211460 kb
Host smart-180bd7e0-115a-4f1f-9b74-36d59dca44a8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2671880628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2671880628
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.4179731304
Short name T390
Test name
Test status
Simulation time 233102093 ps
CPU time 22.18 seconds
Started Jul 26 04:25:55 PM PDT 24
Finished Jul 26 04:26:17 PM PDT 24
Peak memory 204464 kb
Host smart-ea3e5e0c-cfa3-4d4a-86a7-2653d386627e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179731304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.4179731304
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.3634302056
Short name T539
Test name
Test status
Simulation time 3201222113 ps
CPU time 13.12 seconds
Started Jul 26 04:25:54 PM PDT 24
Finished Jul 26 04:26:07 PM PDT 24
Peak memory 203924 kb
Host smart-10dd5469-684c-400c-bef9-d02cbf435aae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3634302056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3634302056
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.1249456559
Short name T216
Test name
Test status
Simulation time 393032378 ps
CPU time 3.61 seconds
Started Jul 26 04:25:57 PM PDT 24
Finished Jul 26 04:26:01 PM PDT 24
Peak memory 203312 kb
Host smart-256c4d63-532c-4e77-8acc-818bca4d1b7e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1249456559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1249456559
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.4258473613
Short name T647
Test name
Test status
Simulation time 12755788455 ps
CPU time 36.69 seconds
Started Jul 26 04:25:52 PM PDT 24
Finished Jul 26 04:26:29 PM PDT 24
Peak memory 203424 kb
Host smart-024df66c-eeba-4c0a-90d7-04e075101694
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258473613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.4258473613
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.472257526
Short name T791
Test name
Test status
Simulation time 5641371997 ps
CPU time 34.32 seconds
Started Jul 26 04:25:57 PM PDT 24
Finished Jul 26 04:26:32 PM PDT 24
Peak memory 203384 kb
Host smart-951479a6-8202-4702-9959-6e0a65b3a942
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=472257526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.472257526
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.1581829859
Short name T641
Test name
Test status
Simulation time 25053896 ps
CPU time 2.39 seconds
Started Jul 26 04:25:43 PM PDT 24
Finished Jul 26 04:25:45 PM PDT 24
Peak memory 203304 kb
Host smart-58407d4c-01ae-4798-a523-4ba8c0465d48
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581829859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.1581829859
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.1289552793
Short name T83
Test name
Test status
Simulation time 4288813966 ps
CPU time 87.97 seconds
Started Jul 26 04:25:53 PM PDT 24
Finished Jul 26 04:27:21 PM PDT 24
Peak memory 206108 kb
Host smart-dde72097-9fa4-48f5-bb2e-4d7e9184d376
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1289552793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1289552793
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2795825572
Short name T503
Test name
Test status
Simulation time 7067860474 ps
CPU time 172.45 seconds
Started Jul 26 04:25:57 PM PDT 24
Finished Jul 26 04:28:50 PM PDT 24
Peak memory 206820 kb
Host smart-f189f18b-0cda-4b6e-bf78-c763ebe2ec85
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2795825572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2795825572
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1083982628
Short name T485
Test name
Test status
Simulation time 47180877 ps
CPU time 5.72 seconds
Started Jul 26 04:25:55 PM PDT 24
Finished Jul 26 04:26:01 PM PDT 24
Peak memory 205416 kb
Host smart-ee91663d-1533-47bf-8887-c6f810e51b5f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1083982628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran
d_reset.1083982628
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2284013034
Short name T772
Test name
Test status
Simulation time 103510109 ps
CPU time 14.3 seconds
Started Jul 26 04:26:03 PM PDT 24
Finished Jul 26 04:26:18 PM PDT 24
Peak memory 205144 kb
Host smart-b4e09f18-04b4-47d1-99b6-8c5f0ad19073
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2284013034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re
set_error.2284013034
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.1151536828
Short name T439
Test name
Test status
Simulation time 600855326 ps
CPU time 22.13 seconds
Started Jul 26 04:25:57 PM PDT 24
Finished Jul 26 04:26:20 PM PDT 24
Peak memory 211488 kb
Host smart-d39365a7-5579-4086-9b95-119737ed6be2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1151536828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1151536828
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.1087492979
Short name T749
Test name
Test status
Simulation time 712648469 ps
CPU time 44.01 seconds
Started Jul 26 04:25:54 PM PDT 24
Finished Jul 26 04:26:38 PM PDT 24
Peak memory 211508 kb
Host smart-d87b34c8-fb55-47c2-9562-f94eefff6a48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1087492979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.1087492979
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2890886993
Short name T710
Test name
Test status
Simulation time 10056048660 ps
CPU time 45.01 seconds
Started Jul 26 04:25:53 PM PDT 24
Finished Jul 26 04:26:38 PM PDT 24
Peak memory 211492 kb
Host smart-196d3b46-980a-451e-8569-82f92519d679
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2890886993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl
ow_rsp.2890886993
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.601291945
Short name T153
Test name
Test status
Simulation time 341864027 ps
CPU time 12.09 seconds
Started Jul 26 04:26:09 PM PDT 24
Finished Jul 26 04:26:22 PM PDT 24
Peak memory 203748 kb
Host smart-8f39436f-1ea0-4fc6-9812-29f482083c5f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=601291945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.601291945
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.2422143012
Short name T208
Test name
Test status
Simulation time 979092861 ps
CPU time 33.36 seconds
Started Jul 26 04:26:05 PM PDT 24
Finished Jul 26 04:26:39 PM PDT 24
Peak memory 203292 kb
Host smart-aa3e2aab-3d5e-476a-950f-448cd5f80e88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2422143012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2422143012
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.2505105359
Short name T57
Test name
Test status
Simulation time 602549149 ps
CPU time 18.19 seconds
Started Jul 26 04:25:53 PM PDT 24
Finished Jul 26 04:26:12 PM PDT 24
Peak memory 211468 kb
Host smart-98919c80-300d-468a-b17c-d80a3b8d5756
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2505105359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2505105359
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.1168577195
Short name T263
Test name
Test status
Simulation time 25916074378 ps
CPU time 138.76 seconds
Started Jul 26 04:25:55 PM PDT 24
Finished Jul 26 04:28:14 PM PDT 24
Peak memory 211512 kb
Host smart-d5be720e-4f88-46af-9511-f0b632fee097
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168577195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1168577195
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2287550904
Short name T650
Test name
Test status
Simulation time 10138757580 ps
CPU time 67.39 seconds
Started Jul 26 04:25:51 PM PDT 24
Finished Jul 26 04:26:59 PM PDT 24
Peak memory 204744 kb
Host smart-803a0744-436e-468e-819a-818f5b1291af
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2287550904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2287550904
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.1991649226
Short name T714
Test name
Test status
Simulation time 318458468 ps
CPU time 25.55 seconds
Started Jul 26 04:25:52 PM PDT 24
Finished Jul 26 04:26:17 PM PDT 24
Peak memory 211496 kb
Host smart-09f5b536-e65f-4fbb-804f-ff44255d8df4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991649226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.1991649226
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.3917849888
Short name T42
Test name
Test status
Simulation time 1529104789 ps
CPU time 32.12 seconds
Started Jul 26 04:26:05 PM PDT 24
Finished Jul 26 04:26:38 PM PDT 24
Peak memory 203340 kb
Host smart-5e7c61c2-0e5f-4e8b-80db-c52f24cd7254
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3917849888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3917849888
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.1733969196
Short name T388
Test name
Test status
Simulation time 123371431 ps
CPU time 3.04 seconds
Started Jul 26 04:25:55 PM PDT 24
Finished Jul 26 04:25:58 PM PDT 24
Peak memory 203252 kb
Host smart-36bc4d1f-e849-47ae-8244-3dec484d4332
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1733969196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1733969196
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.4086579897
Short name T408
Test name
Test status
Simulation time 5399248813 ps
CPU time 28.04 seconds
Started Jul 26 04:25:57 PM PDT 24
Finished Jul 26 04:26:26 PM PDT 24
Peak memory 203360 kb
Host smart-93d0c8b6-4927-4426-ba9b-edcf18cfc381
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086579897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.4086579897
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.523412705
Short name T396
Test name
Test status
Simulation time 5164808380 ps
CPU time 31.98 seconds
Started Jul 26 04:26:02 PM PDT 24
Finished Jul 26 04:26:34 PM PDT 24
Peak memory 203528 kb
Host smart-ce5f773b-27d7-4312-932f-f8679c4cc0cb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=523412705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.523412705
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.1626152170
Short name T606
Test name
Test status
Simulation time 142757613 ps
CPU time 2.45 seconds
Started Jul 26 04:25:55 PM PDT 24
Finished Jul 26 04:25:57 PM PDT 24
Peak memory 203296 kb
Host smart-c7f89a61-df57-4b91-b788-cf38f1ada9bf
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626152170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.1626152170
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.3439417862
Short name T615
Test name
Test status
Simulation time 1934661179 ps
CPU time 65.02 seconds
Started Jul 26 04:26:12 PM PDT 24
Finished Jul 26 04:27:17 PM PDT 24
Peak memory 205580 kb
Host smart-07a3b53a-2ff5-406f-b43b-6abb161b99f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3439417862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3439417862
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3850880590
Short name T253
Test name
Test status
Simulation time 859301234 ps
CPU time 240.8 seconds
Started Jul 26 04:26:11 PM PDT 24
Finished Jul 26 04:30:12 PM PDT 24
Peak memory 208968 kb
Host smart-be518d5b-a91d-4e00-bb57-b7b7483cd325
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3850880590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran
d_reset.3850880590
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.129513810
Short name T782
Test name
Test status
Simulation time 45053620 ps
CPU time 18.63 seconds
Started Jul 26 04:26:09 PM PDT 24
Finished Jul 26 04:26:27 PM PDT 24
Peak memory 205420 kb
Host smart-93325e24-f4a5-4fa4-ac44-cfbf52c55048
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=129513810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_res
et_error.129513810
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.829581909
Short name T773
Test name
Test status
Simulation time 160247753 ps
CPU time 19.96 seconds
Started Jul 26 04:26:12 PM PDT 24
Finished Jul 26 04:26:32 PM PDT 24
Peak memory 211440 kb
Host smart-abb776ec-d12d-4c75-a5c0-70587cd83fe2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=829581909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.829581909
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.2990110884
Short name T639
Test name
Test status
Simulation time 132191351 ps
CPU time 15.79 seconds
Started Jul 26 04:26:10 PM PDT 24
Finished Jul 26 04:26:26 PM PDT 24
Peak memory 205524 kb
Host smart-fdccd6f3-cc33-4a50-a84d-2024b836436e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2990110884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.2990110884
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1677877757
Short name T266
Test name
Test status
Simulation time 87836651825 ps
CPU time 720.96 seconds
Started Jul 26 04:26:08 PM PDT 24
Finished Jul 26 04:38:09 PM PDT 24
Peak memory 211528 kb
Host smart-4ab84ba0-8984-4d42-be6d-eb8c104d031f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1677877757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl
ow_rsp.1677877757
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.1201645434
Short name T660
Test name
Test status
Simulation time 139247501 ps
CPU time 13.19 seconds
Started Jul 26 04:26:07 PM PDT 24
Finished Jul 26 04:26:21 PM PDT 24
Peak memory 203272 kb
Host smart-ae73a07b-3618-4072-8131-abec78bfb170
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1201645434 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.1201645434
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.2263555433
Short name T386
Test name
Test status
Simulation time 3758766652 ps
CPU time 25.53 seconds
Started Jul 26 04:26:08 PM PDT 24
Finished Jul 26 04:26:33 PM PDT 24
Peak memory 203312 kb
Host smart-856d3e8d-9a3f-4d57-8c69-8246662f0548
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2263555433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2263555433
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.4170587652
Short name T839
Test name
Test status
Simulation time 76116982 ps
CPU time 2.78 seconds
Started Jul 26 04:26:04 PM PDT 24
Finished Jul 26 04:26:07 PM PDT 24
Peak memory 203276 kb
Host smart-78f1aee3-0508-44cc-9124-c2dd36bf6484
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4170587652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.4170587652
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.1139619861
Short name T194
Test name
Test status
Simulation time 21287158836 ps
CPU time 98.28 seconds
Started Jul 26 04:26:13 PM PDT 24
Finished Jul 26 04:27:52 PM PDT 24
Peak memory 211548 kb
Host smart-5cd0b12c-4969-4a31-8134-278cc3480a51
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139619861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1139619861
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.2958361188
Short name T862
Test name
Test status
Simulation time 44509071107 ps
CPU time 230.05 seconds
Started Jul 26 04:26:04 PM PDT 24
Finished Jul 26 04:29:54 PM PDT 24
Peak memory 211472 kb
Host smart-5d531067-19d2-4458-978f-bc1e90112ffb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2958361188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2958361188
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.1303665356
Short name T665
Test name
Test status
Simulation time 77862406 ps
CPU time 8.57 seconds
Started Jul 26 04:26:08 PM PDT 24
Finished Jul 26 04:26:17 PM PDT 24
Peak memory 211432 kb
Host smart-3941ffff-52cd-4eac-835c-29d5814dfd79
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303665356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.1303665356
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.1852791098
Short name T548
Test name
Test status
Simulation time 2754768585 ps
CPU time 32.08 seconds
Started Jul 26 04:26:26 PM PDT 24
Finished Jul 26 04:26:58 PM PDT 24
Peak memory 203816 kb
Host smart-290a7bf2-19a8-42fd-99f5-2c075e587586
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1852791098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1852791098
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.3086967655
Short name T161
Test name
Test status
Simulation time 153184085 ps
CPU time 3.92 seconds
Started Jul 26 04:26:08 PM PDT 24
Finished Jul 26 04:26:12 PM PDT 24
Peak memory 203308 kb
Host smart-1ea0904a-ff82-4ff2-95c4-e2557bfc9584
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3086967655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3086967655
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1718549467
Short name T308
Test name
Test status
Simulation time 5667673420 ps
CPU time 24.04 seconds
Started Jul 26 04:26:09 PM PDT 24
Finished Jul 26 04:26:33 PM PDT 24
Peak memory 203372 kb
Host smart-0270cd1a-107a-455a-ae6d-c69aafa94ec3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718549467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1718549467
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.866970483
Short name T339
Test name
Test status
Simulation time 6075027081 ps
CPU time 24.73 seconds
Started Jul 26 04:26:05 PM PDT 24
Finished Jul 26 04:26:30 PM PDT 24
Peak memory 203388 kb
Host smart-f77b242d-2b24-4cb1-8490-c458bbfed7ea
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=866970483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.866970483
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.1062922998
Short name T572
Test name
Test status
Simulation time 32858323 ps
CPU time 2.6 seconds
Started Jul 26 04:26:12 PM PDT 24
Finished Jul 26 04:26:15 PM PDT 24
Peak memory 203280 kb
Host smart-4a7716ea-cf55-4b3c-8e0a-2b98502fc4b0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062922998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.1062922998
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.1236011327
Short name T507
Test name
Test status
Simulation time 14471213690 ps
CPU time 254.61 seconds
Started Jul 26 04:26:10 PM PDT 24
Finished Jul 26 04:30:25 PM PDT 24
Peak memory 210636 kb
Host smart-6db821f4-de8d-4039-a537-b70670466c26
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1236011327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.1236011327
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.4050913780
Short name T20
Test name
Test status
Simulation time 3068663211 ps
CPU time 81.87 seconds
Started Jul 26 04:26:09 PM PDT 24
Finished Jul 26 04:27:31 PM PDT 24
Peak memory 204764 kb
Host smart-bac9250e-a021-47b2-89a3-bc9aefb95bf6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4050913780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.4050913780
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.409021196
Short name T700
Test name
Test status
Simulation time 97127646 ps
CPU time 51.04 seconds
Started Jul 26 04:26:06 PM PDT 24
Finished Jul 26 04:26:58 PM PDT 24
Peak memory 206812 kb
Host smart-f98884b6-403d-464d-b4f1-d596c6dd3bd6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=409021196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand
_reset.409021196
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1065540176
Short name T874
Test name
Test status
Simulation time 466467907 ps
CPU time 68.21 seconds
Started Jul 26 04:26:05 PM PDT 24
Finished Jul 26 04:27:13 PM PDT 24
Peak memory 207040 kb
Host smart-52086ff1-c45f-4528-83d6-93e170bb0664
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1065540176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re
set_error.1065540176
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.1258665453
Short name T502
Test name
Test status
Simulation time 1418994160 ps
CPU time 20.81 seconds
Started Jul 26 04:26:25 PM PDT 24
Finished Jul 26 04:26:46 PM PDT 24
Peak memory 205092 kb
Host smart-2ee330f0-bf15-40d2-842e-d55f2aaf928b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1258665453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1258665453
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.1589068209
Short name T348
Test name
Test status
Simulation time 399301170 ps
CPU time 33.72 seconds
Started Jul 26 04:26:12 PM PDT 24
Finished Jul 26 04:26:46 PM PDT 24
Peak memory 211464 kb
Host smart-a6b64448-1dea-4a0c-9a81-c3d05d65b8ca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1589068209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.1589068209
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3488429640
Short name T192
Test name
Test status
Simulation time 22083804709 ps
CPU time 160.87 seconds
Started Jul 26 04:26:09 PM PDT 24
Finished Jul 26 04:28:50 PM PDT 24
Peak memory 211360 kb
Host smart-38dc0240-2150-4d4f-b5d5-ed5dc1cfc4bb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3488429640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl
ow_rsp.3488429640
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.1306739000
Short name T745
Test name
Test status
Simulation time 57760704 ps
CPU time 3.85 seconds
Started Jul 26 04:26:07 PM PDT 24
Finished Jul 26 04:26:11 PM PDT 24
Peak memory 203144 kb
Host smart-949336e7-77e3-435d-9c4e-be732d375dde
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1306739000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.1306739000
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.3749540657
Short name T541
Test name
Test status
Simulation time 1570418550 ps
CPU time 28.91 seconds
Started Jul 26 04:26:06 PM PDT 24
Finished Jul 26 04:26:35 PM PDT 24
Peak memory 203264 kb
Host smart-665132d2-9cf5-4e17-bcdd-ac0afb02f48d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3749540657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3749540657
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.3983671976
Short name T813
Test name
Test status
Simulation time 80548747 ps
CPU time 2.56 seconds
Started Jul 26 04:26:06 PM PDT 24
Finished Jul 26 04:26:09 PM PDT 24
Peak memory 203324 kb
Host smart-09d3402d-2c4e-4a75-9253-5e5a112ba3e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3983671976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.3983671976
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.1052171750
Short name T54
Test name
Test status
Simulation time 21112766463 ps
CPU time 61.33 seconds
Started Jul 26 04:26:07 PM PDT 24
Finished Jul 26 04:27:09 PM PDT 24
Peak memory 211472 kb
Host smart-b8754a7e-4882-468c-8a1c-99c521378e50
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052171750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1052171750
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3518595477
Short name T609
Test name
Test status
Simulation time 11237811348 ps
CPU time 100.71 seconds
Started Jul 26 04:26:05 PM PDT 24
Finished Jul 26 04:27:46 PM PDT 24
Peak memory 211556 kb
Host smart-96101169-d9c6-4bbc-ba67-78524b2b8638
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3518595477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3518595477
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.1119661908
Short name T227
Test name
Test status
Simulation time 303507644 ps
CPU time 20.79 seconds
Started Jul 26 04:26:04 PM PDT 24
Finished Jul 26 04:26:25 PM PDT 24
Peak memory 211392 kb
Host smart-205bb8cb-6a97-4137-956f-67eac693a142
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119661908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1119661908
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.2418289103
Short name T535
Test name
Test status
Simulation time 290255862 ps
CPU time 19.32 seconds
Started Jul 26 04:26:13 PM PDT 24
Finished Jul 26 04:26:32 PM PDT 24
Peak memory 203900 kb
Host smart-fa710ed4-2eeb-4d71-a89d-9ca4f40a8879
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2418289103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2418289103
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke.1157741820
Short name T602
Test name
Test status
Simulation time 324492995 ps
CPU time 3.42 seconds
Started Jul 26 04:26:15 PM PDT 24
Finished Jul 26 04:26:19 PM PDT 24
Peak memory 203308 kb
Host smart-da5ca716-54a8-412c-88fd-cc9c1b18da71
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1157741820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1157741820
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1739172105
Short name T734
Test name
Test status
Simulation time 8635227791 ps
CPU time 29.88 seconds
Started Jul 26 04:26:07 PM PDT 24
Finished Jul 26 04:26:37 PM PDT 24
Peak memory 203360 kb
Host smart-ad0ba07e-d8a5-4d2b-99da-6f3e308c6c25
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739172105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1739172105
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.3995309058
Short name T271
Test name
Test status
Simulation time 5366960950 ps
CPU time 33.39 seconds
Started Jul 26 04:26:07 PM PDT 24
Finished Jul 26 04:26:41 PM PDT 24
Peak memory 203228 kb
Host smart-00907e35-1eb2-4303-9edd-74fb15cfa4a7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3995309058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.3995309058
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3034153268
Short name T501
Test name
Test status
Simulation time 22611159 ps
CPU time 2.04 seconds
Started Jul 26 04:26:04 PM PDT 24
Finished Jul 26 04:26:06 PM PDT 24
Peak memory 203288 kb
Host smart-a8f283a9-11d9-4fa8-b201-bcb96b6a31fe
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034153268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.3034153268
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.1960108040
Short name T630
Test name
Test status
Simulation time 1094780099 ps
CPU time 34.81 seconds
Started Jul 26 04:26:10 PM PDT 24
Finished Jul 26 04:26:45 PM PDT 24
Peak memory 205732 kb
Host smart-52a235cb-6b8f-4617-8360-17da14ddf487
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1960108040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1960108040
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.4118893396
Short name T21
Test name
Test status
Simulation time 213723199 ps
CPU time 20.2 seconds
Started Jul 26 04:26:05 PM PDT 24
Finished Jul 26 04:26:25 PM PDT 24
Peak memory 203640 kb
Host smart-eb99b849-f140-4a74-b55b-f1f79d191a0a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4118893396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.4118893396
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3943768309
Short name T38
Test name
Test status
Simulation time 1835448297 ps
CPU time 346.53 seconds
Started Jul 26 04:26:04 PM PDT 24
Finished Jul 26 04:31:51 PM PDT 24
Peak memory 209364 kb
Host smart-66c2224a-b7a9-4d8e-91a4-addb51e727fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3943768309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran
d_reset.3943768309
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.1513326973
Short name T401
Test name
Test status
Simulation time 2096157609 ps
CPU time 45.5 seconds
Started Jul 26 04:26:08 PM PDT 24
Finished Jul 26 04:26:54 PM PDT 24
Peak memory 205812 kb
Host smart-c13944d9-4985-408d-8909-f177f76dccb5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1513326973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re
set_error.1513326973
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.2277450411
Short name T235
Test name
Test status
Simulation time 321333427 ps
CPU time 7.43 seconds
Started Jul 26 04:26:11 PM PDT 24
Finished Jul 26 04:26:19 PM PDT 24
Peak memory 211468 kb
Host smart-7e14ca0c-4a80-4822-8bc2-4fd1e5dde70f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2277450411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2277450411
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.3385557575
Short name T52
Test name
Test status
Simulation time 2143404192 ps
CPU time 34.38 seconds
Started Jul 26 04:26:10 PM PDT 24
Finished Jul 26 04:26:44 PM PDT 24
Peak memory 211480 kb
Host smart-023d74a4-bb86-4f4c-bf94-80a22c208347
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3385557575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.3385557575
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.760893457
Short name T694
Test name
Test status
Simulation time 66397928178 ps
CPU time 546.95 seconds
Started Jul 26 04:26:11 PM PDT 24
Finished Jul 26 04:35:18 PM PDT 24
Peak memory 211472 kb
Host smart-bdcbaead-db3f-4c0e-a12d-f74421b5c640
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=760893457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slo
w_rsp.760893457
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2641795847
Short name T458
Test name
Test status
Simulation time 1267856915 ps
CPU time 22.04 seconds
Started Jul 26 04:26:08 PM PDT 24
Finished Jul 26 04:26:30 PM PDT 24
Peak memory 203280 kb
Host smart-3f511311-a8b7-44e6-8b83-a2ca52ee6949
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2641795847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.2641795847
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.2481437852
Short name T328
Test name
Test status
Simulation time 31044082 ps
CPU time 4.12 seconds
Started Jul 26 04:26:05 PM PDT 24
Finished Jul 26 04:26:09 PM PDT 24
Peak memory 203252 kb
Host smart-108c79ee-740c-40f3-a73b-d6e856dadd42
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2481437852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2481437852
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.2158343639
Short name T218
Test name
Test status
Simulation time 238946793 ps
CPU time 22.61 seconds
Started Jul 26 04:26:06 PM PDT 24
Finished Jul 26 04:26:29 PM PDT 24
Peak memory 211476 kb
Host smart-45826bc4-39d7-4ec5-866b-be065c444d6b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2158343639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.2158343639
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.1643406450
Short name T282
Test name
Test status
Simulation time 57385437850 ps
CPU time 83.7 seconds
Started Jul 26 04:26:25 PM PDT 24
Finished Jul 26 04:27:49 PM PDT 24
Peak memory 211532 kb
Host smart-d068be3a-d13e-4617-b405-4b4d05a34237
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643406450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.1643406450
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2032689496
Short name T104
Test name
Test status
Simulation time 12670265325 ps
CPU time 39.83 seconds
Started Jul 26 04:26:23 PM PDT 24
Finished Jul 26 04:27:03 PM PDT 24
Peak memory 204508 kb
Host smart-f1af0ee1-cdd2-455c-8329-02ad08f68b47
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2032689496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2032689496
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.1438219438
Short name T49
Test name
Test status
Simulation time 228978924 ps
CPU time 22.97 seconds
Started Jul 26 04:26:05 PM PDT 24
Finished Jul 26 04:26:29 PM PDT 24
Peak memory 211528 kb
Host smart-7f4997b3-3127-49b3-ab94-616acb42a996
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438219438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.1438219438
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.1824219997
Short name T320
Test name
Test status
Simulation time 157670732 ps
CPU time 2.94 seconds
Started Jul 26 04:26:10 PM PDT 24
Finished Jul 26 04:26:13 PM PDT 24
Peak memory 203412 kb
Host smart-cb21e750-2e18-49a7-be4e-b2de2497a4d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1824219997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1824219997
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.24947819
Short name T484
Test name
Test status
Simulation time 38831523 ps
CPU time 2.46 seconds
Started Jul 26 04:26:24 PM PDT 24
Finished Jul 26 04:26:27 PM PDT 24
Peak memory 203256 kb
Host smart-f66671b1-289a-473e-bfa4-37e7bcfdf7d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=24947819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.24947819
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.753418052
Short name T459
Test name
Test status
Simulation time 28857603420 ps
CPU time 48.63 seconds
Started Jul 26 04:26:05 PM PDT 24
Finished Jul 26 04:26:54 PM PDT 24
Peak memory 203364 kb
Host smart-187533f4-5e5d-46ed-9cb0-7be45e166c79
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=753418052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.753418052
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.4163810969
Short name T100
Test name
Test status
Simulation time 8381074167 ps
CPU time 26.1 seconds
Started Jul 26 04:26:07 PM PDT 24
Finished Jul 26 04:26:34 PM PDT 24
Peak memory 203408 kb
Host smart-e22da27c-9c1a-4098-9ab4-4109f527d682
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4163810969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.4163810969
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3647028527
Short name T307
Test name
Test status
Simulation time 97425419 ps
CPU time 2.17 seconds
Started Jul 26 04:26:09 PM PDT 24
Finished Jul 26 04:26:12 PM PDT 24
Peak memory 203296 kb
Host smart-2fd6bdff-6148-4b5f-84a8-17ce761f8e39
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647028527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.3647028527
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all.2349073620
Short name T774
Test name
Test status
Simulation time 1701756083 ps
CPU time 58.48 seconds
Started Jul 26 04:26:08 PM PDT 24
Finished Jul 26 04:27:07 PM PDT 24
Peak memory 206000 kb
Host smart-f5ecb56f-e8bf-4bdf-a48f-1acc6aacf39c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2349073620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.2349073620
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.497122807
Short name T515
Test name
Test status
Simulation time 3648962063 ps
CPU time 31.43 seconds
Started Jul 26 04:26:16 PM PDT 24
Finished Jul 26 04:26:47 PM PDT 24
Peak memory 204776 kb
Host smart-ce35b013-05f1-496a-bd0a-fbaa5cba334f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=497122807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.497122807
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.61324649
Short name T247
Test name
Test status
Simulation time 2036031718 ps
CPU time 265.61 seconds
Started Jul 26 04:26:12 PM PDT 24
Finished Jul 26 04:30:37 PM PDT 24
Peak memory 208436 kb
Host smart-5f17d091-8573-41d5-a3fc-eda6fa11d442
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=61324649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_
reset.61324649
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1611452988
Short name T356
Test name
Test status
Simulation time 12429867036 ps
CPU time 283.5 seconds
Started Jul 26 04:26:17 PM PDT 24
Finished Jul 26 04:31:01 PM PDT 24
Peak memory 220444 kb
Host smart-43d6d545-0062-427b-888b-b0f078d2ee4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1611452988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re
set_error.1611452988
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.1329825298
Short name T274
Test name
Test status
Simulation time 3597760934 ps
CPU time 29.66 seconds
Started Jul 26 04:26:06 PM PDT 24
Finished Jul 26 04:26:36 PM PDT 24
Peak memory 211456 kb
Host smart-8d65e783-b5d5-494a-91ea-af24374f069e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1329825298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1329825298
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.380478220
Short name T118
Test name
Test status
Simulation time 4883765754 ps
CPU time 44.33 seconds
Started Jul 26 04:26:21 PM PDT 24
Finished Jul 26 04:27:06 PM PDT 24
Peak memory 204484 kb
Host smart-fde14ab3-e0d8-422d-af40-a51182686b79
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=380478220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.380478220
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.638857959
Short name T400
Test name
Test status
Simulation time 56263804781 ps
CPU time 283.11 seconds
Started Jul 26 04:26:15 PM PDT 24
Finished Jul 26 04:30:58 PM PDT 24
Peak memory 211452 kb
Host smart-2b8ecbdd-ae1a-4c6c-869e-ea5ed9020c9f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=638857959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slo
w_rsp.638857959
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3005092647
Short name T802
Test name
Test status
Simulation time 132151877 ps
CPU time 9.1 seconds
Started Jul 26 04:26:31 PM PDT 24
Finished Jul 26 04:26:40 PM PDT 24
Peak memory 203288 kb
Host smart-c7b42c93-d718-4e87-a6e4-7c95034ad618
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3005092647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.3005092647
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.2678113670
Short name T182
Test name
Test status
Simulation time 78441280 ps
CPU time 9 seconds
Started Jul 26 04:26:15 PM PDT 24
Finished Jul 26 04:26:24 PM PDT 24
Peak memory 203240 kb
Host smart-f122f43b-7bdf-421b-af0e-7163fb0f38d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2678113670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2678113670
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.2312398452
Short name T209
Test name
Test status
Simulation time 83926386 ps
CPU time 2.54 seconds
Started Jul 26 04:26:19 PM PDT 24
Finished Jul 26 04:26:22 PM PDT 24
Peak memory 203308 kb
Host smart-9c2f7a5c-328e-49cd-9ffa-c221c52343b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2312398452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2312398452
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.1029919641
Short name T880
Test name
Test status
Simulation time 15030416221 ps
CPU time 53.68 seconds
Started Jul 26 04:26:26 PM PDT 24
Finished Jul 26 04:27:20 PM PDT 24
Peak memory 211568 kb
Host smart-cdaf58ea-97e4-474a-afe3-634aeb0c3245
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029919641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1029919641
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3871070640
Short name T150
Test name
Test status
Simulation time 72913245945 ps
CPU time 216.53 seconds
Started Jul 26 04:26:20 PM PDT 24
Finished Jul 26 04:29:56 PM PDT 24
Peak memory 211572 kb
Host smart-21e3396b-7e94-4d95-8524-281908914751
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3871070640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3871070640
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2210994858
Short name T363
Test name
Test status
Simulation time 186282043 ps
CPU time 22.01 seconds
Started Jul 26 04:26:13 PM PDT 24
Finished Jul 26 04:26:35 PM PDT 24
Peak memory 211484 kb
Host smart-63211ed4-34e2-414a-b28c-78cfe5d3e4a9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210994858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2210994858
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.2030345041
Short name T593
Test name
Test status
Simulation time 2567004236 ps
CPU time 27.31 seconds
Started Jul 26 04:26:14 PM PDT 24
Finished Jul 26 04:26:42 PM PDT 24
Peak memory 203336 kb
Host smart-90451d70-bc8c-48b1-bc57-37e41fa4a4ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2030345041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2030345041
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.3375923093
Short name T613
Test name
Test status
Simulation time 247043129 ps
CPU time 3.43 seconds
Started Jul 26 04:26:26 PM PDT 24
Finished Jul 26 04:26:29 PM PDT 24
Peak memory 203304 kb
Host smart-7f1e6a4e-f3e8-4545-8af6-023846f8c7cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3375923093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3375923093
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1464398323
Short name T469
Test name
Test status
Simulation time 38263853132 ps
CPU time 50.14 seconds
Started Jul 26 04:26:28 PM PDT 24
Finished Jul 26 04:27:18 PM PDT 24
Peak memory 203524 kb
Host smart-84fc5192-e5c8-4d25-97ad-e30bceabfac7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464398323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1464398323
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1262050482
Short name T155
Test name
Test status
Simulation time 3859479933 ps
CPU time 22.19 seconds
Started Jul 26 04:26:33 PM PDT 24
Finished Jul 26 04:26:55 PM PDT 24
Peak memory 203340 kb
Host smart-266fd15a-9b69-4bd6-993b-2f3aabca3d8f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1262050482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1262050482
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1656508293
Short name T828
Test name
Test status
Simulation time 95028252 ps
CPU time 2.17 seconds
Started Jul 26 04:26:16 PM PDT 24
Finished Jul 26 04:26:18 PM PDT 24
Peak memory 203224 kb
Host smart-5062ff8b-66f8-4449-8c12-920568a62f05
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656508293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1656508293
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.4249833937
Short name T736
Test name
Test status
Simulation time 520453794 ps
CPU time 36.48 seconds
Started Jul 26 04:26:13 PM PDT 24
Finished Jul 26 04:26:49 PM PDT 24
Peak memory 205940 kb
Host smart-13779a2d-f1ab-4465-a576-c3960d157d42
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4249833937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.4249833937
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1420988369
Short name T758
Test name
Test status
Simulation time 7928156261 ps
CPU time 202.83 seconds
Started Jul 26 04:26:12 PM PDT 24
Finished Jul 26 04:29:35 PM PDT 24
Peak memory 210780 kb
Host smart-79489f3a-ebef-4642-90aa-5817dbc405f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1420988369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1420988369
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1571428708
Short name T544
Test name
Test status
Simulation time 71382422 ps
CPU time 2.7 seconds
Started Jul 26 04:26:23 PM PDT 24
Finished Jul 26 04:26:26 PM PDT 24
Peak memory 204024 kb
Host smart-a1a9b578-3ae0-4000-a608-18a5e507928c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1571428708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran
d_reset.1571428708
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.1588150647
Short name T231
Test name
Test status
Simulation time 122131594 ps
CPU time 46.05 seconds
Started Jul 26 04:26:17 PM PDT 24
Finished Jul 26 04:27:03 PM PDT 24
Peak memory 207880 kb
Host smart-fc572c82-b171-49a3-a413-550f3a3880b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1588150647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re
set_error.1588150647
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.3943051381
Short name T337
Test name
Test status
Simulation time 210980628 ps
CPU time 28.24 seconds
Started Jul 26 04:26:19 PM PDT 24
Finished Jul 26 04:26:47 PM PDT 24
Peak memory 211504 kb
Host smart-e5fee993-a43b-451f-8797-b5e9dda2a7ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3943051381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.3943051381
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.887611545
Short name T89
Test name
Test status
Simulation time 54465960745 ps
CPU time 137.34 seconds
Started Jul 26 04:26:12 PM PDT 24
Finished Jul 26 04:28:29 PM PDT 24
Peak memory 211604 kb
Host smart-13f0fc58-bbfa-4c1e-a45c-c52acea8ad84
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=887611545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slo
w_rsp.887611545
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2029987097
Short name T314
Test name
Test status
Simulation time 127097280 ps
CPU time 13.76 seconds
Started Jul 26 04:26:24 PM PDT 24
Finished Jul 26 04:26:38 PM PDT 24
Peak memory 203296 kb
Host smart-94e0ec25-571b-408a-a012-6ccedbd9faee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2029987097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2029987097
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.27883006
Short name T221
Test name
Test status
Simulation time 922081470 ps
CPU time 23.45 seconds
Started Jul 26 04:26:51 PM PDT 24
Finished Jul 26 04:27:15 PM PDT 24
Peak memory 203308 kb
Host smart-c11ac8ef-ea56-459b-bca6-184bcdd7955d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=27883006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.27883006
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.2491286817
Short name T667
Test name
Test status
Simulation time 30987786116 ps
CPU time 174.87 seconds
Started Jul 26 04:26:22 PM PDT 24
Finished Jul 26 04:29:17 PM PDT 24
Peak memory 211472 kb
Host smart-45d3f7df-60e3-4262-8bef-7aeb19f4a78a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491286817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.2491286817
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.89482385
Short name T66
Test name
Test status
Simulation time 54805955147 ps
CPU time 206.58 seconds
Started Jul 26 04:26:13 PM PDT 24
Finished Jul 26 04:29:40 PM PDT 24
Peak memory 204864 kb
Host smart-2c8f682d-f141-4f9f-a94f-21b921c6a000
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=89482385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.89482385
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.2367119937
Short name T129
Test name
Test status
Simulation time 1354482317 ps
CPU time 28.53 seconds
Started Jul 26 04:26:36 PM PDT 24
Finished Jul 26 04:27:04 PM PDT 24
Peak memory 211516 kb
Host smart-8ed3c683-81e8-4d93-8230-15af95e57343
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367119937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.2367119937
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.136300690
Short name T22
Test name
Test status
Simulation time 152744243 ps
CPU time 13.3 seconds
Started Jul 26 04:26:16 PM PDT 24
Finished Jul 26 04:26:30 PM PDT 24
Peak memory 203788 kb
Host smart-a18d5a6a-2aa2-43ed-9832-807ac472f524
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=136300690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.136300690
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.4142129160
Short name T229
Test name
Test status
Simulation time 250232942 ps
CPU time 3.76 seconds
Started Jul 26 04:26:51 PM PDT 24
Finished Jul 26 04:26:55 PM PDT 24
Peak memory 203312 kb
Host smart-7b80f068-32e0-4f9f-a853-d677a12ba436
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4142129160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.4142129160
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1575875857
Short name T565
Test name
Test status
Simulation time 26440535909 ps
CPU time 42.37 seconds
Started Jul 26 04:26:13 PM PDT 24
Finished Jul 26 04:26:56 PM PDT 24
Peak memory 203316 kb
Host smart-9bcb2c43-7fe9-4497-a29d-e09543675b43
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575875857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1575875857
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3868231222
Short name T692
Test name
Test status
Simulation time 3571899762 ps
CPU time 27.51 seconds
Started Jul 26 04:26:26 PM PDT 24
Finished Jul 26 04:26:54 PM PDT 24
Peak memory 203384 kb
Host smart-2d4363b5-67a6-4d58-8161-cf8a4fdbb94e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3868231222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3868231222
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.4035558353
Short name T800
Test name
Test status
Simulation time 40759360 ps
CPU time 2.13 seconds
Started Jul 26 04:26:30 PM PDT 24
Finished Jul 26 04:26:33 PM PDT 24
Peak memory 203240 kb
Host smart-5bc38a48-b085-4446-b78b-48eac4f7ff7d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035558353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.4035558353
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.2622462338
Short name T693
Test name
Test status
Simulation time 299018964 ps
CPU time 10.83 seconds
Started Jul 26 04:26:14 PM PDT 24
Finished Jul 26 04:26:25 PM PDT 24
Peak memory 204892 kb
Host smart-4ef63aac-77be-4261-ac47-687e15700de6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2622462338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2622462338
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2241934230
Short name T404
Test name
Test status
Simulation time 3508669680 ps
CPU time 87.14 seconds
Started Jul 26 04:26:15 PM PDT 24
Finished Jul 26 04:27:42 PM PDT 24
Peak memory 211548 kb
Host smart-2ae2e7ca-e92a-471f-bf73-525a693f4326
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2241934230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2241934230
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3803748643
Short name T398
Test name
Test status
Simulation time 7928865 ps
CPU time 0.8 seconds
Started Jul 26 04:26:16 PM PDT 24
Finished Jul 26 04:26:17 PM PDT 24
Peak memory 195092 kb
Host smart-fcb5efcd-3b60-42c0-af7a-a754366fe702
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3803748643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran
d_reset.3803748643
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2848743500
Short name T145
Test name
Test status
Simulation time 781966206 ps
CPU time 177.67 seconds
Started Jul 26 04:26:33 PM PDT 24
Finished Jul 26 04:29:31 PM PDT 24
Peak memory 211504 kb
Host smart-d02539d7-1c8d-4245-89e8-a707e5241bc7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2848743500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re
set_error.2848743500
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.3962390782
Short name T327
Test name
Test status
Simulation time 68065492 ps
CPU time 7.4 seconds
Started Jul 26 04:26:24 PM PDT 24
Finished Jul 26 04:26:32 PM PDT 24
Peak memory 211460 kb
Host smart-0cf59ac2-1ef7-45d9-be32-a5843ae31efc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3962390782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3962390782
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.486824926
Short name T753
Test name
Test status
Simulation time 150264136757 ps
CPU time 642.74 seconds
Started Jul 26 04:26:12 PM PDT 24
Finished Jul 26 04:36:54 PM PDT 24
Peak memory 207064 kb
Host smart-a152b59c-3354-42aa-a457-a4a9c4d13572
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=486824926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slo
w_rsp.486824926
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.2716612113
Short name T233
Test name
Test status
Simulation time 90441020 ps
CPU time 13.26 seconds
Started Jul 26 04:26:19 PM PDT 24
Finished Jul 26 04:26:33 PM PDT 24
Peak memory 203320 kb
Host smart-ef6e1286-9bdb-4482-a006-ab356e4260a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2716612113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.2716612113
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.535378222
Short name T599
Test name
Test status
Simulation time 58816077 ps
CPU time 4.56 seconds
Started Jul 26 04:26:19 PM PDT 24
Finished Jul 26 04:26:23 PM PDT 24
Peak memory 203156 kb
Host smart-87e39d3f-3cee-4cf6-a195-8ff59791d6e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=535378222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.535378222
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.1904483486
Short name T516
Test name
Test status
Simulation time 830640584 ps
CPU time 16.75 seconds
Started Jul 26 04:26:15 PM PDT 24
Finished Jul 26 04:26:32 PM PDT 24
Peak memory 204448 kb
Host smart-9a7105d7-3ffb-438e-a03b-93aba551ea77
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1904483486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.1904483486
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.2909655963
Short name T883
Test name
Test status
Simulation time 89589925500 ps
CPU time 189.34 seconds
Started Jul 26 04:26:25 PM PDT 24
Finished Jul 26 04:29:34 PM PDT 24
Peak memory 211568 kb
Host smart-10e97e08-82c4-47f0-b38b-a2fe70f6ebea
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909655963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2909655963
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.1344809585
Short name T793
Test name
Test status
Simulation time 41021476482 ps
CPU time 164.87 seconds
Started Jul 26 04:26:21 PM PDT 24
Finished Jul 26 04:29:06 PM PDT 24
Peak memory 205228 kb
Host smart-16da7efa-1e33-4bce-94d0-9fe0e0afdafe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1344809585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.1344809585
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.2129685437
Short name T853
Test name
Test status
Simulation time 346993348 ps
CPU time 24.3 seconds
Started Jul 26 04:26:14 PM PDT 24
Finished Jul 26 04:26:38 PM PDT 24
Peak memory 211460 kb
Host smart-9fda5f07-5eea-4861-ada8-9e8ec108dd26
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129685437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.2129685437
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.498862712
Short name T199
Test name
Test status
Simulation time 4131675723 ps
CPU time 31.04 seconds
Started Jul 26 04:26:19 PM PDT 24
Finished Jul 26 04:26:50 PM PDT 24
Peak memory 203404 kb
Host smart-03181d56-6e57-450c-8935-551d458c6fef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=498862712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.498862712
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.503944200
Short name T750
Test name
Test status
Simulation time 24968251 ps
CPU time 2.07 seconds
Started Jul 26 04:26:18 PM PDT 24
Finished Jul 26 04:26:20 PM PDT 24
Peak memory 203308 kb
Host smart-a7033ed6-08bc-4d36-b7bf-73ca8893634f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=503944200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.503944200
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.282163410
Short name T381
Test name
Test status
Simulation time 7862253146 ps
CPU time 26.7 seconds
Started Jul 26 04:26:11 PM PDT 24
Finished Jul 26 04:26:38 PM PDT 24
Peak memory 203380 kb
Host smart-68c31df8-72b3-47ab-9adc-9648e8874749
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=282163410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.282163410
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1522356283
Short name T530
Test name
Test status
Simulation time 3039199397 ps
CPU time 28.48 seconds
Started Jul 26 04:26:30 PM PDT 24
Finished Jul 26 04:26:59 PM PDT 24
Peak memory 203336 kb
Host smart-1f50e166-36db-4d85-ab9c-3643a93d3f84
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1522356283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1522356283
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2905277645
Short name T403
Test name
Test status
Simulation time 33359316 ps
CPU time 2.19 seconds
Started Jul 26 04:26:51 PM PDT 24
Finished Jul 26 04:26:53 PM PDT 24
Peak memory 203152 kb
Host smart-7dbe2247-93c1-47ea-8a84-9841336044a5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905277645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2905277645
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.1025552006
Short name T9
Test name
Test status
Simulation time 11202388073 ps
CPU time 40.45 seconds
Started Jul 26 04:26:18 PM PDT 24
Finished Jul 26 04:26:58 PM PDT 24
Peak memory 205568 kb
Host smart-8118939e-7bf9-40e9-aa47-ab0b3d910498
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1025552006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1025552006
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.133123843
Short name T329
Test name
Test status
Simulation time 14512062686 ps
CPU time 152.76 seconds
Started Jul 26 04:26:54 PM PDT 24
Finished Jul 26 04:29:26 PM PDT 24
Peak memory 206584 kb
Host smart-007b29b8-eed9-42a6-8cfd-3de460d6587b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=133123843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.133123843
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.1282225138
Short name T46
Test name
Test status
Simulation time 629339318 ps
CPU time 234.28 seconds
Started Jul 26 04:26:14 PM PDT 24
Finished Jul 26 04:30:08 PM PDT 24
Peak memory 208624 kb
Host smart-8af7e7ec-751c-483b-b90f-9e88f4c37c78
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1282225138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran
d_reset.1282225138
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3751153582
Short name T836
Test name
Test status
Simulation time 56281183 ps
CPU time 16.07 seconds
Started Jul 26 04:26:42 PM PDT 24
Finished Jul 26 04:26:58 PM PDT 24
Peak memory 205540 kb
Host smart-113c29ab-d87b-4ac2-b465-4c2eb7b1f7a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3751153582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re
set_error.3751153582
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.4115146632
Short name T546
Test name
Test status
Simulation time 103563153 ps
CPU time 10.61 seconds
Started Jul 26 04:26:26 PM PDT 24
Finished Jul 26 04:26:36 PM PDT 24
Peak memory 204940 kb
Host smart-1fe0a701-1ab1-4a16-8ace-95c86336b6cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4115146632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.4115146632
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.4225886538
Short name T75
Test name
Test status
Simulation time 599194573 ps
CPU time 7.33 seconds
Started Jul 26 04:26:25 PM PDT 24
Finished Jul 26 04:26:32 PM PDT 24
Peak memory 203328 kb
Host smart-9840ccfe-1565-47b7-9f25-67c8a9da583e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4225886538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.4225886538
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.1090855844
Short name T452
Test name
Test status
Simulation time 207250627520 ps
CPU time 708.35 seconds
Started Jul 26 04:26:15 PM PDT 24
Finished Jul 26 04:38:04 PM PDT 24
Peak memory 206000 kb
Host smart-00a1f933-c2e9-4d8b-8359-367c1e0588c2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1090855844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl
ow_rsp.1090855844
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2459991901
Short name T636
Test name
Test status
Simulation time 400200562 ps
CPU time 12.41 seconds
Started Jul 26 04:26:45 PM PDT 24
Finished Jul 26 04:26:57 PM PDT 24
Peak memory 203344 kb
Host smart-360d036f-0a42-48c0-b02c-d504dedbf314
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2459991901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.2459991901
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.2444053822
Short name T558
Test name
Test status
Simulation time 408302995 ps
CPU time 10.38 seconds
Started Jul 26 04:26:18 PM PDT 24
Finished Jul 26 04:26:29 PM PDT 24
Peak memory 203332 kb
Host smart-b1e57332-0615-490c-8081-b9f0030d78c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2444053822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2444053822
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.956384257
Short name T382
Test name
Test status
Simulation time 898398530 ps
CPU time 5.9 seconds
Started Jul 26 04:26:20 PM PDT 24
Finished Jul 26 04:26:26 PM PDT 24
Peak memory 203336 kb
Host smart-d83e025d-a4ca-4d19-956a-137fd5445320
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=956384257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.956384257
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.1486350533
Short name T514
Test name
Test status
Simulation time 1473439080 ps
CPU time 9.42 seconds
Started Jul 26 04:26:25 PM PDT 24
Finished Jul 26 04:26:35 PM PDT 24
Peak memory 203284 kb
Host smart-48a82210-b84b-4081-a20c-87c0d74ff350
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486350533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1486350533
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3695677424
Short name T587
Test name
Test status
Simulation time 26463584537 ps
CPU time 161.96 seconds
Started Jul 26 04:26:17 PM PDT 24
Finished Jul 26 04:28:59 PM PDT 24
Peak memory 204612 kb
Host smart-52a9a02d-d084-484d-ac88-3d90b76a2629
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3695677424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3695677424
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.3085208395
Short name T871
Test name
Test status
Simulation time 122967537 ps
CPU time 18.34 seconds
Started Jul 26 04:26:25 PM PDT 24
Finished Jul 26 04:26:44 PM PDT 24
Peak memory 211464 kb
Host smart-3937b8b6-377a-40dd-bd18-fd3e14122b30
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085208395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.3085208395
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.767717244
Short name T342
Test name
Test status
Simulation time 2265971218 ps
CPU time 29.55 seconds
Started Jul 26 04:26:34 PM PDT 24
Finished Jul 26 04:27:03 PM PDT 24
Peak memory 203260 kb
Host smart-034be538-def5-48e9-b061-1da1c8d711e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=767717244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.767717244
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.555467612
Short name T385
Test name
Test status
Simulation time 138420928 ps
CPU time 3.39 seconds
Started Jul 26 04:26:37 PM PDT 24
Finished Jul 26 04:26:40 PM PDT 24
Peak memory 203308 kb
Host smart-d87c9788-eb16-4b56-a15c-26751d2fbac0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=555467612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.555467612
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.4027890809
Short name T416
Test name
Test status
Simulation time 5611527749 ps
CPU time 28.9 seconds
Started Jul 26 04:26:52 PM PDT 24
Finished Jul 26 04:27:21 PM PDT 24
Peak memory 203304 kb
Host smart-223c7be6-9724-410c-892f-10e1780c7e08
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027890809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.4027890809
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.2421597584
Short name T352
Test name
Test status
Simulation time 4022825617 ps
CPU time 25.06 seconds
Started Jul 26 04:26:14 PM PDT 24
Finished Jul 26 04:26:39 PM PDT 24
Peak memory 203344 kb
Host smart-c17eb141-3764-4968-8105-66470195fa89
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2421597584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.2421597584
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1604896600
Short name T631
Test name
Test status
Simulation time 26753723 ps
CPU time 2.08 seconds
Started Jul 26 04:26:19 PM PDT 24
Finished Jul 26 04:26:21 PM PDT 24
Peak memory 203296 kb
Host smart-b9724b77-595f-4901-b0f9-9afbee46b8fa
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604896600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1604896600
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.502924017
Short name T78
Test name
Test status
Simulation time 15222282626 ps
CPU time 232.68 seconds
Started Jul 26 04:26:53 PM PDT 24
Finished Jul 26 04:30:46 PM PDT 24
Peak memory 208632 kb
Host smart-e050c612-4099-4af4-b971-40533b34c591
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=502924017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.502924017
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.934904739
Short name T223
Test name
Test status
Simulation time 1274458867 ps
CPU time 15.17 seconds
Started Jul 26 04:26:25 PM PDT 24
Finished Jul 26 04:26:40 PM PDT 24
Peak memory 203268 kb
Host smart-795583c4-6ea8-43cb-b6b0-e14140c78d28
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=934904739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.934904739
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1706147030
Short name T860
Test name
Test status
Simulation time 178716685 ps
CPU time 70.74 seconds
Started Jul 26 04:26:19 PM PDT 24
Finished Jul 26 04:27:29 PM PDT 24
Peak memory 206856 kb
Host smart-5ae46903-355d-413e-b4aa-b921a427eccf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1706147030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran
d_reset.1706147030
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.442523972
Short name T705
Test name
Test status
Simulation time 77416206 ps
CPU time 25.64 seconds
Started Jul 26 04:27:02 PM PDT 24
Finished Jul 26 04:27:28 PM PDT 24
Peak memory 207136 kb
Host smart-b3207e4e-98ef-4010-80c5-451f9b48e068
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=442523972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_res
et_error.442523972
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.2118417449
Short name T505
Test name
Test status
Simulation time 590435993 ps
CPU time 13.91 seconds
Started Jul 26 04:26:34 PM PDT 24
Finished Jul 26 04:26:48 PM PDT 24
Peak memory 211464 kb
Host smart-d0905ed0-2132-40e7-9336-0b8e1ee0e3d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2118417449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2118417449
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.3426166548
Short name T455
Test name
Test status
Simulation time 367817560 ps
CPU time 10.15 seconds
Started Jul 26 04:25:13 PM PDT 24
Finished Jul 26 04:25:23 PM PDT 24
Peak memory 210344 kb
Host smart-ea51ef9a-8761-4d46-91da-bd6c17b455fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3426166548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3426166548
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3151352709
Short name T23
Test name
Test status
Simulation time 83723501778 ps
CPU time 226.84 seconds
Started Jul 26 04:23:17 PM PDT 24
Finished Jul 26 04:27:04 PM PDT 24
Peak memory 211528 kb
Host smart-cbcb8d2d-97ce-4abc-9d3f-34daca04cb7c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3151352709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo
w_rsp.3151352709
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.2660915633
Short name T286
Test name
Test status
Simulation time 63084082 ps
CPU time 8.79 seconds
Started Jul 26 04:21:35 PM PDT 24
Finished Jul 26 04:21:44 PM PDT 24
Peak memory 203476 kb
Host smart-05d202de-fbf2-4d87-95b9-8eb5ca183741
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2660915633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.2660915633
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.976009482
Short name T759
Test name
Test status
Simulation time 260943327 ps
CPU time 24.62 seconds
Started Jul 26 04:22:54 PM PDT 24
Finished Jul 26 04:23:19 PM PDT 24
Peak memory 204008 kb
Host smart-34c3c831-ba72-4847-a70e-d620da7c07d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=976009482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.976009482
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.3494482964
Short name T738
Test name
Test status
Simulation time 83459271 ps
CPU time 11.23 seconds
Started Jul 26 04:25:14 PM PDT 24
Finished Jul 26 04:25:26 PM PDT 24
Peak memory 204132 kb
Host smart-5e6a5793-4e74-4109-adf4-d109c82a6bc5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3494482964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.3494482964
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.2213253657
Short name T442
Test name
Test status
Simulation time 46291117656 ps
CPU time 176.96 seconds
Started Jul 26 04:20:48 PM PDT 24
Finished Jul 26 04:23:45 PM PDT 24
Peak memory 205364 kb
Host smart-770742f6-c761-4691-8022-591415b06a2a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213253657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2213253657
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.3580184835
Short name T63
Test name
Test status
Simulation time 109170752357 ps
CPU time 293.08 seconds
Started Jul 26 04:24:28 PM PDT 24
Finished Jul 26 04:29:22 PM PDT 24
Peak memory 209384 kb
Host smart-b548a2f4-e561-4825-ab06-ab4d2c0a9554
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3580184835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3580184835
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.2225115343
Short name T355
Test name
Test status
Simulation time 16257530 ps
CPU time 1.9 seconds
Started Jul 26 04:25:21 PM PDT 24
Finished Jul 26 04:25:23 PM PDT 24
Peak memory 203004 kb
Host smart-f7b469a5-6080-4c51-b019-c505180dc4c6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225115343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.2225115343
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.1180959303
Short name T245
Test name
Test status
Simulation time 4359617418 ps
CPU time 18.68 seconds
Started Jul 26 04:24:40 PM PDT 24
Finished Jul 26 04:24:58 PM PDT 24
Peak memory 211540 kb
Host smart-53e52acc-ef0b-4389-a686-9557fb143826
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1180959303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1180959303
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.2743538361
Short name T147
Test name
Test status
Simulation time 239349235 ps
CPU time 3.42 seconds
Started Jul 26 04:25:13 PM PDT 24
Finished Jul 26 04:25:17 PM PDT 24
Peak memory 202972 kb
Host smart-ab99f791-40f6-43a1-a26e-478d0ddf1e7e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2743538361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2743538361
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.4277509768
Short name T287
Test name
Test status
Simulation time 4735231419 ps
CPU time 26.29 seconds
Started Jul 26 04:23:17 PM PDT 24
Finished Jul 26 04:23:43 PM PDT 24
Peak memory 203376 kb
Host smart-21e30c6a-eb37-400b-9c24-9e132df99638
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277509768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.4277509768
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.901190206
Short name T106
Test name
Test status
Simulation time 3957102864 ps
CPU time 31.76 seconds
Started Jul 26 04:25:13 PM PDT 24
Finished Jul 26 04:25:45 PM PDT 24
Peak memory 202448 kb
Host smart-1c3d0a78-e1dc-4806-b57c-fe3ffbf0e1c1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=901190206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.901190206
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.3835948138
Short name T618
Test name
Test status
Simulation time 60087716 ps
CPU time 2.35 seconds
Started Jul 26 04:24:28 PM PDT 24
Finished Jul 26 04:24:31 PM PDT 24
Peak memory 202916 kb
Host smart-e393cc3c-1b6c-4c08-8eb8-cf6512ac40a1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835948138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.3835948138
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.614416223
Short name T107
Test name
Test status
Simulation time 6995854359 ps
CPU time 273.1 seconds
Started Jul 26 04:20:38 PM PDT 24
Finished Jul 26 04:25:11 PM PDT 24
Peak memory 211544 kb
Host smart-f0d720d7-d6be-423e-a804-7997d91caf7a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=614416223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.614416223
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2827353169
Short name T142
Test name
Test status
Simulation time 192431600 ps
CPU time 16.14 seconds
Started Jul 26 04:25:14 PM PDT 24
Finished Jul 26 04:25:30 PM PDT 24
Peak memory 203428 kb
Host smart-315068ef-25a1-4ac1-8e71-18c59c702d32
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2827353169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2827353169
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.115552898
Short name T844
Test name
Test status
Simulation time 771087104 ps
CPU time 278.25 seconds
Started Jul 26 04:20:47 PM PDT 24
Finished Jul 26 04:25:25 PM PDT 24
Peak memory 209644 kb
Host smart-cd423dff-31e9-4495-a125-ab2610e840f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=115552898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_
reset.115552898
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.2762757755
Short name T354
Test name
Test status
Simulation time 25504217 ps
CPU time 17.9 seconds
Started Jul 26 04:21:00 PM PDT 24
Finished Jul 26 04:21:18 PM PDT 24
Peak memory 205516 kb
Host smart-4d58a135-5836-4553-9735-6c38d3c2cc8a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2762757755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res
et_error.2762757755
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.547455625
Short name T559
Test name
Test status
Simulation time 658095685 ps
CPU time 24.08 seconds
Started Jul 26 04:24:42 PM PDT 24
Finished Jul 26 04:25:06 PM PDT 24
Peak memory 211256 kb
Host smart-a3699a28-e17d-44a6-a5f5-d843819524ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=547455625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.547455625
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.3761514147
Short name T299
Test name
Test status
Simulation time 1087933585 ps
CPU time 46.01 seconds
Started Jul 26 04:21:08 PM PDT 24
Finished Jul 26 04:21:55 PM PDT 24
Peak memory 205192 kb
Host smart-976fed16-8516-47e5-a6db-c117646d5dac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3761514147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.3761514147
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.3819225282
Short name T163
Test name
Test status
Simulation time 139484985063 ps
CPU time 471.49 seconds
Started Jul 26 04:25:14 PM PDT 24
Finished Jul 26 04:33:06 PM PDT 24
Peak memory 211320 kb
Host smart-bcf2463e-be73-463e-a07c-4ba8764bfe8c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3819225282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo
w_rsp.3819225282
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2984427123
Short name T857
Test name
Test status
Simulation time 682529221 ps
CPU time 19.09 seconds
Started Jul 26 04:24:44 PM PDT 24
Finished Jul 26 04:25:03 PM PDT 24
Peak memory 203084 kb
Host smart-19e2cbd3-9e60-41c5-94d6-75e3fda52eac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2984427123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.2984427123
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.2375188965
Short name T305
Test name
Test status
Simulation time 499041435 ps
CPU time 13.58 seconds
Started Jul 26 04:25:24 PM PDT 24
Finished Jul 26 04:25:38 PM PDT 24
Peak memory 203084 kb
Host smart-39e51776-e317-4b32-b737-6223f88dc560
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2375188965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2375188965
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.938280740
Short name T56
Test name
Test status
Simulation time 1217185446 ps
CPU time 25.56 seconds
Started Jul 26 04:25:14 PM PDT 24
Finished Jul 26 04:25:40 PM PDT 24
Peak memory 210508 kb
Host smart-bf83e7cd-7816-432a-b12f-0aa3133838ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=938280740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.938280740
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.3178954053
Short name T671
Test name
Test status
Simulation time 73877117317 ps
CPU time 252.82 seconds
Started Jul 26 04:24:44 PM PDT 24
Finished Jul 26 04:28:57 PM PDT 24
Peak memory 211316 kb
Host smart-7a60f5c3-e058-438e-8747-269fb312ad94
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178954053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3178954053
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2489077365
Short name T178
Test name
Test status
Simulation time 153002913038 ps
CPU time 339.16 seconds
Started Jul 26 04:25:03 PM PDT 24
Finished Jul 26 04:30:43 PM PDT 24
Peak memory 210724 kb
Host smart-1649f2ea-b7db-445f-8ef4-c0107beba5f3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2489077365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2489077365
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.698805719
Short name T441
Test name
Test status
Simulation time 97192439 ps
CPU time 8.54 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:25:24 PM PDT 24
Peak memory 211240 kb
Host smart-cd8051e1-fcdf-4809-9b14-902c6b925c7a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698805719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.698805719
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.1676757537
Short name T108
Test name
Test status
Simulation time 935831106 ps
CPU time 15.29 seconds
Started Jul 26 04:21:03 PM PDT 24
Finished Jul 26 04:21:19 PM PDT 24
Peak memory 204032 kb
Host smart-9059e6e5-1a1a-4e3b-a301-41f675f5f49c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1676757537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.1676757537
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.1252118946
Short name T309
Test name
Test status
Simulation time 26590860 ps
CPU time 1.99 seconds
Started Jul 26 04:20:08 PM PDT 24
Finished Jul 26 04:20:10 PM PDT 24
Peak memory 203236 kb
Host smart-3b1d496c-2767-4b47-a894-f65b2f57a397
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1252118946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1252118946
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.1449609638
Short name T628
Test name
Test status
Simulation time 9318518671 ps
CPU time 29.36 seconds
Started Jul 26 04:21:52 PM PDT 24
Finished Jul 26 04:22:21 PM PDT 24
Peak memory 203276 kb
Host smart-46560652-cac7-4e42-bf84-a56a4ed9f9c7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449609638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1449609638
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.1043227227
Short name T784
Test name
Test status
Simulation time 11528482057 ps
CPU time 36.71 seconds
Started Jul 26 04:24:44 PM PDT 24
Finished Jul 26 04:25:21 PM PDT 24
Peak memory 203156 kb
Host smart-d4797a05-a7a9-42d8-a9db-b9bc0e05911e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1043227227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1043227227
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.1975473817
Short name T70
Test name
Test status
Simulation time 69442403 ps
CPU time 2.42 seconds
Started Jul 26 04:25:24 PM PDT 24
Finished Jul 26 04:25:27 PM PDT 24
Peak memory 203040 kb
Host smart-f3514b01-9be6-459d-9aeb-967cad2d06c3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975473817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.1975473817
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.4056226211
Short name T477
Test name
Test status
Simulation time 61903360 ps
CPU time 6.86 seconds
Started Jul 26 04:25:22 PM PDT 24
Finished Jul 26 04:25:29 PM PDT 24
Peak memory 204624 kb
Host smart-f93a36dd-4b70-4c96-8892-f7640969395f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4056226211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.4056226211
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.4133753948
Short name T703
Test name
Test status
Simulation time 108689196 ps
CPU time 5.98 seconds
Started Jul 26 04:24:42 PM PDT 24
Finished Jul 26 04:24:49 PM PDT 24
Peak memory 203292 kb
Host smart-dc119f93-d401-4446-a5a4-576e15ccab94
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4133753948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.4133753948
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1203816436
Short name T302
Test name
Test status
Simulation time 303180263 ps
CPU time 99.84 seconds
Started Jul 26 04:25:24 PM PDT 24
Finished Jul 26 04:27:04 PM PDT 24
Peak memory 207828 kb
Host smart-9debf1c6-8feb-4a3e-98b4-dbe2a7a87564
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1203816436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand
_reset.1203816436
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.674564336
Short name T491
Test name
Test status
Simulation time 2185473284 ps
CPU time 270.29 seconds
Started Jul 26 04:21:56 PM PDT 24
Finished Jul 26 04:26:26 PM PDT 24
Peak memory 222776 kb
Host smart-639e09dd-672b-48b9-9ee6-cbc5d73db3f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=674564336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rese
t_error.674564336
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.1450619124
Short name T55
Test name
Test status
Simulation time 219115054 ps
CPU time 5.2 seconds
Started Jul 26 04:23:17 PM PDT 24
Finished Jul 26 04:23:22 PM PDT 24
Peak memory 211544 kb
Host smart-e4b00d95-6a97-4aa0-a78a-2e48428530ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1450619124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1450619124
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.393344853
Short name T518
Test name
Test status
Simulation time 2174141606 ps
CPU time 19.15 seconds
Started Jul 26 04:24:28 PM PDT 24
Finished Jul 26 04:24:48 PM PDT 24
Peak memory 210416 kb
Host smart-5cc8215b-4a05-4961-aa44-0f258c3d31f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=393344853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.393344853
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.1306951939
Short name T358
Test name
Test status
Simulation time 85109377 ps
CPU time 13.85 seconds
Started Jul 26 04:22:59 PM PDT 24
Finished Jul 26 04:23:13 PM PDT 24
Peak memory 203332 kb
Host smart-763ab04c-5a96-45ec-b6ea-5192d0b3a7b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1306951939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.1306951939
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.4998053
Short name T638
Test name
Test status
Simulation time 409712305 ps
CPU time 7.72 seconds
Started Jul 26 04:24:28 PM PDT 24
Finished Jul 26 04:24:36 PM PDT 24
Peak memory 202076 kb
Host smart-e591de22-82b4-4042-9e28-0f23d25e144a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4998053 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.4998053
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.467190155
Short name T387
Test name
Test status
Simulation time 221038655 ps
CPU time 17.62 seconds
Started Jul 26 04:23:18 PM PDT 24
Finished Jul 26 04:23:36 PM PDT 24
Peak memory 211444 kb
Host smart-03dd8268-61ab-44be-85cf-be712bc96345
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=467190155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.467190155
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.1049578221
Short name T870
Test name
Test status
Simulation time 3145782156 ps
CPU time 11 seconds
Started Jul 26 04:25:30 PM PDT 24
Finished Jul 26 04:25:42 PM PDT 24
Peak memory 202944 kb
Host smart-f6c3667b-5118-42ef-bc3e-5d93f46977ae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049578221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1049578221
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.1001073877
Short name T610
Test name
Test status
Simulation time 31813075658 ps
CPU time 173.34 seconds
Started Jul 26 04:25:28 PM PDT 24
Finished Jul 26 04:28:21 PM PDT 24
Peak memory 211556 kb
Host smart-a7552dff-9a3b-4970-86c1-a3d089f0af62
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1001073877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1001073877
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.905747320
Short name T397
Test name
Test status
Simulation time 132201777 ps
CPU time 12.01 seconds
Started Jul 26 04:25:14 PM PDT 24
Finished Jul 26 04:25:27 PM PDT 24
Peak memory 209984 kb
Host smart-c645381d-43b4-4a2e-b1af-998d245862b1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905747320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.905747320
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.615984786
Short name T596
Test name
Test status
Simulation time 2428833388 ps
CPU time 26.43 seconds
Started Jul 26 04:22:37 PM PDT 24
Finished Jul 26 04:23:04 PM PDT 24
Peak memory 203420 kb
Host smart-f89dbbe4-5015-4463-92c3-ff729bb21be2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=615984786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.615984786
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.81099444
Short name T475
Test name
Test status
Simulation time 30886230 ps
CPU time 2.22 seconds
Started Jul 26 04:24:42 PM PDT 24
Finished Jul 26 04:24:45 PM PDT 24
Peak memory 203292 kb
Host smart-56388ef6-b748-44f5-a68d-76718a643b0f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=81099444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.81099444
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2359823909
Short name T423
Test name
Test status
Simulation time 7188048941 ps
CPU time 30.42 seconds
Started Jul 26 04:25:14 PM PDT 24
Finished Jul 26 04:25:45 PM PDT 24
Peak memory 203100 kb
Host smart-8ad5ac78-7ac0-440a-a1d4-3b3c31b16f0b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359823909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2359823909
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3323737947
Short name T506
Test name
Test status
Simulation time 9468785996 ps
CPU time 27.63 seconds
Started Jul 26 04:24:29 PM PDT 24
Finished Jul 26 04:24:57 PM PDT 24
Peak memory 203108 kb
Host smart-70fd3d0b-5aa1-4652-a19d-3f7e0dae4a25
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3323737947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3323737947
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2929649293
Short name T779
Test name
Test status
Simulation time 44154742 ps
CPU time 2.54 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:25:18 PM PDT 24
Peak memory 203032 kb
Host smart-6ebfd30c-f152-4dd9-953b-168430b8ead4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929649293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2929649293
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.2848139987
Short name T2
Test name
Test status
Simulation time 2848770079 ps
CPU time 67.65 seconds
Started Jul 26 04:20:47 PM PDT 24
Finished Jul 26 04:21:55 PM PDT 24
Peak memory 205976 kb
Host smart-344750de-db21-4f32-b7d0-631e587d62a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2848139987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2848139987
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1053621934
Short name T197
Test name
Test status
Simulation time 1208237648 ps
CPU time 60.83 seconds
Started Jul 26 04:26:10 PM PDT 24
Finished Jul 26 04:27:11 PM PDT 24
Peak memory 206744 kb
Host smart-2568c529-4759-4348-8a21-5a40a82fda5c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1053621934 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1053621934
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.1729768850
Short name T419
Test name
Test status
Simulation time 255969843 ps
CPU time 3.94 seconds
Started Jul 26 04:22:57 PM PDT 24
Finished Jul 26 04:23:01 PM PDT 24
Peak memory 204456 kb
Host smart-0c9a5633-fffa-4957-b506-1684d858456d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1729768850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1729768850
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.2073893492
Short name T600
Test name
Test status
Simulation time 2238540977 ps
CPU time 22.12 seconds
Started Jul 26 04:25:29 PM PDT 24
Finished Jul 26 04:25:52 PM PDT 24
Peak memory 211340 kb
Host smart-b5580c28-8c82-4e27-84ae-dab98288620d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2073893492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.2073893492
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.1475811233
Short name T82
Test name
Test status
Simulation time 71500032542 ps
CPU time 334.66 seconds
Started Jul 26 04:26:07 PM PDT 24
Finished Jul 26 04:31:42 PM PDT 24
Peak memory 205760 kb
Host smart-70999d41-d33c-46fa-b145-91441ba16381
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1475811233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo
w_rsp.1475811233
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.3719347590
Short name T684
Test name
Test status
Simulation time 69599538 ps
CPU time 8.25 seconds
Started Jul 26 04:20:44 PM PDT 24
Finished Jul 26 04:20:53 PM PDT 24
Peak memory 203368 kb
Host smart-b73520d5-5cc6-4e43-badf-90aa70fe2af7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3719347590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.3719347590
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.2350831833
Short name T464
Test name
Test status
Simulation time 318005127 ps
CPU time 21.74 seconds
Started Jul 26 04:25:29 PM PDT 24
Finished Jul 26 04:25:51 PM PDT 24
Peak memory 203108 kb
Host smart-5193cc59-664b-4a8a-bf8c-bcd885797295
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2350831833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2350831833
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.2255105285
Short name T644
Test name
Test status
Simulation time 1205523985 ps
CPU time 17.84 seconds
Started Jul 26 04:26:10 PM PDT 24
Finished Jul 26 04:26:28 PM PDT 24
Peak memory 211268 kb
Host smart-6baad835-2d8e-4f83-8a63-0b8b89f4a57b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2255105285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.2255105285
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1494660405
Short name T659
Test name
Test status
Simulation time 32562064354 ps
CPU time 197.04 seconds
Started Jul 26 04:25:07 PM PDT 24
Finished Jul 26 04:28:24 PM PDT 24
Peak memory 210716 kb
Host smart-13cc8720-8024-487e-be0a-6a79b639ad9c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494660405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1494660405
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.1744182345
Short name T827
Test name
Test status
Simulation time 19731902673 ps
CPU time 133.49 seconds
Started Jul 26 04:26:10 PM PDT 24
Finished Jul 26 04:28:24 PM PDT 24
Peak memory 204444 kb
Host smart-6ef201ed-4fde-441f-942d-5dc389de222a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1744182345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1744182345
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.2391422664
Short name T350
Test name
Test status
Simulation time 81937811 ps
CPU time 3.13 seconds
Started Jul 26 04:22:39 PM PDT 24
Finished Jul 26 04:22:42 PM PDT 24
Peak memory 203320 kb
Host smart-9a5958bc-5a81-4c31-b384-ce670b6357e4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391422664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.2391422664
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.2138985069
Short name T643
Test name
Test status
Simulation time 550475003 ps
CPU time 17.02 seconds
Started Jul 26 04:25:52 PM PDT 24
Finished Jul 26 04:26:09 PM PDT 24
Peak memory 202516 kb
Host smart-04425e36-a382-4160-a4bd-8e3f62279f55
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2138985069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2138985069
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.135147538
Short name T825
Test name
Test status
Simulation time 214344955 ps
CPU time 3.78 seconds
Started Jul 26 04:26:09 PM PDT 24
Finished Jul 26 04:26:13 PM PDT 24
Peak memory 202484 kb
Host smart-5aaccc11-c600-4e79-9530-a9c685797675
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=135147538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.135147538
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3344803019
Short name T499
Test name
Test status
Simulation time 8425730939 ps
CPU time 30.43 seconds
Started Jul 26 04:26:10 PM PDT 24
Finished Jul 26 04:26:41 PM PDT 24
Peak memory 203132 kb
Host smart-85d84905-ee8b-434a-8946-8ebbd2b3898b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344803019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3344803019
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.1338278564
Short name T301
Test name
Test status
Simulation time 4408653600 ps
CPU time 33.27 seconds
Started Jul 26 04:25:17 PM PDT 24
Finished Jul 26 04:25:51 PM PDT 24
Peak memory 203132 kb
Host smart-ce35c2ea-c163-40b6-9529-c1bdb25da4d8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1338278564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1338278564
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.3175759790
Short name T708
Test name
Test status
Simulation time 96000310 ps
CPU time 2.13 seconds
Started Jul 26 04:21:52 PM PDT 24
Finished Jul 26 04:21:54 PM PDT 24
Peak memory 203200 kb
Host smart-85f9e8fd-bedc-4d59-8db9-ee8c39c7e566
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175759790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3175759790
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.1569425999
Short name T551
Test name
Test status
Simulation time 4062085172 ps
CPU time 23.16 seconds
Started Jul 26 04:21:50 PM PDT 24
Finished Jul 26 04:22:14 PM PDT 24
Peak memory 205104 kb
Host smart-05e85f22-d4b6-4c32-9899-30e5e3fce1a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1569425999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1569425999
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.3047873858
Short name T674
Test name
Test status
Simulation time 1009521246 ps
CPU time 33.14 seconds
Started Jul 26 04:20:25 PM PDT 24
Finished Jul 26 04:20:58 PM PDT 24
Peak memory 204520 kb
Host smart-852289d6-2cfb-4d3b-b8b0-3737e70a9b4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3047873858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3047873858
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.2808204385
Short name T607
Test name
Test status
Simulation time 1795153273 ps
CPU time 144.16 seconds
Started Jul 26 04:20:12 PM PDT 24
Finished Jul 26 04:22:37 PM PDT 24
Peak memory 208432 kb
Host smart-9ce630e7-c023-449d-95ff-09e60ed4718d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2808204385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand
_reset.2808204385
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.502189185
Short name T884
Test name
Test status
Simulation time 4047044138 ps
CPU time 170.96 seconds
Started Jul 26 04:26:10 PM PDT 24
Finished Jul 26 04:29:01 PM PDT 24
Peak memory 211020 kb
Host smart-1cdded2e-c5e1-461a-b56e-0ddc5b36721b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=502189185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rese
t_error.502189185
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1101034135
Short name T662
Test name
Test status
Simulation time 486333984 ps
CPU time 10.69 seconds
Started Jul 26 04:21:45 PM PDT 24
Finished Jul 26 04:21:56 PM PDT 24
Peak memory 204840 kb
Host smart-0908a3e8-287e-4747-80db-882ac8df34e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1101034135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1101034135
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1502626194
Short name T126
Test name
Test status
Simulation time 1291786587 ps
CPU time 29.66 seconds
Started Jul 26 04:20:50 PM PDT 24
Finished Jul 26 04:21:20 PM PDT 24
Peak memory 211544 kb
Host smart-b1d6a278-396d-4d5a-a7ba-be0cb5aba825
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1502626194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1502626194
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.3500643776
Short name T677
Test name
Test status
Simulation time 15643587808 ps
CPU time 38.43 seconds
Started Jul 26 04:20:12 PM PDT 24
Finished Jul 26 04:20:51 PM PDT 24
Peak memory 203356 kb
Host smart-e8b2b69d-744a-4b82-a76e-ed31d810cd70
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3500643776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo
w_rsp.3500643776
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.575506394
Short name T234
Test name
Test status
Simulation time 90200297 ps
CPU time 10.7 seconds
Started Jul 26 04:20:22 PM PDT 24
Finished Jul 26 04:20:33 PM PDT 24
Peak memory 203472 kb
Host smart-a92e83e6-a8a5-4b6a-aca1-fd4666461dff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=575506394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.575506394
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.3301380400
Short name T17
Test name
Test status
Simulation time 2014998137 ps
CPU time 30.33 seconds
Started Jul 26 04:25:15 PM PDT 24
Finished Jul 26 04:25:46 PM PDT 24
Peak memory 202220 kb
Host smart-b20bcc39-2bb6-47b1-a281-321ddee0b36b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3301380400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3301380400
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.2869215418
Short name T454
Test name
Test status
Simulation time 161516026 ps
CPU time 18.7 seconds
Started Jul 26 04:21:36 PM PDT 24
Finished Jul 26 04:21:55 PM PDT 24
Peak memory 204396 kb
Host smart-37626613-f514-4c9e-b427-3188f5bc2eb4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2869215418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.2869215418
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.1045517306
Short name T138
Test name
Test status
Simulation time 14731581214 ps
CPU time 67.9 seconds
Started Jul 26 04:20:12 PM PDT 24
Finished Jul 26 04:21:20 PM PDT 24
Peak memory 204756 kb
Host smart-1119d10b-1989-46b5-b820-6ef449de2fd5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045517306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1045517306
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.745703449
Short name T428
Test name
Test status
Simulation time 1062903376 ps
CPU time 9.87 seconds
Started Jul 26 04:20:13 PM PDT 24
Finished Jul 26 04:20:23 PM PDT 24
Peak memory 203336 kb
Host smart-267cc560-753a-4967-87a2-15ceba4ab9a8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=745703449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.745703449
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.1645446474
Short name T414
Test name
Test status
Simulation time 93224552 ps
CPU time 6.26 seconds
Started Jul 26 04:26:02 PM PDT 24
Finished Jul 26 04:26:09 PM PDT 24
Peak memory 204352 kb
Host smart-b7f812e5-9b5c-49fb-9646-53f1a2e63d6b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645446474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1645446474
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.3814015874
Short name T488
Test name
Test status
Simulation time 1089906704 ps
CPU time 20.51 seconds
Started Jul 26 04:20:24 PM PDT 24
Finished Jul 26 04:20:44 PM PDT 24
Peak memory 203884 kb
Host smart-c9c73d2c-ffd0-4e2a-a216-ce39b71c1502
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3814015874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3814015874
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.707220247
Short name T564
Test name
Test status
Simulation time 128096400 ps
CPU time 2.82 seconds
Started Jul 26 04:20:12 PM PDT 24
Finished Jul 26 04:20:15 PM PDT 24
Peak memory 203280 kb
Host smart-4b6f76bd-9d4b-412c-8336-00940abd8dbc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=707220247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.707220247
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3888378810
Short name T834
Test name
Test status
Simulation time 10519865298 ps
CPU time 33.1 seconds
Started Jul 26 04:26:01 PM PDT 24
Finished Jul 26 04:26:35 PM PDT 24
Peak memory 203116 kb
Host smart-cb0f5f0d-6069-4cf4-80d1-d683acda752b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888378810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3888378810
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.829348350
Short name T757
Test name
Test status
Simulation time 2882933028 ps
CPU time 24.55 seconds
Started Jul 26 04:20:12 PM PDT 24
Finished Jul 26 04:20:37 PM PDT 24
Peak memory 203380 kb
Host smart-5c727ca0-894a-431c-b231-f251c4be6494
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=829348350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.829348350
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.2818141461
Short name T463
Test name
Test status
Simulation time 26318147 ps
CPU time 2.2 seconds
Started Jul 26 04:20:15 PM PDT 24
Finished Jul 26 04:20:17 PM PDT 24
Peak memory 203272 kb
Host smart-53038fff-7ddf-46d2-b6d8-3c187cb0db1f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818141461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2818141461
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.2744301792
Short name T412
Test name
Test status
Simulation time 619823917 ps
CPU time 37.83 seconds
Started Jul 26 04:20:47 PM PDT 24
Finished Jul 26 04:21:25 PM PDT 24
Peak memory 206572 kb
Host smart-462aabc9-bdc2-429d-94b6-849d0227c005
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2744301792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2744301792
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.1446014139
Short name T637
Test name
Test status
Simulation time 2495831643 ps
CPU time 77.99 seconds
Started Jul 26 04:20:26 PM PDT 24
Finished Jul 26 04:21:44 PM PDT 24
Peak memory 205816 kb
Host smart-bae4a521-69ef-431c-b0c4-e34796682073
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1446014139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1446014139
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.2301661099
Short name T556
Test name
Test status
Simulation time 158195655 ps
CPU time 62.29 seconds
Started Jul 26 04:25:13 PM PDT 24
Finished Jul 26 04:26:16 PM PDT 24
Peak memory 206620 kb
Host smart-0e546bbd-ab27-4109-bfae-711c4d5820cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2301661099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand
_reset.2301661099
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.4161523351
Short name T222
Test name
Test status
Simulation time 95818423 ps
CPU time 37.06 seconds
Started Jul 26 04:21:26 PM PDT 24
Finished Jul 26 04:22:03 PM PDT 24
Peak memory 206180 kb
Host smart-d07f748b-2e42-4bca-8c65-877606d24f15
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4161523351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res
et_error.4161523351
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.3767099313
Short name T580
Test name
Test status
Simulation time 112749567 ps
CPU time 13.12 seconds
Started Jul 26 04:20:21 PM PDT 24
Finished Jul 26 04:20:34 PM PDT 24
Peak memory 211816 kb
Host smart-97ccaf70-0598-4993-8d38-4fee0535f6bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3767099313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3767099313
Directory /workspace/9.xbar_unmapped_addr/latest
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