Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 507 1 T3 1 T10 2 T11 1
all_values[1] 495 1 T9 1 T18 1 T17 7
all_values[2] 491 1 T3 2 T4 1 T9 2
all_values[3] 504 1 T9 1 T11 1 T17 2
all_values[4] 536 1 T4 2 T10 1 T18 1
all_values[5] 514 1 T3 1 T4 1 T10 1
all_values[6] 466 1 T18 1 T17 4 T24 4
all_values[7] 521 1 T3 1 T4 1 T17 4
all_values[8] 440 1 T4 1 T10 2 T17 2
all_values[9] 480 1 T3 1 T4 1 T11 2
all_values[10] 495 1 T4 1 T10 2 T11 2
all_values[11] 488 1 T3 2 T4 2 T9 1
all_values[12] 453 1 T3 1 T11 1 T18 1
all_values[13] 521 1 T4 3 T9 1 T10 1
all_values[14] 513 1 T9 1 T10 2 T17 4
all_values[15] 516 1 T3 1 T4 4 T10 1
all_values[16] 517 1 T3 1 T4 1 T10 2
all_values[17] 514 1 T3 2 T4 2 T17 5
all_values[18] 524 1 T3 1 T4 2 T9 1
all_values[19] 510 1 T3 1 T4 1 T10 2
all_values[20] 478 1 T3 2 T4 1 T11 1
all_values[21] 464 1 T4 1 T10 1 T17 3
all_values[22] 517 1 T3 1 T4 3 T17 3
all_values[23] 537 1 T3 1 T4 2 T10 1

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