Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1808	1			T3	8		T13	2		T16	5
all_values[1]	1807	1			T3	8		T8	1		T13	3
all_values[2]	1835	1			T3	4		T8	2		T13	4
all_values[3]	1822	1			T3	4		T8	2		T13	1
all_values[4]	1781	1			T3	8		T13	3		T16	3
all_values[5]	1833	1			T3	5		T8	4		T13	2
all_values[6]	1861	1			T3	5		T8	2		T13	2
all_values[7]	1741	1			T3	5		T8	7		T13	2
all_values[8]	1796	1			T3	6		T8	3		T13	4
all_values[9]	1834	1			T3	4		T8	1		T13	3
all_values[10]	1780	1			T3	7		T8	2		T13	2
all_values[11]	1781	1			T3	4		T8	1		T13	1
all_values[12]	1843	1			T3	6		T8	4		T13	3
all_values[13]	1751	1			T3	5		T8	3		T13	4
all_values[14]	1760	1			T3	2		T8	4		T13	1
all_values[15]	1816	1			T3	3		T8	1		T13	5
all_values[16]	1764	1			T3	2		T8	4		T13	2
all_values[17]	1841	1			T3	5		T8	2		T13	3
all_values[18]	1795	1			T3	5		T8	2		T13	4
all_values[19]	1782	1			T3	2		T8	1		T13	1
all_values[20]	1755	1			T3	6		T8	6		T13	4
all_values[21]	1894	1			T3	4		T8	4		T13	1
all_values[22]	1786	1			T3	2		T13	3		T16	4
all_values[23]	1820	1			T3	6		T8	1		T13	6
all_values[24]	1746	1			T3	3		T8	1		T13	1
all_values[25]	1799	1			T3	8		T8	3		T13	3
all_values[26]	1866	1			T3	6		T8	5		T13	2
all_values[27]	1768	1			T3	6		T8	1		T13	2
all_values[28]	1787	1			T3	5		T13	1		T16	3
all_values[29]	1830	1			T3	3		T8	5		T16	1
all_values[30]	1875	1			T3	8		T8	1		T13	1
all_values[31]	1807	1			T3	7		T8	3		T13	4
all_values[32]	1813	1			T3	8		T8	6		T13	4
all_values[33]	1759	1			T3	6		T8	3		T13	4
all_values[34]	1859	1			T3	3		T13	4		T16	5
all_values[35]	1808	1			T3	4		T8	2		T13	2
all_values[36]	1825	1			T3	4		T8	1		T13	1
all_values[37]	1785	1			T3	6		T8	1		T13	1
all_values[38]	1782	1			T3	4		T8	1		T13	10
all_values[39]	1875	1			T3	3		T8	3		T13	4
all_values[40]	1815	1			T3	3		T8	1		T13	4
all_values[41]	1828	1			T3	11		T8	4		T13	2
all_values[42]	1843	1			T3	5		T8	2		T13	2
all_values[43]	1814	1			T3	9		T8	2		T13	2
all_values[44]	1836	1			T3	7		T8	3		T13	4
all_values[45]	1842	1			T3	7		T8	3		T13	1
all_values[46]	1774	1			T3	4		T8	3		T13	6
all_values[47]	1867	1			T3	3		T8	1		T13	1
all_values[48]	1787	1			T3	4		T8	4		T13	3
all_values[49]	1777	1			T3	4		T8	2		T13	4
all_values[50]	1782	1			T3	4		T8	3		T13	3
all_values[51]	1892	1			T3	8		T8	3		T13	2
all_values[52]	1773	1			T3	5		T8	2		T13	4
all_values[53]	1875	1			T3	6		T13	2		T16	1
all_values[54]	1753	1			T3	6		T13	3		T16	3
all_values[55]	1862	1			T3	4		T8	2		T13	4
all_values[56]	1828	1			T3	7		T8	5		T13	2
all_values[57]	1833	1			T3	4		T8	3		T13	4
all_values[58]	1791	1			T3	5		T8	1		T13	2
all_values[59]	1859	1			T3	7		T8	3		T13	4
all_values[60]	1885	1			T3	4		T8	3		T13	4
all_values[61]	1808	1			T3	2		T8	5		T13	2
all_values[62]	1774	1			T3	4		T8	4		T13	2
all_values[63]	1879	1			T3	4		T8	1		T13	1