Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.02 99.26 88.94 98.80 95.88 99.26 100.00


Total test records in report: 900
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T762 /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3226533855 Jul 27 04:23:47 PM PDT 24 Jul 27 04:24:43 PM PDT 24 3625640512 ps
T763 /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.406342360 Jul 27 04:22:09 PM PDT 24 Jul 27 04:24:32 PM PDT 24 6455896010 ps
T764 /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2354174713 Jul 27 04:23:54 PM PDT 24 Jul 27 04:23:56 PM PDT 24 26844674 ps
T765 /workspace/coverage/xbar_build_mode/27.xbar_stress_all.1771939009 Jul 27 04:23:02 PM PDT 24 Jul 27 04:24:34 PM PDT 24 870276907 ps
T766 /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3269757809 Jul 27 04:22:38 PM PDT 24 Jul 27 04:24:12 PM PDT 24 45641944120 ps
T767 /workspace/coverage/xbar_build_mode/1.xbar_stress_all.1439546129 Jul 27 04:19:31 PM PDT 24 Jul 27 04:19:41 PM PDT 24 1551859617 ps
T768 /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3741165119 Jul 27 04:23:16 PM PDT 24 Jul 27 04:25:03 PM PDT 24 8625828523 ps
T214 /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.4131518259 Jul 27 04:24:07 PM PDT 24 Jul 27 04:28:17 PM PDT 24 124345721488 ps
T769 /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1581331297 Jul 27 04:23:21 PM PDT 24 Jul 27 04:23:40 PM PDT 24 913375189 ps
T770 /workspace/coverage/xbar_build_mode/46.xbar_error_random.2497422761 Jul 27 04:23:57 PM PDT 24 Jul 27 04:24:12 PM PDT 24 1123452131 ps
T771 /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.4099324893 Jul 27 04:23:56 PM PDT 24 Jul 27 04:24:15 PM PDT 24 195690117 ps
T772 /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.1343391902 Jul 27 04:23:17 PM PDT 24 Jul 27 04:23:22 PM PDT 24 126335132 ps
T773 /workspace/coverage/xbar_build_mode/13.xbar_same_source.177140601 Jul 27 04:22:07 PM PDT 24 Jul 27 04:22:11 PM PDT 24 187893653 ps
T774 /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.2775047797 Jul 27 04:23:25 PM PDT 24 Jul 27 04:24:25 PM PDT 24 481851298 ps
T775 /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.893850225 Jul 27 04:23:38 PM PDT 24 Jul 27 04:26:13 PM PDT 24 21369455149 ps
T776 /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.3489670446 Jul 27 04:22:23 PM PDT 24 Jul 27 04:22:27 PM PDT 24 50874552 ps
T777 /workspace/coverage/xbar_build_mode/18.xbar_same_source.3826166875 Jul 27 04:20:42 PM PDT 24 Jul 27 04:20:56 PM PDT 24 242296736 ps
T778 /workspace/coverage/xbar_build_mode/9.xbar_error_random.2381867942 Jul 27 04:19:38 PM PDT 24 Jul 27 04:20:10 PM PDT 24 1628852876 ps
T779 /workspace/coverage/xbar_build_mode/3.xbar_same_source.1348837157 Jul 27 04:19:44 PM PDT 24 Jul 27 04:19:47 PM PDT 24 77355254 ps
T780 /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.3864247748 Jul 27 04:23:41 PM PDT 24 Jul 27 04:27:25 PM PDT 24 39331005803 ps
T781 /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1660202320 Jul 27 04:17:34 PM PDT 24 Jul 27 04:18:30 PM PDT 24 25493743879 ps
T782 /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.848665450 Jul 27 04:23:55 PM PDT 24 Jul 27 04:31:16 PM PDT 24 182408159710 ps
T783 /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2395403024 Jul 27 04:23:56 PM PDT 24 Jul 27 04:27:26 PM PDT 24 30238967255 ps
T784 /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.2393349335 Jul 27 04:22:29 PM PDT 24 Jul 27 04:23:32 PM PDT 24 7472847286 ps
T785 /workspace/coverage/xbar_build_mode/39.xbar_smoke.2396910764 Jul 27 04:23:40 PM PDT 24 Jul 27 04:23:43 PM PDT 24 307633099 ps
T786 /workspace/coverage/xbar_build_mode/31.xbar_stress_all.1604241096 Jul 27 04:23:13 PM PDT 24 Jul 27 04:23:42 PM PDT 24 2543327775 ps
T787 /workspace/coverage/xbar_build_mode/19.xbar_random.485177048 Jul 27 04:22:23 PM PDT 24 Jul 27 04:22:27 PM PDT 24 63845847 ps
T788 /workspace/coverage/xbar_build_mode/2.xbar_random.1381929324 Jul 27 04:18:39 PM PDT 24 Jul 27 04:18:59 PM PDT 24 1056934998 ps
T789 /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.2219827285 Jul 27 04:23:14 PM PDT 24 Jul 27 04:23:48 PM PDT 24 5387709032 ps
T790 /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1743100281 Jul 27 04:23:48 PM PDT 24 Jul 27 04:24:19 PM PDT 24 7898251507 ps
T256 /workspace/coverage/xbar_build_mode/46.xbar_random.1791813 Jul 27 04:24:03 PM PDT 24 Jul 27 04:24:42 PM PDT 24 1755939463 ps
T791 /workspace/coverage/xbar_build_mode/32.xbar_stress_all.2485451721 Jul 27 04:23:13 PM PDT 24 Jul 27 04:24:01 PM PDT 24 1420013309 ps
T792 /workspace/coverage/xbar_build_mode/21.xbar_smoke.1803466815 Jul 27 04:23:20 PM PDT 24 Jul 27 04:23:23 PM PDT 24 141465654 ps
T793 /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2347686105 Jul 27 04:23:06 PM PDT 24 Jul 27 04:25:35 PM PDT 24 70218330772 ps
T26 /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.251578544 Jul 27 04:22:48 PM PDT 24 Jul 27 04:24:17 PM PDT 24 274647001 ps
T794 /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3725261419 Jul 27 04:24:06 PM PDT 24 Jul 27 04:24:09 PM PDT 24 58238107 ps
T795 /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.553846377 Jul 27 04:18:46 PM PDT 24 Jul 27 04:22:14 PM PDT 24 410176070 ps
T215 /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.3906364198 Jul 27 04:23:18 PM PDT 24 Jul 27 04:23:55 PM PDT 24 408409148 ps
T796 /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.4158376407 Jul 27 04:22:27 PM PDT 24 Jul 27 04:25:37 PM PDT 24 31337252235 ps
T797 /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.522540393 Jul 27 04:23:25 PM PDT 24 Jul 27 04:23:54 PM PDT 24 1069513536 ps
T798 /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.679586941 Jul 27 04:22:38 PM PDT 24 Jul 27 04:23:36 PM PDT 24 726876779 ps
T799 /workspace/coverage/xbar_build_mode/11.xbar_error_random.3839703209 Jul 27 04:19:00 PM PDT 24 Jul 27 04:19:03 PM PDT 24 224436756 ps
T800 /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.741168286 Jul 27 04:23:50 PM PDT 24 Jul 27 04:24:19 PM PDT 24 5840111617 ps
T801 /workspace/coverage/xbar_build_mode/29.xbar_random.3176595432 Jul 27 04:23:09 PM PDT 24 Jul 27 04:23:19 PM PDT 24 639342710 ps
T802 /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.3515365681 Jul 27 04:21:06 PM PDT 24 Jul 27 04:21:30 PM PDT 24 137762183 ps
T803 /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.1106289687 Jul 27 04:18:51 PM PDT 24 Jul 27 04:18:59 PM PDT 24 180218556 ps
T804 /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1999366094 Jul 27 04:23:20 PM PDT 24 Jul 27 04:25:05 PM PDT 24 3472833435 ps
T805 /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1028985241 Jul 27 04:24:07 PM PDT 24 Jul 27 04:26:55 PM PDT 24 328614178 ps
T806 /workspace/coverage/xbar_build_mode/47.xbar_stress_all.32378741 Jul 27 04:24:10 PM PDT 24 Jul 27 04:26:26 PM PDT 24 4312255403 ps
T807 /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.528139819 Jul 27 04:23:07 PM PDT 24 Jul 27 04:30:52 PM PDT 24 79576262052 ps
T808 /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.2361420102 Jul 27 04:23:50 PM PDT 24 Jul 27 04:24:20 PM PDT 24 3591528012 ps
T809 /workspace/coverage/xbar_build_mode/26.xbar_stress_all.2009313436 Jul 27 04:23:06 PM PDT 24 Jul 27 04:27:40 PM PDT 24 12765762301 ps
T810 /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3609326246 Jul 27 04:23:38 PM PDT 24 Jul 27 04:24:03 PM PDT 24 7936411003 ps
T811 /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.4112771675 Jul 27 04:24:47 PM PDT 24 Jul 27 04:24:50 PM PDT 24 32083823 ps
T812 /workspace/coverage/xbar_build_mode/45.xbar_random.2066196611 Jul 27 04:23:55 PM PDT 24 Jul 27 04:24:16 PM PDT 24 740397134 ps
T813 /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2796133035 Jul 27 04:22:07 PM PDT 24 Jul 27 04:22:11 PM PDT 24 144685846 ps
T814 /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.916339921 Jul 27 04:23:09 PM PDT 24 Jul 27 04:29:52 PM PDT 24 8543809307 ps
T815 /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1836593404 Jul 27 04:24:06 PM PDT 24 Jul 27 04:33:03 PM PDT 24 62108229383 ps
T816 /workspace/coverage/xbar_build_mode/46.xbar_stress_all.493029445 Jul 27 04:24:04 PM PDT 24 Jul 27 04:26:21 PM PDT 24 10886550136 ps
T817 /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.4102876346 Jul 27 04:18:08 PM PDT 24 Jul 27 04:19:33 PM PDT 24 242483202 ps
T818 /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.4100269433 Jul 27 04:23:16 PM PDT 24 Jul 27 04:23:36 PM PDT 24 152758328 ps
T819 /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.3235536777 Jul 27 04:23:04 PM PDT 24 Jul 27 04:23:24 PM PDT 24 171058783 ps
T820 /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2511632095 Jul 27 04:22:35 PM PDT 24 Jul 27 04:24:11 PM PDT 24 294555737 ps
T821 /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.1014551253 Jul 27 04:23:14 PM PDT 24 Jul 27 04:23:54 PM PDT 24 13924755928 ps
T822 /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.241222259 Jul 27 04:23:24 PM PDT 24 Jul 27 04:23:53 PM PDT 24 3306954456 ps
T823 /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.1657627222 Jul 27 04:22:34 PM PDT 24 Jul 27 04:23:00 PM PDT 24 3288348897 ps
T824 /workspace/coverage/xbar_build_mode/19.xbar_error_random.3560211969 Jul 27 04:22:21 PM PDT 24 Jul 27 04:22:37 PM PDT 24 836400125 ps
T825 /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3771354338 Jul 27 04:23:26 PM PDT 24 Jul 27 04:27:19 PM PDT 24 1093209952 ps
T826 /workspace/coverage/xbar_build_mode/40.xbar_error_random.675627642 Jul 27 04:23:33 PM PDT 24 Jul 27 04:23:44 PM PDT 24 1225192743 ps
T827 /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.2962090150 Jul 27 04:23:13 PM PDT 24 Jul 27 04:23:18 PM PDT 24 37245266 ps
T151 /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1759753904 Jul 27 04:23:32 PM PDT 24 Jul 27 04:23:34 PM PDT 24 89845969 ps
T828 /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.3115204406 Jul 27 04:22:21 PM PDT 24 Jul 27 04:23:01 PM PDT 24 19514387123 ps
T829 /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.133575121 Jul 27 04:22:01 PM PDT 24 Jul 27 04:22:22 PM PDT 24 411558806 ps
T830 /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2109902425 Jul 27 04:22:07 PM PDT 24 Jul 27 04:22:10 PM PDT 24 27593200 ps
T831 /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.3421334349 Jul 27 04:23:19 PM PDT 24 Jul 27 04:23:45 PM PDT 24 3470664494 ps
T832 /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.115851222 Jul 27 04:23:29 PM PDT 24 Jul 27 04:24:55 PM PDT 24 1815051824 ps
T833 /workspace/coverage/xbar_build_mode/12.xbar_random.4019615343 Jul 27 04:22:51 PM PDT 24 Jul 27 04:23:04 PM PDT 24 148405970 ps
T834 /workspace/coverage/xbar_build_mode/5.xbar_stress_all.2706921940 Jul 27 04:18:22 PM PDT 24 Jul 27 04:21:02 PM PDT 24 10813963442 ps
T835 /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.3196950639 Jul 27 04:23:24 PM PDT 24 Jul 27 04:23:43 PM PDT 24 546698478 ps
T836 /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.4151019964 Jul 27 04:23:05 PM PDT 24 Jul 27 04:23:30 PM PDT 24 7220410006 ps
T837 /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3689394983 Jul 27 04:23:40 PM PDT 24 Jul 27 04:24:32 PM PDT 24 189263998 ps
T838 /workspace/coverage/xbar_build_mode/16.xbar_random.3574865895 Jul 27 04:23:01 PM PDT 24 Jul 27 04:23:08 PM PDT 24 218496516 ps
T839 /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.4021508933 Jul 27 04:23:16 PM PDT 24 Jul 27 04:30:19 PM PDT 24 3033623772 ps
T840 /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.4094815688 Jul 27 04:18:49 PM PDT 24 Jul 27 04:19:28 PM PDT 24 22826703830 ps
T841 /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.4011941507 Jul 27 04:19:31 PM PDT 24 Jul 27 04:20:02 PM PDT 24 8570305517 ps
T842 /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1259527285 Jul 27 04:22:11 PM PDT 24 Jul 27 04:22:40 PM PDT 24 11176981305 ps
T843 /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.1869139102 Jul 27 04:23:38 PM PDT 24 Jul 27 04:24:00 PM PDT 24 230260337 ps
T844 /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.549701976 Jul 27 04:23:33 PM PDT 24 Jul 27 04:25:31 PM PDT 24 6845216596 ps
T216 /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.1172741250 Jul 27 04:23:15 PM PDT 24 Jul 27 04:23:46 PM PDT 24 465518676 ps
T845 /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.3033983310 Jul 27 04:22:06 PM PDT 24 Jul 27 04:25:33 PM PDT 24 68892612389 ps
T846 /workspace/coverage/xbar_build_mode/18.xbar_random.3692571922 Jul 27 04:22:27 PM PDT 24 Jul 27 04:22:55 PM PDT 24 940435216 ps
T847 /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.22443725 Jul 27 04:24:06 PM PDT 24 Jul 27 04:24:28 PM PDT 24 2802241030 ps
T848 /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.1078674290 Jul 27 04:23:26 PM PDT 24 Jul 27 04:23:28 PM PDT 24 19016455 ps
T849 /workspace/coverage/xbar_build_mode/31.xbar_error_random.1764058192 Jul 27 04:23:14 PM PDT 24 Jul 27 04:23:18 PM PDT 24 151273061 ps
T850 /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2103489558 Jul 27 04:25:01 PM PDT 24 Jul 27 04:25:47 PM PDT 24 21707748179 ps
T851 /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.2631252725 Jul 27 04:22:34 PM PDT 24 Jul 27 04:22:43 PM PDT 24 331095093 ps
T852 /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1101533848 Jul 27 04:23:09 PM PDT 24 Jul 27 04:32:52 PM PDT 24 80249813429 ps
T853 /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.3461422355 Jul 27 04:21:13 PM PDT 24 Jul 27 04:21:36 PM PDT 24 592845061 ps
T854 /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.104808436 Jul 27 04:17:41 PM PDT 24 Jul 27 04:18:09 PM PDT 24 4312833988 ps
T855 /workspace/coverage/xbar_build_mode/26.xbar_random.1064485865 Jul 27 04:22:54 PM PDT 24 Jul 27 04:22:58 PM PDT 24 360157133 ps
T856 /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.960753427 Jul 27 04:22:27 PM PDT 24 Jul 27 04:22:44 PM PDT 24 172891932 ps
T141 /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2611419609 Jul 27 04:18:42 PM PDT 24 Jul 27 04:26:17 PM PDT 24 162438399982 ps
T857 /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1498697783 Jul 27 04:23:06 PM PDT 24 Jul 27 04:23:34 PM PDT 24 5245589491 ps
T858 /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.4078740350 Jul 27 04:22:08 PM PDT 24 Jul 27 04:23:39 PM PDT 24 6975440103 ps
T859 /workspace/coverage/xbar_build_mode/3.xbar_smoke.2309500471 Jul 27 04:18:55 PM PDT 24 Jul 27 04:18:57 PM PDT 24 28668938 ps
T860 /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.1840924313 Jul 27 04:23:49 PM PDT 24 Jul 27 04:23:50 PM PDT 24 26397315 ps
T861 /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1799514404 Jul 27 04:23:44 PM PDT 24 Jul 27 04:29:01 PM PDT 24 8251737499 ps
T862 /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.78853014 Jul 27 04:23:11 PM PDT 24 Jul 27 04:23:21 PM PDT 24 1481220857 ps
T863 /workspace/coverage/xbar_build_mode/18.xbar_error_random.1196972420 Jul 27 04:22:25 PM PDT 24 Jul 27 04:22:36 PM PDT 24 360321596 ps
T864 /workspace/coverage/xbar_build_mode/38.xbar_error_random.3153327156 Jul 27 04:23:41 PM PDT 24 Jul 27 04:24:07 PM PDT 24 770383340 ps
T22 /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1219724385 Jul 27 04:22:27 PM PDT 24 Jul 27 04:27:16 PM PDT 24 2499809948 ps
T865 /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.3017441263 Jul 27 04:18:40 PM PDT 24 Jul 27 04:20:35 PM PDT 24 23491490266 ps
T866 /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2104268031 Jul 27 04:23:47 PM PDT 24 Jul 27 04:24:19 PM PDT 24 7187653238 ps
T867 /workspace/coverage/xbar_build_mode/13.xbar_error_random.1077536543 Jul 27 04:22:22 PM PDT 24 Jul 27 04:22:55 PM PDT 24 1305744532 ps
T868 /workspace/coverage/xbar_build_mode/26.xbar_same_source.1296174472 Jul 27 04:23:07 PM PDT 24 Jul 27 04:23:21 PM PDT 24 712392700 ps
T869 /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.92582380 Jul 27 04:20:15 PM PDT 24 Jul 27 04:20:43 PM PDT 24 3556333204 ps
T870 /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1836502654 Jul 27 04:22:11 PM PDT 24 Jul 27 04:22:25 PM PDT 24 1509206297 ps
T871 /workspace/coverage/xbar_build_mode/49.xbar_random.1590861250 Jul 27 04:24:05 PM PDT 24 Jul 27 04:24:18 PM PDT 24 494577090 ps
T872 /workspace/coverage/xbar_build_mode/34.xbar_error_random.4039576352 Jul 27 04:23:24 PM PDT 24 Jul 27 04:23:35 PM PDT 24 114103566 ps
T873 /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.4040864431 Jul 27 04:24:05 PM PDT 24 Jul 27 04:27:26 PM PDT 24 102845041458 ps
T874 /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1442274336 Jul 27 04:22:06 PM PDT 24 Jul 27 04:22:08 PM PDT 24 68034135 ps
T875 /workspace/coverage/xbar_build_mode/12.xbar_stress_all.2204891653 Jul 27 04:19:26 PM PDT 24 Jul 27 04:22:35 PM PDT 24 7650712931 ps
T146 /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2500765186 Jul 27 04:23:44 PM PDT 24 Jul 27 04:32:27 PM PDT 24 9161776000 ps
T876 /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.1027792793 Jul 27 04:23:21 PM PDT 24 Jul 27 04:28:31 PM PDT 24 187572832484 ps
T877 /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.3683396688 Jul 27 04:17:48 PM PDT 24 Jul 27 04:17:50 PM PDT 24 38701817 ps
T878 /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.4246093829 Jul 27 04:22:06 PM PDT 24 Jul 27 04:22:18 PM PDT 24 200190472 ps
T879 /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1316632125 Jul 27 04:22:47 PM PDT 24 Jul 27 04:26:04 PM PDT 24 47943588976 ps
T880 /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.1877523394 Jul 27 04:22:24 PM PDT 24 Jul 27 04:22:52 PM PDT 24 6654123232 ps
T881 /workspace/coverage/xbar_build_mode/1.xbar_error_random.1928757463 Jul 27 04:19:40 PM PDT 24 Jul 27 04:19:55 PM PDT 24 575307610 ps
T152 /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2985309168 Jul 27 04:23:54 PM PDT 24 Jul 27 04:24:17 PM PDT 24 3286860328 ps
T882 /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1325668298 Jul 27 04:21:31 PM PDT 24 Jul 27 04:21:52 PM PDT 24 644157932 ps
T883 /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2929308599 Jul 27 04:23:26 PM PDT 24 Jul 27 04:24:12 PM PDT 24 1503221883 ps
T884 /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1597274578 Jul 27 04:22:30 PM PDT 24 Jul 27 04:22:33 PM PDT 24 77118602 ps
T885 /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2655147244 Jul 27 04:23:09 PM PDT 24 Jul 27 04:25:29 PM PDT 24 477685375 ps
T886 /workspace/coverage/xbar_build_mode/23.xbar_error_random.3983947605 Jul 27 04:22:03 PM PDT 24 Jul 27 04:22:08 PM PDT 24 112732796 ps
T887 /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1664467763 Jul 27 04:23:03 PM PDT 24 Jul 27 04:23:43 PM PDT 24 9182618320 ps
T888 /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.843198855 Jul 27 04:24:05 PM PDT 24 Jul 27 04:26:40 PM PDT 24 32155795585 ps
T889 /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.1918792806 Jul 27 04:20:44 PM PDT 24 Jul 27 04:22:11 PM PDT 24 413801919 ps
T890 /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.204614928 Jul 27 04:23:04 PM PDT 24 Jul 27 04:27:41 PM PDT 24 39889665500 ps
T891 /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.4237629016 Jul 27 04:23:44 PM PDT 24 Jul 27 04:34:31 PM PDT 24 335818441399 ps
T153 /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.4144480917 Jul 27 04:22:07 PM PDT 24 Jul 27 04:22:09 PM PDT 24 43500151 ps
T892 /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.3854979062 Jul 27 04:23:20 PM PDT 24 Jul 27 04:23:41 PM PDT 24 156079378 ps
T893 /workspace/coverage/xbar_build_mode/34.xbar_smoke.50228347 Jul 27 04:23:14 PM PDT 24 Jul 27 04:23:16 PM PDT 24 33890109 ps
T894 /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.4101183714 Jul 27 04:23:26 PM PDT 24 Jul 27 04:23:33 PM PDT 24 14124736 ps
T895 /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2641412212 Jul 27 04:22:59 PM PDT 24 Jul 27 04:26:21 PM PDT 24 24047051510 ps
T896 /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2537581366 Jul 27 04:22:38 PM PDT 24 Jul 27 04:24:35 PM PDT 24 5220353148 ps
T897 /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2348715459 Jul 27 04:24:07 PM PDT 24 Jul 27 04:25:00 PM PDT 24 36205358334 ps
T898 /workspace/coverage/xbar_build_mode/30.xbar_error_random.3087139395 Jul 27 04:23:16 PM PDT 24 Jul 27 04:23:32 PM PDT 24 1188418670 ps
T899 /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.3429322691 Jul 27 04:23:13 PM PDT 24 Jul 27 04:23:23 PM PDT 24 91451757 ps
T900 /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2422837145 Jul 27 04:22:07 PM PDT 24 Jul 27 04:28:49 PM PDT 24 5981406637 ps

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.2283571491
Short name T4
Test name
Test status
Simulation time 6797826196 ps
CPU time 166.42 seconds
Started Jul 27 04:23:22 PM PDT 24
Finished Jul 27 04:26:08 PM PDT 24
Peak memory 206364 kb
Host smart-57718234-374f-4d21-9bd0-78b6d6b6a621
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2283571491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2283571491
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.3671709638
Short name T11
Test name
Test status
Simulation time 65724533298 ps
CPU time 387.49 seconds
Started Jul 27 04:22:34 PM PDT 24
Finished Jul 27 04:29:02 PM PDT 24
Peak memory 211444 kb
Host smart-924cef31-13e9-43fd-a538-7596bcf10374
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3671709638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl
ow_rsp.3671709638
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1810940547
Short name T119
Test name
Test status
Simulation time 81759487705 ps
CPU time 517.17 seconds
Started Jul 27 04:23:55 PM PDT 24
Finished Jul 27 04:32:32 PM PDT 24
Peak memory 207272 kb
Host smart-7915d100-3708-48de-aba6-8d63c9e81a6c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1810940547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl
ow_rsp.1810940547
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.589234996
Short name T79
Test name
Test status
Simulation time 305092991780 ps
CPU time 767.51 seconds
Started Jul 27 04:23:00 PM PDT 24
Finished Jul 27 04:35:47 PM PDT 24
Peak memory 211536 kb
Host smart-1b00857b-49b5-4b8b-8e56-5a8fa94215de
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=589234996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slo
w_rsp.589234996
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.2842045393
Short name T3
Test name
Test status
Simulation time 1217602841 ps
CPU time 120.75 seconds
Started Jul 27 04:21:04 PM PDT 24
Finished Jul 27 04:23:05 PM PDT 24
Peak memory 211500 kb
Host smart-b862c9dc-7e34-4ec8-931e-6ee2dc7a1b6c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2842045393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand
_reset.2842045393
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3606484738
Short name T86
Test name
Test status
Simulation time 20963637459 ps
CPU time 942.72 seconds
Started Jul 27 04:23:28 PM PDT 24
Finished Jul 27 04:39:11 PM PDT 24
Peak memory 222476 kb
Host smart-e38c1572-e358-4c6b-8825-ae3991c225e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3606484738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran
d_reset.3606484738
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.397946515
Short name T19
Test name
Test status
Simulation time 9183871726 ps
CPU time 49.46 seconds
Started Jul 27 04:22:44 PM PDT 24
Finished Jul 27 04:23:34 PM PDT 24
Peak memory 204384 kb
Host smart-cac95539-7eea-4301-adcc-7def3d074d20
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=397946515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.397946515
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2110513665
Short name T5
Test name
Test status
Simulation time 3951619250 ps
CPU time 391.3 seconds
Started Jul 27 04:20:44 PM PDT 24
Finished Jul 27 04:27:15 PM PDT 24
Peak memory 211176 kb
Host smart-e6d1a474-be50-4910-9de1-2d0721b3b640
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2110513665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran
d_reset.2110513665
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3057344442
Short name T105
Test name
Test status
Simulation time 56789160425 ps
CPU time 418.35 seconds
Started Jul 27 04:20:18 PM PDT 24
Finished Jul 27 04:27:16 PM PDT 24
Peak memory 211444 kb
Host smart-ccaa5dae-ca37-4d5e-8d4b-48218ca89f8e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3057344442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl
ow_rsp.3057344442
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.4005637088
Short name T34
Test name
Test status
Simulation time 10357278489 ps
CPU time 367.47 seconds
Started Jul 27 04:20:56 PM PDT 24
Finished Jul 27 04:27:03 PM PDT 24
Peak memory 210120 kb
Host smart-347f5c14-0604-47d0-8a21-771cd1f53364
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4005637088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran
d_reset.4005637088
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1332555369
Short name T17
Test name
Test status
Simulation time 13136511794 ps
CPU time 277.86 seconds
Started Jul 27 04:21:24 PM PDT 24
Finished Jul 27 04:26:02 PM PDT 24
Peak memory 209656 kb
Host smart-3fc90916-87f0-4105-9b05-26ffad7146ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1332555369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran
d_reset.1332555369
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1721606582
Short name T20
Test name
Test status
Simulation time 13960185919 ps
CPU time 151.19 seconds
Started Jul 27 04:22:23 PM PDT 24
Finished Jul 27 04:24:54 PM PDT 24
Peak memory 209884 kb
Host smart-34fac460-e508-488a-9060-90fd4d94011c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1721606582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand
_reset.1721606582
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.4056002161
Short name T140
Test name
Test status
Simulation time 49085569041 ps
CPU time 339.54 seconds
Started Jul 27 04:22:21 PM PDT 24
Finished Jul 27 04:28:01 PM PDT 24
Peak memory 211192 kb
Host smart-026735c6-a342-4079-859f-3d52bf0e7496
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4056002161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl
ow_rsp.4056002161
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1129108709
Short name T31
Test name
Test status
Simulation time 4111487290 ps
CPU time 498.02 seconds
Started Jul 27 04:19:56 PM PDT 24
Finished Jul 27 04:28:14 PM PDT 24
Peak memory 219876 kb
Host smart-6d231627-792c-4eec-8154-73d372fccb05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1129108709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re
set_error.1129108709
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.3314928566
Short name T6
Test name
Test status
Simulation time 370695901 ps
CPU time 12.58 seconds
Started Jul 27 04:23:03 PM PDT 24
Finished Jul 27 04:23:16 PM PDT 24
Peak memory 211868 kb
Host smart-a0877036-3d11-4929-ae18-5d7c0232b016
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3314928566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3314928566
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.1893168449
Short name T39
Test name
Test status
Simulation time 1015052997 ps
CPU time 27.13 seconds
Started Jul 27 04:22:38 PM PDT 24
Finished Jul 27 04:23:05 PM PDT 24
Peak memory 211496 kb
Host smart-6846013f-2580-445f-908d-4ee7585825ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1893168449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1893168449
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1219724385
Short name T22
Test name
Test status
Simulation time 2499809948 ps
CPU time 288.39 seconds
Started Jul 27 04:22:27 PM PDT 24
Finished Jul 27 04:27:16 PM PDT 24
Peak memory 219156 kb
Host smart-9c068453-7302-4a66-8d57-8a3b4d6cc906
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1219724385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re
set_error.1219724385
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.251578544
Short name T26
Test name
Test status
Simulation time 274647001 ps
CPU time 88.57 seconds
Started Jul 27 04:22:48 PM PDT 24
Finished Jul 27 04:24:17 PM PDT 24
Peak memory 207096 kb
Host smart-79389a9d-cc25-4c6b-9e02-a070383958de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=251578544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand
_reset.251578544
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.2374867226
Short name T28
Test name
Test status
Simulation time 7351426466 ps
CPU time 275.65 seconds
Started Jul 27 04:22:39 PM PDT 24
Finished Jul 27 04:27:15 PM PDT 24
Peak memory 219524 kb
Host smart-bde2a2f2-5762-4112-b398-ab3ca26dca16
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2374867226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res
et_error.2374867226
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.1475602760
Short name T131
Test name
Test status
Simulation time 8598731133 ps
CPU time 159.1 seconds
Started Jul 27 04:22:21 PM PDT 24
Finished Jul 27 04:25:00 PM PDT 24
Peak memory 207340 kb
Host smart-05405128-3249-43dc-9ca6-9a705c74b173
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1475602760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1475602760
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.1849857484
Short name T398
Test name
Test status
Simulation time 76318465 ps
CPU time 9.09 seconds
Started Jul 27 04:17:40 PM PDT 24
Finished Jul 27 04:17:49 PM PDT 24
Peak memory 211276 kb
Host smart-f8fe0622-a22d-48c6-bca6-ae975bba70d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1849857484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.1849857484
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2308397128
Short name T165
Test name
Test status
Simulation time 36909309392 ps
CPU time 187.93 seconds
Started Jul 27 04:17:45 PM PDT 24
Finished Jul 27 04:20:53 PM PDT 24
Peak memory 211708 kb
Host smart-3eb1d043-ea48-40a6-849c-028a3269a64b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2308397128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo
w_rsp.2308397128
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.3271249589
Short name T228
Test name
Test status
Simulation time 253522049 ps
CPU time 17.59 seconds
Started Jul 27 04:17:33 PM PDT 24
Finished Jul 27 04:17:51 PM PDT 24
Peak memory 202720 kb
Host smart-4b2045f0-104b-43b9-b191-9c46c6ec83ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3271249589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3271249589
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.3457590747
Short name T346
Test name
Test status
Simulation time 270306387 ps
CPU time 6.32 seconds
Started Jul 27 04:18:49 PM PDT 24
Finished Jul 27 04:18:56 PM PDT 24
Peak memory 203288 kb
Host smart-cfe020d4-f5b6-441b-8ddc-c2c2c19a830c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3457590747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3457590747
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.783611512
Short name T82
Test name
Test status
Simulation time 1230983361 ps
CPU time 28.98 seconds
Started Jul 27 04:17:40 PM PDT 24
Finished Jul 27 04:18:09 PM PDT 24
Peak memory 204008 kb
Host smart-0c9eeb6f-189d-4c34-887c-1dd91780c982
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=783611512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.783611512
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.1070436460
Short name T761
Test name
Test status
Simulation time 75053537830 ps
CPU time 251.74 seconds
Started Jul 27 04:17:45 PM PDT 24
Finished Jul 27 04:21:57 PM PDT 24
Peak memory 205560 kb
Host smart-34198650-54f8-4bc1-9a4c-cf0768680fe7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070436460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1070436460
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.3017441263
Short name T865
Test name
Test status
Simulation time 23491490266 ps
CPU time 114.58 seconds
Started Jul 27 04:18:40 PM PDT 24
Finished Jul 27 04:20:35 PM PDT 24
Peak memory 210372 kb
Host smart-62307888-063d-4403-85fe-a30a4000eada
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3017441263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3017441263
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.1459488296
Short name T712
Test name
Test status
Simulation time 448670734 ps
CPU time 33.69 seconds
Started Jul 27 04:17:45 PM PDT 24
Finished Jul 27 04:18:19 PM PDT 24
Peak memory 211656 kb
Host smart-ac49aaec-fafd-4990-8d87-56e4eeb08e35
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459488296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.1459488296
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.1451685000
Short name T484
Test name
Test status
Simulation time 342134674 ps
CPU time 14.21 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:22:21 PM PDT 24
Peak memory 203168 kb
Host smart-be93a75e-98ab-4ed5-a44a-bfb0e7d8c240
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1451685000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1451685000
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.2025526955
Short name T580
Test name
Test status
Simulation time 179355162 ps
CPU time 3.58 seconds
Started Jul 27 04:22:20 PM PDT 24
Finished Jul 27 04:22:24 PM PDT 24
Peak memory 203288 kb
Host smart-37a37d8e-9bf0-4564-bb90-5edb0742a05e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2025526955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2025526955
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.104808436
Short name T854
Test name
Test status
Simulation time 4312833988 ps
CPU time 27.33 seconds
Started Jul 27 04:17:41 PM PDT 24
Finished Jul 27 04:18:09 PM PDT 24
Peak memory 203752 kb
Host smart-6793129f-18fb-4abf-91c2-77b632e9a485
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=104808436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.104808436
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.90952141
Short name T352
Test name
Test status
Simulation time 2617352101 ps
CPU time 20.07 seconds
Started Jul 27 04:17:31 PM PDT 24
Finished Jul 27 04:17:51 PM PDT 24
Peak memory 203644 kb
Host smart-932f7aec-6d49-45a1-9b19-6bebba43dc47
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=90952141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.90952141
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.583979375
Short name T447
Test name
Test status
Simulation time 192538706 ps
CPU time 2.83 seconds
Started Jul 27 04:17:34 PM PDT 24
Finished Jul 27 04:17:37 PM PDT 24
Peak memory 202124 kb
Host smart-7e3f8597-b9ce-405f-8baa-37e617dfae23
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583979375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.583979375
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.55303875
Short name T556
Test name
Test status
Simulation time 8361335969 ps
CPU time 144.87 seconds
Started Jul 27 04:22:08 PM PDT 24
Finished Jul 27 04:24:34 PM PDT 24
Peak memory 205652 kb
Host smart-8451328a-c9ff-4c64-869d-6e5fd5217696
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=55303875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.55303875
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.2393349335
Short name T784
Test name
Test status
Simulation time 7472847286 ps
CPU time 62.98 seconds
Started Jul 27 04:22:29 PM PDT 24
Finished Jul 27 04:23:32 PM PDT 24
Peak memory 204944 kb
Host smart-ba096f02-0679-47b4-8a7a-7a599af8d0f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2393349335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.2393349335
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.644279677
Short name T473
Test name
Test status
Simulation time 102089294 ps
CPU time 36.2 seconds
Started Jul 27 04:17:28 PM PDT 24
Finished Jul 27 04:18:05 PM PDT 24
Peak memory 205740 kb
Host smart-76ffd344-4bda-4b99-ad3f-178047e5e740
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=644279677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_
reset.644279677
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.1400886119
Short name T430
Test name
Test status
Simulation time 14589548440 ps
CPU time 459.96 seconds
Started Jul 27 04:17:34 PM PDT 24
Finished Jul 27 04:25:14 PM PDT 24
Peak memory 218992 kb
Host smart-831a2be5-b6f5-4965-afdf-0b88518f51c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1400886119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res
et_error.1400886119
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.2413037896
Short name T734
Test name
Test status
Simulation time 527552709 ps
CPU time 11.35 seconds
Started Jul 27 04:17:40 PM PDT 24
Finished Jul 27 04:17:51 PM PDT 24
Peak memory 203872 kb
Host smart-fc10b081-3304-4dfe-a98e-30b39a8273aa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2413037896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2413037896
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.1804726795
Short name T597
Test name
Test status
Simulation time 667653507 ps
CPU time 14.79 seconds
Started Jul 27 04:17:41 PM PDT 24
Finished Jul 27 04:17:56 PM PDT 24
Peak memory 211892 kb
Host smart-83389df6-f92d-415c-9fb3-9622d118eb53
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1804726795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.1804726795
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.4093946689
Short name T392
Test name
Test status
Simulation time 59226394364 ps
CPU time 517.75 seconds
Started Jul 27 04:22:18 PM PDT 24
Finished Jul 27 04:30:56 PM PDT 24
Peak memory 211432 kb
Host smart-d9d801a5-fe9b-4a98-8c74-b3b54b360e50
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4093946689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo
w_rsp.4093946689
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1951491438
Short name T205
Test name
Test status
Simulation time 2425160577 ps
CPU time 28.02 seconds
Started Jul 27 04:22:54 PM PDT 24
Finished Jul 27 04:23:22 PM PDT 24
Peak memory 203180 kb
Host smart-ea703565-a486-4468-bd2c-22e271ecc766
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1951491438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1951491438
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.1928757463
Short name T881
Test name
Test status
Simulation time 575307610 ps
CPU time 14.68 seconds
Started Jul 27 04:19:40 PM PDT 24
Finished Jul 27 04:19:55 PM PDT 24
Peak memory 203456 kb
Host smart-e0e6afd5-799a-46d8-b03f-f292f4e89031
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1928757463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1928757463
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.2028240878
Short name T258
Test name
Test status
Simulation time 154211710 ps
CPU time 15.66 seconds
Started Jul 27 04:17:45 PM PDT 24
Finished Jul 27 04:18:01 PM PDT 24
Peak memory 211616 kb
Host smart-77578a9c-6d3b-46ad-9833-e1fcb1006f94
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2028240878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.2028240878
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.2254701717
Short name T255
Test name
Test status
Simulation time 38448715820 ps
CPU time 206.41 seconds
Started Jul 27 04:17:33 PM PDT 24
Finished Jul 27 04:21:00 PM PDT 24
Peak memory 211232 kb
Host smart-e1a18fed-cceb-43a5-a75a-2ff6b53ee063
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254701717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2254701717
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2354169060
Short name T466
Test name
Test status
Simulation time 13531794159 ps
CPU time 121.77 seconds
Started Jul 27 04:17:30 PM PDT 24
Finished Jul 27 04:19:32 PM PDT 24
Peak memory 211840 kb
Host smart-d158969d-7861-4a36-a557-e1b794633ad8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2354169060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2354169060
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.3680506012
Short name T224
Test name
Test status
Simulation time 187411138 ps
CPU time 13.77 seconds
Started Jul 27 04:17:36 PM PDT 24
Finished Jul 27 04:17:50 PM PDT 24
Peak memory 203664 kb
Host smart-eb419fcc-0380-4804-ae15-6e40583abc9a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680506012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.3680506012
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.2353050679
Short name T439
Test name
Test status
Simulation time 46536033 ps
CPU time 2.58 seconds
Started Jul 27 04:17:35 PM PDT 24
Finished Jul 27 04:17:37 PM PDT 24
Peak memory 203440 kb
Host smart-41ff3e0a-d9a5-468c-a7c4-c4d56e9a9f4f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2353050679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2353050679
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.2208491109
Short name T166
Test name
Test status
Simulation time 134609069 ps
CPU time 3.35 seconds
Started Jul 27 04:22:14 PM PDT 24
Finished Jul 27 04:22:17 PM PDT 24
Peak memory 203216 kb
Host smart-ab34d1a4-04c4-4bf0-a428-362e3d5e6492
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2208491109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2208491109
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.2205034734
Short name T422
Test name
Test status
Simulation time 9014163623 ps
CPU time 36.25 seconds
Started Jul 27 04:22:42 PM PDT 24
Finished Jul 27 04:23:18 PM PDT 24
Peak memory 203368 kb
Host smart-83e6e189-5de0-45d9-8fe7-5f466f928f24
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205034734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2205034734
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1660202320
Short name T781
Test name
Test status
Simulation time 25493743879 ps
CPU time 55.92 seconds
Started Jul 27 04:17:34 PM PDT 24
Finished Jul 27 04:18:30 PM PDT 24
Peak memory 202352 kb
Host smart-9d223c85-9216-46ef-9761-7546f305afad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1660202320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1660202320
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.3683396688
Short name T877
Test name
Test status
Simulation time 38701817 ps
CPU time 2.42 seconds
Started Jul 27 04:17:48 PM PDT 24
Finished Jul 27 04:17:50 PM PDT 24
Peak memory 203336 kb
Host smart-3bbe5118-27cd-4244-8bdc-03c3b6779825
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683396688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3683396688
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.1439546129
Short name T767
Test name
Test status
Simulation time 1551859617 ps
CPU time 10.05 seconds
Started Jul 27 04:19:31 PM PDT 24
Finished Jul 27 04:19:41 PM PDT 24
Peak memory 205004 kb
Host smart-8ab8e4bf-5e7f-4bab-99e9-1e30e65bc794
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1439546129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1439546129
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.1601131369
Short name T482
Test name
Test status
Simulation time 6162027062 ps
CPU time 233.13 seconds
Started Jul 27 04:19:56 PM PDT 24
Finished Jul 27 04:23:49 PM PDT 24
Peak memory 206932 kb
Host smart-07fbca7e-7b24-4121-bea3-1c8c34fb188c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1601131369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1601131369
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.1015515603
Short name T586
Test name
Test status
Simulation time 4051504995 ps
CPU time 152.34 seconds
Started Jul 27 04:19:46 PM PDT 24
Finished Jul 27 04:22:18 PM PDT 24
Peak memory 209024 kb
Host smart-afb09d59-47ee-4391-9487-2ea481307f72
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1015515603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand
_reset.1015515603
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.260033296
Short name T687
Test name
Test status
Simulation time 185205777 ps
CPU time 7.78 seconds
Started Jul 27 04:21:30 PM PDT 24
Finished Jul 27 04:21:38 PM PDT 24
Peak memory 204760 kb
Host smart-fa01af02-fb29-4324-a83d-7d211e7f7293
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=260033296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.260033296
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.410993608
Short name T488
Test name
Test status
Simulation time 1306389621 ps
CPU time 47.17 seconds
Started Jul 27 04:19:29 PM PDT 24
Finished Jul 27 04:20:16 PM PDT 24
Peak memory 211396 kb
Host smart-ba3572e8-a9bd-4c92-8559-dbc63922a21d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=410993608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.410993608
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2611419609
Short name T141
Test name
Test status
Simulation time 162438399982 ps
CPU time 454.88 seconds
Started Jul 27 04:18:42 PM PDT 24
Finished Jul 27 04:26:17 PM PDT 24
Peak memory 211544 kb
Host smart-1f6ba245-1f9d-4caa-935c-d3e3277c53d5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2611419609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl
ow_rsp.2611419609
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3969015339
Short name T174
Test name
Test status
Simulation time 222426183 ps
CPU time 17.34 seconds
Started Jul 27 04:18:48 PM PDT 24
Finished Jul 27 04:19:05 PM PDT 24
Peak memory 203348 kb
Host smart-efc1e7aa-a00c-4fb0-9bbe-b1cf7d6a54fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3969015339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3969015339
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.2011715276
Short name T12
Test name
Test status
Simulation time 351493042 ps
CPU time 7.57 seconds
Started Jul 27 04:22:21 PM PDT 24
Finished Jul 27 04:22:29 PM PDT 24
Peak memory 203252 kb
Host smart-a0db387e-048f-4304-9770-6edfda0c3bdd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2011715276 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2011715276
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.4062290728
Short name T578
Test name
Test status
Simulation time 5757213348 ps
CPU time 39.29 seconds
Started Jul 27 04:23:08 PM PDT 24
Finished Jul 27 04:23:47 PM PDT 24
Peak memory 211232 kb
Host smart-69f3ffd3-d545-4e53-b884-8bf5ebe2034d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4062290728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.4062290728
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.3398588127
Short name T351
Test name
Test status
Simulation time 43594458237 ps
CPU time 200.31 seconds
Started Jul 27 04:18:40 PM PDT 24
Finished Jul 27 04:22:00 PM PDT 24
Peak memory 204940 kb
Host smart-0cde879f-fc7b-4491-abf6-5c8a726803c6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398588127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3398588127
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3269757809
Short name T766
Test name
Test status
Simulation time 45641944120 ps
CPU time 94.14 seconds
Started Jul 27 04:22:38 PM PDT 24
Finished Jul 27 04:24:12 PM PDT 24
Peak memory 204332 kb
Host smart-8d0b996e-746a-4edf-be0e-deadc8d68672
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3269757809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3269757809
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.1209753952
Short name T662
Test name
Test status
Simulation time 128957283 ps
CPU time 8.23 seconds
Started Jul 27 04:18:40 PM PDT 24
Finished Jul 27 04:18:48 PM PDT 24
Peak memory 211476 kb
Host smart-517de4ed-49a6-4c38-bb08-21b8c0029ca5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209753952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.1209753952
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.991581365
Short name T8
Test name
Test status
Simulation time 248125620 ps
CPU time 17.36 seconds
Started Jul 27 04:18:39 PM PDT 24
Finished Jul 27 04:18:56 PM PDT 24
Peak memory 204104 kb
Host smart-59ce0768-52f2-4761-9948-9bf749684afb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=991581365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.991581365
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.2987121420
Short name T116
Test name
Test status
Simulation time 227825774 ps
CPU time 3.38 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:22:09 PM PDT 24
Peak memory 202376 kb
Host smart-a08c8877-8219-465e-b0a1-6bf09edbc5f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2987121420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2987121420
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1259527285
Short name T842
Test name
Test status
Simulation time 11176981305 ps
CPU time 28.9 seconds
Started Jul 27 04:22:11 PM PDT 24
Finished Jul 27 04:22:40 PM PDT 24
Peak memory 203136 kb
Host smart-8d68c737-97a0-4cb4-aac5-8346c11117af
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259527285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1259527285
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.2546542054
Short name T387
Test name
Test status
Simulation time 5973629702 ps
CPU time 34.68 seconds
Started Jul 27 04:18:41 PM PDT 24
Finished Jul 27 04:19:16 PM PDT 24
Peak memory 203344 kb
Host smart-666977d6-9a29-4849-9756-5644d2801e83
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2546542054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.2546542054
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1442274336
Short name T874
Test name
Test status
Simulation time 68034135 ps
CPU time 2.1 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:22:08 PM PDT 24
Peak memory 202808 kb
Host smart-aa6b7579-214b-406a-a70e-d36ff6a01c49
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442274336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.1442274336
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.139103512
Short name T460
Test name
Test status
Simulation time 1450539158 ps
CPU time 179.22 seconds
Started Jul 27 04:22:01 PM PDT 24
Finished Jul 27 04:25:01 PM PDT 24
Peak memory 206288 kb
Host smart-fc83972b-3ae9-4a65-9d5f-7079f50803de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=139103512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.139103512
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.406342360
Short name T763
Test name
Test status
Simulation time 6455896010 ps
CPU time 142.95 seconds
Started Jul 27 04:22:09 PM PDT 24
Finished Jul 27 04:24:32 PM PDT 24
Peak memory 208696 kb
Host smart-d4b977ef-29be-4d51-83d9-06d56d0748ca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=406342360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.406342360
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.553846377
Short name T795
Test name
Test status
Simulation time 410176070 ps
CPU time 207.88 seconds
Started Jul 27 04:18:46 PM PDT 24
Finished Jul 27 04:22:14 PM PDT 24
Peak memory 209132 kb
Host smart-d4e569e2-0327-49e6-9122-3f79cc49a392
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=553846377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand
_reset.553846377
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.522578907
Short name T355
Test name
Test status
Simulation time 1419122296 ps
CPU time 207.53 seconds
Started Jul 27 04:23:12 PM PDT 24
Finished Jul 27 04:26:39 PM PDT 24
Peak memory 211384 kb
Host smart-bd7affe8-2d59-4606-9b85-30716ed9d124
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=522578907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_res
et_error.522578907
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.2004829071
Short name T673
Test name
Test status
Simulation time 31951120 ps
CPU time 4.9 seconds
Started Jul 27 04:22:05 PM PDT 24
Finished Jul 27 04:22:11 PM PDT 24
Peak memory 203700 kb
Host smart-46885dd1-4265-4b25-b962-17e87d565266
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2004829071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2004829071
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3875631142
Short name T432
Test name
Test status
Simulation time 79841151 ps
CPU time 4.69 seconds
Started Jul 27 04:22:27 PM PDT 24
Finished Jul 27 04:22:32 PM PDT 24
Peak memory 203044 kb
Host smart-e328309a-d26b-4b65-9775-c6d239db7190
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3875631142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3875631142
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.3342173485
Short name T391
Test name
Test status
Simulation time 420756006783 ps
CPU time 685.18 seconds
Started Jul 27 04:22:25 PM PDT 24
Finished Jul 27 04:33:51 PM PDT 24
Peak memory 205812 kb
Host smart-d0c3c03e-9679-4ce4-9449-b6797da99c15
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3342173485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl
ow_rsp.3342173485
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.1793561119
Short name T741
Test name
Test status
Simulation time 615673082 ps
CPU time 20.46 seconds
Started Jul 27 04:19:03 PM PDT 24
Finished Jul 27 04:19:24 PM PDT 24
Peak memory 203952 kb
Host smart-03f81d68-799a-4bb2-8c74-4b4cb6191c66
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1793561119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.1793561119
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.3839703209
Short name T799
Test name
Test status
Simulation time 224436756 ps
CPU time 2.89 seconds
Started Jul 27 04:19:00 PM PDT 24
Finished Jul 27 04:19:03 PM PDT 24
Peak memory 203308 kb
Host smart-5a097cf2-811a-464c-a124-5423e978f3d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3839703209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3839703209
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.1118030825
Short name T287
Test name
Test status
Simulation time 194255263 ps
CPU time 24.46 seconds
Started Jul 27 04:22:27 PM PDT 24
Finished Jul 27 04:22:52 PM PDT 24
Peak memory 211240 kb
Host smart-56f546d0-23a4-49ae-96a4-253bd537853b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1118030825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1118030825
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.4158376407
Short name T796
Test name
Test status
Simulation time 31337252235 ps
CPU time 189.26 seconds
Started Jul 27 04:22:27 PM PDT 24
Finished Jul 27 04:25:37 PM PDT 24
Peak memory 211276 kb
Host smart-bab9e3fb-8600-46fe-9898-71c061f79538
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158376407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.4158376407
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.4082789024
Short name T330
Test name
Test status
Simulation time 13877960268 ps
CPU time 73.34 seconds
Started Jul 27 04:18:53 PM PDT 24
Finished Jul 27 04:20:07 PM PDT 24
Peak memory 211680 kb
Host smart-cbeceb16-8345-498f-acb7-f64165e7675a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4082789024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.4082789024
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.3813382724
Short name T702
Test name
Test status
Simulation time 288093174 ps
CPU time 10.42 seconds
Started Jul 27 04:19:55 PM PDT 24
Finished Jul 27 04:20:06 PM PDT 24
Peak memory 204476 kb
Host smart-aeb642ac-1006-48f9-b0e1-af3b0ce4aea3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813382724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.3813382724
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.2093405087
Short name T587
Test name
Test status
Simulation time 2170460326 ps
CPU time 30.54 seconds
Started Jul 27 04:22:27 PM PDT 24
Finished Jul 27 04:22:58 PM PDT 24
Peak memory 203124 kb
Host smart-683cccbb-3e72-4c58-801c-6b199e0418d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2093405087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2093405087
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.899463524
Short name T657
Test name
Test status
Simulation time 25610735 ps
CPU time 1.73 seconds
Started Jul 27 04:22:08 PM PDT 24
Finished Jul 27 04:22:10 PM PDT 24
Peak memory 203024 kb
Host smart-94fe3561-5aaa-4444-9dc1-066ce5bd8b6f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=899463524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.899463524
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.4094815688
Short name T840
Test name
Test status
Simulation time 22826703830 ps
CPU time 38.85 seconds
Started Jul 27 04:18:49 PM PDT 24
Finished Jul 27 04:19:28 PM PDT 24
Peak memory 203388 kb
Host smart-bc23b35a-957c-4d05-b6ac-c341bc72c335
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094815688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.4094815688
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.2865960942
Short name T62
Test name
Test status
Simulation time 3641088484 ps
CPU time 27.84 seconds
Started Jul 27 04:22:17 PM PDT 24
Finished Jul 27 04:22:46 PM PDT 24
Peak memory 202556 kb
Host smart-d44b4d53-20a6-43b1-b98d-ce3a9356ba1a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2865960942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.2865960942
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.4160462952
Short name T276
Test name
Test status
Simulation time 28272684 ps
CPU time 2.26 seconds
Started Jul 27 04:22:07 PM PDT 24
Finished Jul 27 04:22:10 PM PDT 24
Peak memory 202496 kb
Host smart-8a7e4c28-3a64-40a7-bff5-7db51070c37a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160462952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.4160462952
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.2523611727
Short name T570
Test name
Test status
Simulation time 1302771463 ps
CPU time 90.45 seconds
Started Jul 27 04:18:59 PM PDT 24
Finished Jul 27 04:20:30 PM PDT 24
Peak memory 208476 kb
Host smart-e011f6d5-76d8-4ed8-89bd-a6c48764c17a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2523611727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2523611727
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.839987745
Short name T677
Test name
Test status
Simulation time 1305770883 ps
CPU time 82.31 seconds
Started Jul 27 04:22:35 PM PDT 24
Finished Jul 27 04:23:57 PM PDT 24
Peak memory 207448 kb
Host smart-dce6b6b3-3e23-4619-aa53-9d9b7d7b8f97
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=839987745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.839987745
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3991315504
Short name T172
Test name
Test status
Simulation time 462356506 ps
CPU time 154.39 seconds
Started Jul 27 04:22:21 PM PDT 24
Finished Jul 27 04:24:56 PM PDT 24
Peak memory 207956 kb
Host smart-57b18bff-82dd-48f8-85e7-c2cd6779ae19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3991315504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran
d_reset.3991315504
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.1035585420
Short name T84
Test name
Test status
Simulation time 801990772 ps
CPU time 24.19 seconds
Started Jul 27 04:22:31 PM PDT 24
Finished Jul 27 04:22:55 PM PDT 24
Peak memory 211076 kb
Host smart-51f11c2e-84f7-45b9-997c-0ea0f14cf6e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1035585420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1035585420
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.1172741250
Short name T216
Test name
Test status
Simulation time 465518676 ps
CPU time 31.18 seconds
Started Jul 27 04:23:15 PM PDT 24
Finished Jul 27 04:23:46 PM PDT 24
Peak memory 205192 kb
Host smart-87592106-dab4-4362-ae7b-d712e4ccb688
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1172741250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1172741250
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2714430720
Short name T220
Test name
Test status
Simulation time 334779364509 ps
CPU time 709.12 seconds
Started Jul 27 04:19:16 PM PDT 24
Finished Jul 27 04:31:05 PM PDT 24
Peak memory 207836 kb
Host smart-fd6879ab-3f3c-4b4f-a3be-c505498efcdc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2714430720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl
ow_rsp.2714430720
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.3998623825
Short name T322
Test name
Test status
Simulation time 118647948 ps
CPU time 8.12 seconds
Started Jul 27 04:22:34 PM PDT 24
Finished Jul 27 04:22:42 PM PDT 24
Peak memory 203556 kb
Host smart-06eabeb5-b017-4bd7-9170-17f473e32bc4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3998623825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.3998623825
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.1551704321
Short name T333
Test name
Test status
Simulation time 831211795 ps
CPU time 27.52 seconds
Started Jul 27 04:19:19 PM PDT 24
Finished Jul 27 04:19:46 PM PDT 24
Peak memory 203456 kb
Host smart-76e48547-eeb4-49f3-9a25-93dc5e44084d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1551704321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1551704321
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.4019615343
Short name T833
Test name
Test status
Simulation time 148405970 ps
CPU time 13.4 seconds
Started Jul 27 04:22:51 PM PDT 24
Finished Jul 27 04:23:04 PM PDT 24
Peak memory 211188 kb
Host smart-655d4253-5156-4e81-b36d-b09b2ffa1d6a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4019615343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.4019615343
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.2853720532
Short name T388
Test name
Test status
Simulation time 11182226876 ps
CPU time 29.19 seconds
Started Jul 27 04:22:07 PM PDT 24
Finished Jul 27 04:22:36 PM PDT 24
Peak memory 203904 kb
Host smart-6728e56d-dee9-4912-9052-831cae348f33
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853720532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2853720532
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3829561340
Short name T561
Test name
Test status
Simulation time 65537722126 ps
CPU time 278.28 seconds
Started Jul 27 04:19:18 PM PDT 24
Finished Jul 27 04:23:56 PM PDT 24
Peak memory 211680 kb
Host smart-a3f488ad-10dd-401f-8b4b-b4bc6357340d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3829561340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3829561340
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.4246093829
Short name T878
Test name
Test status
Simulation time 200190472 ps
CPU time 12.11 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:22:18 PM PDT 24
Peak memory 211060 kb
Host smart-cbe5e13c-ade8-45eb-85e2-adc11f68d07b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246093829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.4246093829
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.131016622
Short name T185
Test name
Test status
Simulation time 1204836347 ps
CPU time 23.04 seconds
Started Jul 27 04:19:16 PM PDT 24
Finished Jul 27 04:19:39 PM PDT 24
Peak memory 203920 kb
Host smart-24a7400c-8455-44c7-b4d0-6a7e0cf36bf7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=131016622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.131016622
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.439999428
Short name T721
Test name
Test status
Simulation time 133923440 ps
CPU time 2.07 seconds
Started Jul 27 04:19:04 PM PDT 24
Finished Jul 27 04:19:06 PM PDT 24
Peak memory 203296 kb
Host smart-6d1e728e-93f6-4439-adb8-8054216651a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=439999428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.439999428
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.780803877
Short name T592
Test name
Test status
Simulation time 7520220841 ps
CPU time 32.99 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:22:39 PM PDT 24
Peak memory 202968 kb
Host smart-57572688-0998-4371-887b-e98eca51e0b3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=780803877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.780803877
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1175571520
Short name T226
Test name
Test status
Simulation time 3239755637 ps
CPU time 28.46 seconds
Started Jul 27 04:22:41 PM PDT 24
Finished Jul 27 04:23:10 PM PDT 24
Peak memory 203348 kb
Host smart-35ea8f74-f9ff-4a9e-b858-7452c0842e25
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1175571520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1175571520
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.493104803
Short name T719
Test name
Test status
Simulation time 38430173 ps
CPU time 2.3 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:22:09 PM PDT 24
Peak memory 202880 kb
Host smart-50e60deb-5c17-4933-9bd2-d73fd295cc40
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493104803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.493104803
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.2204891653
Short name T875
Test name
Test status
Simulation time 7650712931 ps
CPU time 189.31 seconds
Started Jul 27 04:19:26 PM PDT 24
Finished Jul 27 04:22:35 PM PDT 24
Peak memory 209248 kb
Host smart-f6234b44-dc7a-4b44-98ab-7d7e5a532da9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2204891653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2204891653
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2537581366
Short name T896
Test name
Test status
Simulation time 5220353148 ps
CPU time 116.38 seconds
Started Jul 27 04:22:38 PM PDT 24
Finished Jul 27 04:24:35 PM PDT 24
Peak memory 208176 kb
Host smart-22081009-dd89-4fcb-8e6d-4c516beeedb5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2537581366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2537581366
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.2732184220
Short name T630
Test name
Test status
Simulation time 4565418395 ps
CPU time 323.2 seconds
Started Jul 27 04:22:33 PM PDT 24
Finished Jul 27 04:27:57 PM PDT 24
Peak memory 219748 kb
Host smart-2e402f2c-9115-472b-962d-240f5933ae66
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2732184220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re
set_error.2732184220
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.2227119275
Short name T250
Test name
Test status
Simulation time 63688170 ps
CPU time 9.95 seconds
Started Jul 27 04:19:17 PM PDT 24
Finished Jul 27 04:19:27 PM PDT 24
Peak memory 204848 kb
Host smart-86276c48-b9d2-4b9e-ac1e-2fb192576949
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2227119275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2227119275
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.3814996614
Short name T461
Test name
Test status
Simulation time 1343062477 ps
CPU time 35.99 seconds
Started Jul 27 04:22:07 PM PDT 24
Finished Jul 27 04:22:43 PM PDT 24
Peak memory 210980 kb
Host smart-b2b9249c-7d19-4b88-9e11-765645df070c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3814996614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.3814996614
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.2599089323
Short name T545
Test name
Test status
Simulation time 137416206179 ps
CPU time 508.94 seconds
Started Jul 27 04:23:05 PM PDT 24
Finished Jul 27 04:31:35 PM PDT 24
Peak memory 206196 kb
Host smart-bdb3bb2c-fd44-4279-8146-d983b78053a7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2599089323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl
ow_rsp.2599089323
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.1061335143
Short name T526
Test name
Test status
Simulation time 21774006 ps
CPU time 2.79 seconds
Started Jul 27 04:22:21 PM PDT 24
Finished Jul 27 04:22:24 PM PDT 24
Peak memory 203196 kb
Host smart-0bcde9c7-263f-4a61-ba74-8f1eaf382902
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1061335143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.1061335143
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.1077536543
Short name T867
Test name
Test status
Simulation time 1305744532 ps
CPU time 32.78 seconds
Started Jul 27 04:22:22 PM PDT 24
Finished Jul 27 04:22:55 PM PDT 24
Peak memory 203052 kb
Host smart-9c0b48e1-2221-40cc-9ff7-14e838b8a3e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1077536543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1077536543
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.3229087291
Short name T513
Test name
Test status
Simulation time 1853315321 ps
CPU time 23.5 seconds
Started Jul 27 04:22:28 PM PDT 24
Finished Jul 27 04:22:52 PM PDT 24
Peak memory 210636 kb
Host smart-5f04e1aa-5634-406c-bb1a-1668078a305a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3229087291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.3229087291
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.3706026656
Short name T60
Test name
Test status
Simulation time 19748401083 ps
CPU time 83.51 seconds
Started Jul 27 04:22:38 PM PDT 24
Finished Jul 27 04:24:02 PM PDT 24
Peak memory 211516 kb
Host smart-4df3bf31-ca1d-4834-bad2-18f3ca576594
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706026656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3706026656
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.559592292
Short name T389
Test name
Test status
Simulation time 28936319435 ps
CPU time 191.09 seconds
Started Jul 27 04:19:42 PM PDT 24
Finished Jul 27 04:22:53 PM PDT 24
Peak memory 204544 kb
Host smart-0dc8846d-421f-4efb-a75d-6f7a8a59f3d0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=559592292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.559592292
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.618593556
Short name T208
Test name
Test status
Simulation time 91903165 ps
CPU time 10.76 seconds
Started Jul 27 04:19:28 PM PDT 24
Finished Jul 27 04:19:39 PM PDT 24
Peak memory 211324 kb
Host smart-bcb45adb-531c-428c-8b16-9a29d05d374c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618593556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.618593556
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.177140601
Short name T773
Test name
Test status
Simulation time 187893653 ps
CPU time 3.48 seconds
Started Jul 27 04:22:07 PM PDT 24
Finished Jul 27 04:22:11 PM PDT 24
Peak memory 202848 kb
Host smart-e389c071-c659-4a17-a52f-ce1c10364b6d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=177140601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.177140601
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.428074060
Short name T365
Test name
Test status
Simulation time 180004327 ps
CPU time 3.56 seconds
Started Jul 27 04:19:24 PM PDT 24
Finished Jul 27 04:19:27 PM PDT 24
Peak memory 203300 kb
Host smart-405a3f27-f46c-4ba2-b050-1399bb797685
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=428074060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.428074060
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.3200639709
Short name T693
Test name
Test status
Simulation time 6508530854 ps
CPU time 30.77 seconds
Started Jul 27 04:22:22 PM PDT 24
Finished Jul 27 04:22:53 PM PDT 24
Peak memory 203128 kb
Host smart-d139f14c-b394-4372-b5cb-a54a68ad7cc3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200639709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3200639709
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.3115204406
Short name T828
Test name
Test status
Simulation time 19514387123 ps
CPU time 39.81 seconds
Started Jul 27 04:22:21 PM PDT 24
Finished Jul 27 04:23:01 PM PDT 24
Peak memory 203120 kb
Host smart-383f97b2-143d-4aaf-9908-48df0eced514
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3115204406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3115204406
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.205960508
Short name T618
Test name
Test status
Simulation time 38400127 ps
CPU time 2.37 seconds
Started Jul 27 04:20:23 PM PDT 24
Finished Jul 27 04:20:26 PM PDT 24
Peak memory 203284 kb
Host smart-204c2b1e-a1c0-44eb-9ed3-388fb40dfb1a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205960508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.205960508
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.699157658
Short name T703
Test name
Test status
Simulation time 118173877 ps
CPU time 17.06 seconds
Started Jul 27 04:22:34 PM PDT 24
Finished Jul 27 04:22:51 PM PDT 24
Peak memory 211400 kb
Host smart-28b84034-0b78-46c2-8dcb-17f2085fa6e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=699157658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.699157658
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.1228311482
Short name T589
Test name
Test status
Simulation time 631779154 ps
CPU time 6.51 seconds
Started Jul 27 04:19:35 PM PDT 24
Finished Jul 27 04:19:42 PM PDT 24
Peak memory 203296 kb
Host smart-2044f22c-b678-4cda-8c35-a30942514029
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1228311482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1228311482
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.2326565554
Short name T179
Test name
Test status
Simulation time 8181348403 ps
CPU time 501.49 seconds
Started Jul 27 04:19:36 PM PDT 24
Finished Jul 27 04:27:58 PM PDT 24
Peak memory 208860 kb
Host smart-d37968b4-7384-47b7-9ed2-122aae1a350d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2326565554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran
d_reset.2326565554
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.2943791956
Short name T264
Test name
Test status
Simulation time 2376938937 ps
CPU time 304.49 seconds
Started Jul 27 04:22:20 PM PDT 24
Finished Jul 27 04:27:25 PM PDT 24
Peak memory 211416 kb
Host smart-d4eac827-876d-46f4-b617-d389ea67476b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2943791956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re
set_error.2943791956
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.3906364198
Short name T215
Test name
Test status
Simulation time 408409148 ps
CPU time 37.58 seconds
Started Jul 27 04:23:18 PM PDT 24
Finished Jul 27 04:23:55 PM PDT 24
Peak memory 211444 kb
Host smart-451f2646-a376-4894-9b58-d6906ff4eabe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3906364198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.3906364198
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1182307694
Short name T61
Test name
Test status
Simulation time 90326161358 ps
CPU time 704.16 seconds
Started Jul 27 04:22:09 PM PDT 24
Finished Jul 27 04:33:53 PM PDT 24
Peak memory 211292 kb
Host smart-57176c57-e05a-4ba8-989a-aa1143f758c9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1182307694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl
ow_rsp.1182307694
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3981157451
Short name T274
Test name
Test status
Simulation time 80456197 ps
CPU time 7.46 seconds
Started Jul 27 04:22:10 PM PDT 24
Finished Jul 27 04:22:18 PM PDT 24
Peak memory 203436 kb
Host smart-fb9fdccd-c363-40de-8aaf-2af343524c6e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3981157451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.3981157451
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.2490688030
Short name T529
Test name
Test status
Simulation time 377866985 ps
CPU time 22.87 seconds
Started Jul 27 04:20:03 PM PDT 24
Finished Jul 27 04:20:26 PM PDT 24
Peak memory 203280 kb
Host smart-95933929-94ce-40e8-a36d-e97dc93478ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2490688030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2490688030
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.3576498342
Short name T237
Test name
Test status
Simulation time 1607823849 ps
CPU time 35.77 seconds
Started Jul 27 04:21:29 PM PDT 24
Finished Jul 27 04:22:05 PM PDT 24
Peak memory 204496 kb
Host smart-1ba7fb09-ee01-4934-9a04-757861c1b980
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3576498342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.3576498342
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.441888332
Short name T437
Test name
Test status
Simulation time 245985757830 ps
CPU time 305.74 seconds
Started Jul 27 04:22:20 PM PDT 24
Finished Jul 27 04:27:26 PM PDT 24
Peak memory 211440 kb
Host smart-5e41d1e9-0fe9-4445-ae1f-a8ed2f69c144
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=441888332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.441888332
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.1696775929
Short name T97
Test name
Test status
Simulation time 47897052644 ps
CPU time 185.17 seconds
Started Jul 27 04:22:38 PM PDT 24
Finished Jul 27 04:25:44 PM PDT 24
Peak memory 211192 kb
Host smart-7f2ac94d-4a4e-4c01-94ed-9d1d312b6f2b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1696775929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1696775929
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.1953499661
Short name T711
Test name
Test status
Simulation time 31391885 ps
CPU time 3.05 seconds
Started Jul 27 04:22:21 PM PDT 24
Finished Jul 27 04:22:24 PM PDT 24
Peak memory 203180 kb
Host smart-013fc3ee-793c-49e7-8667-cf90ccaa2aab
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953499661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.1953499661
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.1921394261
Short name T464
Test name
Test status
Simulation time 413925698 ps
CPU time 12.12 seconds
Started Jul 27 04:19:53 PM PDT 24
Finished Jul 27 04:20:06 PM PDT 24
Peak memory 204176 kb
Host smart-1c2be7d2-3202-495f-9920-2a8250efb9eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1921394261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1921394261
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke.199249963
Short name T102
Test name
Test status
Simulation time 409521279 ps
CPU time 3.42 seconds
Started Jul 27 04:22:21 PM PDT 24
Finished Jul 27 04:22:25 PM PDT 24
Peak memory 202100 kb
Host smart-9784b64e-0215-4130-9950-ee9377b06555
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=199249963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.199249963
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3328151244
Short name T281
Test name
Test status
Simulation time 9372411655 ps
CPU time 31.99 seconds
Started Jul 27 04:22:54 PM PDT 24
Finished Jul 27 04:23:26 PM PDT 24
Peak memory 203344 kb
Host smart-574304b7-edb1-4724-81f8-1dda4d08d08d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328151244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3328151244
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.948465508
Short name T690
Test name
Test status
Simulation time 4062590924 ps
CPU time 22.33 seconds
Started Jul 27 04:22:07 PM PDT 24
Finished Jul 27 04:22:29 PM PDT 24
Peak memory 201412 kb
Host smart-d505a1d8-d0b5-4302-a7a5-f5ab66ceb806
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=948465508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.948465508
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.4144480917
Short name T153
Test name
Test status
Simulation time 43500151 ps
CPU time 2.29 seconds
Started Jul 27 04:22:07 PM PDT 24
Finished Jul 27 04:22:09 PM PDT 24
Peak memory 201284 kb
Host smart-23a64d30-4804-4831-8c2a-1d963a6ee645
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144480917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.4144480917
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.3182479696
Short name T230
Test name
Test status
Simulation time 505725985 ps
CPU time 34.72 seconds
Started Jul 27 04:22:09 PM PDT 24
Finished Jul 27 04:22:44 PM PDT 24
Peak memory 205672 kb
Host smart-d4280ff6-6358-42a9-b886-bc075ceb74df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3182479696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3182479696
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.577544429
Short name T664
Test name
Test status
Simulation time 5150901946 ps
CPU time 217.99 seconds
Started Jul 27 04:19:51 PM PDT 24
Finished Jul 27 04:23:29 PM PDT 24
Peak memory 209836 kb
Host smart-462bc7ea-44d0-44ec-9231-04f0eeac8c43
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=577544429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.577544429
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.1702753817
Short name T368
Test name
Test status
Simulation time 361992600 ps
CPU time 210.05 seconds
Started Jul 27 04:20:32 PM PDT 24
Finished Jul 27 04:24:02 PM PDT 24
Peak memory 208820 kb
Host smart-c59b4432-059d-4c98-9805-2816c93def13
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1702753817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran
d_reset.1702753817
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.678721533
Short name T364
Test name
Test status
Simulation time 76189506 ps
CPU time 24.85 seconds
Started Jul 27 04:22:16 PM PDT 24
Finished Jul 27 04:22:41 PM PDT 24
Peak memory 205484 kb
Host smart-4f4f49e1-ce9f-4d06-bc31-ed843f218db9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=678721533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_res
et_error.678721533
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.1794434036
Short name T81
Test name
Test status
Simulation time 647876314 ps
CPU time 12.48 seconds
Started Jul 27 04:22:02 PM PDT 24
Finished Jul 27 04:22:14 PM PDT 24
Peak memory 211092 kb
Host smart-d48dd4b3-2761-4a16-878b-de06d2984b9e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1794434036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1794434036
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.2962090150
Short name T827
Test name
Test status
Simulation time 37245266 ps
CPU time 4.48 seconds
Started Jul 27 04:23:13 PM PDT 24
Finished Jul 27 04:23:18 PM PDT 24
Peak memory 203468 kb
Host smart-6ebe5e0f-49b6-4cb5-9de1-44972e83061b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2962090150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2962090150
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1720260684
Short name T710
Test name
Test status
Simulation time 62794730062 ps
CPU time 565.35 seconds
Started Jul 27 04:20:14 PM PDT 24
Finished Jul 27 04:29:40 PM PDT 24
Peak memory 211516 kb
Host smart-791e67a0-f053-4514-b73b-4a15e24eadb0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1720260684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl
ow_rsp.1720260684
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2215658240
Short name T263
Test name
Test status
Simulation time 720351574 ps
CPU time 26.32 seconds
Started Jul 27 04:20:48 PM PDT 24
Finished Jul 27 04:21:14 PM PDT 24
Peak memory 203356 kb
Host smart-e4a79bdc-08ac-4cee-9751-eb8771c0b04b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2215658240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2215658240
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.95812686
Short name T343
Test name
Test status
Simulation time 78291802 ps
CPU time 8.72 seconds
Started Jul 27 04:22:05 PM PDT 24
Finished Jul 27 04:22:14 PM PDT 24
Peak memory 201472 kb
Host smart-dfe8605a-e0d7-4f48-bc57-f59b5698e49f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=95812686 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.95812686
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.3992820787
Short name T234
Test name
Test status
Simulation time 843653895 ps
CPU time 31.43 seconds
Started Jul 27 04:22:09 PM PDT 24
Finished Jul 27 04:22:41 PM PDT 24
Peak memory 211244 kb
Host smart-bdd004e7-98cb-4407-8b70-a2d6df5a9066
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3992820787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.3992820787
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.1842946757
Short name T50
Test name
Test status
Simulation time 46826053276 ps
CPU time 175.27 seconds
Started Jul 27 04:20:03 PM PDT 24
Finished Jul 27 04:22:58 PM PDT 24
Peak memory 211588 kb
Host smart-51992d14-f197-479b-b50a-47abc064d49b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842946757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1842946757
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1622273461
Short name T299
Test name
Test status
Simulation time 73307586500 ps
CPU time 154.13 seconds
Started Jul 27 04:22:07 PM PDT 24
Finished Jul 27 04:24:41 PM PDT 24
Peak memory 209596 kb
Host smart-e2469121-d3a7-4c42-9435-7b67549b6fc3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1622273461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1622273461
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.1833467970
Short name T489
Test name
Test status
Simulation time 242551682 ps
CPU time 18.42 seconds
Started Jul 27 04:22:05 PM PDT 24
Finished Jul 27 04:22:23 PM PDT 24
Peak memory 209180 kb
Host smart-99c63ed5-74a8-4d6e-b3a6-5ae4f4a30f30
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833467970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.1833467970
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.1924008765
Short name T129
Test name
Test status
Simulation time 3316983660 ps
CPU time 24.69 seconds
Started Jul 27 04:23:12 PM PDT 24
Finished Jul 27 04:23:37 PM PDT 24
Peak memory 203932 kb
Host smart-9186c419-0b01-47ca-8e0b-b1266e01b81e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1924008765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1924008765
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.817569595
Short name T750
Test name
Test status
Simulation time 27728383 ps
CPU time 1.98 seconds
Started Jul 27 04:22:08 PM PDT 24
Finished Jul 27 04:22:10 PM PDT 24
Peak memory 203036 kb
Host smart-a4e16b98-7565-4314-9802-014f552e6e24
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=817569595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.817569595
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1949011189
Short name T531
Test name
Test status
Simulation time 5226233030 ps
CPU time 32.48 seconds
Started Jul 27 04:22:09 PM PDT 24
Finished Jul 27 04:22:41 PM PDT 24
Peak memory 203120 kb
Host smart-96cef826-ce14-46ca-9111-955fdcd9c4c0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949011189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1949011189
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.3058810037
Short name T312
Test name
Test status
Simulation time 3462717894 ps
CPU time 18.78 seconds
Started Jul 27 04:22:16 PM PDT 24
Finished Jul 27 04:22:34 PM PDT 24
Peak memory 203364 kb
Host smart-8a33dbd7-9886-429d-b8d7-927639b15d19
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3058810037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3058810037
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3498662378
Short name T694
Test name
Test status
Simulation time 72013424 ps
CPU time 2.25 seconds
Started Jul 27 04:22:09 PM PDT 24
Finished Jul 27 04:22:11 PM PDT 24
Peak memory 203068 kb
Host smart-cb41812d-5d79-4b90-a59f-638f0a7d1fc4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498662378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.3498662378
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.146683336
Short name T438
Test name
Test status
Simulation time 6446731446 ps
CPU time 153.15 seconds
Started Jul 27 04:23:30 PM PDT 24
Finished Jul 27 04:26:03 PM PDT 24
Peak memory 208772 kb
Host smart-489ba8ba-c1c0-4f7e-8c71-2ba13884556c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=146683336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.146683336
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.2108374922
Short name T350
Test name
Test status
Simulation time 202721612 ps
CPU time 12.66 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:22:19 PM PDT 24
Peak memory 203520 kb
Host smart-8a83e36a-dc30-4178-971e-8075a87526b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2108374922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2108374922
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.1926168553
Short name T211
Test name
Test status
Simulation time 3001653721 ps
CPU time 444.89 seconds
Started Jul 27 04:20:04 PM PDT 24
Finished Jul 27 04:27:29 PM PDT 24
Peak memory 208212 kb
Host smart-0432d477-7dea-4993-84ff-7d3bba2c4d6e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1926168553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran
d_reset.1926168553
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2422837145
Short name T900
Test name
Test status
Simulation time 5981406637 ps
CPU time 402.02 seconds
Started Jul 27 04:22:07 PM PDT 24
Finished Jul 27 04:28:49 PM PDT 24
Peak memory 222740 kb
Host smart-56d3cf8d-0d26-4e8d-9dd6-25a4492b1a93
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2422837145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re
set_error.2422837145
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.3113093640
Short name T124
Test name
Test status
Simulation time 135086300 ps
CPU time 19.68 seconds
Started Jul 27 04:22:05 PM PDT 24
Finished Jul 27 04:22:25 PM PDT 24
Peak memory 203748 kb
Host smart-e6c8e1ed-b7c3-472e-99b7-8954d26cb677
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3113093640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3113093640
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2796133035
Short name T813
Test name
Test status
Simulation time 144685846 ps
CPU time 3.31 seconds
Started Jul 27 04:22:07 PM PDT 24
Finished Jul 27 04:22:11 PM PDT 24
Peak memory 203016 kb
Host smart-06aa6ec9-cd6c-428b-9446-6823e96d50de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2796133035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2796133035
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1614738406
Short name T471
Test name
Test status
Simulation time 123282871 ps
CPU time 15.48 seconds
Started Jul 27 04:22:22 PM PDT 24
Finished Jul 27 04:22:38 PM PDT 24
Peak memory 203328 kb
Host smart-2b95da9a-a9e5-4b6d-8342-08392f67009f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1614738406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1614738406
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_random.997665870
Short name T681
Test name
Test status
Simulation time 568687736 ps
CPU time 10.86 seconds
Started Jul 27 04:20:16 PM PDT 24
Finished Jul 27 04:20:27 PM PDT 24
Peak memory 203356 kb
Host smart-a1ec2536-397e-4881-8bf2-bb1246126a19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=997665870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.997665870
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.3574865895
Short name T838
Test name
Test status
Simulation time 218496516 ps
CPU time 6.63 seconds
Started Jul 27 04:23:01 PM PDT 24
Finished Jul 27 04:23:08 PM PDT 24
Peak memory 210340 kb
Host smart-182e5f65-5896-4682-bf0c-a2d1b5896990
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3574865895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.3574865895
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.340262729
Short name T757
Test name
Test status
Simulation time 50213333361 ps
CPU time 142.42 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:24:29 PM PDT 24
Peak memory 211232 kb
Host smart-e7f8bfdc-a1ff-4870-9406-0473220711e9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=340262729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.340262729
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.894833930
Short name T756
Test name
Test status
Simulation time 18276664374 ps
CPU time 142 seconds
Started Jul 27 04:22:09 PM PDT 24
Finished Jul 27 04:24:31 PM PDT 24
Peak memory 203596 kb
Host smart-84c3df1a-ef7e-4762-95b5-3deef7dab521
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=894833930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.894833930
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.1417596493
Short name T661
Test name
Test status
Simulation time 224586940 ps
CPU time 21.5 seconds
Started Jul 27 04:23:12 PM PDT 24
Finished Jul 27 04:23:34 PM PDT 24
Peak memory 211396 kb
Host smart-97200fb9-8ac1-40be-a6d0-3374bdc5d7b4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417596493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.1417596493
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.3971685931
Short name T524
Test name
Test status
Simulation time 5522727194 ps
CPU time 30.98 seconds
Started Jul 27 04:22:22 PM PDT 24
Finished Jul 27 04:22:54 PM PDT 24
Peak memory 211540 kb
Host smart-641c79fe-f8f2-44a7-ad01-9f8ea6c3ba48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3971685931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3971685931
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.2432391387
Short name T303
Test name
Test status
Simulation time 27429128 ps
CPU time 2.21 seconds
Started Jul 27 04:22:05 PM PDT 24
Finished Jul 27 04:22:07 PM PDT 24
Peak memory 201648 kb
Host smart-6704ed18-c3e1-45ea-9338-288590ff3e3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2432391387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2432391387
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2913637986
Short name T748
Test name
Test status
Simulation time 14344077655 ps
CPU time 34.99 seconds
Started Jul 27 04:22:05 PM PDT 24
Finished Jul 27 04:22:40 PM PDT 24
Peak memory 201100 kb
Host smart-96e1143a-1796-485d-be0f-26cbec80df47
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913637986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2913637986
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1993812234
Short name T280
Test name
Test status
Simulation time 3795926876 ps
CPU time 28.84 seconds
Started Jul 27 04:22:05 PM PDT 24
Finished Jul 27 04:22:34 PM PDT 24
Peak memory 201392 kb
Host smart-2727ecd4-8a56-472a-ab9c-32463335e0cd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1993812234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1993812234
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.780769276
Short name T543
Test name
Test status
Simulation time 58151369 ps
CPU time 2.18 seconds
Started Jul 27 04:21:02 PM PDT 24
Finished Jul 27 04:21:04 PM PDT 24
Peak memory 203268 kb
Host smart-7914b2cb-2734-487c-aaca-583fe4e3142b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780769276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.780769276
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.188696403
Short name T89
Test name
Test status
Simulation time 8566388922 ps
CPU time 128.03 seconds
Started Jul 27 04:22:10 PM PDT 24
Finished Jul 27 04:24:19 PM PDT 24
Peak memory 208976 kb
Host smart-d6549aaf-bdb0-4010-af3e-b787e82b02c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=188696403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.188696403
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.3417804037
Short name T554
Test name
Test status
Simulation time 420666294 ps
CPU time 13.89 seconds
Started Jul 27 04:22:25 PM PDT 24
Finished Jul 27 04:22:39 PM PDT 24
Peak memory 202548 kb
Host smart-c3e1a91a-4f71-4489-b72d-0c45aa243607
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3417804037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3417804037
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3725502984
Short name T210
Test name
Test status
Simulation time 3064154806 ps
CPU time 477.73 seconds
Started Jul 27 04:20:18 PM PDT 24
Finished Jul 27 04:28:16 PM PDT 24
Peak memory 219644 kb
Host smart-238e3905-fc4f-482d-82b6-eafc02d1a3c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3725502984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran
d_reset.3725502984
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.1657746921
Short name T442
Test name
Test status
Simulation time 2765884285 ps
CPU time 203.29 seconds
Started Jul 27 04:22:34 PM PDT 24
Finished Jul 27 04:25:57 PM PDT 24
Peak memory 211300 kb
Host smart-2b720cf8-fde7-49db-9ac7-156c60fbc2a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1657746921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re
set_error.1657746921
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.1364288370
Short name T530
Test name
Test status
Simulation time 403911753 ps
CPU time 4.26 seconds
Started Jul 27 04:22:10 PM PDT 24
Finished Jul 27 04:22:14 PM PDT 24
Peak memory 204120 kb
Host smart-efd07e18-49ad-45f3-b55e-2191577a21ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1364288370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1364288370
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.3407536621
Short name T88
Test name
Test status
Simulation time 5648490993 ps
CPU time 76.16 seconds
Started Jul 27 04:22:22 PM PDT 24
Finished Jul 27 04:23:38 PM PDT 24
Peak memory 211516 kb
Host smart-622f437b-0470-42e8-870f-f92019c835da
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3407536621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.3407536621
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1474182846
Short name T704
Test name
Test status
Simulation time 142501765401 ps
CPU time 263.46 seconds
Started Jul 27 04:22:40 PM PDT 24
Finished Jul 27 04:27:04 PM PDT 24
Peak memory 206288 kb
Host smart-daa8cade-f3c3-4ae5-a76d-18483536a655
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1474182846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl
ow_rsp.1474182846
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3236743172
Short name T99
Test name
Test status
Simulation time 119910532 ps
CPU time 11.85 seconds
Started Jul 27 04:22:10 PM PDT 24
Finished Jul 27 04:22:22 PM PDT 24
Peak memory 203092 kb
Host smart-979294dc-da67-47bf-95aa-d7ee01f1ae05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3236743172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3236743172
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.1692738115
Short name T533
Test name
Test status
Simulation time 859327608 ps
CPU time 9.42 seconds
Started Jul 27 04:22:25 PM PDT 24
Finished Jul 27 04:22:34 PM PDT 24
Peak memory 202212 kb
Host smart-bcbd581e-c24d-4621-ad3e-dfd78506131b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1692738115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1692738115
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.707014352
Short name T240
Test name
Test status
Simulation time 444859746 ps
CPU time 10.55 seconds
Started Jul 27 04:20:26 PM PDT 24
Finished Jul 27 04:20:37 PM PDT 24
Peak memory 204564 kb
Host smart-8831d867-7d03-47af-a9e7-a1c51c225c67
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=707014352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.707014352
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.838904419
Short name T238
Test name
Test status
Simulation time 68606906824 ps
CPU time 225.13 seconds
Started Jul 27 04:22:26 PM PDT 24
Finished Jul 27 04:26:11 PM PDT 24
Peak memory 203708 kb
Host smart-db5c5f74-a2a9-47a8-92c3-d1b81cbdca6a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=838904419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.838904419
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.998438251
Short name T612
Test name
Test status
Simulation time 20113492338 ps
CPU time 139.2 seconds
Started Jul 27 04:20:28 PM PDT 24
Finished Jul 27 04:22:47 PM PDT 24
Peak memory 211456 kb
Host smart-b7e625c9-d8b5-40c5-b656-029006b5d863
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=998438251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.998438251
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3546919187
Short name T241
Test name
Test status
Simulation time 55022099 ps
CPU time 3.45 seconds
Started Jul 27 04:21:04 PM PDT 24
Finished Jul 27 04:21:08 PM PDT 24
Peak memory 203360 kb
Host smart-e0c73a38-8cae-4a3b-acf8-b361bc626ddc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546919187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3546919187
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.2193405475
Short name T685
Test name
Test status
Simulation time 183615561 ps
CPU time 6.1 seconds
Started Jul 27 04:22:08 PM PDT 24
Finished Jul 27 04:22:15 PM PDT 24
Peak memory 201808 kb
Host smart-a870aec3-d9ee-432e-9802-d22cc45d8939
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2193405475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2193405475
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.2001341531
Short name T341
Test name
Test status
Simulation time 36027424 ps
CPU time 2.38 seconds
Started Jul 27 04:20:33 PM PDT 24
Finished Jul 27 04:20:36 PM PDT 24
Peak memory 203292 kb
Host smart-bcea8948-a4d4-476a-8c61-2c2cedbcaf77
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2001341531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2001341531
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.3136755135
Short name T218
Test name
Test status
Simulation time 34062997187 ps
CPU time 45.65 seconds
Started Jul 27 04:22:34 PM PDT 24
Finished Jul 27 04:23:19 PM PDT 24
Peak memory 202944 kb
Host smart-bf567f20-d4d9-4602-939c-a03848e2a29d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136755135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.3136755135
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.825940139
Short name T358
Test name
Test status
Simulation time 3833308584 ps
CPU time 26.1 seconds
Started Jul 27 04:20:26 PM PDT 24
Finished Jul 27 04:20:52 PM PDT 24
Peak memory 203360 kb
Host smart-8d28275e-ebe3-44d7-9cce-488d0f961659
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=825940139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.825940139
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3994601312
Short name T593
Test name
Test status
Simulation time 66477669 ps
CPU time 1.91 seconds
Started Jul 27 04:22:20 PM PDT 24
Finished Jul 27 04:22:22 PM PDT 24
Peak memory 203272 kb
Host smart-d8df0500-6002-4c9b-9ae7-e38ce3e18cf4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994601312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3994601312
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.1758723634
Short name T521
Test name
Test status
Simulation time 790537104 ps
CPU time 74.88 seconds
Started Jul 27 04:22:09 PM PDT 24
Finished Jul 27 04:23:24 PM PDT 24
Peak memory 205692 kb
Host smart-7b6ab4b6-d959-4e20-b406-e32c62324f90
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1758723634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1758723634
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.2604154669
Short name T728
Test name
Test status
Simulation time 1082011096 ps
CPU time 30.5 seconds
Started Jul 27 04:22:33 PM PDT 24
Finished Jul 27 04:23:04 PM PDT 24
Peak memory 205280 kb
Host smart-72c6f655-25d9-4062-bb8b-56b2f88b6fa0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2604154669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2604154669
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.4078740350
Short name T858
Test name
Test status
Simulation time 6975440103 ps
CPU time 90.57 seconds
Started Jul 27 04:22:08 PM PDT 24
Finished Jul 27 04:23:39 PM PDT 24
Peak memory 206816 kb
Host smart-098303a6-ac1e-46a2-9d2d-c7987c687511
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4078740350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran
d_reset.4078740350
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.2616299431
Short name T691
Test name
Test status
Simulation time 189430518 ps
CPU time 47.58 seconds
Started Jul 27 04:22:23 PM PDT 24
Finished Jul 27 04:23:11 PM PDT 24
Peak memory 206592 kb
Host smart-ef7aaeb2-5c6c-472a-8f2e-5a1726ac08c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2616299431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re
set_error.2616299431
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.4127415945
Short name T342
Test name
Test status
Simulation time 832455946 ps
CPU time 25.39 seconds
Started Jul 27 04:22:08 PM PDT 24
Finished Jul 27 04:22:34 PM PDT 24
Peak memory 203940 kb
Host smart-42c42d45-58be-4be0-8399-d293692288fc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4127415945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.4127415945
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1416092780
Short name T605
Test name
Test status
Simulation time 626072766 ps
CPU time 44.14 seconds
Started Jul 27 04:22:07 PM PDT 24
Finished Jul 27 04:22:51 PM PDT 24
Peak memory 205760 kb
Host smart-cf74ecbc-d39f-4604-a517-76fa867d3593
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1416092780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1416092780
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.3051955067
Short name T145
Test name
Test status
Simulation time 28549787355 ps
CPU time 170.64 seconds
Started Jul 27 04:23:10 PM PDT 24
Finished Jul 27 04:26:01 PM PDT 24
Peak memory 205444 kb
Host smart-6514a108-f205-4ad7-82ca-9649e62eb45e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3051955067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl
ow_rsp.3051955067
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.4268553067
Short name T244
Test name
Test status
Simulation time 33360836 ps
CPU time 4.87 seconds
Started Jul 27 04:23:21 PM PDT 24
Finished Jul 27 04:23:26 PM PDT 24
Peak memory 203204 kb
Host smart-c3327141-d9b0-4014-bf22-36114f7e2d06
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4268553067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.4268553067
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.1196972420
Short name T863
Test name
Test status
Simulation time 360321596 ps
CPU time 10.97 seconds
Started Jul 27 04:22:25 PM PDT 24
Finished Jul 27 04:22:36 PM PDT 24
Peak memory 202468 kb
Host smart-2e0aba32-7f1a-43ee-a6e6-53ebc02d41fc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1196972420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1196972420
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.3692571922
Short name T846
Test name
Test status
Simulation time 940435216 ps
CPU time 27.42 seconds
Started Jul 27 04:22:27 PM PDT 24
Finished Jul 27 04:22:55 PM PDT 24
Peak memory 211284 kb
Host smart-8dad4bfb-4157-41f4-8f7e-f037c68b4275
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3692571922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.3692571922
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.578442505
Short name T271
Test name
Test status
Simulation time 12951619465 ps
CPU time 73.09 seconds
Started Jul 27 04:22:25 PM PDT 24
Finished Jul 27 04:23:39 PM PDT 24
Peak memory 203936 kb
Host smart-97b9004a-6849-4ed0-9636-4f00badc7b8b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=578442505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.578442505
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.942113149
Short name T93
Test name
Test status
Simulation time 31723425352 ps
CPU time 214.44 seconds
Started Jul 27 04:22:26 PM PDT 24
Finished Jul 27 04:26:00 PM PDT 24
Peak memory 211328 kb
Host smart-21469746-40dc-4725-a61b-ce7699915857
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=942113149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.942113149
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.1571968247
Short name T384
Test name
Test status
Simulation time 146637851 ps
CPU time 7.5 seconds
Started Jul 27 04:22:26 PM PDT 24
Finished Jul 27 04:22:34 PM PDT 24
Peak memory 211240 kb
Host smart-792a3141-2fe6-4fd4-a033-ab1cd5859661
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571968247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.1571968247
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.3826166875
Short name T777
Test name
Test status
Simulation time 242296736 ps
CPU time 13.47 seconds
Started Jul 27 04:20:42 PM PDT 24
Finished Jul 27 04:20:56 PM PDT 24
Peak memory 204352 kb
Host smart-8ddab6a0-0395-4f27-9cd8-853b8def6a49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3826166875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3826166875
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.3818504303
Short name T527
Test name
Test status
Simulation time 100187252 ps
CPU time 2.92 seconds
Started Jul 27 04:22:34 PM PDT 24
Finished Jul 27 04:22:37 PM PDT 24
Peak memory 202892 kb
Host smart-4a29158c-4951-4afc-98c8-a23a5205f453
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3818504303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3818504303
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.2727724696
Short name T652
Test name
Test status
Simulation time 17333416285 ps
CPU time 32.5 seconds
Started Jul 27 04:23:09 PM PDT 24
Finished Jul 27 04:23:42 PM PDT 24
Peak memory 203080 kb
Host smart-1c744c8f-5f58-4ab8-bfe0-7c745fbd9000
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727724696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2727724696
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.104697064
Short name T443
Test name
Test status
Simulation time 4217907696 ps
CPU time 31.12 seconds
Started Jul 27 04:20:45 PM PDT 24
Finished Jul 27 04:21:16 PM PDT 24
Peak memory 203348 kb
Host smart-0a989139-3f18-472c-83c6-678c4e73d396
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=104697064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.104697064
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1035298391
Short name T539
Test name
Test status
Simulation time 50208370 ps
CPU time 1.85 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:22:08 PM PDT 24
Peak memory 202836 kb
Host smart-ff6181ef-1121-4008-aaa6-26586ae21e12
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035298391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1035298391
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.3961383157
Short name T468
Test name
Test status
Simulation time 2935136957 ps
CPU time 72.36 seconds
Started Jul 27 04:22:39 PM PDT 24
Finished Jul 27 04:23:51 PM PDT 24
Peak memory 206688 kb
Host smart-8b748136-51a3-4b1e-8e0b-d66828d96dca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3961383157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.3961383157
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.687811583
Short name T510
Test name
Test status
Simulation time 5253813774 ps
CPU time 87.89 seconds
Started Jul 27 04:22:27 PM PDT 24
Finished Jul 27 04:23:55 PM PDT 24
Peak memory 205948 kb
Host smart-d7149636-b134-455e-bc48-03ba2808533d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=687811583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.687811583
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.3735009694
Short name T157
Test name
Test status
Simulation time 64322386 ps
CPU time 6.46 seconds
Started Jul 27 04:22:33 PM PDT 24
Finished Jul 27 04:22:39 PM PDT 24
Peak memory 203960 kb
Host smart-99e41d1c-ad4c-46ef-af96-350269a28f0b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3735009694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re
set_error.3735009694
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.792245702
Short name T647
Test name
Test status
Simulation time 833404447 ps
CPU time 17.95 seconds
Started Jul 27 04:22:28 PM PDT 24
Finished Jul 27 04:22:46 PM PDT 24
Peak memory 204360 kb
Host smart-2bd430a2-9592-4253-bda0-782ce55993ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=792245702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.792245702
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.2915095400
Short name T656
Test name
Test status
Simulation time 2927447066 ps
CPU time 59.89 seconds
Started Jul 27 04:23:07 PM PDT 24
Finished Jul 27 04:24:07 PM PDT 24
Peak memory 210272 kb
Host smart-9d336a0f-74f7-40e5-9288-774cc0fdf283
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2915095400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.2915095400
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.4266658068
Short name T198
Test name
Test status
Simulation time 412443959 ps
CPU time 14.86 seconds
Started Jul 27 04:23:07 PM PDT 24
Finished Jul 27 04:23:22 PM PDT 24
Peak memory 202184 kb
Host smart-ddc88238-20b3-4634-ab61-4fbd28f1fcc8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4266658068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.4266658068
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.3560211969
Short name T824
Test name
Test status
Simulation time 836400125 ps
CPU time 15.57 seconds
Started Jul 27 04:22:21 PM PDT 24
Finished Jul 27 04:22:37 PM PDT 24
Peak memory 202508 kb
Host smart-f0d7d782-f836-4ec9-872c-735842d8e2ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3560211969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.3560211969
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.485177048
Short name T787
Test name
Test status
Simulation time 63845847 ps
CPU time 3.87 seconds
Started Jul 27 04:22:23 PM PDT 24
Finished Jul 27 04:22:27 PM PDT 24
Peak memory 203176 kb
Host smart-3a8d1b4c-9163-4f9a-979a-8cd58dde39a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=485177048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.485177048
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.1813346387
Short name T43
Test name
Test status
Simulation time 14855838992 ps
CPU time 47.43 seconds
Started Jul 27 04:22:24 PM PDT 24
Finished Jul 27 04:23:12 PM PDT 24
Peak memory 204532 kb
Host smart-2fa96fd3-27e4-44f2-b21a-7f406b1c526f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813346387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1813346387
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.1076245271
Short name T139
Test name
Test status
Simulation time 29482779944 ps
CPU time 178.31 seconds
Started Jul 27 04:23:20 PM PDT 24
Finished Jul 27 04:26:18 PM PDT 24
Peak memory 211500 kb
Host smart-eec372d0-423a-4337-9b1d-872d0e977c42
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1076245271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1076245271
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.3489670446
Short name T776
Test name
Test status
Simulation time 50874552 ps
CPU time 3.76 seconds
Started Jul 27 04:22:23 PM PDT 24
Finished Jul 27 04:22:27 PM PDT 24
Peak memory 203704 kb
Host smart-c3f653f1-c188-49e5-b724-a1106216e028
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489670446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.3489670446
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.381087622
Short name T427
Test name
Test status
Simulation time 142918803 ps
CPU time 4.29 seconds
Started Jul 27 04:22:32 PM PDT 24
Finished Jul 27 04:22:36 PM PDT 24
Peak memory 203408 kb
Host smart-bbc47168-0e3e-4cca-aa4c-fc491af8c1c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=381087622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.381087622
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.3558802742
Short name T2
Test name
Test status
Simulation time 262024040 ps
CPU time 3.34 seconds
Started Jul 27 04:22:23 PM PDT 24
Finished Jul 27 04:22:26 PM PDT 24
Peak memory 202968 kb
Host smart-26c64c23-62c6-434c-8683-56ace7cc9ff4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3558802742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3558802742
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.2773039601
Short name T546
Test name
Test status
Simulation time 5779076112 ps
CPU time 34.44 seconds
Started Jul 27 04:22:23 PM PDT 24
Finished Jul 27 04:22:57 PM PDT 24
Peak memory 202672 kb
Host smart-20d20e63-8ee6-4a99-b8f0-b80a29823604
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773039601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2773039601
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1770998850
Short name T547
Test name
Test status
Simulation time 3371939511 ps
CPU time 30.53 seconds
Started Jul 27 04:22:34 PM PDT 24
Finished Jul 27 04:23:05 PM PDT 24
Peak memory 203140 kb
Host smart-3d83470a-a057-4c0a-a558-67c0b754e95e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1770998850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1770998850
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1597274578
Short name T884
Test name
Test status
Simulation time 77118602 ps
CPU time 2.34 seconds
Started Jul 27 04:22:30 PM PDT 24
Finished Jul 27 04:22:33 PM PDT 24
Peak memory 203032 kb
Host smart-ee16b004-a7e6-4a28-981d-88cb43fee1ac
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597274578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1597274578
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.2679711884
Short name T724
Test name
Test status
Simulation time 1443396493 ps
CPU time 22.13 seconds
Started Jul 27 04:22:22 PM PDT 24
Finished Jul 27 04:22:44 PM PDT 24
Peak memory 204172 kb
Host smart-ecb01dbb-bb93-419b-987f-8116ad82146c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2679711884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2679711884
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.547511698
Short name T227
Test name
Test status
Simulation time 1533991018 ps
CPU time 320.43 seconds
Started Jul 27 04:22:30 PM PDT 24
Finished Jul 27 04:27:51 PM PDT 24
Peak memory 210452 kb
Host smart-8cb0bce9-66ce-4e7a-85a8-f10d9834a1a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=547511698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand
_reset.547511698
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1751683224
Short name T40
Test name
Test status
Simulation time 441477815 ps
CPU time 83.28 seconds
Started Jul 27 04:22:21 PM PDT 24
Finished Jul 27 04:23:44 PM PDT 24
Peak memory 207940 kb
Host smart-92919c5f-35d8-43b6-b515-3c5d9b88e658
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1751683224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re
set_error.1751683224
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.1877808449
Short name T328
Test name
Test status
Simulation time 2334565427 ps
CPU time 30.75 seconds
Started Jul 27 04:22:32 PM PDT 24
Finished Jul 27 04:23:03 PM PDT 24
Peak memory 211340 kb
Host smart-646de8f6-cd62-4874-a66c-3b0fd1649026
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1877808449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.1877808449
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.294403093
Short name T121
Test name
Test status
Simulation time 272884777 ps
CPU time 16.66 seconds
Started Jul 27 04:23:19 PM PDT 24
Finished Jul 27 04:23:36 PM PDT 24
Peak memory 204136 kb
Host smart-629f089d-eade-4ec2-88ba-b4d8e082f8d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=294403093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.294403093
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.2560393569
Short name T100
Test name
Test status
Simulation time 76704228817 ps
CPU time 255.99 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:26:22 PM PDT 24
Peak memory 210840 kb
Host smart-1ea8b48f-7619-44fa-9f58-ad81f80a5cbb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2560393569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo
w_rsp.2560393569
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3469998966
Short name T709
Test name
Test status
Simulation time 251636940 ps
CPU time 8.14 seconds
Started Jul 27 04:23:18 PM PDT 24
Finished Jul 27 04:23:26 PM PDT 24
Peak memory 203452 kb
Host smart-cf117da0-1488-40e7-ac9b-9a7908cabe3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3469998966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3469998966
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.1880687670
Short name T507
Test name
Test status
Simulation time 427122899 ps
CPU time 20.02 seconds
Started Jul 27 04:19:32 PM PDT 24
Finished Jul 27 04:19:52 PM PDT 24
Peak memory 203308 kb
Host smart-0c1ee1b4-e2d8-47a4-aec3-dc1ae31085d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1880687670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1880687670
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.1381929324
Short name T788
Test name
Test status
Simulation time 1056934998 ps
CPU time 20.44 seconds
Started Jul 27 04:18:39 PM PDT 24
Finished Jul 27 04:18:59 PM PDT 24
Peak memory 211464 kb
Host smart-06cbedf6-cec3-4571-b807-8f60b2f8d9fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1381929324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.1381929324
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.3788835248
Short name T504
Test name
Test status
Simulation time 21844990855 ps
CPU time 166.66 seconds
Started Jul 27 04:22:31 PM PDT 24
Finished Jul 27 04:25:18 PM PDT 24
Peak memory 210712 kb
Host smart-06e29469-adda-4bd0-964a-8c4f15885df4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3788835248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3788835248
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.1106289687
Short name T803
Test name
Test status
Simulation time 180218556 ps
CPU time 8.77 seconds
Started Jul 27 04:18:51 PM PDT 24
Finished Jul 27 04:18:59 PM PDT 24
Peak memory 204464 kb
Host smart-2dfb33b2-d373-43b1-a409-ff806da13182
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106289687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.1106289687
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.4180792277
Short name T655
Test name
Test status
Simulation time 342301191 ps
CPU time 16.13 seconds
Started Jul 27 04:22:54 PM PDT 24
Finished Jul 27 04:23:10 PM PDT 24
Peak memory 203616 kb
Host smart-c36a8797-b2e7-47aa-a5f5-41e4d3e5ae66
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4180792277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.4180792277
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.3881875527
Short name T519
Test name
Test status
Simulation time 156274572 ps
CPU time 3.19 seconds
Started Jul 27 04:23:19 PM PDT 24
Finished Jul 27 04:23:23 PM PDT 24
Peak memory 203240 kb
Host smart-a76aa44c-a0f4-4c04-a664-e91544945b2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3881875527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3881875527
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.413035072
Short name T125
Test name
Test status
Simulation time 5131437220 ps
CPU time 27.17 seconds
Started Jul 27 04:18:25 PM PDT 24
Finished Jul 27 04:18:53 PM PDT 24
Peak memory 203388 kb
Host smart-8298be67-a594-42be-bb9c-4868fc22a768
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=413035072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.413035072
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.4011941507
Short name T841
Test name
Test status
Simulation time 8570305517 ps
CPU time 31.09 seconds
Started Jul 27 04:19:31 PM PDT 24
Finished Jul 27 04:20:02 PM PDT 24
Peak memory 203340 kb
Host smart-a7780f57-3bc7-431b-9d1f-a32534b6bcab
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4011941507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.4011941507
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3502340486
Short name T740
Test name
Test status
Simulation time 45687968 ps
CPU time 2.12 seconds
Started Jul 27 04:22:34 PM PDT 24
Finished Jul 27 04:22:37 PM PDT 24
Peak memory 203236 kb
Host smart-f1d53048-d406-4298-9d45-aab5b8230f91
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502340486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3502340486
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.4252703883
Short name T583
Test name
Test status
Simulation time 5038083800 ps
CPU time 152.72 seconds
Started Jul 27 04:22:21 PM PDT 24
Finished Jul 27 04:24:54 PM PDT 24
Peak memory 207052 kb
Host smart-282867ee-4627-40da-a79d-2a3aab428e89
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4252703883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.4252703883
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.1637876002
Short name T225
Test name
Test status
Simulation time 1756467248 ps
CPU time 116.31 seconds
Started Jul 27 04:23:18 PM PDT 24
Finished Jul 27 04:25:14 PM PDT 24
Peak memory 208232 kb
Host smart-f8ab0df9-70fd-4d91-9551-21318b26aafc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1637876002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1637876002
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1325668298
Short name T882
Test name
Test status
Simulation time 644157932 ps
CPU time 20.73 seconds
Started Jul 27 04:21:31 PM PDT 24
Finished Jul 27 04:21:52 PM PDT 24
Peak memory 205996 kb
Host smart-ed1e0022-c887-4c86-a032-5724e8ded2ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1325668298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand
_reset.1325668298
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.4291393026
Short name T222
Test name
Test status
Simulation time 15591164737 ps
CPU time 336.54 seconds
Started Jul 27 04:22:58 PM PDT 24
Finished Jul 27 04:28:34 PM PDT 24
Peak memory 220360 kb
Host smart-293aad43-272d-4f25-8162-e014cfa4d902
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4291393026 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res
et_error.4291393026
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.1064298396
Short name T148
Test name
Test status
Simulation time 693889126 ps
CPU time 33.6 seconds
Started Jul 27 04:18:22 PM PDT 24
Finished Jul 27 04:18:55 PM PDT 24
Peak memory 211640 kb
Host smart-e871c1c9-fbcf-4021-a907-e6604649e47d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1064298396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1064298396
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.809596957
Short name T69
Test name
Test status
Simulation time 216280488 ps
CPU time 14.02 seconds
Started Jul 27 04:22:27 PM PDT 24
Finished Jul 27 04:22:42 PM PDT 24
Peak memory 211172 kb
Host smart-8218eeaa-a116-45d3-a99d-e7e99816a38b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=809596957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.809596957
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3774287570
Short name T217
Test name
Test status
Simulation time 74209083853 ps
CPU time 499.65 seconds
Started Jul 27 04:22:27 PM PDT 24
Finished Jul 27 04:30:47 PM PDT 24
Peak memory 207092 kb
Host smart-b90d1f3f-4090-4b95-9ceb-d08b721c09dd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3774287570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl
ow_rsp.3774287570
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.3461422355
Short name T853
Test name
Test status
Simulation time 592845061 ps
CPU time 22.91 seconds
Started Jul 27 04:21:13 PM PDT 24
Finished Jul 27 04:21:36 PM PDT 24
Peak memory 203456 kb
Host smart-1c01f00b-2f4a-4ee9-a8c8-05f9e6d36f36
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3461422355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.3461422355
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.2450153596
Short name T614
Test name
Test status
Simulation time 1033936781 ps
CPU time 24.15 seconds
Started Jul 27 04:22:27 PM PDT 24
Finished Jul 27 04:22:51 PM PDT 24
Peak memory 202888 kb
Host smart-301884bd-2095-4131-97ef-454221b5dbb3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2450153596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.2450153596
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.852874914
Short name T511
Test name
Test status
Simulation time 270301529 ps
CPU time 9.66 seconds
Started Jul 27 04:23:21 PM PDT 24
Finished Jul 27 04:23:31 PM PDT 24
Peak memory 211468 kb
Host smart-dfa6da44-d094-4116-a560-e9a82e2389ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=852874914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.852874914
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.2520384809
Short name T149
Test name
Test status
Simulation time 19636359304 ps
CPU time 69.33 seconds
Started Jul 27 04:22:26 PM PDT 24
Finished Jul 27 04:23:36 PM PDT 24
Peak memory 210188 kb
Host smart-15fdb370-894e-4522-8b89-2ed69ad71e21
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520384809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2520384809
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3916058321
Short name T536
Test name
Test status
Simulation time 39736612195 ps
CPU time 120.06 seconds
Started Jul 27 04:22:26 PM PDT 24
Finished Jul 27 04:24:27 PM PDT 24
Peak memory 211076 kb
Host smart-ab761bf7-b26f-4f94-aa58-881239b3bf3f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3916058321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3916058321
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.207626539
Short name T369
Test name
Test status
Simulation time 284433484 ps
CPU time 13.25 seconds
Started Jul 27 04:21:17 PM PDT 24
Finished Jul 27 04:21:31 PM PDT 24
Peak memory 204304 kb
Host smart-5c4d6a6e-02a0-4c6e-b223-68943b3e92e4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207626539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.207626539
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.1769964946
Short name T540
Test name
Test status
Simulation time 35687181 ps
CPU time 2 seconds
Started Jul 27 04:22:26 PM PDT 24
Finished Jul 27 04:22:29 PM PDT 24
Peak memory 201788 kb
Host smart-a519b345-9919-42a1-aec6-fe926a0f2709
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1769964946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1769964946
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.2868355799
Short name T118
Test name
Test status
Simulation time 22666514 ps
CPU time 2.09 seconds
Started Jul 27 04:22:24 PM PDT 24
Finished Jul 27 04:22:26 PM PDT 24
Peak memory 203056 kb
Host smart-987cb495-5fbd-4792-8d48-caf5b795331a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2868355799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2868355799
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.2317306981
Short name T463
Test name
Test status
Simulation time 35551915920 ps
CPU time 44.49 seconds
Started Jul 27 04:22:30 PM PDT 24
Finished Jul 27 04:23:15 PM PDT 24
Peak memory 203144 kb
Host smart-3505e920-ec43-4a36-ade4-5bcbdb026213
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317306981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2317306981
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.1204730400
Short name T199
Test name
Test status
Simulation time 3937419666 ps
CPU time 25.65 seconds
Started Jul 27 04:22:27 PM PDT 24
Finished Jul 27 04:22:53 PM PDT 24
Peak memory 202432 kb
Host smart-04b1d9b4-a3a8-4202-b80f-c098529e689a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1204730400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1204730400
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1806492076
Short name T115
Test name
Test status
Simulation time 39668904 ps
CPU time 2.1 seconds
Started Jul 27 04:22:34 PM PDT 24
Finished Jul 27 04:22:36 PM PDT 24
Peak memory 203000 kb
Host smart-a099baa1-fa03-41e3-b09f-916d9a35e9f8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806492076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1806492076
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.1569133648
Short name T638
Test name
Test status
Simulation time 5433937096 ps
CPU time 156.96 seconds
Started Jul 27 04:22:27 PM PDT 24
Finished Jul 27 04:25:04 PM PDT 24
Peak memory 206964 kb
Host smart-4a92798e-dc18-43e9-af3c-e18ace495bd7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1569133648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1569133648
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.960753427
Short name T856
Test name
Test status
Simulation time 172891932 ps
CPU time 16.45 seconds
Started Jul 27 04:22:27 PM PDT 24
Finished Jul 27 04:22:44 PM PDT 24
Peak memory 210612 kb
Host smart-e69637fc-a6cc-4e62-982b-0efcea3297f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=960753427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.960753427
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.3366764940
Short name T449
Test name
Test status
Simulation time 205949136 ps
CPU time 23.3 seconds
Started Jul 27 04:21:24 PM PDT 24
Finished Jul 27 04:21:47 PM PDT 24
Peak memory 204424 kb
Host smart-826ad421-cf0f-4912-8fb3-c8123e4f954d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3366764940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.3366764940
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.4026698872
Short name T9
Test name
Test status
Simulation time 130897786480 ps
CPU time 347.6 seconds
Started Jul 27 04:21:26 PM PDT 24
Finished Jul 27 04:27:13 PM PDT 24
Peak memory 206468 kb
Host smart-a2226846-17e9-4a41-863c-e4fb2b544106
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4026698872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl
ow_rsp.4026698872
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2994800916
Short name T415
Test name
Test status
Simulation time 110577403 ps
CPU time 2.5 seconds
Started Jul 27 04:21:26 PM PDT 24
Finished Jul 27 04:21:29 PM PDT 24
Peak memory 203176 kb
Host smart-aacecd41-04da-4ff4-ae1b-fde728fe3514
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2994800916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.2994800916
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.3471180352
Short name T386
Test name
Test status
Simulation time 116098698 ps
CPU time 13.86 seconds
Started Jul 27 04:21:26 PM PDT 24
Finished Jul 27 04:21:40 PM PDT 24
Peak memory 203304 kb
Host smart-e223f4c2-e7e8-41cb-a00a-7a96943d19f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3471180352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3471180352
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.946709235
Short name T72
Test name
Test status
Simulation time 114389998 ps
CPU time 12.66 seconds
Started Jul 27 04:23:22 PM PDT 24
Finished Jul 27 04:23:34 PM PDT 24
Peak memory 211468 kb
Host smart-62b5e66a-86c4-4d3e-9908-ac0da906168b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=946709235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.946709235
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.1027792793
Short name T876
Test name
Test status
Simulation time 187572832484 ps
CPU time 309.69 seconds
Started Jul 27 04:23:21 PM PDT 24
Finished Jul 27 04:28:31 PM PDT 24
Peak memory 211508 kb
Host smart-afbd175d-1f61-4d62-9800-295cb5966997
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027792793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1027792793
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.831920860
Short name T729
Test name
Test status
Simulation time 17388645027 ps
CPU time 136.69 seconds
Started Jul 27 04:23:09 PM PDT 24
Finished Jul 27 04:25:26 PM PDT 24
Peak memory 211220 kb
Host smart-db9a7456-978b-4b53-98b1-89ff5baa45fc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=831920860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.831920860
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.77374149
Short name T356
Test name
Test status
Simulation time 110175592 ps
CPU time 9.32 seconds
Started Jul 27 04:22:39 PM PDT 24
Finished Jul 27 04:22:48 PM PDT 24
Peak memory 211472 kb
Host smart-248d73bf-c074-48a2-ad66-d84af097e111
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77374149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.77374149
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.2026220612
Short name T441
Test name
Test status
Simulation time 321421802 ps
CPU time 13.68 seconds
Started Jul 27 04:21:24 PM PDT 24
Finished Jul 27 04:21:37 PM PDT 24
Peak memory 203348 kb
Host smart-aafc5d16-b083-439c-81da-d17b43dccffa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2026220612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2026220612
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.1803466815
Short name T792
Test name
Test status
Simulation time 141465654 ps
CPU time 3.26 seconds
Started Jul 27 04:23:20 PM PDT 24
Finished Jul 27 04:23:23 PM PDT 24
Peak memory 203272 kb
Host smart-53fbf330-d48c-4b90-8ee7-d40ec357e6a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1803466815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1803466815
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.353388385
Short name T71
Test name
Test status
Simulation time 15296111298 ps
CPU time 32.71 seconds
Started Jul 27 04:22:26 PM PDT 24
Finished Jul 27 04:22:59 PM PDT 24
Peak memory 201820 kb
Host smart-e7fa4d20-a264-4764-ae15-69135779412a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=353388385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.353388385
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2930172542
Short name T32
Test name
Test status
Simulation time 4810089031 ps
CPU time 40.07 seconds
Started Jul 27 04:22:27 PM PDT 24
Finished Jul 27 04:23:07 PM PDT 24
Peak memory 202964 kb
Host smart-100adeb1-0c8a-4453-9c20-1f5dc16b1b0e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2930172542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2930172542
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3772146240
Short name T155
Test name
Test status
Simulation time 41376094 ps
CPU time 2 seconds
Started Jul 27 04:23:08 PM PDT 24
Finished Jul 27 04:23:10 PM PDT 24
Peak memory 202196 kb
Host smart-1ef6070f-b6eb-437e-9ffe-294eaa7368d4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772146240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3772146240
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.196912732
Short name T665
Test name
Test status
Simulation time 1377834216 ps
CPU time 108.01 seconds
Started Jul 27 04:22:52 PM PDT 24
Finished Jul 27 04:24:40 PM PDT 24
Peak memory 207828 kb
Host smart-552a0737-344b-4e94-bc98-c4d4d8d7722f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=196912732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.196912732
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.4293849030
Short name T739
Test name
Test status
Simulation time 1667995794 ps
CPU time 42.17 seconds
Started Jul 27 04:22:49 PM PDT 24
Finished Jul 27 04:23:31 PM PDT 24
Peak memory 204608 kb
Host smart-bb35aabc-d4c0-4bb8-b95d-633431be9099
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4293849030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.4293849030
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.2785573669
Short name T207
Test name
Test status
Simulation time 366327632 ps
CPU time 107.28 seconds
Started Jul 27 04:22:53 PM PDT 24
Finished Jul 27 04:24:40 PM PDT 24
Peak memory 209644 kb
Host smart-de35eb60-e8c5-4fa3-8427-b4e5bfd5141a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2785573669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re
set_error.2785573669
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.1405200902
Short name T289
Test name
Test status
Simulation time 41051005 ps
CPU time 1.97 seconds
Started Jul 27 04:22:37 PM PDT 24
Finished Jul 27 04:22:39 PM PDT 24
Peak memory 202440 kb
Host smart-0ec45f1b-2071-49f8-9770-5476d887948e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1405200902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1405200902
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.3944326324
Short name T615
Test name
Test status
Simulation time 727420485 ps
CPU time 22.26 seconds
Started Jul 27 04:21:40 PM PDT 24
Finished Jul 27 04:22:02 PM PDT 24
Peak memory 211620 kb
Host smart-89495c18-6456-4c59-9331-2e65279bd0d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3944326324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3944326324
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3950066527
Short name T404
Test name
Test status
Simulation time 4153239744 ps
CPU time 29.18 seconds
Started Jul 27 04:21:41 PM PDT 24
Finished Jul 27 04:22:10 PM PDT 24
Peak memory 203532 kb
Host smart-94a7ef8d-139b-4999-896c-a11f0744211b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3950066527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl
ow_rsp.3950066527
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2862242399
Short name T758
Test name
Test status
Simulation time 344603937 ps
CPU time 11.89 seconds
Started Jul 27 04:22:45 PM PDT 24
Finished Jul 27 04:22:57 PM PDT 24
Peak memory 203700 kb
Host smart-38358188-1969-41a7-9676-133f569e346a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2862242399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.2862242399
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.1188863629
Short name T568
Test name
Test status
Simulation time 320388522 ps
CPU time 9.94 seconds
Started Jul 27 04:21:37 PM PDT 24
Finished Jul 27 04:21:47 PM PDT 24
Peak memory 203300 kb
Host smart-d4afb466-07fc-4aa7-848f-2876f8994465
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1188863629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1188863629
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.376659653
Short name T495
Test name
Test status
Simulation time 584679356 ps
CPU time 11.47 seconds
Started Jul 27 04:22:44 PM PDT 24
Finished Jul 27 04:22:56 PM PDT 24
Peak memory 204416 kb
Host smart-98b74681-3c25-48af-8a00-e4b063e573c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=376659653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.376659653
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.3506177348
Short name T183
Test name
Test status
Simulation time 47622681521 ps
CPU time 194.47 seconds
Started Jul 27 04:21:42 PM PDT 24
Finished Jul 27 04:24:56 PM PDT 24
Peak memory 211512 kb
Host smart-56c48f62-816c-4021-ad25-940bc5f739f9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506177348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3506177348
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.2084773453
Short name T603
Test name
Test status
Simulation time 131230768133 ps
CPU time 321.09 seconds
Started Jul 27 04:21:39 PM PDT 24
Finished Jul 27 04:27:01 PM PDT 24
Peak memory 211708 kb
Host smart-7d02423a-283a-455e-84ec-d5512014d33c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2084773453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2084773453
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.418129819
Short name T254
Test name
Test status
Simulation time 118964582 ps
CPU time 9.08 seconds
Started Jul 27 04:22:45 PM PDT 24
Finished Jul 27 04:22:54 PM PDT 24
Peak memory 211488 kb
Host smart-131189f5-f5a2-47dd-b2b2-7eaf7bbfbd47
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418129819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.418129819
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.3711030429
Short name T348
Test name
Test status
Simulation time 102524998 ps
CPU time 7.82 seconds
Started Jul 27 04:21:35 PM PDT 24
Finished Jul 27 04:21:43 PM PDT 24
Peak memory 203964 kb
Host smart-1a72ba04-1565-47d2-92c7-3ffea440f5f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3711030429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3711030429
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.115393835
Short name T44
Test name
Test status
Simulation time 44550561 ps
CPU time 2.74 seconds
Started Jul 27 04:22:45 PM PDT 24
Finished Jul 27 04:22:47 PM PDT 24
Peak memory 203264 kb
Host smart-24b1a895-8a02-49ea-a498-41f7ec6c0778
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=115393835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.115393835
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.4251698655
Short name T261
Test name
Test status
Simulation time 28879915858 ps
CPU time 54.47 seconds
Started Jul 27 04:21:38 PM PDT 24
Finished Jul 27 04:22:33 PM PDT 24
Peak memory 203352 kb
Host smart-aaad8017-820b-4181-a9e4-8af59d9c72c9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251698655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.4251698655
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.2260948807
Short name T759
Test name
Test status
Simulation time 3763708787 ps
CPU time 26.57 seconds
Started Jul 27 04:21:37 PM PDT 24
Finished Jul 27 04:22:04 PM PDT 24
Peak memory 203372 kb
Host smart-4def555c-419e-4352-b18b-962a457815ae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2260948807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2260948807
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.2979683838
Short name T594
Test name
Test status
Simulation time 64662890 ps
CPU time 2.45 seconds
Started Jul 27 04:21:37 PM PDT 24
Finished Jul 27 04:21:39 PM PDT 24
Peak memory 203288 kb
Host smart-14e1d389-b66c-4876-95db-63504a90b31e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979683838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.2979683838
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.2674612844
Short name T474
Test name
Test status
Simulation time 888955130 ps
CPU time 82.15 seconds
Started Jul 27 04:21:36 PM PDT 24
Finished Jul 27 04:22:58 PM PDT 24
Peak memory 208060 kb
Host smart-2b960bb3-3cfc-422c-9fcf-f84b29dd5fb9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2674612844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2674612844
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.841673662
Short name T306
Test name
Test status
Simulation time 1650971107 ps
CPU time 29.85 seconds
Started Jul 27 04:21:50 PM PDT 24
Finished Jul 27 04:22:20 PM PDT 24
Peak memory 203752 kb
Host smart-dc961ab3-7733-44bd-a6d2-8236849faed8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=841673662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.841673662
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1732235189
Short name T21
Test name
Test status
Simulation time 1960070873 ps
CPU time 163.74 seconds
Started Jul 27 04:21:36 PM PDT 24
Finished Jul 27 04:24:20 PM PDT 24
Peak memory 209444 kb
Host smart-0a56bbd2-b40c-4a6a-9324-37b83a978aff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1732235189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran
d_reset.1732235189
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2376023128
Short name T563
Test name
Test status
Simulation time 8911194940 ps
CPU time 209.99 seconds
Started Jul 27 04:22:58 PM PDT 24
Finished Jul 27 04:26:28 PM PDT 24
Peak memory 209600 kb
Host smart-510f84ce-9952-421a-9fe1-65a79a596686
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2376023128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re
set_error.2376023128
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.1293075514
Short name T584
Test name
Test status
Simulation time 273248013 ps
CPU time 14.91 seconds
Started Jul 27 04:21:35 PM PDT 24
Finished Jul 27 04:21:50 PM PDT 24
Peak memory 211892 kb
Host smart-625e262e-c796-4b0d-8827-cb621992bd35
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1293075514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1293075514
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.2785905815
Short name T74
Test name
Test status
Simulation time 1503279281 ps
CPU time 14.07 seconds
Started Jul 27 04:23:00 PM PDT 24
Finished Jul 27 04:23:14 PM PDT 24
Peak memory 211468 kb
Host smart-15398eb7-2d89-4efe-ac57-fde5e614d426
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2785905815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.2785905815
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.2921227592
Short name T446
Test name
Test status
Simulation time 3977940589 ps
CPU time 29.35 seconds
Started Jul 27 04:22:03 PM PDT 24
Finished Jul 27 04:22:32 PM PDT 24
Peak memory 203624 kb
Host smart-6932bd3e-0908-4d23-a6f1-9aaad0e7c60d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2921227592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.2921227592
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.3983947605
Short name T886
Test name
Test status
Simulation time 112732796 ps
CPU time 5.4 seconds
Started Jul 27 04:22:03 PM PDT 24
Finished Jul 27 04:22:08 PM PDT 24
Peak memory 203364 kb
Host smart-f987ae98-d55d-4700-b327-9b0ed14cd2d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3983947605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3983947605
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.3967843951
Short name T410
Test name
Test status
Simulation time 913315179 ps
CPU time 23.69 seconds
Started Jul 27 04:22:58 PM PDT 24
Finished Jul 27 04:23:22 PM PDT 24
Peak memory 211456 kb
Host smart-c61881cb-dfb3-4d98-b4bc-f91dcd934979
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3967843951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3967843951
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.1410367796
Short name T132
Test name
Test status
Simulation time 7731763390 ps
CPU time 51.19 seconds
Started Jul 27 04:21:54 PM PDT 24
Finished Jul 27 04:22:45 PM PDT 24
Peak memory 204808 kb
Host smart-729f2b62-411a-469f-b423-18885c9efd29
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410367796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.1410367796
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.4331655
Short name T651
Test name
Test status
Simulation time 30710066324 ps
CPU time 99.74 seconds
Started Jul 27 04:21:50 PM PDT 24
Finished Jul 27 04:23:30 PM PDT 24
Peak memory 211576 kb
Host smart-fc4a4d8c-1bc7-490c-851a-28870e53aa04
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4331655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.4331655
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.1183092375
Short name T314
Test name
Test status
Simulation time 170661366 ps
CPU time 20.92 seconds
Started Jul 27 04:21:50 PM PDT 24
Finished Jul 27 04:22:11 PM PDT 24
Peak memory 211544 kb
Host smart-2620e24f-6923-4d33-828f-52b13a4574ac
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183092375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.1183092375
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.3579678927
Short name T13
Test name
Test status
Simulation time 1515648983 ps
CPU time 19.35 seconds
Started Jul 27 04:22:58 PM PDT 24
Finished Jul 27 04:23:17 PM PDT 24
Peak memory 203336 kb
Host smart-1e48ee5c-f267-46a2-bce8-d9ca9dfd8380
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3579678927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3579678927
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.2477334994
Short name T223
Test name
Test status
Simulation time 267506841 ps
CPU time 3.36 seconds
Started Jul 27 04:23:10 PM PDT 24
Finished Jul 27 04:23:13 PM PDT 24
Peak memory 203044 kb
Host smart-56fbede0-9315-403a-923c-31d5b60fd240
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2477334994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2477334994
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.1635359072
Short name T408
Test name
Test status
Simulation time 8209921633 ps
CPU time 34.44 seconds
Started Jul 27 04:21:53 PM PDT 24
Finished Jul 27 04:22:28 PM PDT 24
Peak memory 203752 kb
Host smart-3ae72c3a-4678-4ebc-a37b-b877afa6b6f3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635359072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1635359072
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.3771152128
Short name T197
Test name
Test status
Simulation time 4243729781 ps
CPU time 34.04 seconds
Started Jul 27 04:23:11 PM PDT 24
Finished Jul 27 04:23:46 PM PDT 24
Peak memory 203120 kb
Host smart-56d5e06e-3bf8-4681-9d39-6d0d357f9881
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3771152128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3771152128
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1160807204
Short name T604
Test name
Test status
Simulation time 24434276 ps
CPU time 1.9 seconds
Started Jul 27 04:23:11 PM PDT 24
Finished Jul 27 04:23:13 PM PDT 24
Peak memory 203032 kb
Host smart-a2aa788f-16f3-48b8-88bf-39ae93049735
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160807204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1160807204
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.3720314200
Short name T106
Test name
Test status
Simulation time 3550978060 ps
CPU time 81.78 seconds
Started Jul 27 04:22:01 PM PDT 24
Finished Jul 27 04:23:23 PM PDT 24
Peak memory 211952 kb
Host smart-0ca13128-a22e-44e5-81b0-24e1d97c36f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3720314200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3720314200
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1398106847
Short name T317
Test name
Test status
Simulation time 1583081011 ps
CPU time 136.48 seconds
Started Jul 27 04:22:02 PM PDT 24
Finished Jul 27 04:24:19 PM PDT 24
Peak memory 209104 kb
Host smart-9ea53fb0-4827-4c24-8eeb-32f5062d2942
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1398106847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1398106847
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.1070122193
Short name T38
Test name
Test status
Simulation time 2819065979 ps
CPU time 273.7 seconds
Started Jul 27 04:22:00 PM PDT 24
Finished Jul 27 04:26:34 PM PDT 24
Peak memory 210440 kb
Host smart-c7cb31cf-a44d-4c57-8eb7-cb620f747cc5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1070122193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran
d_reset.1070122193
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3862627663
Short name T645
Test name
Test status
Simulation time 1128533520 ps
CPU time 188.86 seconds
Started Jul 27 04:22:13 PM PDT 24
Finished Jul 27 04:25:22 PM PDT 24
Peak memory 211496 kb
Host smart-058d9515-9d29-4b64-852e-f5786ae98b0d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3862627663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re
set_error.3862627663
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.133575121
Short name T829
Test name
Test status
Simulation time 411558806 ps
CPU time 21.38 seconds
Started Jul 27 04:22:01 PM PDT 24
Finished Jul 27 04:22:22 PM PDT 24
Peak memory 205140 kb
Host smart-c9e4ed8b-854e-4d25-9da7-568c0daaa3d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=133575121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.133575121
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2135496329
Short name T143
Test name
Test status
Simulation time 833892150 ps
CPU time 28.14 seconds
Started Jul 27 04:22:11 PM PDT 24
Finished Jul 27 04:22:39 PM PDT 24
Peak memory 205264 kb
Host smart-1678f9e0-443e-465e-9e89-db25b8cc7476
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2135496329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2135496329
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1185195931
Short name T402
Test name
Test status
Simulation time 15104013887 ps
CPU time 92.44 seconds
Started Jul 27 04:22:12 PM PDT 24
Finished Jul 27 04:23:44 PM PDT 24
Peak memory 206088 kb
Host smart-d2e59af2-e564-4676-890d-b8a2f3646649
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1185195931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl
ow_rsp.1185195931
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2358192222
Short name T379
Test name
Test status
Simulation time 525265748 ps
CPU time 13.06 seconds
Started Jul 27 04:22:23 PM PDT 24
Finished Jul 27 04:22:36 PM PDT 24
Peak memory 203868 kb
Host smart-f9409cf3-c915-4598-8f43-b5e3790e9a51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2358192222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2358192222
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.2864629609
Short name T562
Test name
Test status
Simulation time 144687033 ps
CPU time 18.96 seconds
Started Jul 27 04:22:23 PM PDT 24
Finished Jul 27 04:22:42 PM PDT 24
Peak memory 203460 kb
Host smart-608cf3b6-c9b8-476d-939e-b736a4d91ee2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2864629609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2864629609
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.132045880
Short name T424
Test name
Test status
Simulation time 314049570 ps
CPU time 20.15 seconds
Started Jul 27 04:22:12 PM PDT 24
Finished Jul 27 04:22:33 PM PDT 24
Peak memory 211504 kb
Host smart-239fa565-b164-46a6-bc18-16d7a3a6bd44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=132045880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.132045880
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.4211525087
Short name T738
Test name
Test status
Simulation time 50697745403 ps
CPU time 147.71 seconds
Started Jul 27 04:22:12 PM PDT 24
Finished Jul 27 04:24:40 PM PDT 24
Peak memory 211536 kb
Host smart-6b7c2e80-749d-4bbc-80af-24398bab93dd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211525087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.4211525087
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2641412212
Short name T895
Test name
Test status
Simulation time 24047051510 ps
CPU time 201.98 seconds
Started Jul 27 04:22:59 PM PDT 24
Finished Jul 27 04:26:21 PM PDT 24
Peak memory 211536 kb
Host smart-9d601b54-42b3-4961-bc25-6b5c22fb6029
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2641412212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2641412212
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.2963470457
Short name T229
Test name
Test status
Simulation time 89480080 ps
CPU time 10.1 seconds
Started Jul 27 04:22:16 PM PDT 24
Finished Jul 27 04:22:26 PM PDT 24
Peak memory 211448 kb
Host smart-04faa0ad-0c98-456b-9b6c-dbf8f68c7eee
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963470457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.2963470457
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.3426977458
Short name T122
Test name
Test status
Simulation time 1220633985 ps
CPU time 25.05 seconds
Started Jul 27 04:22:14 PM PDT 24
Finished Jul 27 04:22:40 PM PDT 24
Peak memory 211468 kb
Host smart-6a1f61b0-f8cc-48e9-bf74-9222bcb5f176
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3426977458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3426977458
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.3612233897
Short name T658
Test name
Test status
Simulation time 153675800 ps
CPU time 3.66 seconds
Started Jul 27 04:22:11 PM PDT 24
Finished Jul 27 04:22:15 PM PDT 24
Peak memory 203300 kb
Host smart-d3f19837-fb33-4227-bd1a-708b9d6f268b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3612233897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3612233897
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.967169098
Short name T246
Test name
Test status
Simulation time 24506876928 ps
CPU time 44.62 seconds
Started Jul 27 04:22:12 PM PDT 24
Finished Jul 27 04:22:57 PM PDT 24
Peak memory 203368 kb
Host smart-7cef46f6-a444-433d-90ae-87ea9d06beaa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=967169098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.967169098
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.565555106
Short name T606
Test name
Test status
Simulation time 8777529499 ps
CPU time 31.84 seconds
Started Jul 27 04:22:11 PM PDT 24
Finished Jul 27 04:22:43 PM PDT 24
Peak memory 203348 kb
Host smart-eb0a3ede-68fa-4ce4-b0b8-0ac7a2178a4e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=565555106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.565555106
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3745416479
Short name T367
Test name
Test status
Simulation time 25663398 ps
CPU time 2.2 seconds
Started Jul 27 04:22:12 PM PDT 24
Finished Jul 27 04:22:14 PM PDT 24
Peak memory 203284 kb
Host smart-60920f48-355d-4118-a62b-e1c3d2172f48
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745416479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3745416479
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.4100570045
Short name T111
Test name
Test status
Simulation time 27469432545 ps
CPU time 249.23 seconds
Started Jul 27 04:22:23 PM PDT 24
Finished Jul 27 04:26:32 PM PDT 24
Peak memory 206952 kb
Host smart-c9f82690-22e5-4c8f-adda-3c1c7d18e1fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4100570045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.4100570045
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.1891811125
Short name T451
Test name
Test status
Simulation time 1197028975 ps
CPU time 40.7 seconds
Started Jul 27 04:22:24 PM PDT 24
Finished Jul 27 04:23:05 PM PDT 24
Peak memory 204612 kb
Host smart-d0ff4437-a042-4770-bef3-bfdd3e4c3049
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1891811125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1891811125
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.1198560924
Short name T25
Test name
Test status
Simulation time 925172594 ps
CPU time 355.04 seconds
Started Jul 27 04:22:25 PM PDT 24
Finished Jul 27 04:28:20 PM PDT 24
Peak memory 211496 kb
Host smart-1c4735a4-e786-4195-a3e7-a18970d00655
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1198560924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran
d_reset.1198560924
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.2240033264
Short name T649
Test name
Test status
Simulation time 516092877 ps
CPU time 176.74 seconds
Started Jul 27 04:22:26 PM PDT 24
Finished Jul 27 04:25:23 PM PDT 24
Peak memory 211360 kb
Host smart-263608c0-d391-454b-b3a6-1679769baac8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2240033264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re
set_error.2240033264
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.3676956545
Short name T288
Test name
Test status
Simulation time 134529636 ps
CPU time 14.76 seconds
Started Jul 27 04:22:25 PM PDT 24
Finished Jul 27 04:22:40 PM PDT 24
Peak memory 211336 kb
Host smart-47627cef-02be-4bed-9ad4-c40377d781c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3676956545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3676956545
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3909887802
Short name T723
Test name
Test status
Simulation time 435913886 ps
CPU time 14.19 seconds
Started Jul 27 04:22:35 PM PDT 24
Finished Jul 27 04:22:49 PM PDT 24
Peak memory 211356 kb
Host smart-17320b4e-e1d4-47b0-bbe7-bdb874164355
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3909887802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3909887802
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.1272405157
Short name T293
Test name
Test status
Simulation time 163678159 ps
CPU time 16.84 seconds
Started Jul 27 04:22:55 PM PDT 24
Finished Jul 27 04:23:12 PM PDT 24
Peak memory 203220 kb
Host smart-214d5ff3-d65d-4fb3-b0bb-2b38b6dd5280
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1272405157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.1272405157
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.1955457103
Short name T302
Test name
Test status
Simulation time 175995617 ps
CPU time 5.35 seconds
Started Jul 27 04:22:55 PM PDT 24
Finished Jul 27 04:23:01 PM PDT 24
Peak memory 203188 kb
Host smart-16db7aaf-4f76-4cfd-b1f1-ca1a06548796
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1955457103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1955457103
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.1989467687
Short name T235
Test name
Test status
Simulation time 1017813194 ps
CPU time 35.29 seconds
Started Jul 27 04:22:24 PM PDT 24
Finished Jul 27 04:23:00 PM PDT 24
Peak memory 211456 kb
Host smart-710743fa-0bd2-439e-891d-bbc8ce83f71c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1989467687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.1989467687
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.1671899087
Short name T176
Test name
Test status
Simulation time 14874921273 ps
CPU time 82.41 seconds
Started Jul 27 04:22:36 PM PDT 24
Finished Jul 27 04:23:59 PM PDT 24
Peak memory 211512 kb
Host smart-3cc4ecd6-8054-4890-9cfd-33b454f3b6a8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671899087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1671899087
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.4067026802
Short name T663
Test name
Test status
Simulation time 1459048164 ps
CPU time 12.81 seconds
Started Jul 27 04:22:34 PM PDT 24
Finished Jul 27 04:22:47 PM PDT 24
Peak memory 203340 kb
Host smart-f59511bb-ff44-4ce2-937e-ae792c630487
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4067026802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.4067026802
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.4118653073
Short name T450
Test name
Test status
Simulation time 58304122 ps
CPU time 4.29 seconds
Started Jul 27 04:22:34 PM PDT 24
Finished Jul 27 04:22:38 PM PDT 24
Peak memory 211888 kb
Host smart-01a249db-a52f-46fd-94f8-ce595ab715a3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118653073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.4118653073
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.17884910
Short name T399
Test name
Test status
Simulation time 251108695 ps
CPU time 4.32 seconds
Started Jul 27 04:22:33 PM PDT 24
Finished Jul 27 04:22:38 PM PDT 24
Peak memory 203440 kb
Host smart-65167333-a808-454d-add5-53a1713195cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=17884910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.17884910
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.2782888667
Short name T41
Test name
Test status
Simulation time 224017783 ps
CPU time 4.01 seconds
Started Jul 27 04:22:22 PM PDT 24
Finished Jul 27 04:22:27 PM PDT 24
Peak memory 203448 kb
Host smart-183656e1-aa60-4119-8081-9bf412b2e108
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2782888667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2782888667
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.3543840646
Short name T202
Test name
Test status
Simulation time 9395268636 ps
CPU time 29.62 seconds
Started Jul 27 04:22:23 PM PDT 24
Finished Jul 27 04:22:53 PM PDT 24
Peak memory 203372 kb
Host smart-944ac791-ff64-4f0d-b0ed-a82b2e5f7431
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543840646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3543840646
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.1877523394
Short name T880
Test name
Test status
Simulation time 6654123232 ps
CPU time 27.88 seconds
Started Jul 27 04:22:24 PM PDT 24
Finished Jul 27 04:22:52 PM PDT 24
Peak memory 203348 kb
Host smart-91ecffa6-a4be-4553-a275-4ee884856fb5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1877523394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1877523394
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.3339477736
Short name T393
Test name
Test status
Simulation time 32716366 ps
CPU time 2.39 seconds
Started Jul 27 04:22:25 PM PDT 24
Finished Jul 27 04:22:27 PM PDT 24
Peak memory 203284 kb
Host smart-20fba65b-68d9-4306-8a2b-2ed12440d389
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339477736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.3339477736
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.3051704470
Short name T472
Test name
Test status
Simulation time 389944098 ps
CPU time 55.76 seconds
Started Jul 27 04:22:55 PM PDT 24
Finished Jul 27 04:23:51 PM PDT 24
Peak memory 207264 kb
Host smart-1b189d6b-8682-40d4-bd0b-defe4f355eb7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3051704470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3051704470
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1871405454
Short name T650
Test name
Test status
Simulation time 5220969245 ps
CPU time 87.81 seconds
Started Jul 27 04:22:53 PM PDT 24
Finished Jul 27 04:24:21 PM PDT 24
Peak memory 204960 kb
Host smart-09eefe7f-fbe2-4134-bf1d-f40e61ee88f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1871405454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1871405454
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.3563609135
Short name T154
Test name
Test status
Simulation time 880478336 ps
CPU time 265.19 seconds
Started Jul 27 04:22:54 PM PDT 24
Finished Jul 27 04:27:19 PM PDT 24
Peak memory 208664 kb
Host smart-f25fa793-25e9-4892-9ab9-5bbcd651ac0e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3563609135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran
d_reset.3563609135
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.1308297512
Short name T523
Test name
Test status
Simulation time 3003031478 ps
CPU time 146.13 seconds
Started Jul 27 04:22:54 PM PDT 24
Finished Jul 27 04:25:21 PM PDT 24
Peak memory 211116 kb
Host smart-0f5cc360-be66-4d61-afb1-f54f64c314df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1308297512 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re
set_error.1308297512
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.3170490179
Short name T671
Test name
Test status
Simulation time 131712426 ps
CPU time 19.16 seconds
Started Jul 27 04:22:55 PM PDT 24
Finished Jul 27 04:23:14 PM PDT 24
Peak memory 211220 kb
Host smart-b87a9e2a-d353-4ce8-b261-09721ef0e9b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3170490179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3170490179
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.4098975490
Short name T104
Test name
Test status
Simulation time 2267523220 ps
CPU time 60.76 seconds
Started Jul 27 04:23:04 PM PDT 24
Finished Jul 27 04:24:05 PM PDT 24
Peak memory 206380 kb
Host smart-c0063b06-2d09-45c0-962e-afdf7adace74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4098975490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.4098975490
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.4267706691
Short name T706
Test name
Test status
Simulation time 8430010137 ps
CPU time 76.59 seconds
Started Jul 27 04:23:04 PM PDT 24
Finished Jul 27 04:24:21 PM PDT 24
Peak memory 204584 kb
Host smart-da24e01d-fe42-40dd-ac9a-928e0bb4988b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4267706691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl
ow_rsp.4267706691
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1132773356
Short name T532
Test name
Test status
Simulation time 121657786 ps
CPU time 13.33 seconds
Started Jul 27 04:23:02 PM PDT 24
Finished Jul 27 04:23:16 PM PDT 24
Peak memory 204004 kb
Host smart-eaaf3593-90c8-477f-aefb-eb24ce3ae272
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1132773356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1132773356
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.2217118832
Short name T736
Test name
Test status
Simulation time 182528462 ps
CPU time 17.67 seconds
Started Jul 27 04:23:06 PM PDT 24
Finished Jul 27 04:23:24 PM PDT 24
Peak memory 203408 kb
Host smart-4897ecb9-970b-4568-8828-3cf9153f3958
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2217118832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2217118832
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.1064485865
Short name T855
Test name
Test status
Simulation time 360157133 ps
CPU time 4.57 seconds
Started Jul 27 04:22:54 PM PDT 24
Finished Jul 27 04:22:58 PM PDT 24
Peak memory 204324 kb
Host smart-9d6d32e3-a546-40f7-8775-b42dbdbe5d90
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1064485865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.1064485865
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.1633324690
Short name T610
Test name
Test status
Simulation time 53341323342 ps
CPU time 183.11 seconds
Started Jul 27 04:23:03 PM PDT 24
Finished Jul 27 04:26:06 PM PDT 24
Peak memory 211548 kb
Host smart-43794f8a-4b37-4514-b5ff-61ab6041d925
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633324690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1633324690
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.3324897561
Short name T514
Test name
Test status
Simulation time 44337559778 ps
CPU time 179.12 seconds
Started Jul 27 04:23:02 PM PDT 24
Finished Jul 27 04:26:02 PM PDT 24
Peak memory 211524 kb
Host smart-fd6909cf-618b-4ab0-9290-698b84ac8047
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3324897561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3324897561
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.3235536777
Short name T819
Test name
Test status
Simulation time 171058783 ps
CPU time 20.17 seconds
Started Jul 27 04:23:04 PM PDT 24
Finished Jul 27 04:23:24 PM PDT 24
Peak memory 204656 kb
Host smart-b3b92004-95e0-48f7-8450-29a661905833
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235536777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3235536777
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.1296174472
Short name T868
Test name
Test status
Simulation time 712392700 ps
CPU time 13.39 seconds
Started Jul 27 04:23:07 PM PDT 24
Finished Jul 27 04:23:21 PM PDT 24
Peak memory 203356 kb
Host smart-7d46ffec-883b-4495-a31e-d86d983b9d4c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1296174472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1296174472
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.3109836607
Short name T204
Test name
Test status
Simulation time 126474480 ps
CPU time 2.1 seconds
Started Jul 27 04:22:54 PM PDT 24
Finished Jul 27 04:22:56 PM PDT 24
Peak memory 203200 kb
Host smart-0bb8427f-1b2e-4e34-8f4b-4defc34369b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3109836607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3109836607
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.620911604
Short name T701
Test name
Test status
Simulation time 8427308512 ps
CPU time 23.85 seconds
Started Jul 27 04:22:55 PM PDT 24
Finished Jul 27 04:23:19 PM PDT 24
Peak memory 203348 kb
Host smart-d5a725ce-36be-4137-ba7d-8498b1145eac
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=620911604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.620911604
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.710548238
Short name T98
Test name
Test status
Simulation time 14600392391 ps
CPU time 32.33 seconds
Started Jul 27 04:22:53 PM PDT 24
Finished Jul 27 04:23:25 PM PDT 24
Peak memory 203276 kb
Host smart-354fbeac-6822-4154-832d-4b72848af2a3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=710548238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.710548238
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.2410207387
Short name T91
Test name
Test status
Simulation time 50566228 ps
CPU time 2.18 seconds
Started Jul 27 04:22:54 PM PDT 24
Finished Jul 27 04:22:56 PM PDT 24
Peak memory 203272 kb
Host smart-d1a28d9e-6ab5-4be8-9297-ebae552ce6b1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410207387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.2410207387
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.2009313436
Short name T809
Test name
Test status
Simulation time 12765762301 ps
CPU time 273.88 seconds
Started Jul 27 04:23:06 PM PDT 24
Finished Jul 27 04:27:40 PM PDT 24
Peak memory 211788 kb
Host smart-afd91d14-ad30-472d-be5c-0d463c5bcf60
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2009313436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2009313436
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1320484054
Short name T608
Test name
Test status
Simulation time 467183688 ps
CPU time 28.72 seconds
Started Jul 27 04:23:04 PM PDT 24
Finished Jul 27 04:23:33 PM PDT 24
Peak memory 204304 kb
Host smart-922956a7-1452-46db-9cd4-70a0074b7e52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1320484054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1320484054
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.4281440106
Short name T426
Test name
Test status
Simulation time 271652782 ps
CPU time 60.38 seconds
Started Jul 27 04:23:07 PM PDT 24
Finished Jul 27 04:24:07 PM PDT 24
Peak memory 207536 kb
Host smart-61603356-739c-4595-9ea4-1de71d1f0076
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4281440106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran
d_reset.4281440106
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2655147244
Short name T885
Test name
Test status
Simulation time 477685375 ps
CPU time 140.06 seconds
Started Jul 27 04:23:09 PM PDT 24
Finished Jul 27 04:25:29 PM PDT 24
Peak memory 210956 kb
Host smart-e383b112-ad88-4575-814c-2b43d6595147
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2655147244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re
set_error.2655147244
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.4152317348
Short name T727
Test name
Test status
Simulation time 792097232 ps
CPU time 22.22 seconds
Started Jul 27 04:23:04 PM PDT 24
Finished Jul 27 04:23:27 PM PDT 24
Peak memory 211464 kb
Host smart-ad7153b8-947a-4629-836b-fcae2b1f1e3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4152317348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.4152317348
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.3774204745
Short name T135
Test name
Test status
Simulation time 3572871805 ps
CPU time 72.13 seconds
Started Jul 27 04:23:16 PM PDT 24
Finished Jul 27 04:24:28 PM PDT 24
Peak memory 211480 kb
Host smart-1b7ac60b-e868-4e85-9c50-79e8caba1c3c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3774204745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.3774204745
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.204614928
Short name T890
Test name
Test status
Simulation time 39889665500 ps
CPU time 276.27 seconds
Started Jul 27 04:23:04 PM PDT 24
Finished Jul 27 04:27:41 PM PDT 24
Peak memory 206756 kb
Host smart-b154e8d0-a225-4a48-80e7-3f8619aa45fa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=204614928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slo
w_rsp.204614928
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.78853014
Short name T862
Test name
Test status
Simulation time 1481220857 ps
CPU time 9.91 seconds
Started Jul 27 04:23:11 PM PDT 24
Finished Jul 27 04:23:21 PM PDT 24
Peak memory 203484 kb
Host smart-11fb6af0-25c1-49ce-b7e1-4e9e71a180f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=78853014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.78853014
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.1297900043
Short name T113
Test name
Test status
Simulation time 218075210 ps
CPU time 22.46 seconds
Started Jul 27 04:23:04 PM PDT 24
Finished Jul 27 04:23:27 PM PDT 24
Peak memory 203216 kb
Host smart-902c2a77-2e85-4c3a-8fd1-d798605de142
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1297900043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1297900043
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.3699985373
Short name T412
Test name
Test status
Simulation time 148805712 ps
CPU time 12.4 seconds
Started Jul 27 04:23:09 PM PDT 24
Finished Jul 27 04:23:22 PM PDT 24
Peak memory 211348 kb
Host smart-c34c35e7-7210-48b1-ae69-d0b23b617eea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3699985373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.3699985373
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.2518487120
Short name T260
Test name
Test status
Simulation time 159498095384 ps
CPU time 315.45 seconds
Started Jul 27 04:23:08 PM PDT 24
Finished Jul 27 04:28:24 PM PDT 24
Peak memory 205476 kb
Host smart-557ce775-651b-4bcf-a9a5-f7c4f878b2f4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518487120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2518487120
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3730825851
Short name T292
Test name
Test status
Simulation time 39164295667 ps
CPU time 182.5 seconds
Started Jul 27 04:23:02 PM PDT 24
Finished Jul 27 04:26:05 PM PDT 24
Peak memory 211552 kb
Host smart-f02282ef-9a22-4b81-b8b3-c3609b6a73c7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3730825851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3730825851
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.1409025802
Short name T458
Test name
Test status
Simulation time 284208323 ps
CPU time 22.29 seconds
Started Jul 27 04:23:03 PM PDT 24
Finished Jul 27 04:23:26 PM PDT 24
Peak memory 211480 kb
Host smart-b27f211b-a462-43cf-b013-7695caeedb6c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409025802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1409025802
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.4232652760
Short name T494
Test name
Test status
Simulation time 985577988 ps
CPU time 15.23 seconds
Started Jul 27 04:23:16 PM PDT 24
Finished Jul 27 04:23:31 PM PDT 24
Peak memory 203668 kb
Host smart-600015c6-23e1-4d06-9558-b753c8afe897
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4232652760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.4232652760
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.3417085757
Short name T636
Test name
Test status
Simulation time 146012106 ps
CPU time 2.34 seconds
Started Jul 27 04:23:05 PM PDT 24
Finished Jul 27 04:23:07 PM PDT 24
Peak memory 203276 kb
Host smart-70dad573-0027-46e5-a4d3-b3e2e442fd42
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3417085757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3417085757
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1125791541
Short name T243
Test name
Test status
Simulation time 28417264331 ps
CPU time 49.43 seconds
Started Jul 27 04:23:07 PM PDT 24
Finished Jul 27 04:23:57 PM PDT 24
Peak memory 203348 kb
Host smart-87f140fb-4b49-4a6e-8f97-254b94e8c575
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125791541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1125791541
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.1960636350
Short name T363
Test name
Test status
Simulation time 16461193704 ps
CPU time 38.87 seconds
Started Jul 27 04:23:01 PM PDT 24
Finished Jul 27 04:23:40 PM PDT 24
Peak memory 203368 kb
Host smart-f6e1a2af-4cfb-47ba-8a57-1dd9cf76ffec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1960636350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1960636350
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.3736935340
Short name T571
Test name
Test status
Simulation time 45885338 ps
CPU time 2.27 seconds
Started Jul 27 04:23:07 PM PDT 24
Finished Jul 27 04:23:09 PM PDT 24
Peak memory 203272 kb
Host smart-48c816a5-0adf-4d0a-b4be-61b23c85c2f9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736935340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.3736935340
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.1771939009
Short name T765
Test name
Test status
Simulation time 870276907 ps
CPU time 91.53 seconds
Started Jul 27 04:23:02 PM PDT 24
Finished Jul 27 04:24:34 PM PDT 24
Peak memory 208400 kb
Host smart-2ec0b0c1-4e44-4309-85c1-6b398a6d91cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1771939009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1771939009
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2614186801
Short name T382
Test name
Test status
Simulation time 6425691025 ps
CPU time 113.56 seconds
Started Jul 27 04:23:06 PM PDT 24
Finished Jul 27 04:25:00 PM PDT 24
Peak memory 207352 kb
Host smart-e6c081aa-d557-4bba-bf16-a45cea9a638b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2614186801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2614186801
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.2963964356
Short name T476
Test name
Test status
Simulation time 1161031603 ps
CPU time 173.44 seconds
Started Jul 27 04:23:09 PM PDT 24
Finished Jul 27 04:26:02 PM PDT 24
Peak memory 209576 kb
Host smart-58de8c3a-6cf9-49fb-8970-fdb42ea86646
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2963964356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran
d_reset.2963964356
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.916339921
Short name T814
Test name
Test status
Simulation time 8543809307 ps
CPU time 402.69 seconds
Started Jul 27 04:23:09 PM PDT 24
Finished Jul 27 04:29:52 PM PDT 24
Peak memory 219760 kb
Host smart-7e078440-1af7-4002-932e-078a0374a9af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=916339921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_res
et_error.916339921
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.3612601174
Short name T73
Test name
Test status
Simulation time 83623931 ps
CPU time 2.34 seconds
Started Jul 27 04:23:04 PM PDT 24
Finished Jul 27 04:23:06 PM PDT 24
Peak memory 203312 kb
Host smart-c6db3ecb-4dd9-4a9c-9586-0d2c19e36b99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3612601174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3612601174
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.3026465070
Short name T535
Test name
Test status
Simulation time 28071203422 ps
CPU time 218.19 seconds
Started Jul 27 04:23:03 PM PDT 24
Finished Jul 27 04:26:42 PM PDT 24
Peak memory 211524 kb
Host smart-decb339b-4666-4a2d-a566-e7ef4d2261bf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3026465070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl
ow_rsp.3026465070
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2973894469
Short name T309
Test name
Test status
Simulation time 492162871 ps
CPU time 14.49 seconds
Started Jul 27 04:23:03 PM PDT 24
Finished Jul 27 04:23:18 PM PDT 24
Peak memory 203312 kb
Host smart-70a6cbdf-cceb-414d-aabf-30caa5eb3830
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2973894469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2973894469
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.3090802976
Short name T14
Test name
Test status
Simulation time 150276197 ps
CPU time 3.96 seconds
Started Jul 27 04:23:03 PM PDT 24
Finished Jul 27 04:23:07 PM PDT 24
Peak memory 203308 kb
Host smart-ea8960b4-aacd-45c1-8289-4c4c8eaebb3f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3090802976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3090802976
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.4054338453
Short name T401
Test name
Test status
Simulation time 64064321 ps
CPU time 8.78 seconds
Started Jul 27 04:23:07 PM PDT 24
Finished Jul 27 04:23:16 PM PDT 24
Peak memory 211524 kb
Host smart-889655a3-bff7-4a4b-a247-df9b356f5437
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4054338453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.4054338453
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.3251008823
Short name T345
Test name
Test status
Simulation time 5000798117 ps
CPU time 23.26 seconds
Started Jul 27 04:23:04 PM PDT 24
Finished Jul 27 04:23:27 PM PDT 24
Peak memory 211512 kb
Host smart-0212e483-36a0-4aaf-b4e9-ceb2618a473a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251008823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3251008823
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.991435980
Short name T416
Test name
Test status
Simulation time 23097742855 ps
CPU time 159.15 seconds
Started Jul 27 04:23:07 PM PDT 24
Finished Jul 27 04:25:47 PM PDT 24
Peak memory 204968 kb
Host smart-9d798d55-8140-45dd-9e68-db8f174ef304
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=991435980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.991435980
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.3902615489
Short name T326
Test name
Test status
Simulation time 351355469 ps
CPU time 22.51 seconds
Started Jul 27 04:23:09 PM PDT 24
Finished Jul 27 04:23:31 PM PDT 24
Peak memory 211440 kb
Host smart-c666b754-a00d-44eb-87b5-e244912354c3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902615489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3902615489
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.1840731238
Short name T648
Test name
Test status
Simulation time 405454649 ps
CPU time 8.64 seconds
Started Jul 27 04:23:05 PM PDT 24
Finished Jul 27 04:23:14 PM PDT 24
Peak memory 203268 kb
Host smart-cca53fcf-efa0-46fc-8a1c-7fa761a27433
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1840731238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1840731238
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.2316526405
Short name T417
Test name
Test status
Simulation time 157312359 ps
CPU time 3.51 seconds
Started Jul 27 04:23:10 PM PDT 24
Finished Jul 27 04:23:13 PM PDT 24
Peak memory 203200 kb
Host smart-e0bc74b2-6a92-4d41-9e09-b31b12df5172
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2316526405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2316526405
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.2010984973
Short name T57
Test name
Test status
Simulation time 4003731552 ps
CPU time 23 seconds
Started Jul 27 04:23:09 PM PDT 24
Finished Jul 27 04:23:32 PM PDT 24
Peak memory 203344 kb
Host smart-185f0743-77aa-48a4-8637-2af0afc894bf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010984973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2010984973
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.2877879340
Short name T462
Test name
Test status
Simulation time 3200151826 ps
CPU time 23.14 seconds
Started Jul 27 04:23:02 PM PDT 24
Finished Jul 27 04:23:25 PM PDT 24
Peak memory 203388 kb
Host smart-de682ea6-e3e0-487d-bac6-35a3d5767905
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2877879340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2877879340
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.2146272105
Short name T332
Test name
Test status
Simulation time 21408132 ps
CPU time 1.98 seconds
Started Jul 27 04:23:06 PM PDT 24
Finished Jul 27 04:23:08 PM PDT 24
Peak memory 203288 kb
Host smart-9322d050-f132-4eac-853c-23ee7adf79c8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146272105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.2146272105
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.3344415999
Short name T641
Test name
Test status
Simulation time 796557823 ps
CPU time 81.97 seconds
Started Jul 27 04:23:06 PM PDT 24
Finished Jul 27 04:24:28 PM PDT 24
Peak memory 205792 kb
Host smart-b986db8a-32bc-4a74-a2b6-408c783efa60
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3344415999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3344415999
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3741165119
Short name T768
Test name
Test status
Simulation time 8625828523 ps
CPU time 106.94 seconds
Started Jul 27 04:23:16 PM PDT 24
Finished Jul 27 04:25:03 PM PDT 24
Peak memory 211464 kb
Host smart-7c305bad-fff5-4840-bbc8-c6b3bf5b591d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3741165119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3741165119
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2186171963
Short name T78
Test name
Test status
Simulation time 969062112 ps
CPU time 251.22 seconds
Started Jul 27 04:23:10 PM PDT 24
Finished Jul 27 04:27:22 PM PDT 24
Peak memory 208264 kb
Host smart-c9f2f142-a1f0-4a11-8795-fba8356aebd2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2186171963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran
d_reset.2186171963
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1063554609
Short name T33
Test name
Test status
Simulation time 954151877 ps
CPU time 216.6 seconds
Started Jul 27 04:23:09 PM PDT 24
Finished Jul 27 04:26:45 PM PDT 24
Peak memory 211420 kb
Host smart-fdbf8e96-f462-4e04-b5c1-37203ac23985
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1063554609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re
set_error.1063554609
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.3429322691
Short name T899
Test name
Test status
Simulation time 91451757 ps
CPU time 9.36 seconds
Started Jul 27 04:23:13 PM PDT 24
Finished Jul 27 04:23:23 PM PDT 24
Peak memory 204796 kb
Host smart-c217c63e-5f83-4480-9feb-3a6cc7b26b06
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3429322691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3429322691
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.1173222813
Short name T103
Test name
Test status
Simulation time 2538666935 ps
CPU time 50.28 seconds
Started Jul 27 04:23:06 PM PDT 24
Finished Jul 27 04:23:57 PM PDT 24
Peak memory 206324 kb
Host smart-e242d37b-91ba-4580-a2f0-cc5dee70c707
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1173222813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1173222813
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.528139819
Short name T807
Test name
Test status
Simulation time 79576262052 ps
CPU time 464.12 seconds
Started Jul 27 04:23:07 PM PDT 24
Finished Jul 27 04:30:52 PM PDT 24
Peak memory 207412 kb
Host smart-c9e6dc40-269b-48c8-bdb8-f93907157896
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=528139819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slo
w_rsp.528139819
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.3369408709
Short name T751
Test name
Test status
Simulation time 1072842010 ps
CPU time 20.44 seconds
Started Jul 27 04:23:10 PM PDT 24
Finished Jul 27 04:23:30 PM PDT 24
Peak memory 203272 kb
Host smart-00ece260-851d-4182-8a95-e7b20ec1f9c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3369408709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.3369408709
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.3037986920
Short name T678
Test name
Test status
Simulation time 1655502104 ps
CPU time 29.33 seconds
Started Jul 27 04:23:16 PM PDT 24
Finished Jul 27 04:23:45 PM PDT 24
Peak memory 203192 kb
Host smart-a3e6405d-5349-4605-aa06-2fffedc1b10e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3037986920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3037986920
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.3176595432
Short name T801
Test name
Test status
Simulation time 639342710 ps
CPU time 9.35 seconds
Started Jul 27 04:23:09 PM PDT 24
Finished Jul 27 04:23:19 PM PDT 24
Peak memory 204452 kb
Host smart-0af7cc63-fa6f-4094-9e82-dc5b6f32d752
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3176595432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.3176595432
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2347686105
Short name T793
Test name
Test status
Simulation time 70218330772 ps
CPU time 149.67 seconds
Started Jul 27 04:23:06 PM PDT 24
Finished Jul 27 04:25:35 PM PDT 24
Peak memory 211536 kb
Host smart-9f78aa97-aaa4-4166-9f8c-8805d2fa3f55
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347686105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2347686105
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1391497779
Short name T285
Test name
Test status
Simulation time 51622683206 ps
CPU time 232.24 seconds
Started Jul 27 04:23:09 PM PDT 24
Finished Jul 27 04:27:01 PM PDT 24
Peak memory 211480 kb
Host smart-47e49c2a-b355-4b5f-ab60-9a666674d2fe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1391497779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1391497779
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.3514665885
Short name T45
Test name
Test status
Simulation time 120623690 ps
CPU time 16.58 seconds
Started Jul 27 04:23:04 PM PDT 24
Finished Jul 27 04:23:21 PM PDT 24
Peak memory 211524 kb
Host smart-4d7446ff-2983-4e1f-85aa-c3625cc03193
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514665885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.3514665885
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.4265468720
Short name T42
Test name
Test status
Simulation time 875713225 ps
CPU time 16.68 seconds
Started Jul 27 04:23:03 PM PDT 24
Finished Jul 27 04:23:20 PM PDT 24
Peak memory 203996 kb
Host smart-baa01e44-ee76-452f-bdfa-553a3240df4c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4265468720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.4265468720
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.2229046873
Short name T53
Test name
Test status
Simulation time 134487090 ps
CPU time 3.34 seconds
Started Jul 27 04:23:16 PM PDT 24
Finished Jul 27 04:23:19 PM PDT 24
Peak memory 203128 kb
Host smart-385a498d-7b16-4f63-b194-aee804ddb8c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2229046873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2229046873
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.1014551253
Short name T821
Test name
Test status
Simulation time 13924755928 ps
CPU time 39.56 seconds
Started Jul 27 04:23:14 PM PDT 24
Finished Jul 27 04:23:54 PM PDT 24
Peak memory 203356 kb
Host smart-417d37ec-1f0c-4708-b57c-6cbff25aa356
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014551253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1014551253
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1498697783
Short name T857
Test name
Test status
Simulation time 5245589491 ps
CPU time 28.17 seconds
Started Jul 27 04:23:06 PM PDT 24
Finished Jul 27 04:23:34 PM PDT 24
Peak memory 203280 kb
Host smart-d1d85811-ff24-449f-a519-5f99e014de97
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1498697783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1498697783
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.161874212
Short name T747
Test name
Test status
Simulation time 34837725 ps
CPU time 2.3 seconds
Started Jul 27 04:23:11 PM PDT 24
Finished Jul 27 04:23:13 PM PDT 24
Peak memory 203168 kb
Host smart-42e87999-ff7f-4c7f-8241-56d0f7f4fce2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161874212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.161874212
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.1721901787
Short name T359
Test name
Test status
Simulation time 16204895087 ps
CPU time 232.57 seconds
Started Jul 27 04:23:14 PM PDT 24
Finished Jul 27 04:27:08 PM PDT 24
Peak memory 210448 kb
Host smart-3e0de5e4-e183-46c6-801d-e0f597b03bb2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1721901787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1721901787
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.978942250
Short name T383
Test name
Test status
Simulation time 31202274 ps
CPU time 2.14 seconds
Started Jul 27 04:23:14 PM PDT 24
Finished Jul 27 04:23:16 PM PDT 24
Peak memory 203284 kb
Host smart-3722ebbb-f042-4066-a955-52be9bfc1152
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=978942250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.978942250
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.2937672448
Short name T372
Test name
Test status
Simulation time 737431204 ps
CPU time 282.25 seconds
Started Jul 27 04:23:09 PM PDT 24
Finished Jul 27 04:27:52 PM PDT 24
Peak memory 208160 kb
Host smart-c074e8ff-5c26-4b21-a6f4-97d37f0969e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2937672448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran
d_reset.2937672448
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.1943311693
Short name T24
Test name
Test status
Simulation time 1947942564 ps
CPU time 221.8 seconds
Started Jul 27 04:23:09 PM PDT 24
Finished Jul 27 04:26:51 PM PDT 24
Peak memory 219664 kb
Host smart-0bc06d46-73b4-4a42-a721-07c0fe9c5295
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1943311693 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re
set_error.1943311693
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.3416356200
Short name T374
Test name
Test status
Simulation time 820086248 ps
CPU time 24.31 seconds
Started Jul 27 04:23:10 PM PDT 24
Finished Jul 27 04:23:34 PM PDT 24
Peak memory 204808 kb
Host smart-24d2b67b-f24d-4ede-9be2-4f0683eff818
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3416356200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3416356200
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.1357305093
Short name T239
Test name
Test status
Simulation time 966523998 ps
CPU time 18.36 seconds
Started Jul 27 04:23:04 PM PDT 24
Finished Jul 27 04:23:22 PM PDT 24
Peak memory 210244 kb
Host smart-0b82e5af-7da9-4ae1-b42b-bcc058d4c9e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1357305093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1357305093
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.3811447946
Short name T142
Test name
Test status
Simulation time 23444344483 ps
CPU time 110.38 seconds
Started Jul 27 04:23:18 PM PDT 24
Finished Jul 27 04:25:08 PM PDT 24
Peak memory 211484 kb
Host smart-3262d186-6c30-407e-978e-7c7749a64e1f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3811447946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo
w_rsp.3811447946
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.30501963
Short name T319
Test name
Test status
Simulation time 95983093 ps
CPU time 12.07 seconds
Started Jul 27 04:20:15 PM PDT 24
Finished Jul 27 04:20:28 PM PDT 24
Peak memory 203292 kb
Host smart-b8017275-e887-423c-ba3d-2e47f2c6d8a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=30501963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.30501963
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.1433486422
Short name T30
Test name
Test status
Simulation time 672825954 ps
CPU time 12.99 seconds
Started Jul 27 04:18:12 PM PDT 24
Finished Jul 27 04:18:25 PM PDT 24
Peak memory 203308 kb
Host smart-8c3d501d-3915-4cf3-a23b-4a8a6ed9e28a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1433486422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1433486422
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.2777104132
Short name T117
Test name
Test status
Simulation time 151115470 ps
CPU time 10.21 seconds
Started Jul 27 04:19:43 PM PDT 24
Finished Jul 27 04:19:53 PM PDT 24
Peak memory 211460 kb
Host smart-cef97916-e176-4a8d-8dfa-5d17250f4b17
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2777104132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.2777104132
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.2943210636
Short name T475
Test name
Test status
Simulation time 35028581728 ps
CPU time 180.62 seconds
Started Jul 27 04:22:23 PM PDT 24
Finished Jul 27 04:25:23 PM PDT 24
Peak memory 211316 kb
Host smart-0580061f-5e6c-4688-be71-6b70a6bcdd0a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943210636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2943210636
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.2086023321
Short name T572
Test name
Test status
Simulation time 32748053033 ps
CPU time 194.22 seconds
Started Jul 27 04:18:12 PM PDT 24
Finished Jul 27 04:21:26 PM PDT 24
Peak memory 211520 kb
Host smart-78254b3c-abd1-4e4e-a7c7-e6235bd4731f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2086023321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.2086023321
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.4057229327
Short name T538
Test name
Test status
Simulation time 430472033 ps
CPU time 15.18 seconds
Started Jul 27 04:22:44 PM PDT 24
Finished Jul 27 04:22:59 PM PDT 24
Peak memory 209880 kb
Host smart-b87cf92a-4da5-4c53-bdf8-72bcbe6329a2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057229327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.4057229327
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.1348837157
Short name T779
Test name
Test status
Simulation time 77355254 ps
CPU time 3.32 seconds
Started Jul 27 04:19:44 PM PDT 24
Finished Jul 27 04:19:47 PM PDT 24
Peak memory 203540 kb
Host smart-475cd0ba-17f6-4685-903c-23d249aded8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1348837157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1348837157
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.2309500471
Short name T859
Test name
Test status
Simulation time 28668938 ps
CPU time 2.13 seconds
Started Jul 27 04:18:55 PM PDT 24
Finished Jul 27 04:18:57 PM PDT 24
Peak memory 203336 kb
Host smart-12d2b1b6-0aad-4ffc-8fcc-3c04a5a87c80
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2309500471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2309500471
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.568068049
Short name T414
Test name
Test status
Simulation time 9305157628 ps
CPU time 35.15 seconds
Started Jul 27 04:18:13 PM PDT 24
Finished Jul 27 04:18:48 PM PDT 24
Peak memory 203348 kb
Host smart-b7b39a7a-80d6-42c0-a29e-4fe9fc992612
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=568068049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.568068049
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.597177671
Short name T700
Test name
Test status
Simulation time 4007360338 ps
CPU time 32.17 seconds
Started Jul 27 04:23:19 PM PDT 24
Finished Jul 27 04:23:51 PM PDT 24
Peak memory 203312 kb
Host smart-8d1237c2-543c-4068-82b6-210613112057
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=597177671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.597177671
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3376286871
Short name T282
Test name
Test status
Simulation time 64930660 ps
CPU time 2.1 seconds
Started Jul 27 04:23:04 PM PDT 24
Finished Jul 27 04:23:06 PM PDT 24
Peak memory 202064 kb
Host smart-623a9a0c-f9e5-4deb-91a8-8ad6206d2af3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376286871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3376286871
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.3812403801
Short name T128
Test name
Test status
Simulation time 2760888377 ps
CPU time 51.08 seconds
Started Jul 27 04:21:03 PM PDT 24
Finished Jul 27 04:21:54 PM PDT 24
Peak memory 205564 kb
Host smart-b55c2008-2529-41f6-be0a-5128894a1ce8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3812403801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3812403801
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.2605694819
Short name T577
Test name
Test status
Simulation time 513961511 ps
CPU time 52.15 seconds
Started Jul 27 04:23:19 PM PDT 24
Finished Jul 27 04:24:12 PM PDT 24
Peak memory 206824 kb
Host smart-89ccfb13-f0fa-472f-8612-7696de3df6d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2605694819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2605694819
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.732452953
Short name T232
Test name
Test status
Simulation time 2262977134 ps
CPU time 232.06 seconds
Started Jul 27 04:22:44 PM PDT 24
Finished Jul 27 04:26:36 PM PDT 24
Peak memory 207964 kb
Host smart-9b269954-4353-45f5-9e00-6f03a0e1c18a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=732452953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_
reset.732452953
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.491877326
Short name T553
Test name
Test status
Simulation time 478107857 ps
CPU time 167.96 seconds
Started Jul 27 04:18:23 PM PDT 24
Finished Jul 27 04:21:11 PM PDT 24
Peak memory 210808 kb
Host smart-e9c6e314-455f-431c-9e4e-a215a1da4c59
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=491877326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rese
t_error.491877326
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.515621578
Short name T433
Test name
Test status
Simulation time 229667797 ps
CPU time 4.02 seconds
Started Jul 27 04:21:28 PM PDT 24
Finished Jul 27 04:21:32 PM PDT 24
Peak memory 211336 kb
Host smart-41adcf92-2074-491c-a77b-a8ac3b83cb11
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=515621578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.515621578
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.1313061992
Short name T718
Test name
Test status
Simulation time 2839033702 ps
CPU time 52.22 seconds
Started Jul 27 04:23:04 PM PDT 24
Finished Jul 27 04:23:57 PM PDT 24
Peak memory 211492 kb
Host smart-9ed108e9-6271-4beb-ae34-7429d2053ac4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1313061992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1313061992
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.1819654927
Short name T164
Test name
Test status
Simulation time 10151878396 ps
CPU time 51.68 seconds
Started Jul 27 04:23:15 PM PDT 24
Finished Jul 27 04:24:07 PM PDT 24
Peak memory 211680 kb
Host smart-2d685396-f42f-41ae-b23d-59d29f121001
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1819654927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl
ow_rsp.1819654927
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.1372248068
Short name T634
Test name
Test status
Simulation time 1594826664 ps
CPU time 24.55 seconds
Started Jul 27 04:23:17 PM PDT 24
Finished Jul 27 04:23:42 PM PDT 24
Peak memory 203332 kb
Host smart-ee055d58-d060-4307-a26d-9cf75c251718
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1372248068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.1372248068
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.3087139395
Short name T898
Test name
Test status
Simulation time 1188418670 ps
CPU time 16.26 seconds
Started Jul 27 04:23:16 PM PDT 24
Finished Jul 27 04:23:32 PM PDT 24
Peak memory 203452 kb
Host smart-eb7a5227-959e-4fe4-866b-1b5179f54ed7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3087139395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3087139395
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.59915412
Short name T465
Test name
Test status
Simulation time 1680519873 ps
CPU time 31.14 seconds
Started Jul 27 04:23:04 PM PDT 24
Finished Jul 27 04:23:36 PM PDT 24
Peak memory 211356 kb
Host smart-4274ca4c-dbf5-497f-b302-a75004b7e9f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=59915412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.59915412
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.3688608818
Short name T735
Test name
Test status
Simulation time 41526773471 ps
CPU time 133.97 seconds
Started Jul 27 04:23:14 PM PDT 24
Finished Jul 27 04:25:28 PM PDT 24
Peak memory 211536 kb
Host smart-e7d0f425-bb8f-40c5-9492-25f235307280
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688608818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.3688608818
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.2078652940
Short name T191
Test name
Test status
Simulation time 24164520098 ps
CPU time 60.32 seconds
Started Jul 27 04:23:15 PM PDT 24
Finished Jul 27 04:24:16 PM PDT 24
Peak memory 204812 kb
Host smart-a4091675-4454-4ab0-a0b5-18496aadc1c6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2078652940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.2078652940
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.1343391902
Short name T772
Test name
Test status
Simulation time 126335132 ps
CPU time 4.7 seconds
Started Jul 27 04:23:17 PM PDT 24
Finished Jul 27 04:23:22 PM PDT 24
Peak memory 204364 kb
Host smart-19f2229e-afe4-43a1-bfda-019c4a1ca2bd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343391902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.1343391902
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.2264851866
Short name T624
Test name
Test status
Simulation time 590304890 ps
CPU time 13.58 seconds
Started Jul 27 04:23:17 PM PDT 24
Finished Jul 27 04:23:31 PM PDT 24
Peak memory 203384 kb
Host smart-efc500ba-667d-42dd-aeed-180833338886
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2264851866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2264851866
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.745420179
Short name T275
Test name
Test status
Simulation time 286248616 ps
CPU time 3.59 seconds
Started Jul 27 04:23:07 PM PDT 24
Finished Jul 27 04:23:10 PM PDT 24
Peak memory 203188 kb
Host smart-aa349ab3-936d-4935-99c5-6100f8d527c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=745420179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.745420179
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1664467763
Short name T887
Test name
Test status
Simulation time 9182618320 ps
CPU time 39.48 seconds
Started Jul 27 04:23:03 PM PDT 24
Finished Jul 27 04:23:43 PM PDT 24
Peak memory 203348 kb
Host smart-3b4b4bcc-5f62-4940-8581-c61328dc3ee9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664467763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1664467763
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.1345092466
Short name T481
Test name
Test status
Simulation time 19644277163 ps
CPU time 45.12 seconds
Started Jul 27 04:23:12 PM PDT 24
Finished Jul 27 04:23:57 PM PDT 24
Peak memory 203512 kb
Host smart-dbe7158a-cf6a-4950-982a-ac332c1b76cb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1345092466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1345092466
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2824972236
Short name T283
Test name
Test status
Simulation time 35966711 ps
CPU time 2.19 seconds
Started Jul 27 04:23:13 PM PDT 24
Finished Jul 27 04:23:16 PM PDT 24
Peak memory 203284 kb
Host smart-c22d689a-61b9-4865-bbd4-492822e51638
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824972236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2824972236
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all.925172089
Short name T370
Test name
Test status
Simulation time 1579848255 ps
CPU time 118.31 seconds
Started Jul 27 04:23:16 PM PDT 24
Finished Jul 27 04:25:14 PM PDT 24
Peak memory 206988 kb
Host smart-200b4e38-e99c-49c6-9b5d-53c63b6bf66c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=925172089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.925172089
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3280274499
Short name T560
Test name
Test status
Simulation time 6512090338 ps
CPU time 168.33 seconds
Started Jul 27 04:23:09 PM PDT 24
Finished Jul 27 04:25:58 PM PDT 24
Peak memory 209308 kb
Host smart-1c714dfc-8d4c-46ba-b4f4-8a337eeda462
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3280274499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3280274499
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2598521569
Short name T134
Test name
Test status
Simulation time 5716802645 ps
CPU time 353.98 seconds
Started Jul 27 04:23:11 PM PDT 24
Finished Jul 27 04:29:05 PM PDT 24
Peak memory 211440 kb
Host smart-5e4da0c6-714f-4fe6-9f1e-936a04b2c954
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2598521569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran
d_reset.2598521569
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.542097774
Short name T632
Test name
Test status
Simulation time 269866441 ps
CPU time 71.29 seconds
Started Jul 27 04:23:18 PM PDT 24
Finished Jul 27 04:24:30 PM PDT 24
Peak memory 207300 kb
Host smart-b0edd2cf-f7e6-4457-be4d-c0e641569871
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=542097774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_res
et_error.542097774
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.138190039
Short name T325
Test name
Test status
Simulation time 656480585 ps
CPU time 16.23 seconds
Started Jul 27 04:23:17 PM PDT 24
Finished Jul 27 04:23:34 PM PDT 24
Peak memory 205008 kb
Host smart-922d8c2b-47a7-4c26-99dd-6dd7c02425f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=138190039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.138190039
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.182274221
Short name T749
Test name
Test status
Simulation time 11726882856 ps
CPU time 64.88 seconds
Started Jul 27 04:23:24 PM PDT 24
Finished Jul 27 04:24:29 PM PDT 24
Peak memory 211540 kb
Host smart-032f118f-3160-47b2-88f3-96478422a033
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=182274221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.182274221
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.214061450
Short name T18
Test name
Test status
Simulation time 42940099726 ps
CPU time 206.87 seconds
Started Jul 27 04:23:24 PM PDT 24
Finished Jul 27 04:26:51 PM PDT 24
Peak memory 211532 kb
Host smart-f8bedd57-175f-4127-8cf5-b97edab5154c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=214061450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slo
w_rsp.214061450
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1581331297
Short name T769
Test name
Test status
Simulation time 913375189 ps
CPU time 18.5 seconds
Started Jul 27 04:23:21 PM PDT 24
Finished Jul 27 04:23:40 PM PDT 24
Peak memory 203308 kb
Host smart-3f4f49fd-5b97-4967-8b3f-e9f9dd4e16d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1581331297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.1581331297
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.1764058192
Short name T849
Test name
Test status
Simulation time 151273061 ps
CPU time 3.96 seconds
Started Jul 27 04:23:14 PM PDT 24
Finished Jul 27 04:23:18 PM PDT 24
Peak memory 203292 kb
Host smart-491bc196-333e-4e8d-875f-61a1d4bae089
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1764058192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1764058192
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.2222020190
Short name T120
Test name
Test status
Simulation time 90413627 ps
CPU time 8.68 seconds
Started Jul 27 04:23:08 PM PDT 24
Finished Jul 27 04:23:16 PM PDT 24
Peak memory 211740 kb
Host smart-fd071604-dd5c-4fea-a53f-40c5a5615096
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2222020190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.2222020190
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.564172161
Short name T95
Test name
Test status
Simulation time 37329556524 ps
CPU time 139.14 seconds
Started Jul 27 04:23:06 PM PDT 24
Finished Jul 27 04:25:25 PM PDT 24
Peak memory 211608 kb
Host smart-382e6e39-edc3-4ea2-87b8-4e6d5f5ca495
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=564172161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.564172161
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.3531195701
Short name T305
Test name
Test status
Simulation time 49077842678 ps
CPU time 159.28 seconds
Started Jul 27 04:23:24 PM PDT 24
Finished Jul 27 04:26:03 PM PDT 24
Peak memory 211536 kb
Host smart-40ff4fe8-01e4-48b4-9ed7-9f8d8d330a83
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3531195701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3531195701
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.1920910870
Short name T366
Test name
Test status
Simulation time 55055069 ps
CPU time 3.71 seconds
Started Jul 27 04:23:06 PM PDT 24
Finished Jul 27 04:23:10 PM PDT 24
Peak memory 204004 kb
Host smart-43cc5efe-d66c-49a1-8c1d-9cd63876a5c3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920910870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.1920910870
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.3213591805
Short name T448
Test name
Test status
Simulation time 2304250796 ps
CPU time 26.81 seconds
Started Jul 27 04:23:18 PM PDT 24
Finished Jul 27 04:23:45 PM PDT 24
Peak memory 203896 kb
Host smart-b59bc3de-be1d-45c8-a30d-ec8fd6b4bc91
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3213591805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3213591805
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.3000535502
Short name T457
Test name
Test status
Simulation time 46332320 ps
CPU time 2.43 seconds
Started Jul 27 04:23:16 PM PDT 24
Finished Jul 27 04:23:19 PM PDT 24
Peak memory 203216 kb
Host smart-1389ec6d-51ef-438c-a076-3387e3538a4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3000535502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3000535502
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.350302325
Short name T459
Test name
Test status
Simulation time 15641664953 ps
CPU time 34.81 seconds
Started Jul 27 04:23:18 PM PDT 24
Finished Jul 27 04:23:53 PM PDT 24
Peak memory 203380 kb
Host smart-003793a4-29f3-467c-9d24-7f4194ec3b30
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=350302325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.350302325
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.1680305152
Short name T171
Test name
Test status
Simulation time 13384247724 ps
CPU time 32.52 seconds
Started Jul 27 04:23:17 PM PDT 24
Finished Jul 27 04:23:50 PM PDT 24
Peak memory 203360 kb
Host smart-3a255a57-3e38-41f8-95c1-d02ef7deec50
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1680305152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1680305152
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1954196842
Short name T311
Test name
Test status
Simulation time 26255937 ps
CPU time 2.1 seconds
Started Jul 27 04:23:14 PM PDT 24
Finished Jul 27 04:23:17 PM PDT 24
Peak memory 203456 kb
Host smart-c10f5315-9532-40a4-9a94-9abad61baf27
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954196842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1954196842
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.1604241096
Short name T786
Test name
Test status
Simulation time 2543327775 ps
CPU time 29.13 seconds
Started Jul 27 04:23:13 PM PDT 24
Finished Jul 27 04:23:42 PM PDT 24
Peak memory 205060 kb
Host smart-2a3cab2e-87a6-42d7-9710-61f9bfd6eede
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1604241096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1604241096
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.2219827285
Short name T789
Test name
Test status
Simulation time 5387709032 ps
CPU time 32.74 seconds
Started Jul 27 04:23:14 PM PDT 24
Finished Jul 27 04:23:48 PM PDT 24
Peak memory 203524 kb
Host smart-8ddc1173-6747-4212-aa64-0d158be6b965
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2219827285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2219827285
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.627510040
Short name T213
Test name
Test status
Simulation time 1637412557 ps
CPU time 273.23 seconds
Started Jul 27 04:23:18 PM PDT 24
Finished Jul 27 04:27:51 PM PDT 24
Peak memory 212376 kb
Host smart-f8aff19b-291d-41e6-a858-32ac25a712f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=627510040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand
_reset.627510040
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.951432934
Short name T715
Test name
Test status
Simulation time 9405015415 ps
CPU time 252.05 seconds
Started Jul 27 04:23:18 PM PDT 24
Finished Jul 27 04:27:31 PM PDT 24
Peak memory 219760 kb
Host smart-4d3f0332-7624-4539-9376-d7d2d0a45496
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=951432934 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_res
et_error.951432934
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1892441834
Short name T558
Test name
Test status
Simulation time 625533911 ps
CPU time 18.04 seconds
Started Jul 27 04:23:18 PM PDT 24
Finished Jul 27 04:23:36 PM PDT 24
Peak memory 211512 kb
Host smart-5efc6924-11ae-4d4b-b912-43c46dccd6a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1892441834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1892441834
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.3903087935
Short name T619
Test name
Test status
Simulation time 293759425 ps
CPU time 9.86 seconds
Started Jul 27 04:23:22 PM PDT 24
Finished Jul 27 04:23:31 PM PDT 24
Peak memory 211460 kb
Host smart-27b1787f-1d27-4dc5-b1ce-569d79f4ccd4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3903087935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.3903087935
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1101533848
Short name T852
Test name
Test status
Simulation time 80249813429 ps
CPU time 582.84 seconds
Started Jul 27 04:23:09 PM PDT 24
Finished Jul 27 04:32:52 PM PDT 24
Peak memory 211536 kb
Host smart-799b4f50-6bba-427f-93fc-bf11c3987129
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1101533848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl
ow_rsp.1101533848
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3403102214
Short name T669
Test name
Test status
Simulation time 1234026594 ps
CPU time 7.29 seconds
Started Jul 27 04:23:16 PM PDT 24
Finished Jul 27 04:23:23 PM PDT 24
Peak memory 203220 kb
Host smart-e645cad1-147e-47c5-8872-ef6131a35389
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3403102214 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3403102214
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.1976896705
Short name T576
Test name
Test status
Simulation time 3131182786 ps
CPU time 19.85 seconds
Started Jul 27 04:23:20 PM PDT 24
Finished Jul 27 04:23:40 PM PDT 24
Peak memory 203364 kb
Host smart-66d5af4f-ff61-485b-8fe6-dff4acc10d5e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1976896705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1976896705
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.1321036841
Short name T259
Test name
Test status
Simulation time 968694822 ps
CPU time 34.45 seconds
Started Jul 27 04:23:14 PM PDT 24
Finished Jul 27 04:23:49 PM PDT 24
Peak memory 211460 kb
Host smart-1ea163c3-75be-41c9-9ae9-846cdc539e08
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1321036841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.1321036841
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.611229352
Short name T434
Test name
Test status
Simulation time 26541346188 ps
CPU time 147.44 seconds
Started Jul 27 04:23:23 PM PDT 24
Finished Jul 27 04:25:50 PM PDT 24
Peak memory 211500 kb
Host smart-c005400c-773c-4ddc-8b91-2be59ee82bf2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=611229352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.611229352
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.926691830
Short name T54
Test name
Test status
Simulation time 34290374653 ps
CPU time 250.78 seconds
Started Jul 27 04:23:14 PM PDT 24
Finished Jul 27 04:27:25 PM PDT 24
Peak memory 211548 kb
Host smart-d37317e2-fd3d-4b88-a558-ebd8edc55f57
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=926691830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.926691830
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.3854979062
Short name T892
Test name
Test status
Simulation time 156079378 ps
CPU time 21.1 seconds
Started Jul 27 04:23:20 PM PDT 24
Finished Jul 27 04:23:41 PM PDT 24
Peak memory 211472 kb
Host smart-5b093e9b-7f08-4060-9332-dc5930cc74f7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854979062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.3854979062
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.1298759742
Short name T397
Test name
Test status
Simulation time 1567797548 ps
CPU time 26.59 seconds
Started Jul 27 04:23:24 PM PDT 24
Finished Jul 27 04:23:50 PM PDT 24
Peak memory 203844 kb
Host smart-64b7011c-e625-4a00-899e-98710fff891c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1298759742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1298759742
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.3313770896
Short name T689
Test name
Test status
Simulation time 142122322 ps
CPU time 2.99 seconds
Started Jul 27 04:23:15 PM PDT 24
Finished Jul 27 04:23:18 PM PDT 24
Peak memory 203304 kb
Host smart-21cc0621-4b70-4139-b182-bd19a6dc6564
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3313770896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3313770896
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.2406007777
Short name T743
Test name
Test status
Simulation time 17155202565 ps
CPU time 33.49 seconds
Started Jul 27 04:23:14 PM PDT 24
Finished Jul 27 04:23:48 PM PDT 24
Peak memory 203356 kb
Host smart-028e8122-eec2-4a05-ac09-098750fe1587
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406007777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2406007777
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.1318599641
Short name T51
Test name
Test status
Simulation time 8169510022 ps
CPU time 23.25 seconds
Started Jul 27 04:23:11 PM PDT 24
Finished Jul 27 04:23:35 PM PDT 24
Peak memory 203372 kb
Host smart-47a94d58-b9b6-434a-98bd-a27017b87b3b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1318599641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1318599641
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.3703445565
Short name T499
Test name
Test status
Simulation time 31526090 ps
CPU time 2.02 seconds
Started Jul 27 04:23:20 PM PDT 24
Finished Jul 27 04:23:27 PM PDT 24
Peak memory 203276 kb
Host smart-515ddf24-c040-4710-886e-480accc502bd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703445565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.3703445565
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.2485451721
Short name T791
Test name
Test status
Simulation time 1420013309 ps
CPU time 47.41 seconds
Started Jul 27 04:23:13 PM PDT 24
Finished Jul 27 04:24:01 PM PDT 24
Peak memory 205992 kb
Host smart-f3dbc234-3f45-416c-8929-f9bd2bd11273
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2485451721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2485451721
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1999366094
Short name T804
Test name
Test status
Simulation time 3472833435 ps
CPU time 104.6 seconds
Started Jul 27 04:23:20 PM PDT 24
Finished Jul 27 04:25:05 PM PDT 24
Peak memory 208460 kb
Host smart-3af433a8-ceb6-4057-a2e8-18c12e2d8d26
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1999366094 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1999366094
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.1425437025
Short name T10
Test name
Test status
Simulation time 100547892 ps
CPU time 47.05 seconds
Started Jul 27 04:23:24 PM PDT 24
Finished Jul 27 04:24:11 PM PDT 24
Peak memory 206572 kb
Host smart-adcfb47d-7b5a-4cb9-b174-85cd58c4b8a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1425437025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran
d_reset.1425437025
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.983440301
Short name T512
Test name
Test status
Simulation time 151218900 ps
CPU time 36.77 seconds
Started Jul 27 04:23:21 PM PDT 24
Finished Jul 27 04:23:57 PM PDT 24
Peak memory 207068 kb
Host smart-6f388283-458c-4374-b858-abecdeea6a9e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=983440301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_res
et_error.983440301
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.922082764
Short name T354
Test name
Test status
Simulation time 300832652 ps
CPU time 18.74 seconds
Started Jul 27 04:23:14 PM PDT 24
Finished Jul 27 04:23:34 PM PDT 24
Peak memory 211464 kb
Host smart-66b8539c-7dfd-4f67-9329-431a5fd4e4d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=922082764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.922082764
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.770823633
Short name T720
Test name
Test status
Simulation time 1014611952 ps
CPU time 15.05 seconds
Started Jul 27 04:23:21 PM PDT 24
Finished Jul 27 04:23:36 PM PDT 24
Peak memory 203388 kb
Host smart-c00cf7d8-6f6a-4338-8fa6-e2956270a73b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=770823633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.770823633
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3284558191
Short name T550
Test name
Test status
Simulation time 193980963212 ps
CPU time 719.55 seconds
Started Jul 27 04:23:22 PM PDT 24
Finished Jul 27 04:35:22 PM PDT 24
Peak memory 211508 kb
Host smart-c25002ee-4e04-4d08-b7a9-b8b182b45185
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3284558191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl
ow_rsp.3284558191
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.3774396057
Short name T682
Test name
Test status
Simulation time 318119547 ps
CPU time 9.8 seconds
Started Jul 27 04:23:20 PM PDT 24
Finished Jul 27 04:23:30 PM PDT 24
Peak memory 203416 kb
Host smart-b3264d39-ae0c-453d-82a6-064f135e97cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3774396057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3774396057
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.3271545983
Short name T286
Test name
Test status
Simulation time 1047053486 ps
CPU time 27.93 seconds
Started Jul 27 04:23:14 PM PDT 24
Finished Jul 27 04:23:43 PM PDT 24
Peak memory 203276 kb
Host smart-0dd308ec-6728-43ce-b3f3-0259e68a5a19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3271545983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3271545983
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.1549298190
Short name T46
Test name
Test status
Simulation time 458824082 ps
CPU time 9.59 seconds
Started Jul 27 04:23:18 PM PDT 24
Finished Jul 27 04:23:27 PM PDT 24
Peak memory 211436 kb
Host smart-9210dfd3-4598-4004-b4e7-4f55a7c20512
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1549298190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.1549298190
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.2487577236
Short name T714
Test name
Test status
Simulation time 34898463306 ps
CPU time 216.99 seconds
Started Jul 27 04:23:17 PM PDT 24
Finished Jul 27 04:26:54 PM PDT 24
Peak memory 211548 kb
Host smart-7d284683-bf7e-44c6-8d29-69f6c63231df
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487577236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2487577236
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.695466664
Short name T555
Test name
Test status
Simulation time 25984303508 ps
CPU time 167.59 seconds
Started Jul 27 04:23:16 PM PDT 24
Finished Jul 27 04:26:03 PM PDT 24
Peak memory 211484 kb
Host smart-d8dde5e6-aff4-464d-b348-35888a406b9a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=695466664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.695466664
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2181546305
Short name T1
Test name
Test status
Simulation time 22615378 ps
CPU time 2.01 seconds
Started Jul 27 04:23:12 PM PDT 24
Finished Jul 27 04:23:14 PM PDT 24
Peak memory 203216 kb
Host smart-2bc3ef18-07c6-4ca8-977b-7b95f497de2b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181546305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2181546305
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.1786672645
Short name T668
Test name
Test status
Simulation time 713754761 ps
CPU time 12.04 seconds
Started Jul 27 04:23:17 PM PDT 24
Finished Jul 27 04:23:29 PM PDT 24
Peak memory 203332 kb
Host smart-a28e180d-b532-491c-93be-d54936657932
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1786672645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1786672645
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.3585165806
Short name T627
Test name
Test status
Simulation time 162253822 ps
CPU time 3.64 seconds
Started Jul 27 04:23:24 PM PDT 24
Finished Jul 27 04:23:28 PM PDT 24
Peak memory 203284 kb
Host smart-68c03110-f22f-46ec-936c-610a7fe6f01e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3585165806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.3585165806
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.1984978991
Short name T707
Test name
Test status
Simulation time 25229936672 ps
CPU time 43.14 seconds
Started Jul 27 04:23:22 PM PDT 24
Finished Jul 27 04:24:05 PM PDT 24
Peak memory 203336 kb
Host smart-90b9babb-9c02-462c-86c5-73cee6a9084a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984978991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1984978991
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.904762988
Short name T66
Test name
Test status
Simulation time 7162987674 ps
CPU time 25.24 seconds
Started Jul 27 04:23:23 PM PDT 24
Finished Jul 27 04:23:48 PM PDT 24
Peak memory 203340 kb
Host smart-f37a79c6-c477-4027-a8c1-51116d2229d7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=904762988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.904762988
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.1010180215
Short name T436
Test name
Test status
Simulation time 36311741 ps
CPU time 2.27 seconds
Started Jul 27 04:23:22 PM PDT 24
Finished Jul 27 04:23:24 PM PDT 24
Peak memory 203252 kb
Host smart-391ee673-c4e6-4c14-9727-c8a495fec591
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010180215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.1010180215
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.3014395977
Short name T371
Test name
Test status
Simulation time 1046376829 ps
CPU time 84.43 seconds
Started Jul 27 04:23:24 PM PDT 24
Finished Jul 27 04:24:48 PM PDT 24
Peak memory 207600 kb
Host smart-15ebfd56-684b-4850-a9a5-2d71cf0ffb86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3014395977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3014395977
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3651838084
Short name T515
Test name
Test status
Simulation time 2311577966 ps
CPU time 33.31 seconds
Started Jul 27 04:23:14 PM PDT 24
Finished Jul 27 04:23:47 PM PDT 24
Peak memory 205028 kb
Host smart-412370e9-68f5-4412-9937-97ca87961946
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3651838084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3651838084
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3193405647
Short name T541
Test name
Test status
Simulation time 127173580 ps
CPU time 43.42 seconds
Started Jul 27 04:23:16 PM PDT 24
Finished Jul 27 04:24:00 PM PDT 24
Peak memory 207656 kb
Host smart-aee203c4-5372-49ac-898e-11141c9737d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3193405647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran
d_reset.3193405647
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.4021508933
Short name T839
Test name
Test status
Simulation time 3033623772 ps
CPU time 422.76 seconds
Started Jul 27 04:23:16 PM PDT 24
Finished Jul 27 04:30:19 PM PDT 24
Peak memory 220600 kb
Host smart-ffd67986-e6e9-4081-91d5-7a3bd1331d0d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4021508933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re
set_error.4021508933
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.4086805184
Short name T269
Test name
Test status
Simulation time 58104700 ps
CPU time 8.53 seconds
Started Jul 27 04:23:16 PM PDT 24
Finished Jul 27 04:23:25 PM PDT 24
Peak memory 211504 kb
Host smart-6da8c149-3e30-41d4-a1b3-a8870fe74d22
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4086805184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.4086805184
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.1633684584
Short name T77
Test name
Test status
Simulation time 1371411748 ps
CPU time 47.51 seconds
Started Jul 27 04:23:24 PM PDT 24
Finished Jul 27 04:24:12 PM PDT 24
Peak memory 205356 kb
Host smart-b83851e4-dfb8-4b7f-ba08-9f93baad3f3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1633684584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1633684584
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.2168097011
Short name T137
Test name
Test status
Simulation time 93173079127 ps
CPU time 641.08 seconds
Started Jul 27 04:23:25 PM PDT 24
Finished Jul 27 04:34:07 PM PDT 24
Peak memory 205960 kb
Host smart-ccfffc56-8489-49bd-995e-1fbb503d8492
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2168097011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl
ow_rsp.2168097011
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.3759349033
Short name T431
Test name
Test status
Simulation time 223100768 ps
CPU time 4.52 seconds
Started Jul 27 04:23:23 PM PDT 24
Finished Jul 27 04:23:28 PM PDT 24
Peak memory 203296 kb
Host smart-ca4d4959-de1e-4c18-9a2a-398f6dbab1fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3759349033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.3759349033
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.4039576352
Short name T872
Test name
Test status
Simulation time 114103566 ps
CPU time 10.64 seconds
Started Jul 27 04:23:24 PM PDT 24
Finished Jul 27 04:23:35 PM PDT 24
Peak memory 203180 kb
Host smart-28bb5ea6-838b-41d0-9c0a-dea4a08bd321
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4039576352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.4039576352
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.1808626551
Short name T209
Test name
Test status
Simulation time 175099348 ps
CPU time 14.2 seconds
Started Jul 27 04:23:19 PM PDT 24
Finished Jul 27 04:23:33 PM PDT 24
Peak memory 211480 kb
Host smart-34065f37-0c45-4f20-9eb4-ab5b3bfd344f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1808626551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.1808626551
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.4109089855
Short name T162
Test name
Test status
Simulation time 124994825285 ps
CPU time 177.35 seconds
Started Jul 27 04:23:24 PM PDT 24
Finished Jul 27 04:26:21 PM PDT 24
Peak memory 211540 kb
Host smart-bbc85f8b-2f5a-4c21-855e-29d06925396c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109089855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.4109089855
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.843767132
Short name T67
Test name
Test status
Simulation time 3778449471 ps
CPU time 15.7 seconds
Started Jul 27 04:23:26 PM PDT 24
Finished Jul 27 04:23:42 PM PDT 24
Peak memory 203344 kb
Host smart-db8a5b66-aad3-48c4-9617-da55af1638e7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=843767132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.843767132
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.18600777
Short name T418
Test name
Test status
Simulation time 114017894 ps
CPU time 9.99 seconds
Started Jul 27 04:23:26 PM PDT 24
Finished Jul 27 04:23:36 PM PDT 24
Peak memory 204336 kb
Host smart-db8246a9-bda5-4fbd-b972-3404069e3d60
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18600777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.18600777
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.2844845082
Short name T557
Test name
Test status
Simulation time 595936135 ps
CPU time 8.25 seconds
Started Jul 27 04:23:37 PM PDT 24
Finished Jul 27 04:23:46 PM PDT 24
Peak memory 203316 kb
Host smart-00aeca13-4794-4a60-8c61-f90169c7988c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2844845082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2844845082
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.50228347
Short name T893
Test name
Test status
Simulation time 33890109 ps
CPU time 2.29 seconds
Started Jul 27 04:23:14 PM PDT 24
Finished Jul 27 04:23:16 PM PDT 24
Peak memory 203352 kb
Host smart-b1996474-ea39-40d6-9275-7016e63e83b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=50228347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.50228347
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.3842056512
Short name T544
Test name
Test status
Simulation time 29718631780 ps
CPU time 39.87 seconds
Started Jul 27 04:23:22 PM PDT 24
Finished Jul 27 04:24:02 PM PDT 24
Peak memory 203340 kb
Host smart-c00abcac-4494-46f4-bcab-b643180be246
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842056512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3842056512
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.3421334349
Short name T831
Test name
Test status
Simulation time 3470664494 ps
CPU time 25.25 seconds
Started Jul 27 04:23:19 PM PDT 24
Finished Jul 27 04:23:45 PM PDT 24
Peak memory 203344 kb
Host smart-b59f4e53-1974-4c90-af8b-32277cdd2672
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3421334349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3421334349
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.1512573545
Short name T277
Test name
Test status
Simulation time 41571022 ps
CPU time 2.34 seconds
Started Jul 27 04:23:12 PM PDT 24
Finished Jul 27 04:23:14 PM PDT 24
Peak memory 203288 kb
Host smart-94e1832e-6627-4e1b-929c-d7d249240118
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512573545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.1512573545
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.2773489464
Short name T87
Test name
Test status
Simulation time 7462600309 ps
CPU time 190 seconds
Started Jul 27 04:23:26 PM PDT 24
Finished Jul 27 04:26:36 PM PDT 24
Peak memory 207164 kb
Host smart-cb74071e-323f-440a-a527-456c8397f1b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2773489464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2773489464
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.2373514247
Short name T378
Test name
Test status
Simulation time 8953667380 ps
CPU time 202.08 seconds
Started Jul 27 04:23:29 PM PDT 24
Finished Jul 27 04:26:51 PM PDT 24
Peak memory 207176 kb
Host smart-e8e88aad-c374-4bd0-a6d9-20c205749eb7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2373514247 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2373514247
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3065508241
Short name T611
Test name
Test status
Simulation time 633145058 ps
CPU time 215.73 seconds
Started Jul 27 04:23:40 PM PDT 24
Finished Jul 27 04:27:16 PM PDT 24
Peak memory 209284 kb
Host smart-24414f2e-8df9-470d-8785-b47bf763d208
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3065508241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran
d_reset.3065508241
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3771354338
Short name T825
Test name
Test status
Simulation time 1093209952 ps
CPU time 233 seconds
Started Jul 27 04:23:26 PM PDT 24
Finished Jul 27 04:27:19 PM PDT 24
Peak memory 219668 kb
Host smart-3646cd8e-d551-42f5-8cb6-25c0b3eec7b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3771354338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re
set_error.3771354338
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.522540393
Short name T797
Test name
Test status
Simulation time 1069513536 ps
CPU time 28.92 seconds
Started Jul 27 04:23:25 PM PDT 24
Finished Jul 27 04:23:54 PM PDT 24
Peak memory 211480 kb
Host smart-081794f8-ee9c-44a7-a9bc-f5af9d43df3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=522540393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.522540393
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.785696670
Short name T339
Test name
Test status
Simulation time 632340852 ps
CPU time 37.78 seconds
Started Jul 27 04:23:26 PM PDT 24
Finished Jul 27 04:24:04 PM PDT 24
Peak memory 211488 kb
Host smart-1c1d7c86-5633-42b5-a092-6f744a587e9b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=785696670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.785696670
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3110568873
Short name T201
Test name
Test status
Simulation time 46842039408 ps
CPU time 216.78 seconds
Started Jul 27 04:23:26 PM PDT 24
Finished Jul 27 04:27:03 PM PDT 24
Peak memory 211544 kb
Host smart-9ca18c2c-6194-45e9-aeca-90d546ebf1b1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3110568873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl
ow_rsp.3110568873
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.3915229335
Short name T731
Test name
Test status
Simulation time 96376637 ps
CPU time 7.77 seconds
Started Jul 27 04:23:24 PM PDT 24
Finished Jul 27 04:23:32 PM PDT 24
Peak memory 203308 kb
Host smart-b31f1654-9812-44de-ab7c-0d1cc82f2d6b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3915229335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.3915229335
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.3708569300
Short name T480
Test name
Test status
Simulation time 183877693 ps
CPU time 13.55 seconds
Started Jul 27 04:23:30 PM PDT 24
Finished Jul 27 04:23:43 PM PDT 24
Peak memory 203536 kb
Host smart-77d7b20e-aa94-4019-93a1-48bb55af55d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3708569300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3708569300
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.3815459669
Short name T713
Test name
Test status
Simulation time 541945644 ps
CPU time 20.82 seconds
Started Jul 27 04:23:28 PM PDT 24
Finished Jul 27 04:23:49 PM PDT 24
Peak memory 211472 kb
Host smart-a4262f6e-2d83-4928-b0da-2c34e7fa6b66
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3815459669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.3815459669
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.89534186
Short name T68
Test name
Test status
Simulation time 50079973557 ps
CPU time 88.1 seconds
Started Jul 27 04:23:32 PM PDT 24
Finished Jul 27 04:25:00 PM PDT 24
Peak memory 211492 kb
Host smart-21eca917-d37f-40a1-84d8-70f848c25958
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=89534186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.89534186
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.122857548
Short name T181
Test name
Test status
Simulation time 24429490352 ps
CPU time 175.79 seconds
Started Jul 27 04:23:27 PM PDT 24
Finished Jul 27 04:26:23 PM PDT 24
Peak memory 211532 kb
Host smart-3f935297-d5c0-4132-9861-35e14afe905e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=122857548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.122857548
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.3168857786
Short name T315
Test name
Test status
Simulation time 40505054 ps
CPU time 3.26 seconds
Started Jul 27 04:23:28 PM PDT 24
Finished Jul 27 04:23:31 PM PDT 24
Peak memory 203656 kb
Host smart-45d9ec94-b098-4d8c-ad8e-9d21d31fefa9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168857786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.3168857786
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.3648358363
Short name T16
Test name
Test status
Simulation time 1996715518 ps
CPU time 35.85 seconds
Started Jul 27 04:23:25 PM PDT 24
Finished Jul 27 04:24:01 PM PDT 24
Peak memory 204728 kb
Host smart-320c36da-8bf2-4c6e-9e0a-57a10943eb61
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3648358363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3648358363
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.869372736
Short name T730
Test name
Test status
Simulation time 111687184 ps
CPU time 2.84 seconds
Started Jul 27 04:23:25 PM PDT 24
Finished Jul 27 04:23:28 PM PDT 24
Peak memory 203256 kb
Host smart-93d6b580-a6c1-418b-b290-86654f717059
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=869372736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.869372736
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.2878079657
Short name T596
Test name
Test status
Simulation time 13177417754 ps
CPU time 29.61 seconds
Started Jul 27 04:23:25 PM PDT 24
Finished Jul 27 04:23:55 PM PDT 24
Peak memory 203324 kb
Host smart-0e091fe5-53a1-48ac-a21a-c809a1858c1f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878079657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2878079657
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.701352188
Short name T590
Test name
Test status
Simulation time 2831026857 ps
CPU time 25.88 seconds
Started Jul 27 04:23:29 PM PDT 24
Finished Jul 27 04:23:55 PM PDT 24
Peak memory 203360 kb
Host smart-cfdfa163-ed65-4922-baf3-444b65078799
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=701352188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.701352188
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1207625033
Short name T680
Test name
Test status
Simulation time 104286474 ps
CPU time 1.93 seconds
Started Jul 27 04:23:26 PM PDT 24
Finished Jul 27 04:23:28 PM PDT 24
Peak memory 203276 kb
Host smart-ca5fcfc4-f2dd-4e87-a95c-983fbd17bf16
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207625033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1207625033
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.55572750
Short name T338
Test name
Test status
Simulation time 2268383410 ps
CPU time 56.66 seconds
Started Jul 27 04:23:24 PM PDT 24
Finished Jul 27 04:24:21 PM PDT 24
Peak memory 211548 kb
Host smart-e8300d61-e5bd-4d08-bbeb-0d554b8c3cbd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=55572750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.55572750
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2929308599
Short name T883
Test name
Test status
Simulation time 1503221883 ps
CPU time 45.21 seconds
Started Jul 27 04:23:26 PM PDT 24
Finished Jul 27 04:24:12 PM PDT 24
Peak memory 211492 kb
Host smart-b32df4ed-4178-450e-b95c-8768a02531c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2929308599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2929308599
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.4101183714
Short name T894
Test name
Test status
Simulation time 14124736 ps
CPU time 6.52 seconds
Started Jul 27 04:23:26 PM PDT 24
Finished Jul 27 04:23:33 PM PDT 24
Peak memory 203576 kb
Host smart-d059f14c-6a51-4033-a696-7a089df415b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4101183714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran
d_reset.4101183714
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.891385655
Short name T637
Test name
Test status
Simulation time 2426678948 ps
CPU time 341.09 seconds
Started Jul 27 04:23:25 PM PDT 24
Finished Jul 27 04:29:06 PM PDT 24
Peak memory 226544 kb
Host smart-2266bfe4-63e0-46e2-badf-a9ad3560d810
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=891385655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_res
et_error.891385655
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.3196950639
Short name T835
Test name
Test status
Simulation time 546698478 ps
CPU time 18.32 seconds
Started Jul 27 04:23:24 PM PDT 24
Finished Jul 27 04:23:43 PM PDT 24
Peak memory 211436 kb
Host smart-a5048480-89e1-4b37-9cd2-dcbdce0b4197
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3196950639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3196950639
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.1746533728
Short name T178
Test name
Test status
Simulation time 1388100520 ps
CPU time 30.06 seconds
Started Jul 27 04:23:28 PM PDT 24
Finished Jul 27 04:23:58 PM PDT 24
Peak memory 211488 kb
Host smart-a00a186a-03b4-4afd-8453-11c649881087
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1746533728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.1746533728
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.425833417
Short name T195
Test name
Test status
Simulation time 12226561577 ps
CPU time 116.63 seconds
Started Jul 27 04:23:25 PM PDT 24
Finished Jul 27 04:25:22 PM PDT 24
Peak memory 211432 kb
Host smart-313f8cb7-1a09-4fd7-81d9-baf1de2d63d9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=425833417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slo
w_rsp.425833417
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.505721827
Short name T672
Test name
Test status
Simulation time 148656175 ps
CPU time 18.07 seconds
Started Jul 27 04:23:29 PM PDT 24
Finished Jul 27 04:23:47 PM PDT 24
Peak memory 203316 kb
Host smart-c9ce5e36-2993-45d4-9706-540e3bb4ab68
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=505721827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.505721827
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.4174766701
Short name T697
Test name
Test status
Simulation time 189691963 ps
CPU time 17.8 seconds
Started Jul 27 04:23:24 PM PDT 24
Finished Jul 27 04:23:41 PM PDT 24
Peak memory 203476 kb
Host smart-e18fb00d-db29-4a84-aaca-67fa432c6f44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4174766701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.4174766701
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.2158475414
Short name T737
Test name
Test status
Simulation time 649353946 ps
CPU time 15.58 seconds
Started Jul 27 04:23:25 PM PDT 24
Finished Jul 27 04:23:40 PM PDT 24
Peak memory 211480 kb
Host smart-43aafa23-697f-44a0-8037-154cf21483cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2158475414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.2158475414
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.3998226855
Short name T114
Test name
Test status
Simulation time 21352896484 ps
CPU time 108.42 seconds
Started Jul 27 04:23:25 PM PDT 24
Finished Jul 27 04:25:13 PM PDT 24
Peak memory 204552 kb
Host smart-ac1e8215-f4fb-4b85-80c4-ac8cb12722f3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998226855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3998226855
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.3558684902
Short name T329
Test name
Test status
Simulation time 30946864318 ps
CPU time 251.54 seconds
Started Jul 27 04:23:24 PM PDT 24
Finished Jul 27 04:27:36 PM PDT 24
Peak memory 211520 kb
Host smart-ee02e02e-9c62-4a93-a92a-9c20c0e11709
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3558684902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3558684902
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.133465867
Short name T362
Test name
Test status
Simulation time 57379000 ps
CPU time 6.78 seconds
Started Jul 27 04:23:29 PM PDT 24
Finished Jul 27 04:23:36 PM PDT 24
Peak memory 211380 kb
Host smart-762896d8-2334-40c7-978e-5fec65196c32
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133465867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.133465867
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.631388036
Short name T373
Test name
Test status
Simulation time 238006875 ps
CPU time 19.07 seconds
Started Jul 27 04:23:40 PM PDT 24
Finished Jul 27 04:24:00 PM PDT 24
Peak memory 203360 kb
Host smart-3ff2d994-8325-427a-8c01-2c20732e96bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=631388036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.631388036
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.1005713240
Short name T674
Test name
Test status
Simulation time 28430678 ps
CPU time 2.03 seconds
Started Jul 27 04:23:28 PM PDT 24
Finished Jul 27 04:23:31 PM PDT 24
Peak memory 203228 kb
Host smart-5b4f2021-044b-4e3c-aad2-5787072ef392
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1005713240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1005713240
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2492747315
Short name T161
Test name
Test status
Simulation time 6236641613 ps
CPU time 34.13 seconds
Started Jul 27 04:23:24 PM PDT 24
Finished Jul 27 04:23:59 PM PDT 24
Peak memory 203356 kb
Host smart-4d45074b-16c1-4e9d-9bb1-cc7591677537
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492747315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2492747315
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.3324509985
Short name T219
Test name
Test status
Simulation time 3172256148 ps
CPU time 28.88 seconds
Started Jul 27 04:23:25 PM PDT 24
Finished Jul 27 04:23:54 PM PDT 24
Peak memory 203352 kb
Host smart-0c81ff48-a307-4081-bd59-fa81e075c987
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3324509985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3324509985
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1411208591
Short name T296
Test name
Test status
Simulation time 31494102 ps
CPU time 2.35 seconds
Started Jul 27 04:23:25 PM PDT 24
Finished Jul 27 04:23:28 PM PDT 24
Peak memory 203200 kb
Host smart-2cbf147b-9124-45b2-8766-dbbb4af91314
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411208591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1411208591
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.3581261923
Short name T609
Test name
Test status
Simulation time 367376260 ps
CPU time 30.83 seconds
Started Jul 27 04:23:26 PM PDT 24
Finished Jul 27 04:23:57 PM PDT 24
Peak memory 205880 kb
Host smart-cca4e12d-3edb-4ee6-af94-ed1f59804c5c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3581261923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3581261923
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1512564910
Short name T406
Test name
Test status
Simulation time 1033336864 ps
CPU time 70.72 seconds
Started Jul 27 04:23:25 PM PDT 24
Finished Jul 27 04:24:36 PM PDT 24
Peak memory 204708 kb
Host smart-5d2d591b-839d-40b1-87f7-03f0fe61565f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1512564910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1512564910
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.3096126566
Short name T498
Test name
Test status
Simulation time 315185508 ps
CPU time 111.04 seconds
Started Jul 27 04:23:23 PM PDT 24
Finished Jul 27 04:25:14 PM PDT 24
Peak memory 208128 kb
Host smart-6d9b6d10-f53e-4eb3-8dc7-2b5dd256a7d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3096126566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran
d_reset.3096126566
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.4244561133
Short name T633
Test name
Test status
Simulation time 23418494 ps
CPU time 15.4 seconds
Started Jul 27 04:23:28 PM PDT 24
Finished Jul 27 04:23:43 PM PDT 24
Peak memory 204304 kb
Host smart-30a5108a-f653-45c0-9a30-9d53b90482f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4244561133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re
set_error.4244561133
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.135035621
Short name T684
Test name
Test status
Simulation time 230790378 ps
CPU time 2.48 seconds
Started Jul 27 04:23:25 PM PDT 24
Finished Jul 27 04:23:27 PM PDT 24
Peak memory 203272 kb
Host smart-c171239f-79eb-4f58-a439-80eabdbdf2f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=135035621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.135035621
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.885641304
Short name T52
Test name
Test status
Simulation time 75514270 ps
CPU time 3.12 seconds
Started Jul 27 04:23:28 PM PDT 24
Finished Jul 27 04:23:31 PM PDT 24
Peak memory 203308 kb
Host smart-133577f0-ac36-42ab-b1b4-b84aaa9ef295
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=885641304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.885641304
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1594487994
Short name T144
Test name
Test status
Simulation time 51336248711 ps
CPU time 287.35 seconds
Started Jul 27 04:23:29 PM PDT 24
Finished Jul 27 04:28:16 PM PDT 24
Peak memory 211520 kb
Host smart-522f45bc-eee8-41b6-a403-945bb6f00cb5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1594487994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl
ow_rsp.1594487994
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1696033867
Short name T516
Test name
Test status
Simulation time 301529063 ps
CPU time 10.53 seconds
Started Jul 27 04:23:26 PM PDT 24
Finished Jul 27 04:23:36 PM PDT 24
Peak memory 203356 kb
Host smart-cf7a69b3-9827-4d13-abfc-71c1bb897b3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1696033867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1696033867
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.1031778134
Short name T573
Test name
Test status
Simulation time 4422917021 ps
CPU time 31.64 seconds
Started Jul 27 04:23:36 PM PDT 24
Finished Jul 27 04:24:07 PM PDT 24
Peak memory 203324 kb
Host smart-9a96d8d2-fd9f-4f71-8e78-1a26bab4d9cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1031778134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1031778134
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.3970735201
Short name T698
Test name
Test status
Simulation time 79182603 ps
CPU time 7.65 seconds
Started Jul 27 04:23:29 PM PDT 24
Finished Jul 27 04:23:37 PM PDT 24
Peak memory 211468 kb
Host smart-06a00499-5b0d-422e-94d0-d2de80bc5307
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3970735201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.3970735201
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.518049973
Short name T753
Test name
Test status
Simulation time 56362290088 ps
CPU time 130.59 seconds
Started Jul 27 04:23:25 PM PDT 24
Finished Jul 27 04:25:36 PM PDT 24
Peak memory 211564 kb
Host smart-f936c6d0-1f8e-4407-a383-aae92e5cb3e5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=518049973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.518049973
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.3987980499
Short name T63
Test name
Test status
Simulation time 4619217740 ps
CPU time 33.8 seconds
Started Jul 27 04:23:30 PM PDT 24
Finished Jul 27 04:24:09 PM PDT 24
Peak memory 211528 kb
Host smart-e6f7101d-7325-4866-b489-8e8e42062213
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3987980499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3987980499
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.1078674290
Short name T848
Test name
Test status
Simulation time 19016455 ps
CPU time 2.19 seconds
Started Jul 27 04:23:26 PM PDT 24
Finished Jul 27 04:23:28 PM PDT 24
Peak memory 204288 kb
Host smart-5760989c-45d6-4c4f-9abd-368ce23bb4a8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078674290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.1078674290
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.3982722773
Short name T331
Test name
Test status
Simulation time 233910487 ps
CPU time 4.42 seconds
Started Jul 27 04:23:38 PM PDT 24
Finished Jul 27 04:23:42 PM PDT 24
Peak memory 203268 kb
Host smart-79ac1c8d-44b2-490e-a7ef-1e620705714f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3982722773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3982722773
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.30681978
Short name T644
Test name
Test status
Simulation time 124034433 ps
CPU time 2.14 seconds
Started Jul 27 04:23:29 PM PDT 24
Finished Jul 27 04:23:32 PM PDT 24
Peak memory 203300 kb
Host smart-5b8bc231-a308-44a6-9fca-290e64f09f8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=30681978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.30681978
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2802424058
Short name T679
Test name
Test status
Simulation time 5802936025 ps
CPU time 28.96 seconds
Started Jul 27 04:23:27 PM PDT 24
Finished Jul 27 04:23:56 PM PDT 24
Peak memory 203344 kb
Host smart-f5e21dfd-4a6e-4df2-bc81-1466b542f4bd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802424058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2802424058
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.241222259
Short name T822
Test name
Test status
Simulation time 3306954456 ps
CPU time 29.43 seconds
Started Jul 27 04:23:24 PM PDT 24
Finished Jul 27 04:23:53 PM PDT 24
Peak memory 203388 kb
Host smart-5e1625ea-8788-4e98-a0a8-d2918e9adbf0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=241222259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.241222259
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3698294289
Short name T429
Test name
Test status
Simulation time 51389264 ps
CPU time 2.15 seconds
Started Jul 27 04:23:25 PM PDT 24
Finished Jul 27 04:23:28 PM PDT 24
Peak memory 203184 kb
Host smart-670de5c3-9c9a-43b3-909b-aa556e53a59f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698294289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3698294289
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.306977714
Short name T582
Test name
Test status
Simulation time 1519401209 ps
CPU time 111.24 seconds
Started Jul 27 04:23:38 PM PDT 24
Finished Jul 27 04:25:30 PM PDT 24
Peak memory 208452 kb
Host smart-fbd90e6c-3b3b-4326-9dee-ff92b7ae217a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=306977714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.306977714
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.115851222
Short name T832
Test name
Test status
Simulation time 1815051824 ps
CPU time 86.17 seconds
Started Jul 27 04:23:29 PM PDT 24
Finished Jul 27 04:24:55 PM PDT 24
Peak memory 206272 kb
Host smart-bb87425e-8b0d-4b2a-96a4-3233322d988d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=115851222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.115851222
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.2775047797
Short name T774
Test name
Test status
Simulation time 481851298 ps
CPU time 58.97 seconds
Started Jul 27 04:23:25 PM PDT 24
Finished Jul 27 04:24:25 PM PDT 24
Peak memory 207980 kb
Host smart-6ab0d80f-60e5-4bbd-bf21-095d59872ab9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2775047797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re
set_error.2775047797
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.2157323716
Short name T588
Test name
Test status
Simulation time 1104993127 ps
CPU time 20.57 seconds
Started Jul 27 04:23:41 PM PDT 24
Finished Jul 27 04:24:02 PM PDT 24
Peak memory 204972 kb
Host smart-9f374c8c-2ada-438c-b2eb-259f21941b06
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2157323716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2157323716
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.3415968806
Short name T249
Test name
Test status
Simulation time 304216090 ps
CPU time 28.81 seconds
Started Jul 27 04:23:32 PM PDT 24
Finished Jul 27 04:24:01 PM PDT 24
Peak memory 205700 kb
Host smart-4aff75f0-43b9-4535-b1f9-319056dc341f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3415968806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.3415968806
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1231757953
Short name T491
Test name
Test status
Simulation time 15963895626 ps
CPU time 132.3 seconds
Started Jul 27 04:23:50 PM PDT 24
Finished Jul 27 04:26:03 PM PDT 24
Peak memory 211316 kb
Host smart-819f1624-4213-4d49-b8f9-680b5bcb71e8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1231757953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl
ow_rsp.1231757953
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3332150250
Short name T440
Test name
Test status
Simulation time 182212540 ps
CPU time 5.58 seconds
Started Jul 27 04:23:55 PM PDT 24
Finished Jul 27 04:24:00 PM PDT 24
Peak memory 203160 kb
Host smart-077e25d0-4e9f-459c-b237-18f954a1b1a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3332150250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3332150250
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.3153327156
Short name T864
Test name
Test status
Simulation time 770383340 ps
CPU time 25.74 seconds
Started Jul 27 04:23:41 PM PDT 24
Finished Jul 27 04:24:07 PM PDT 24
Peak memory 203340 kb
Host smart-e9f5796e-7e35-4e1f-92cc-661e8e236bcc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3153327156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3153327156
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.3326240098
Short name T549
Test name
Test status
Simulation time 231979206 ps
CPU time 16.13 seconds
Started Jul 27 04:23:40 PM PDT 24
Finished Jul 27 04:23:56 PM PDT 24
Peak memory 211488 kb
Host smart-9b424976-4d8f-44ef-8afc-c775882f7b63
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3326240098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3326240098
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.880705846
Short name T190
Test name
Test status
Simulation time 71407213625 ps
CPU time 271.61 seconds
Started Jul 27 04:23:26 PM PDT 24
Finished Jul 27 04:27:58 PM PDT 24
Peak memory 211548 kb
Host smart-f1fb7e38-1604-4e4e-ab8b-2fb2dd21ba76
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=880705846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.880705846
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2137379071
Short name T59
Test name
Test status
Simulation time 8331621415 ps
CPU time 24.34 seconds
Started Jul 27 04:23:26 PM PDT 24
Finished Jul 27 04:23:50 PM PDT 24
Peak memory 203404 kb
Host smart-4bab19d8-99f4-48eb-9faf-d48d30795d33
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2137379071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2137379071
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.2341095467
Short name T301
Test name
Test status
Simulation time 191185213 ps
CPU time 12.09 seconds
Started Jul 27 04:23:28 PM PDT 24
Finished Jul 27 04:23:41 PM PDT 24
Peak memory 204348 kb
Host smart-30163d1c-c7dc-44be-89f1-e32618370772
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341095467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.2341095467
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.1881080810
Short name T94
Test name
Test status
Simulation time 139611533 ps
CPU time 10.63 seconds
Started Jul 27 04:23:36 PM PDT 24
Finished Jul 27 04:23:46 PM PDT 24
Peak memory 203320 kb
Host smart-1844967b-1d2f-498a-ba4d-848f5a9bb081
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1881080810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1881080810
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.2729525655
Short name T324
Test name
Test status
Simulation time 142914082 ps
CPU time 3.49 seconds
Started Jul 27 04:23:38 PM PDT 24
Finished Jul 27 04:23:41 PM PDT 24
Peak memory 203268 kb
Host smart-615c38ce-9c0e-480e-8277-91b1ffa95e48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2729525655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2729525655
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3609326246
Short name T810
Test name
Test status
Simulation time 7936411003 ps
CPU time 25.13 seconds
Started Jul 27 04:23:38 PM PDT 24
Finished Jul 27 04:24:03 PM PDT 24
Peak memory 203344 kb
Host smart-371ba727-2c9a-4788-81d5-cf4f2c8389ec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609326246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3609326246
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.75270444
Short name T123
Test name
Test status
Simulation time 5748184889 ps
CPU time 31.65 seconds
Started Jul 27 04:23:38 PM PDT 24
Finished Jul 27 04:24:10 PM PDT 24
Peak memory 203340 kb
Host smart-c77110ff-0d04-4188-a5d2-3c3354797572
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=75270444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.75270444
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.485924201
Short name T752
Test name
Test status
Simulation time 25226335 ps
CPU time 2.08 seconds
Started Jul 27 04:23:25 PM PDT 24
Finished Jul 27 04:23:27 PM PDT 24
Peak memory 203200 kb
Host smart-03879237-23b8-4b83-bc21-5b827f1d96ad
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485924201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.485924201
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.2683664728
Short name T676
Test name
Test status
Simulation time 220235039 ps
CPU time 14.87 seconds
Started Jul 27 04:23:34 PM PDT 24
Finished Jul 27 04:23:49 PM PDT 24
Peak memory 205380 kb
Host smart-41aa2a62-20de-4721-963e-add689e730e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2683664728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2683664728
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.549701976
Short name T844
Test name
Test status
Simulation time 6845216596 ps
CPU time 118.24 seconds
Started Jul 27 04:23:33 PM PDT 24
Finished Jul 27 04:25:31 PM PDT 24
Peak memory 211468 kb
Host smart-fb53698a-f34c-46de-8236-7d0b53546b13
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=549701976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.549701976
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.178463095
Short name T692
Test name
Test status
Simulation time 5463162894 ps
CPU time 229.35 seconds
Started Jul 27 04:23:36 PM PDT 24
Finished Jul 27 04:27:25 PM PDT 24
Peak memory 209416 kb
Host smart-da2f5280-48f3-4054-9845-8fdcdf187191
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=178463095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand
_reset.178463095
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3329067302
Short name T27
Test name
Test status
Simulation time 1335065788 ps
CPU time 78.33 seconds
Started Jul 27 04:23:36 PM PDT 24
Finished Jul 27 04:24:54 PM PDT 24
Peak memory 208620 kb
Host smart-71698fd0-2205-411e-8d11-fbe43335544c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3329067302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re
set_error.3329067302
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1777674911
Short name T455
Test name
Test status
Simulation time 199248274 ps
CPU time 17.86 seconds
Started Jul 27 04:23:51 PM PDT 24
Finished Jul 27 04:24:09 PM PDT 24
Peak memory 204796 kb
Host smart-07ba041f-e248-46f4-8446-c0ba9ecd859a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1777674911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1777674911
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.3720661675
Short name T75
Test name
Test status
Simulation time 761878204 ps
CPU time 25.03 seconds
Started Jul 27 04:23:54 PM PDT 24
Finished Jul 27 04:24:20 PM PDT 24
Peak memory 204752 kb
Host smart-35eaf371-9158-491d-959b-e3e300940352
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3720661675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3720661675
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3814108030
Short name T567
Test name
Test status
Simulation time 67222532433 ps
CPU time 557.13 seconds
Started Jul 27 04:23:37 PM PDT 24
Finished Jul 27 04:32:54 PM PDT 24
Peak memory 211536 kb
Host smart-9faffd2e-b528-4bee-8941-a29e9760ad3a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3814108030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl
ow_rsp.3814108030
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.369342354
Short name T396
Test name
Test status
Simulation time 259945860 ps
CPU time 9.15 seconds
Started Jul 27 04:23:55 PM PDT 24
Finished Jul 27 04:24:05 PM PDT 24
Peak memory 203252 kb
Host smart-7c36fee8-36a7-4646-ad28-df5bfbed862d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=369342354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.369342354
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.2154346367
Short name T407
Test name
Test status
Simulation time 38917035 ps
CPU time 3.24 seconds
Started Jul 27 04:23:38 PM PDT 24
Finished Jul 27 04:23:42 PM PDT 24
Peak memory 203264 kb
Host smart-ecf7d568-8d1d-413f-b783-9358fc7bacd2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2154346367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2154346367
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.1606443464
Short name T716
Test name
Test status
Simulation time 235768143 ps
CPU time 15.08 seconds
Started Jul 27 04:23:33 PM PDT 24
Finished Jul 27 04:23:48 PM PDT 24
Peak memory 204308 kb
Host smart-8c733862-9046-480a-998f-e1a6603f07ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1606443464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1606443464
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.1770561309
Short name T654
Test name
Test status
Simulation time 43539063101 ps
CPU time 135.78 seconds
Started Jul 27 04:23:38 PM PDT 24
Finished Jul 27 04:25:54 PM PDT 24
Peak memory 211504 kb
Host smart-265fc5db-ae60-4190-aeff-24f07b8d6906
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770561309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1770561309
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1910737349
Short name T628
Test name
Test status
Simulation time 14285940550 ps
CPU time 129.25 seconds
Started Jul 27 04:23:33 PM PDT 24
Finished Jul 27 04:25:42 PM PDT 24
Peak memory 211536 kb
Host smart-76c23b71-ffe0-4679-9f8e-0f96f4054458
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1910737349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1910737349
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.1215324390
Short name T196
Test name
Test status
Simulation time 63375590 ps
CPU time 3.73 seconds
Started Jul 27 04:23:34 PM PDT 24
Finished Jul 27 04:23:38 PM PDT 24
Peak memory 211480 kb
Host smart-a5d349f3-70ce-4af8-9ba2-d1f326742afc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215324390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.1215324390
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.127844475
Short name T376
Test name
Test status
Simulation time 1614647244 ps
CPU time 16.33 seconds
Started Jul 27 04:23:38 PM PDT 24
Finished Jul 27 04:23:54 PM PDT 24
Peak memory 211424 kb
Host smart-d11c2d98-9240-46f0-bf20-9a1da0876c65
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=127844475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.127844475
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.2396910764
Short name T785
Test name
Test status
Simulation time 307633099 ps
CPU time 3.41 seconds
Started Jul 27 04:23:40 PM PDT 24
Finished Jul 27 04:23:43 PM PDT 24
Peak memory 203296 kb
Host smart-41d2f459-658b-4123-875d-723853a6e0ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2396910764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2396910764
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.601317101
Short name T607
Test name
Test status
Simulation time 17477508052 ps
CPU time 31.1 seconds
Started Jul 27 04:23:51 PM PDT 24
Finished Jul 27 04:24:22 PM PDT 24
Peak memory 203120 kb
Host smart-15133526-65b4-4c0b-8721-0d9f64b88a00
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=601317101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.601317101
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.2818989036
Short name T307
Test name
Test status
Simulation time 6391323030 ps
CPU time 31.92 seconds
Started Jul 27 04:23:36 PM PDT 24
Finished Jul 27 04:24:08 PM PDT 24
Peak memory 203384 kb
Host smart-8890c5da-4260-471c-82da-0d87b7ee6be8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2818989036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2818989036
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.145221227
Short name T625
Test name
Test status
Simulation time 44311437 ps
CPU time 2.41 seconds
Started Jul 27 04:23:40 PM PDT 24
Finished Jul 27 04:23:43 PM PDT 24
Peak memory 203272 kb
Host smart-a4cb86d7-2b74-43ba-902c-de350e33713a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145221227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.145221227
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.2738038840
Short name T245
Test name
Test status
Simulation time 1415365481 ps
CPU time 83.47 seconds
Started Jul 27 04:23:34 PM PDT 24
Finished Jul 27 04:24:58 PM PDT 24
Peak memory 207400 kb
Host smart-d793d51d-d1d7-4264-aab0-98e5423c7a77
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2738038840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.2738038840
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.2074688673
Short name T294
Test name
Test status
Simulation time 6420309072 ps
CPU time 199.8 seconds
Started Jul 27 04:23:41 PM PDT 24
Finished Jul 27 04:27:01 PM PDT 24
Peak memory 206784 kb
Host smart-9e092e48-b534-48c2-98b1-1db987f28c6c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2074688673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2074688673
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.2474852637
Short name T525
Test name
Test status
Simulation time 1843625248 ps
CPU time 255.11 seconds
Started Jul 27 04:23:37 PM PDT 24
Finished Jul 27 04:27:52 PM PDT 24
Peak memory 208948 kb
Host smart-d1454a66-62d4-406c-a29d-13e14ccb85f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2474852637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran
d_reset.2474852637
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3689394983
Short name T837
Test name
Test status
Simulation time 189263998 ps
CPU time 52.2 seconds
Started Jul 27 04:23:40 PM PDT 24
Finished Jul 27 04:24:32 PM PDT 24
Peak memory 208080 kb
Host smart-6b9e0dcd-7d02-4e06-8260-5b28a80492e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3689394983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re
set_error.3689394983
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.2362373798
Short name T405
Test name
Test status
Simulation time 900482798 ps
CPU time 7.93 seconds
Started Jul 27 04:23:37 PM PDT 24
Finished Jul 27 04:23:45 PM PDT 24
Peak memory 204708 kb
Host smart-0f92aac6-25d8-472c-90ff-7efae64b17a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2362373798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2362373798
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.782938274
Short name T233
Test name
Test status
Simulation time 151119049 ps
CPU time 15.1 seconds
Started Jul 27 04:18:08 PM PDT 24
Finished Jul 27 04:18:23 PM PDT 24
Peak memory 211768 kb
Host smart-17f7d06d-7cd5-42eb-8441-58c580a93afd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=782938274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.782938274
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.92582380
Short name T869
Test name
Test status
Simulation time 3556333204 ps
CPU time 28.12 seconds
Started Jul 27 04:20:15 PM PDT 24
Finished Jul 27 04:20:43 PM PDT 24
Peak memory 203292 kb
Host smart-1788ad01-b82b-4ada-9f0a-6f50e46f8564
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=92582380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.92582380
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2353498851
Short name T112
Test name
Test status
Simulation time 543582632 ps
CPU time 20.43 seconds
Started Jul 27 04:22:20 PM PDT 24
Finished Jul 27 04:22:40 PM PDT 24
Peak memory 203080 kb
Host smart-83b60e88-be21-4a16-b3e5-2340a8e1ebb6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2353498851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2353498851
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.3443451523
Short name T508
Test name
Test status
Simulation time 87128317 ps
CPU time 6.41 seconds
Started Jul 27 04:23:05 PM PDT 24
Finished Jul 27 04:23:13 PM PDT 24
Peak memory 201756 kb
Host smart-d42bc47a-3371-49f0-9923-3041f4d3a48b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3443451523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3443451523
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.151288445
Short name T602
Test name
Test status
Simulation time 256820461 ps
CPU time 22.43 seconds
Started Jul 27 04:22:20 PM PDT 24
Finished Jul 27 04:22:43 PM PDT 24
Peak memory 211236 kb
Host smart-9d834f93-2012-42d0-970d-870e634d523d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=151288445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.151288445
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.3033983310
Short name T845
Test name
Test status
Simulation time 68892612389 ps
CPU time 205.89 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:25:33 PM PDT 24
Peak memory 204444 kb
Host smart-c68da454-35f0-4456-aa31-2b5c7e633743
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033983310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3033983310
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.754782261
Short name T231
Test name
Test status
Simulation time 21797006141 ps
CPU time 159.76 seconds
Started Jul 27 04:19:55 PM PDT 24
Finished Jul 27 04:22:34 PM PDT 24
Peak memory 204840 kb
Host smart-112bfac6-4d2a-4b18-ac1c-8b967051a110
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=754782261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.754782261
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.3745249800
Short name T15
Test name
Test status
Simulation time 258207394 ps
CPU time 17.41 seconds
Started Jul 27 04:23:03 PM PDT 24
Finished Jul 27 04:23:21 PM PDT 24
Peak memory 204136 kb
Host smart-e0896983-55fc-4218-990c-0d9ee87da243
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745249800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.3745249800
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.1828067145
Short name T551
Test name
Test status
Simulation time 434851046 ps
CPU time 17.74 seconds
Started Jul 27 04:23:09 PM PDT 24
Finished Jul 27 04:23:27 PM PDT 24
Peak memory 211148 kb
Host smart-d897d773-701c-411f-b9f2-8971d308c848
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1828067145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1828067145
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.3134000104
Short name T598
Test name
Test status
Simulation time 1297086324 ps
CPU time 4.59 seconds
Started Jul 27 04:23:19 PM PDT 24
Finished Jul 27 04:23:23 PM PDT 24
Peak memory 203236 kb
Host smart-b3cfc356-22d2-4aea-8a15-513d22527fb2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3134000104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3134000104
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1510041851
Short name T49
Test name
Test status
Simulation time 4754268500 ps
CPU time 23.78 seconds
Started Jul 27 04:22:39 PM PDT 24
Finished Jul 27 04:23:03 PM PDT 24
Peak memory 203244 kb
Host smart-28b876e6-c406-4049-95aa-a46d379e7e18
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510041851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1510041851
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.1566357538
Short name T56
Test name
Test status
Simulation time 2421855630 ps
CPU time 21.63 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:22:28 PM PDT 24
Peak memory 202928 kb
Host smart-8373f4f3-f52b-494c-880a-8d5c47a61de8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1566357538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1566357538
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.3082550029
Short name T579
Test name
Test status
Simulation time 153438003 ps
CPU time 2.48 seconds
Started Jul 27 04:21:01 PM PDT 24
Finished Jul 27 04:21:04 PM PDT 24
Peak memory 203360 kb
Host smart-50508d6e-3be0-4d9e-8c73-b9579b558971
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082550029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.3082550029
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.302942159
Short name T83
Test name
Test status
Simulation time 18646763975 ps
CPU time 312.19 seconds
Started Jul 27 04:21:43 PM PDT 24
Finished Jul 27 04:26:55 PM PDT 24
Peak memory 207248 kb
Host smart-a9d55621-cfb1-430b-b099-f629b812f8b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=302942159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.302942159
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.661432319
Short name T252
Test name
Test status
Simulation time 6424436244 ps
CPU time 116.14 seconds
Started Jul 27 04:19:05 PM PDT 24
Finished Jul 27 04:21:01 PM PDT 24
Peak memory 206196 kb
Host smart-4bda151b-b849-4dee-a7fa-97c5ab919eca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=661432319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.661432319
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.3845721837
Short name T357
Test name
Test status
Simulation time 4390871119 ps
CPU time 365.09 seconds
Started Jul 27 04:22:07 PM PDT 24
Finished Jul 27 04:28:12 PM PDT 24
Peak memory 211320 kb
Host smart-04868ece-ea15-467a-b47b-ae70c43aa1cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3845721837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand
_reset.3845721837
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.502457595
Short name T477
Test name
Test status
Simulation time 76466020 ps
CPU time 18.2 seconds
Started Jul 27 04:18:12 PM PDT 24
Finished Jul 27 04:18:31 PM PDT 24
Peak memory 205572 kb
Host smart-6ea805ab-4c94-4177-99a0-7c5acf3c9dc1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=502457595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rese
t_error.502457595
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.2416162397
Short name T278
Test name
Test status
Simulation time 76250417 ps
CPU time 7.93 seconds
Started Jul 27 04:23:09 PM PDT 24
Finished Jul 27 04:23:17 PM PDT 24
Peak memory 211136 kb
Host smart-55985e38-f0af-4865-94d2-f1de3284d3c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2416162397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2416162397
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.4112771675
Short name T811
Test name
Test status
Simulation time 32083823 ps
CPU time 2.48 seconds
Started Jul 27 04:24:47 PM PDT 24
Finished Jul 27 04:24:50 PM PDT 24
Peak memory 201132 kb
Host smart-9ce47466-6d9b-4367-8a84-6a01e692828a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4112771675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.4112771675
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.893850225
Short name T775
Test name
Test status
Simulation time 21369455149 ps
CPU time 154.24 seconds
Started Jul 27 04:23:38 PM PDT 24
Finished Jul 27 04:26:13 PM PDT 24
Peak memory 204776 kb
Host smart-78407519-3f7b-4393-8388-8f9eefae7be9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=893850225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slo
w_rsp.893850225
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.3223587876
Short name T344
Test name
Test status
Simulation time 54806335 ps
CPU time 4.35 seconds
Started Jul 27 04:23:55 PM PDT 24
Finished Jul 27 04:23:59 PM PDT 24
Peak memory 203064 kb
Host smart-cbb9dbfe-3697-44a6-80c2-ad81bb8f56c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3223587876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.3223587876
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.675627642
Short name T826
Test name
Test status
Simulation time 1225192743 ps
CPU time 10.7 seconds
Started Jul 27 04:23:33 PM PDT 24
Finished Jul 27 04:23:44 PM PDT 24
Peak memory 203272 kb
Host smart-9c77aa86-16f3-49b1-bba7-21333d74d6f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=675627642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.675627642
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.922115368
Short name T85
Test name
Test status
Simulation time 2274076834 ps
CPU time 33.65 seconds
Started Jul 27 04:24:48 PM PDT 24
Finished Jul 27 04:25:21 PM PDT 24
Peak memory 211048 kb
Host smart-5354e596-cadf-4bf4-aba3-9ac74bcb418e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=922115368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.922115368
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.153504255
Short name T564
Test name
Test status
Simulation time 23409193215 ps
CPU time 121.41 seconds
Started Jul 27 04:23:34 PM PDT 24
Finished Jul 27 04:25:36 PM PDT 24
Peak memory 211552 kb
Host smart-ab444b8e-6380-4a50-864d-beade7f0b535
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=153504255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.153504255
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2103489558
Short name T850
Test name
Test status
Simulation time 21707748179 ps
CPU time 46.26 seconds
Started Jul 27 04:25:01 PM PDT 24
Finished Jul 27 04:25:47 PM PDT 24
Peak memory 204384 kb
Host smart-dc901862-6b7f-42e0-a82f-77d374634217
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2103489558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2103489558
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.1326704299
Short name T375
Test name
Test status
Simulation time 73976700 ps
CPU time 5.23 seconds
Started Jul 27 04:23:37 PM PDT 24
Finished Jul 27 04:23:43 PM PDT 24
Peak memory 203376 kb
Host smart-49240db9-5d7b-4297-bdf8-75607663fdbb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326704299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1326704299
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.3792709950
Short name T189
Test name
Test status
Simulation time 86722189 ps
CPU time 6.65 seconds
Started Jul 27 04:23:50 PM PDT 24
Finished Jul 27 04:23:57 PM PDT 24
Peak memory 203728 kb
Host smart-38a8095a-eafc-4320-b6c4-c718328d969e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3792709950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3792709950
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.1893962373
Short name T381
Test name
Test status
Simulation time 182290340 ps
CPU time 3.31 seconds
Started Jul 27 04:23:38 PM PDT 24
Finished Jul 27 04:23:41 PM PDT 24
Peak memory 203292 kb
Host smart-db52f59d-dc12-4a47-b54a-7c2da417dbc6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1893962373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1893962373
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.3322887981
Short name T413
Test name
Test status
Simulation time 4757236646 ps
CPU time 28.82 seconds
Started Jul 27 04:24:47 PM PDT 24
Finished Jul 27 04:25:16 PM PDT 24
Peak memory 201380 kb
Host smart-a6d5df01-8491-476e-a878-3ee30b4497e8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322887981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.3322887981
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.3814604943
Short name T257
Test name
Test status
Simulation time 4955842414 ps
CPU time 34.51 seconds
Started Jul 27 04:23:42 PM PDT 24
Finished Jul 27 04:24:17 PM PDT 24
Peak memory 203336 kb
Host smart-0778568a-bdfe-445d-b96c-d07d53952b81
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3814604943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3814604943
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1759753904
Short name T151
Test name
Test status
Simulation time 89845969 ps
CPU time 2.08 seconds
Started Jul 27 04:23:32 PM PDT 24
Finished Jul 27 04:23:34 PM PDT 24
Peak memory 203312 kb
Host smart-c0557078-2cf5-4501-b183-041d5d2ea127
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759753904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1759753904
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.205650850
Short name T660
Test name
Test status
Simulation time 845931612 ps
CPU time 95.81 seconds
Started Jul 27 04:25:00 PM PDT 24
Finished Jul 27 04:26:36 PM PDT 24
Peak memory 208292 kb
Host smart-4bbdf808-c338-4407-b12f-92158a3a4ecb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=205650850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.205650850
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3733260631
Short name T193
Test name
Test status
Simulation time 545879228 ps
CPU time 22.67 seconds
Started Jul 27 04:25:01 PM PDT 24
Finished Jul 27 04:25:23 PM PDT 24
Peak memory 203892 kb
Host smart-d7d7f51d-662b-485e-bcf6-8af3b8716edb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3733260631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3733260631
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2500765186
Short name T146
Test name
Test status
Simulation time 9161776000 ps
CPU time 522.66 seconds
Started Jul 27 04:23:44 PM PDT 24
Finished Jul 27 04:32:27 PM PDT 24
Peak memory 219820 kb
Host smart-befcc1b5-ce7e-45b3-bda6-6f2a76d80582
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2500765186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran
d_reset.2500765186
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.306830561
Short name T221
Test name
Test status
Simulation time 184413275 ps
CPU time 44.29 seconds
Started Jul 27 04:23:37 PM PDT 24
Finished Jul 27 04:24:22 PM PDT 24
Peak memory 206224 kb
Host smart-3d523d04-d311-480c-add2-9041fe1a3384
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=306830561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_res
et_error.306830561
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.2121245836
Short name T670
Test name
Test status
Simulation time 237105821 ps
CPU time 8.16 seconds
Started Jul 27 04:24:47 PM PDT 24
Finished Jul 27 04:24:56 PM PDT 24
Peak memory 209260 kb
Host smart-58029a47-8753-4ab6-9465-d8d30252abf9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2121245836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2121245836
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.3628721198
Short name T631
Test name
Test status
Simulation time 335670202 ps
CPU time 30 seconds
Started Jul 27 04:24:47 PM PDT 24
Finished Jul 27 04:25:18 PM PDT 24
Peak memory 202364 kb
Host smart-2583cf7d-fdd8-43af-9602-5384786c276f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3628721198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.3628721198
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.4237629016
Short name T891
Test name
Test status
Simulation time 335818441399 ps
CPU time 646.36 seconds
Started Jul 27 04:23:44 PM PDT 24
Finished Jul 27 04:34:31 PM PDT 24
Peak memory 211512 kb
Host smart-68be03a0-39ae-48d0-bef9-11d899e28130
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4237629016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl
ow_rsp.4237629016
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.2958411900
Short name T566
Test name
Test status
Simulation time 426208238 ps
CPU time 5.03 seconds
Started Jul 27 04:23:36 PM PDT 24
Finished Jul 27 04:23:41 PM PDT 24
Peak memory 203216 kb
Host smart-570a0e01-d880-4230-bfd7-e7e3ee45b873
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2958411900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.2958411900
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.2520351441
Short name T666
Test name
Test status
Simulation time 386475408 ps
CPU time 10.54 seconds
Started Jul 27 04:23:41 PM PDT 24
Finished Jul 27 04:23:52 PM PDT 24
Peak memory 203320 kb
Host smart-e69ec876-6871-4659-960d-bd3b0f600443
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2520351441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2520351441
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.1451039122
Short name T518
Test name
Test status
Simulation time 955422138 ps
CPU time 35.08 seconds
Started Jul 27 04:23:36 PM PDT 24
Finished Jul 27 04:24:11 PM PDT 24
Peak memory 211500 kb
Host smart-5c4ac2cf-9f7a-4b97-85c5-f7c84f4f4a4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1451039122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.1451039122
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.3864247748
Short name T780
Test name
Test status
Simulation time 39331005803 ps
CPU time 223.63 seconds
Started Jul 27 04:23:41 PM PDT 24
Finished Jul 27 04:27:25 PM PDT 24
Peak memory 211480 kb
Host smart-bc068d73-7b90-4c83-ab5f-563e6c9ba825
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864247748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3864247748
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2192937651
Short name T456
Test name
Test status
Simulation time 31737932914 ps
CPU time 188.28 seconds
Started Jul 27 04:23:38 PM PDT 24
Finished Jul 27 04:26:46 PM PDT 24
Peak memory 204916 kb
Host smart-c0f1cd9b-b4b9-4e3a-9dac-2ee96031801f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2192937651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2192937651
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.1869139102
Short name T843
Test name
Test status
Simulation time 230260337 ps
CPU time 22.57 seconds
Started Jul 27 04:23:38 PM PDT 24
Finished Jul 27 04:24:00 PM PDT 24
Peak memory 204728 kb
Host smart-601e2411-9949-491e-9d08-0e65c4276781
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869139102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1869139102
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.1296546100
Short name T266
Test name
Test status
Simulation time 891834144 ps
CPU time 9.61 seconds
Started Jul 27 04:23:40 PM PDT 24
Finished Jul 27 04:23:50 PM PDT 24
Peak memory 203332 kb
Host smart-8ae132c7-7947-4fb2-a490-7a0dfbb1dd5d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1296546100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1296546100
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.2484330355
Short name T159
Test name
Test status
Simulation time 645103025 ps
CPU time 4.07 seconds
Started Jul 27 04:24:59 PM PDT 24
Finished Jul 27 04:25:03 PM PDT 24
Peak memory 203220 kb
Host smart-1f84515b-43d2-48f3-aa0e-50af027d5701
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2484330355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2484330355
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2441274592
Short name T675
Test name
Test status
Simulation time 47537744278 ps
CPU time 53.7 seconds
Started Jul 27 04:23:39 PM PDT 24
Finished Jul 27 04:24:33 PM PDT 24
Peak memory 203352 kb
Host smart-83a4cf9f-87cf-44ff-bd1e-1801d0c4b3d6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441274592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2441274592
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.4061989153
Short name T247
Test name
Test status
Simulation time 10732247694 ps
CPU time 34.18 seconds
Started Jul 27 04:25:01 PM PDT 24
Finished Jul 27 04:25:35 PM PDT 24
Peak memory 203296 kb
Host smart-ee420599-b009-4941-a1d5-8f6656aa7e88
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4061989153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.4061989153
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2354174713
Short name T764
Test name
Test status
Simulation time 26844674 ps
CPU time 1.94 seconds
Started Jul 27 04:23:54 PM PDT 24
Finished Jul 27 04:23:56 PM PDT 24
Peak memory 203032 kb
Host smart-3cda0bfa-2ce8-4713-8a2a-317200413e69
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354174713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2354174713
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.688575376
Short name T575
Test name
Test status
Simulation time 1875492522 ps
CPU time 70.23 seconds
Started Jul 27 04:24:47 PM PDT 24
Finished Jul 27 04:25:58 PM PDT 24
Peak memory 204684 kb
Host smart-da8f5013-210f-422c-b4c5-60a60cbe766a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=688575376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.688575376
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2972084510
Short name T186
Test name
Test status
Simulation time 6725664357 ps
CPU time 150.77 seconds
Started Jul 27 04:23:44 PM PDT 24
Finished Jul 27 04:26:15 PM PDT 24
Peak memory 206460 kb
Host smart-b2faeaa3-e908-47fe-bbbc-c2bd71d833e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2972084510 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2972084510
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3284570396
Short name T130
Test name
Test status
Simulation time 7582874724 ps
CPU time 223.08 seconds
Started Jul 27 04:23:37 PM PDT 24
Finished Jul 27 04:27:20 PM PDT 24
Peak memory 208820 kb
Host smart-80959b42-e5f8-4a84-88e4-40ddf52c5b9f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3284570396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran
d_reset.3284570396
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1650316763
Short name T37
Test name
Test status
Simulation time 6143949366 ps
CPU time 219.18 seconds
Started Jul 27 04:23:50 PM PDT 24
Finished Jul 27 04:27:29 PM PDT 24
Peak memory 210696 kb
Host smart-a9959453-9ee5-475e-a8f0-494945f7fc00
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1650316763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re
set_error.1650316763
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.1002023199
Short name T542
Test name
Test status
Simulation time 708836936 ps
CPU time 13.71 seconds
Started Jul 27 04:23:37 PM PDT 24
Finished Jul 27 04:23:51 PM PDT 24
Peak memory 211460 kb
Host smart-2f5c2013-813e-421d-b2ec-c1dc80b1c1a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1002023199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1002023199
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.1064258478
Short name T335
Test name
Test status
Simulation time 1190630141 ps
CPU time 14.24 seconds
Started Jul 27 04:23:44 PM PDT 24
Finished Jul 27 04:23:58 PM PDT 24
Peak memory 211480 kb
Host smart-50d1d651-fd58-4d5f-a6ad-5e4079ad3267
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1064258478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.1064258478
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.3081359247
Short name T64
Test name
Test status
Simulation time 42249453280 ps
CPU time 320.36 seconds
Started Jul 27 04:23:45 PM PDT 24
Finished Jul 27 04:29:06 PM PDT 24
Peak memory 206484 kb
Host smart-9e2342f3-11f4-41d0-a1b7-80e199fd3e05
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3081359247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl
ow_rsp.3081359247
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.3858234787
Short name T385
Test name
Test status
Simulation time 509584522 ps
CPU time 16.94 seconds
Started Jul 27 04:23:51 PM PDT 24
Finished Jul 27 04:24:08 PM PDT 24
Peak memory 203352 kb
Host smart-bfde0dcd-9c3f-4cf8-a9e8-636a4bff14ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3858234787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.3858234787
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.150936422
Short name T591
Test name
Test status
Simulation time 159970166 ps
CPU time 9.08 seconds
Started Jul 27 04:23:44 PM PDT 24
Finished Jul 27 04:23:53 PM PDT 24
Peak memory 203308 kb
Host smart-faa4d4ff-60cd-4184-bce3-39303fe7a5c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=150936422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.150936422
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.2645733936
Short name T581
Test name
Test status
Simulation time 646258622 ps
CPU time 22.04 seconds
Started Jul 27 04:23:44 PM PDT 24
Finished Jul 27 04:24:06 PM PDT 24
Peak memory 211492 kb
Host smart-ac2af9b8-d9cb-450c-bb87-e59e7fc1e577
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2645733936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2645733936
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.517511876
Short name T517
Test name
Test status
Simulation time 46898771453 ps
CPU time 103.94 seconds
Started Jul 27 04:23:48 PM PDT 24
Finished Jul 27 04:25:33 PM PDT 24
Peak memory 211440 kb
Host smart-140162c6-e2d0-47a8-b15e-8550e87ebd40
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=517511876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.517511876
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2395403024
Short name T783
Test name
Test status
Simulation time 30238967255 ps
CPU time 209.91 seconds
Started Jul 27 04:23:56 PM PDT 24
Finished Jul 27 04:27:26 PM PDT 24
Peak memory 204560 kb
Host smart-d4e29e80-b045-4965-8930-1f48faa37035
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2395403024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2395403024
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.1840924313
Short name T860
Test name
Test status
Simulation time 26397315 ps
CPU time 1.83 seconds
Started Jul 27 04:23:49 PM PDT 24
Finished Jul 27 04:23:50 PM PDT 24
Peak memory 203276 kb
Host smart-d489da22-e3ce-4ad4-b62b-8477e637a09c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840924313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.1840924313
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.687747975
Short name T726
Test name
Test status
Simulation time 251810357 ps
CPU time 19.1 seconds
Started Jul 27 04:23:50 PM PDT 24
Finished Jul 27 04:24:09 PM PDT 24
Peak memory 211476 kb
Host smart-b1cffecc-aa56-4357-917a-02af4231d550
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=687747975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.687747975
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.544234064
Short name T746
Test name
Test status
Simulation time 407863103 ps
CPU time 3.65 seconds
Started Jul 27 04:23:50 PM PDT 24
Finished Jul 27 04:23:54 PM PDT 24
Peak memory 203288 kb
Host smart-51bede5a-3f9d-4224-9b7d-c9ef2b08b9a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=544234064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.544234064
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2104268031
Short name T866
Test name
Test status
Simulation time 7187653238 ps
CPU time 31.9 seconds
Started Jul 27 04:23:47 PM PDT 24
Finished Jul 27 04:24:19 PM PDT 24
Peak memory 203360 kb
Host smart-6461ec61-58ec-471f-af84-d00d8519bfec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104268031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2104268031
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3722780848
Short name T248
Test name
Test status
Simulation time 3575354273 ps
CPU time 26.59 seconds
Started Jul 27 04:23:53 PM PDT 24
Finished Jul 27 04:24:20 PM PDT 24
Peak memory 203364 kb
Host smart-7858df5b-8418-4820-8f81-5d592ef1362b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3722780848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3722780848
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3424755554
Short name T101
Test name
Test status
Simulation time 39017145 ps
CPU time 2.12 seconds
Started Jul 27 04:23:52 PM PDT 24
Finished Jul 27 04:23:54 PM PDT 24
Peak memory 203252 kb
Host smart-7c0abc22-5ac9-4ff9-a524-a88848659f24
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424755554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3424755554
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.4211371162
Short name T126
Test name
Test status
Simulation time 2432758529 ps
CPU time 89.93 seconds
Started Jul 27 04:23:45 PM PDT 24
Finished Jul 27 04:25:16 PM PDT 24
Peak memory 208316 kb
Host smart-88058164-977b-4303-a086-9c8be73c62b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4211371162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.4211371162
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3226533855
Short name T762
Test name
Test status
Simulation time 3625640512 ps
CPU time 56.14 seconds
Started Jul 27 04:23:47 PM PDT 24
Finished Jul 27 04:24:43 PM PDT 24
Peak memory 211012 kb
Host smart-6cc0eba5-bc73-49e0-b906-517a543ffe73
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3226533855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3226533855
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1799514404
Short name T861
Test name
Test status
Simulation time 8251737499 ps
CPU time 317 seconds
Started Jul 27 04:23:44 PM PDT 24
Finished Jul 27 04:29:01 PM PDT 24
Peak memory 208852 kb
Host smart-bf100017-d0e3-4aad-aefb-c29643b33250
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1799514404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran
d_reset.1799514404
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.1246456061
Short name T616
Test name
Test status
Simulation time 178589333 ps
CPU time 55.3 seconds
Started Jul 27 04:23:52 PM PDT 24
Finished Jul 27 04:24:47 PM PDT 24
Peak memory 208012 kb
Host smart-e386edf9-6cad-4510-bc66-dfb09ee6159d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1246456061 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re
set_error.1246456061
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.1683691440
Short name T206
Test name
Test status
Simulation time 87516065 ps
CPU time 15.05 seconds
Started Jul 27 04:23:50 PM PDT 24
Finished Jul 27 04:24:06 PM PDT 24
Peak memory 204908 kb
Host smart-8815ae66-05de-4dab-bf66-314e319f5628
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1683691440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.1683691440
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.4029530797
Short name T268
Test name
Test status
Simulation time 297095113 ps
CPU time 14.54 seconds
Started Jul 27 04:23:49 PM PDT 24
Finished Jul 27 04:24:04 PM PDT 24
Peak memory 205044 kb
Host smart-0105e590-7223-4300-b73b-94fa2398acdb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4029530797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.4029530797
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1511305293
Short name T337
Test name
Test status
Simulation time 86806012601 ps
CPU time 613.61 seconds
Started Jul 27 04:23:49 PM PDT 24
Finished Jul 27 04:34:02 PM PDT 24
Peak memory 207540 kb
Host smart-3e019aa2-b0b8-4b8b-8a74-ce4f3e97dd38
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1511305293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl
ow_rsp.1511305293
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.3858762590
Short name T310
Test name
Test status
Simulation time 160876240 ps
CPU time 5.03 seconds
Started Jul 27 04:23:49 PM PDT 24
Finished Jul 27 04:23:55 PM PDT 24
Peak memory 203276 kb
Host smart-4f20b03c-0f32-45e2-aa2b-f0d511a08127
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3858762590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.3858762590
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.4265075029
Short name T639
Test name
Test status
Simulation time 1253455186 ps
CPU time 31.02 seconds
Started Jul 27 04:23:56 PM PDT 24
Finished Jul 27 04:24:27 PM PDT 24
Peak memory 203212 kb
Host smart-8e772405-c6f5-43b1-bb05-8ccf26a35809
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4265075029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.4265075029
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.3577691283
Short name T643
Test name
Test status
Simulation time 1464538088 ps
CPU time 33.37 seconds
Started Jul 27 04:23:51 PM PDT 24
Finished Jul 27 04:24:24 PM PDT 24
Peak memory 211480 kb
Host smart-8b81181e-ffc7-4ff3-abfa-c2d0696a382a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3577691283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.3577691283
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.741168286
Short name T800
Test name
Test status
Simulation time 5840111617 ps
CPU time 29.78 seconds
Started Jul 27 04:23:50 PM PDT 24
Finished Jul 27 04:24:19 PM PDT 24
Peak memory 204392 kb
Host smart-b27f9a7a-334d-42f8-aee6-406d05f7a09f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=741168286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.741168286
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.2992439084
Short name T522
Test name
Test status
Simulation time 90840728619 ps
CPU time 224.16 seconds
Started Jul 27 04:23:55 PM PDT 24
Finished Jul 27 04:27:39 PM PDT 24
Peak memory 211504 kb
Host smart-6946f3d5-bdf7-4b9f-a9e0-9c946095c964
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2992439084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2992439084
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.1707924709
Short name T187
Test name
Test status
Simulation time 26325127 ps
CPU time 3.75 seconds
Started Jul 27 04:23:51 PM PDT 24
Finished Jul 27 04:23:55 PM PDT 24
Peak memory 203336 kb
Host smart-95ac096a-7b30-40fa-81a2-4bff6eb1df78
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707924709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.1707924709
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.1656002874
Short name T156
Test name
Test status
Simulation time 143441114 ps
CPU time 4 seconds
Started Jul 27 04:23:54 PM PDT 24
Finished Jul 27 04:23:58 PM PDT 24
Peak memory 203364 kb
Host smart-52db6c35-a81b-44fb-b3e5-35132cc94d2b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1656002874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1656002874
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.514144788
Short name T479
Test name
Test status
Simulation time 36890692 ps
CPU time 2.08 seconds
Started Jul 27 04:23:54 PM PDT 24
Finished Jul 27 04:23:56 PM PDT 24
Peak memory 203252 kb
Host smart-25601de4-02b7-404a-bc34-2c7c567f8b73
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=514144788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.514144788
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1619235660
Short name T160
Test name
Test status
Simulation time 10146419117 ps
CPU time 36.3 seconds
Started Jul 27 04:23:52 PM PDT 24
Finished Jul 27 04:24:29 PM PDT 24
Peak memory 203352 kb
Host smart-181b218d-5f04-4d0e-9bdf-5eb60ee059fd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619235660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1619235660
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1743100281
Short name T790
Test name
Test status
Simulation time 7898251507 ps
CPU time 30.43 seconds
Started Jul 27 04:23:48 PM PDT 24
Finished Jul 27 04:24:19 PM PDT 24
Peak memory 203352 kb
Host smart-1cfd87ed-7d84-4411-8234-b13b82e349bc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1743100281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1743100281
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.2590526792
Short name T400
Test name
Test status
Simulation time 36743729 ps
CPU time 2.28 seconds
Started Jul 27 04:23:47 PM PDT 24
Finished Jul 27 04:23:50 PM PDT 24
Peak memory 202860 kb
Host smart-06dc111a-5177-4398-a9c6-5a7d5f39f5db
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590526792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.2590526792
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.2139916417
Short name T653
Test name
Test status
Simulation time 16820158357 ps
CPU time 141.37 seconds
Started Jul 27 04:23:47 PM PDT 24
Finished Jul 27 04:26:09 PM PDT 24
Peak memory 208404 kb
Host smart-a13f8cde-0b4e-4381-97ac-994063771765
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2139916417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2139916417
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1505217467
Short name T659
Test name
Test status
Simulation time 3057718765 ps
CPU time 59.26 seconds
Started Jul 27 04:23:54 PM PDT 24
Finished Jul 27 04:24:54 PM PDT 24
Peak memory 211500 kb
Host smart-1c51832e-98f1-4fa2-8a3e-5db4e6cfe490
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1505217467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1505217467
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1438286264
Short name T506
Test name
Test status
Simulation time 786318694 ps
CPU time 217.59 seconds
Started Jul 27 04:23:51 PM PDT 24
Finished Jul 27 04:27:29 PM PDT 24
Peak memory 208740 kb
Host smart-8642c9d8-ff89-4391-9704-92ca9cef4389
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1438286264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran
d_reset.1438286264
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1649898793
Short name T733
Test name
Test status
Simulation time 3265332123 ps
CPU time 117.02 seconds
Started Jul 27 04:23:46 PM PDT 24
Finished Jul 27 04:25:43 PM PDT 24
Peak memory 207948 kb
Host smart-b5164478-a98e-4644-ac38-3110edc62b37
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1649898793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re
set_error.1649898793
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.3535836633
Short name T601
Test name
Test status
Simulation time 741901990 ps
CPU time 28.2 seconds
Started Jul 27 04:23:52 PM PDT 24
Finished Jul 27 04:24:21 PM PDT 24
Peak memory 211460 kb
Host smart-359aa64e-fb3c-42d2-b765-91e0770c5068
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3535836633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3535836633
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.449196226
Short name T548
Test name
Test status
Simulation time 4341101914 ps
CPU time 62.09 seconds
Started Jul 27 04:23:56 PM PDT 24
Finished Jul 27 04:24:58 PM PDT 24
Peak memory 211548 kb
Host smart-b259add7-835a-47d9-af11-6a9683e5bc88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=449196226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.449196226
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3728077543
Short name T133
Test name
Test status
Simulation time 12160626360 ps
CPU time 112.4 seconds
Started Jul 27 04:24:01 PM PDT 24
Finished Jul 27 04:25:54 PM PDT 24
Peak memory 211528 kb
Host smart-4bac096e-c10e-44b4-bc2b-d6e09d179457
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3728077543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl
ow_rsp.3728077543
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2708726255
Short name T492
Test name
Test status
Simulation time 414434587 ps
CPU time 12.18 seconds
Started Jul 27 04:23:55 PM PDT 24
Finished Jul 27 04:24:07 PM PDT 24
Peak memory 203476 kb
Host smart-2d6b88c7-53c5-42cb-b86f-cb33106a1d7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2708726255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2708726255
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.593834142
Short name T708
Test name
Test status
Simulation time 522949526 ps
CPU time 25.67 seconds
Started Jul 27 04:23:54 PM PDT 24
Finished Jul 27 04:24:20 PM PDT 24
Peak memory 203640 kb
Host smart-62eeb34c-aad8-478a-8e88-e44e67df5ab8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=593834142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.593834142
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.248011142
Short name T421
Test name
Test status
Simulation time 628464118 ps
CPU time 25.88 seconds
Started Jul 27 04:23:56 PM PDT 24
Finished Jul 27 04:24:22 PM PDT 24
Peak memory 204764 kb
Host smart-c84208ca-81ee-4892-a004-0da0e1ea92d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=248011142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.248011142
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.3627742011
Short name T497
Test name
Test status
Simulation time 52870115099 ps
CPU time 153.01 seconds
Started Jul 27 04:23:56 PM PDT 24
Finished Jul 27 04:26:29 PM PDT 24
Peak memory 211528 kb
Host smart-3bd744d0-c9f1-4b05-824d-2500d073a4c5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627742011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3627742011
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.150631404
Short name T502
Test name
Test status
Simulation time 15445068987 ps
CPU time 142.81 seconds
Started Jul 27 04:23:54 PM PDT 24
Finished Jul 27 04:26:17 PM PDT 24
Peak memory 211520 kb
Host smart-21615396-d9bf-4884-9533-33fa93df487d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=150631404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.150631404
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.127104998
Short name T642
Test name
Test status
Simulation time 63965620 ps
CPU time 8.21 seconds
Started Jul 27 04:23:57 PM PDT 24
Finished Jul 27 04:24:05 PM PDT 24
Peak memory 211440 kb
Host smart-fd00a7ba-e98e-4241-b55c-8ed703f385e6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127104998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.127104998
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.3837099400
Short name T349
Test name
Test status
Simulation time 82846825 ps
CPU time 3.11 seconds
Started Jul 27 04:23:53 PM PDT 24
Finished Jul 27 04:23:57 PM PDT 24
Peak memory 203368 kb
Host smart-f1786a87-d8c0-49db-b479-84ad764d1f4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3837099400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3837099400
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke.3669731153
Short name T428
Test name
Test status
Simulation time 150385063 ps
CPU time 2.14 seconds
Started Jul 27 04:24:07 PM PDT 24
Finished Jul 27 04:24:10 PM PDT 24
Peak memory 203220 kb
Host smart-53b6c908-4e9f-4393-b057-5940796757c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3669731153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3669731153
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1946090617
Short name T537
Test name
Test status
Simulation time 18603026808 ps
CPU time 33.74 seconds
Started Jul 27 04:23:56 PM PDT 24
Finished Jul 27 04:24:30 PM PDT 24
Peak memory 203336 kb
Host smart-38a8446d-9b9c-4e15-9d37-683bd790aae7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946090617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1946090617
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.310829039
Short name T686
Test name
Test status
Simulation time 9468785859 ps
CPU time 29.59 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:24:35 PM PDT 24
Peak memory 203352 kb
Host smart-cd6307f0-d1a1-4e4e-ab31-428343ab34f4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=310829039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.310829039
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.1302992235
Short name T300
Test name
Test status
Simulation time 114496612 ps
CPU time 2.76 seconds
Started Jul 27 04:23:56 PM PDT 24
Finished Jul 27 04:23:59 PM PDT 24
Peak memory 203296 kb
Host smart-fcbfe3ea-1a6a-4985-9321-67c9937390bd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302992235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.1302992235
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.3364764735
Short name T505
Test name
Test status
Simulation time 8517784873 ps
CPU time 147.18 seconds
Started Jul 27 04:24:02 PM PDT 24
Finished Jul 27 04:26:29 PM PDT 24
Peak memory 208868 kb
Host smart-573cd4d0-2bb3-48b8-9204-e3090879a66d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3364764735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3364764735
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1673846632
Short name T377
Test name
Test status
Simulation time 3328465595 ps
CPU time 91.86 seconds
Started Jul 27 04:24:00 PM PDT 24
Finished Jul 27 04:25:32 PM PDT 24
Peak memory 206288 kb
Host smart-f4ae1376-2c48-400e-b93b-427b1bfa38c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1673846632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1673846632
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1548197385
Short name T534
Test name
Test status
Simulation time 125883183 ps
CPU time 16.53 seconds
Started Jul 27 04:24:10 PM PDT 24
Finished Jul 27 04:24:27 PM PDT 24
Peak memory 206196 kb
Host smart-91064367-05ab-4cfb-8309-8c27b30a2092
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1548197385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran
d_reset.1548197385
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.1576088341
Short name T600
Test name
Test status
Simulation time 964937335 ps
CPU time 17.61 seconds
Started Jul 27 04:24:02 PM PDT 24
Finished Jul 27 04:24:20 PM PDT 24
Peak memory 205192 kb
Host smart-945a9b1a-ebd7-49da-8f78-10df9a5f7d1d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1576088341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re
set_error.1576088341
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.3394633048
Short name T717
Test name
Test status
Simulation time 115358457 ps
CPU time 14.34 seconds
Started Jul 27 04:23:59 PM PDT 24
Finished Jul 27 04:24:13 PM PDT 24
Peak memory 204740 kb
Host smart-132ccd4d-6aca-46f1-9de4-d8a3a6014c68
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3394633048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3394633048
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.2062402049
Short name T353
Test name
Test status
Simulation time 424601998 ps
CPU time 24.49 seconds
Started Jul 27 04:24:03 PM PDT 24
Finished Jul 27 04:24:28 PM PDT 24
Peak memory 205144 kb
Host smart-abf64b5a-11f5-4cd2-bdbc-dbf477925cf9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2062402049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.2062402049
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.4099324893
Short name T771
Test name
Test status
Simulation time 195690117 ps
CPU time 19.36 seconds
Started Jul 27 04:23:56 PM PDT 24
Finished Jul 27 04:24:15 PM PDT 24
Peak memory 204104 kb
Host smart-4d62895a-5db5-4a41-8dce-fe9b1baa4af7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4099324893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.4099324893
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.1253238651
Short name T336
Test name
Test status
Simulation time 755295037 ps
CPU time 27.05 seconds
Started Jul 27 04:23:54 PM PDT 24
Finished Jul 27 04:24:21 PM PDT 24
Peak memory 203268 kb
Host smart-cb7a8bd3-d25f-4329-a1e9-4abfc885a1f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1253238651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1253238651
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.2066196611
Short name T812
Test name
Test status
Simulation time 740397134 ps
CPU time 21.62 seconds
Started Jul 27 04:23:55 PM PDT 24
Finished Jul 27 04:24:16 PM PDT 24
Peak memory 211372 kb
Host smart-253908e0-b796-42f7-81e5-473479e74674
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2066196611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.2066196611
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.3052803748
Short name T742
Test name
Test status
Simulation time 50031663492 ps
CPU time 204.79 seconds
Started Jul 27 04:24:03 PM PDT 24
Finished Jul 27 04:27:28 PM PDT 24
Peak memory 211488 kb
Host smart-1f080d34-3ce7-4cdd-8364-0a8e0992e6b3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052803748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3052803748
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.937543757
Short name T127
Test name
Test status
Simulation time 29531257814 ps
CPU time 148.01 seconds
Started Jul 27 04:24:00 PM PDT 24
Finished Jul 27 04:26:28 PM PDT 24
Peak memory 211456 kb
Host smart-de87b7d1-41e2-456a-84fd-fe14dcac996c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=937543757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.937543757
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.2154557219
Short name T184
Test name
Test status
Simulation time 59741584 ps
CPU time 3.71 seconds
Started Jul 27 04:23:56 PM PDT 24
Finished Jul 27 04:24:00 PM PDT 24
Peak memory 203952 kb
Host smart-119200e0-1dc9-439e-84d2-d8b3152d1de7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154557219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2154557219
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.3833821291
Short name T509
Test name
Test status
Simulation time 252348691 ps
CPU time 6.8 seconds
Started Jul 27 04:23:56 PM PDT 24
Finished Jul 27 04:24:03 PM PDT 24
Peak memory 203320 kb
Host smart-51cf4d98-a031-44e8-bd3a-2cdd8d2db941
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3833821291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3833821291
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.14275819
Short name T411
Test name
Test status
Simulation time 35968281 ps
CPU time 2.24 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:24:08 PM PDT 24
Peak memory 203232 kb
Host smart-da5da25f-b80f-406f-a606-367d26c06760
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=14275819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.14275819
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2543484353
Short name T267
Test name
Test status
Simulation time 14167076133 ps
CPU time 34.31 seconds
Started Jul 27 04:24:04 PM PDT 24
Finished Jul 27 04:24:38 PM PDT 24
Peak memory 203508 kb
Host smart-adb8bb42-98ec-48ae-a54e-926e29bedde2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543484353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2543484353
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.22443725
Short name T847
Test name
Test status
Simulation time 2802241030 ps
CPU time 21.84 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:24:28 PM PDT 24
Peak memory 203292 kb
Host smart-691c9840-c148-4eaa-8314-05843f9ca327
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=22443725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.22443725
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3432966192
Short name T192
Test name
Test status
Simulation time 37227570 ps
CPU time 1.88 seconds
Started Jul 27 04:23:58 PM PDT 24
Finished Jul 27 04:23:59 PM PDT 24
Peak memory 203572 kb
Host smart-b0a848f5-bb3a-4e15-aca5-a66f7d6393be
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432966192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.3432966192
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all.3822559305
Short name T496
Test name
Test status
Simulation time 268439601 ps
CPU time 28.16 seconds
Started Jul 27 04:24:01 PM PDT 24
Finished Jul 27 04:24:30 PM PDT 24
Peak memory 205440 kb
Host smart-70e504cc-6d1c-4b4b-a0c7-f1b8a1b1bc6d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3822559305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3822559305
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.57011288
Short name T585
Test name
Test status
Simulation time 11887156249 ps
CPU time 218.18 seconds
Started Jul 27 04:24:00 PM PDT 24
Finished Jul 27 04:27:38 PM PDT 24
Peak memory 210612 kb
Host smart-34b86ee8-3529-46dd-9414-3e5cc11596a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=57011288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.57011288
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2015724375
Short name T501
Test name
Test status
Simulation time 622875012 ps
CPU time 236.8 seconds
Started Jul 27 04:23:54 PM PDT 24
Finished Jul 27 04:27:51 PM PDT 24
Peak memory 208512 kb
Host smart-f521753c-bc62-4402-8076-c252efc4c16f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2015724375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran
d_reset.2015724375
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1798808150
Short name T35
Test name
Test status
Simulation time 1976216136 ps
CPU time 182.36 seconds
Started Jul 27 04:23:59 PM PDT 24
Finished Jul 27 04:27:01 PM PDT 24
Peak memory 209220 kb
Host smart-cbd5e713-afbe-46fb-8f3f-37ce7b19c7d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1798808150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re
set_error.1798808150
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.361767282
Short name T423
Test name
Test status
Simulation time 266405324 ps
CPU time 5.44 seconds
Started Jul 27 04:23:57 PM PDT 24
Finished Jul 27 04:24:03 PM PDT 24
Peak memory 204404 kb
Host smart-e8d9d091-d11a-46ef-a7ee-e5055362a89a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=361767282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.361767282
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2377694044
Short name T304
Test name
Test status
Simulation time 133311624 ps
CPU time 8.74 seconds
Started Jul 27 04:23:55 PM PDT 24
Finished Jul 27 04:24:04 PM PDT 24
Peak memory 211384 kb
Host smart-59303dc9-0722-464c-b4af-c52ca040efbf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2377694044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2377694044
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.848665450
Short name T782
Test name
Test status
Simulation time 182408159710 ps
CPU time 440.97 seconds
Started Jul 27 04:23:55 PM PDT 24
Finished Jul 27 04:31:16 PM PDT 24
Peak memory 211496 kb
Host smart-fed9ae90-26e7-4de0-b5c4-29b00d068223
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=848665450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slo
w_rsp.848665450
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.972777603
Short name T500
Test name
Test status
Simulation time 2479695927 ps
CPU time 15.25 seconds
Started Jul 27 04:23:57 PM PDT 24
Finished Jul 27 04:24:12 PM PDT 24
Peak memory 203544 kb
Host smart-cdfa40c8-fc31-407f-95b2-37ee0f415160
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=972777603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.972777603
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.2497422761
Short name T770
Test name
Test status
Simulation time 1123452131 ps
CPU time 14.4 seconds
Started Jul 27 04:23:57 PM PDT 24
Finished Jul 27 04:24:12 PM PDT 24
Peak memory 203300 kb
Host smart-21bfdf9c-1fc1-435d-9cb2-d171b137beb3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2497422761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2497422761
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.1791813
Short name T256
Test name
Test status
Simulation time 1755939463 ps
CPU time 38.89 seconds
Started Jul 27 04:24:03 PM PDT 24
Finished Jul 27 04:24:42 PM PDT 24
Peak memory 211432 kb
Host smart-e43a925d-c5be-47ba-b950-8e963e3644d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1791813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.1791813
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.3103767211
Short name T58
Test name
Test status
Simulation time 133741593692 ps
CPU time 254.73 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:28:21 PM PDT 24
Peak memory 211464 kb
Host smart-93894cd8-b56d-4cd9-964f-352e13c3c17b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103767211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3103767211
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2047811105
Short name T7
Test name
Test status
Simulation time 44699697323 ps
CPU time 111.08 seconds
Started Jul 27 04:23:54 PM PDT 24
Finished Jul 27 04:25:46 PM PDT 24
Peak memory 211472 kb
Host smart-15c68063-dc0d-47c6-9a92-09cbf2d0b5cf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2047811105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2047811105
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.1532561718
Short name T705
Test name
Test status
Simulation time 88783237 ps
CPU time 13.07 seconds
Started Jul 27 04:24:03 PM PDT 24
Finished Jul 27 04:24:17 PM PDT 24
Peak memory 204500 kb
Host smart-d75e9de1-cfe6-4e5e-a442-227721d84d6e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532561718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.1532561718
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.2998249979
Short name T745
Test name
Test status
Simulation time 159105769 ps
CPU time 7.92 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:24:14 PM PDT 24
Peak memory 203204 kb
Host smart-9f4f0829-1e5d-4d62-bc43-4bf87f44ad64
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2998249979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2998249979
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.1817212462
Short name T321
Test name
Test status
Simulation time 550437634 ps
CPU time 3.74 seconds
Started Jul 27 04:23:56 PM PDT 24
Finished Jul 27 04:24:00 PM PDT 24
Peak memory 203284 kb
Host smart-58cac695-56ad-4ee9-b557-7d7d363f6f28
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1817212462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1817212462
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.781102383
Short name T272
Test name
Test status
Simulation time 13497127478 ps
CPU time 36.17 seconds
Started Jul 27 04:23:56 PM PDT 24
Finished Jul 27 04:24:32 PM PDT 24
Peak memory 203348 kb
Host smart-64114c4f-da82-4d20-8b46-a5f9ef78728d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=781102383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.781102383
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3442644984
Short name T467
Test name
Test status
Simulation time 4774811892 ps
CPU time 33.18 seconds
Started Jul 27 04:24:00 PM PDT 24
Finished Jul 27 04:24:33 PM PDT 24
Peak memory 203320 kb
Host smart-ebfd1c56-b071-46e6-96da-15f42072a7e6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3442644984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3442644984
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.42880391
Short name T297
Test name
Test status
Simulation time 26185745 ps
CPU time 2.18 seconds
Started Jul 27 04:23:56 PM PDT 24
Finished Jul 27 04:23:58 PM PDT 24
Peak memory 203268 kb
Host smart-5afd9934-451d-4549-98ff-6f281cda6119
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42880391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.42880391
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.493029445
Short name T816
Test name
Test status
Simulation time 10886550136 ps
CPU time 136.65 seconds
Started Jul 27 04:24:04 PM PDT 24
Finished Jul 27 04:26:21 PM PDT 24
Peak memory 208092 kb
Host smart-64b868c3-8850-4383-b498-870064de7bc3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=493029445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.493029445
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.744721916
Short name T688
Test name
Test status
Simulation time 1842132123 ps
CPU time 101.7 seconds
Started Jul 27 04:23:59 PM PDT 24
Finished Jul 27 04:25:41 PM PDT 24
Peak memory 205360 kb
Host smart-c4650ed9-27b7-40ce-9f22-58df886612ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=744721916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.744721916
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1291869656
Short name T620
Test name
Test status
Simulation time 1062661335 ps
CPU time 57.08 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:25:04 PM PDT 24
Peak memory 206508 kb
Host smart-1c6dbc7e-2f80-4308-981d-3e45e50a4429
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1291869656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran
d_reset.1291869656
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2929140119
Short name T291
Test name
Test status
Simulation time 268826924 ps
CPU time 58.82 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:25:15 PM PDT 24
Peak memory 207944 kb
Host smart-5d87921f-2e4a-45be-8595-3c3e83370a8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2929140119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re
set_error.2929140119
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.2169156974
Short name T454
Test name
Test status
Simulation time 32764473 ps
CPU time 4.83 seconds
Started Jul 27 04:23:54 PM PDT 24
Finished Jul 27 04:23:59 PM PDT 24
Peak memory 211512 kb
Host smart-62bf67cd-e36d-4d5f-80b9-151793d25415
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2169156974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2169156974
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.2664053520
Short name T163
Test name
Test status
Simulation time 1117734071 ps
CPU time 26.66 seconds
Started Jul 27 04:24:05 PM PDT 24
Finished Jul 27 04:24:32 PM PDT 24
Peak memory 204472 kb
Host smart-8d33bc68-067b-4075-ab68-ff8bc72ab693
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2664053520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.2664053520
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1836593404
Short name T815
Test name
Test status
Simulation time 62108229383 ps
CPU time 536.6 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:33:03 PM PDT 24
Peak memory 211580 kb
Host smart-d9a2fa1a-7889-4fc0-9788-dad101427062
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1836593404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl
ow_rsp.1836593404
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3276997049
Short name T646
Test name
Test status
Simulation time 746344391 ps
CPU time 20.45 seconds
Started Jul 27 04:24:05 PM PDT 24
Finished Jul 27 04:24:26 PM PDT 24
Peak memory 203324 kb
Host smart-84130bec-32e2-485b-84fc-95078c1016b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3276997049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.3276997049
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.3505981910
Short name T667
Test name
Test status
Simulation time 3306644999 ps
CPU time 24.17 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:24:31 PM PDT 24
Peak memory 203404 kb
Host smart-d49f95ab-485d-4964-9a8a-11e45fd539ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3505981910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3505981910
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.744507654
Short name T725
Test name
Test status
Simulation time 76479064 ps
CPU time 2.86 seconds
Started Jul 27 04:24:01 PM PDT 24
Finished Jul 27 04:24:04 PM PDT 24
Peak memory 203240 kb
Host smart-1be862f9-e085-4510-82dd-416735758e53
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=744507654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.744507654
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.4040864431
Short name T873
Test name
Test status
Simulation time 102845041458 ps
CPU time 201.18 seconds
Started Jul 27 04:24:05 PM PDT 24
Finished Jul 27 04:27:26 PM PDT 24
Peak memory 204740 kb
Host smart-272c5161-63a7-41dc-aab6-4aad8d028bad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040864431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.4040864431
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2787280986
Short name T138
Test name
Test status
Simulation time 33535629079 ps
CPU time 220.8 seconds
Started Jul 27 04:24:08 PM PDT 24
Finished Jul 27 04:27:49 PM PDT 24
Peak memory 205140 kb
Host smart-ed21de5d-2b2d-4a0b-85d6-7f6c65b94321
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2787280986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2787280986
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.962349649
Short name T520
Test name
Test status
Simulation time 297570356 ps
CPU time 24.02 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:24:31 PM PDT 24
Peak memory 211444 kb
Host smart-57bebaee-9b04-4d46-ae41-79c69f64f5ef
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962349649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.962349649
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.1686058866
Short name T295
Test name
Test status
Simulation time 1170360050 ps
CPU time 17.58 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:24:23 PM PDT 24
Peak memory 203856 kb
Host smart-effe1e43-b15c-44e0-8329-82f2f2b8fb05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1686058866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1686058866
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.2166337710
Short name T626
Test name
Test status
Simulation time 216692753 ps
CPU time 2.78 seconds
Started Jul 27 04:24:05 PM PDT 24
Finished Jul 27 04:24:08 PM PDT 24
Peak memory 203248 kb
Host smart-11517838-bba7-4c1e-9d91-5ed25e1f700a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2166337710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2166337710
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2348715459
Short name T897
Test name
Test status
Simulation time 36205358334 ps
CPU time 52.48 seconds
Started Jul 27 04:24:07 PM PDT 24
Finished Jul 27 04:25:00 PM PDT 24
Peak memory 203280 kb
Host smart-b98f3ace-4fac-4035-b9ae-842ea7acb938
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348715459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2348715459
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2985309168
Short name T152
Test name
Test status
Simulation time 3286860328 ps
CPU time 22.35 seconds
Started Jul 27 04:23:54 PM PDT 24
Finished Jul 27 04:24:17 PM PDT 24
Peak memory 203244 kb
Host smart-f7b1fc8c-ceaa-491e-9a8b-2884e523545d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2985309168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2985309168
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1873039680
Short name T70
Test name
Test status
Simulation time 52890652 ps
CPU time 1.97 seconds
Started Jul 27 04:24:05 PM PDT 24
Finished Jul 27 04:24:07 PM PDT 24
Peak memory 203252 kb
Host smart-aba74fa9-c9e8-4df5-be6d-fd32d7181a34
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873039680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1873039680
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.32378741
Short name T806
Test name
Test status
Simulation time 4312255403 ps
CPU time 135.66 seconds
Started Jul 27 04:24:10 PM PDT 24
Finished Jul 27 04:26:26 PM PDT 24
Peak memory 209248 kb
Host smart-862a6a29-32ee-4003-91de-14eb202af251
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=32378741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.32378741
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3887856189
Short name T290
Test name
Test status
Simulation time 5904028495 ps
CPU time 183.05 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:27:09 PM PDT 24
Peak memory 207772 kb
Host smart-e8fd4ebe-7d79-4b0b-8e14-0a333e281996
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3887856189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3887856189
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2763104334
Short name T29
Test name
Test status
Simulation time 315185762 ps
CPU time 156.46 seconds
Started Jul 27 04:24:09 PM PDT 24
Finished Jul 27 04:26:45 PM PDT 24
Peak memory 208480 kb
Host smart-2386ba80-8e6e-4de7-8071-0fea03e999af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2763104334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran
d_reset.2763104334
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3115363548
Short name T327
Test name
Test status
Simulation time 13146783569 ps
CPU time 319.13 seconds
Started Jul 27 04:24:05 PM PDT 24
Finished Jul 27 04:29:24 PM PDT 24
Peak memory 219640 kb
Host smart-74985945-bcb4-4880-8574-60bffa3994d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3115363548 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re
set_error.3115363548
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.4165465120
Short name T136
Test name
Test status
Simulation time 211391654 ps
CPU time 7.57 seconds
Started Jul 27 04:24:10 PM PDT 24
Finished Jul 27 04:24:18 PM PDT 24
Peak memory 211424 kb
Host smart-1c2421d8-c77f-4b6d-962c-6403ea13d955
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4165465120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.4165465120
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.2174662671
Short name T487
Test name
Test status
Simulation time 5209140450 ps
CPU time 31.92 seconds
Started Jul 27 04:24:05 PM PDT 24
Finished Jul 27 04:24:37 PM PDT 24
Peak memory 211556 kb
Host smart-840e1e26-7241-460d-a720-8eb5b2f0d8ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2174662671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2174662671
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2083889700
Short name T320
Test name
Test status
Simulation time 89999256037 ps
CPU time 284.18 seconds
Started Jul 27 04:24:09 PM PDT 24
Finished Jul 27 04:28:53 PM PDT 24
Peak memory 211468 kb
Host smart-e0efa748-3b8e-4f13-8345-68d6a8fbde1c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2083889700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl
ow_rsp.2083889700
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.2971113274
Short name T347
Test name
Test status
Simulation time 445548644 ps
CPU time 13.31 seconds
Started Jul 27 04:24:10 PM PDT 24
Finished Jul 27 04:24:23 PM PDT 24
Peak memory 203764 kb
Host smart-84f67ea7-08f5-4f50-9b45-586c12b6ddad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2971113274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.2971113274
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.430624525
Short name T340
Test name
Test status
Simulation time 295490595 ps
CPU time 11.77 seconds
Started Jul 27 04:24:04 PM PDT 24
Finished Jul 27 04:24:16 PM PDT 24
Peak memory 203280 kb
Host smart-3cf75592-b6c7-4571-86d7-dd908171b528
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=430624525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.430624525
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.4138429582
Short name T699
Test name
Test status
Simulation time 112130858 ps
CPU time 18.05 seconds
Started Jul 27 04:24:07 PM PDT 24
Finished Jul 27 04:24:25 PM PDT 24
Peak memory 204300 kb
Host smart-d96c48d2-5685-4eb4-a71d-90768a627ad7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4138429582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.4138429582
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.843198855
Short name T888
Test name
Test status
Simulation time 32155795585 ps
CPU time 155.02 seconds
Started Jul 27 04:24:05 PM PDT 24
Finished Jul 27 04:26:40 PM PDT 24
Peak memory 211568 kb
Host smart-69a358e5-14ee-4102-ad3e-d6e37aa74e39
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=843198855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.843198855
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.4131518259
Short name T214
Test name
Test status
Simulation time 124345721488 ps
CPU time 249.59 seconds
Started Jul 27 04:24:07 PM PDT 24
Finished Jul 27 04:28:17 PM PDT 24
Peak memory 205112 kb
Host smart-d67e6f4d-73a9-4ef3-bac1-3d807e01069d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4131518259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.4131518259
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.4128963633
Short name T486
Test name
Test status
Simulation time 347507731 ps
CPU time 22.37 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:24:29 PM PDT 24
Peak memory 211440 kb
Host smart-fe845853-7237-4456-a98a-f6f055d08840
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128963633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.4128963633
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.3317237524
Short name T316
Test name
Test status
Simulation time 2201890450 ps
CPU time 27.34 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:24:34 PM PDT 24
Peak memory 211920 kb
Host smart-a6d317fb-e42b-4373-a755-13fcb1292038
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3317237524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3317237524
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.137438900
Short name T469
Test name
Test status
Simulation time 141196818 ps
CPU time 3.24 seconds
Started Jul 27 04:24:08 PM PDT 24
Finished Jul 27 04:24:11 PM PDT 24
Peak memory 203252 kb
Host smart-48c459db-2a16-4110-8294-2c049f015e8d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=137438900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.137438900
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.333297094
Short name T361
Test name
Test status
Simulation time 18172536698 ps
CPU time 33.01 seconds
Started Jul 27 04:24:08 PM PDT 24
Finished Jul 27 04:24:41 PM PDT 24
Peak memory 203380 kb
Host smart-1baa0d0b-a774-4d58-b605-156e0eda3847
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=333297094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.333297094
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.738128527
Short name T308
Test name
Test status
Simulation time 10985687250 ps
CPU time 40.43 seconds
Started Jul 27 04:24:05 PM PDT 24
Finished Jul 27 04:24:45 PM PDT 24
Peak memory 203336 kb
Host smart-f9798ae5-0b7b-4e40-82a7-42c79d1fcf83
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=738128527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.738128527
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.108550430
Short name T635
Test name
Test status
Simulation time 82938883 ps
CPU time 2.3 seconds
Started Jul 27 04:24:10 PM PDT 24
Finished Jul 27 04:24:12 PM PDT 24
Peak memory 203232 kb
Host smart-799322d0-6f09-4a3a-b32e-e77344b38d38
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108550430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.108550430
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.1853720736
Short name T175
Test name
Test status
Simulation time 1478509166 ps
CPU time 99.22 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:25:45 PM PDT 24
Peak memory 207404 kb
Host smart-fe190d96-5760-42f5-8eb6-e4a6876bcee1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1853720736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1853720736
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2655060713
Short name T696
Test name
Test status
Simulation time 182406697 ps
CPU time 19.92 seconds
Started Jul 27 04:24:07 PM PDT 24
Finished Jul 27 04:24:27 PM PDT 24
Peak memory 203896 kb
Host smart-2f1c07af-545f-4749-8581-8cc3929722dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2655060713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2655060713
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.620016278
Short name T188
Test name
Test status
Simulation time 2240509677 ps
CPU time 164.17 seconds
Started Jul 27 04:24:11 PM PDT 24
Finished Jul 27 04:26:55 PM PDT 24
Peak memory 208516 kb
Host smart-396c5efb-2292-4d97-ab72-a362737b80f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=620016278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand
_reset.620016278
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1595686700
Short name T90
Test name
Test status
Simulation time 7911986612 ps
CPU time 92.28 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:25:38 PM PDT 24
Peak memory 208928 kb
Host smart-707b0961-a6e4-4294-b42a-d1b669697ed7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1595686700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re
set_error.1595686700
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.3281732613
Short name T732
Test name
Test status
Simulation time 813783448 ps
CPU time 12.79 seconds
Started Jul 27 04:24:04 PM PDT 24
Finished Jul 27 04:24:17 PM PDT 24
Peak memory 211480 kb
Host smart-6c016db0-fde3-4e3b-8941-c88b8074612b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3281732613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3281732613
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.1577742022
Short name T180
Test name
Test status
Simulation time 263899928 ps
CPU time 22.32 seconds
Started Jul 27 04:24:11 PM PDT 24
Finished Jul 27 04:24:38 PM PDT 24
Peak memory 205468 kb
Host smart-0395e2f9-1ada-40d3-9172-82823d7d2cd6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1577742022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.1577742022
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.931874584
Short name T760
Test name
Test status
Simulation time 93292462012 ps
CPU time 611.82 seconds
Started Jul 27 04:24:09 PM PDT 24
Finished Jul 27 04:34:21 PM PDT 24
Peak memory 211556 kb
Host smart-feebde89-8a6f-426f-a0f2-7168170fc88a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=931874584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slo
w_rsp.931874584
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.510905111
Short name T420
Test name
Test status
Simulation time 211655422 ps
CPU time 7.58 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:24:14 PM PDT 24
Peak memory 203336 kb
Host smart-acb56f07-ba62-4b44-9ccd-857dadc1e991
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=510905111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.510905111
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.1318020506
Short name T92
Test name
Test status
Simulation time 135746550 ps
CPU time 17.09 seconds
Started Jul 27 04:24:10 PM PDT 24
Finished Jul 27 04:24:27 PM PDT 24
Peak memory 203276 kb
Host smart-77a18202-10a3-4ccc-a492-71405be3afd2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1318020506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.1318020506
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.1590861250
Short name T871
Test name
Test status
Simulation time 494577090 ps
CPU time 13.31 seconds
Started Jul 27 04:24:05 PM PDT 24
Finished Jul 27 04:24:18 PM PDT 24
Peak memory 211388 kb
Host smart-452635d7-c372-4d47-8ead-d429851dbfc5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1590861250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.1590861250
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.1740005726
Short name T177
Test name
Test status
Simulation time 112694352989 ps
CPU time 188.99 seconds
Started Jul 27 04:24:04 PM PDT 24
Finished Jul 27 04:27:13 PM PDT 24
Peak memory 211492 kb
Host smart-3e5d2f10-bc65-4e44-aa5c-5668d74170f9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740005726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1740005726
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3082808829
Short name T419
Test name
Test status
Simulation time 4761663705 ps
CPU time 24.14 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:24:31 PM PDT 24
Peak memory 211420 kb
Host smart-b09593a8-c157-4fd4-8e3c-1cf64eb63813
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3082808829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3082808829
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.965301161
Short name T360
Test name
Test status
Simulation time 181425425 ps
CPU time 16.77 seconds
Started Jul 27 04:24:11 PM PDT 24
Finished Jul 27 04:24:28 PM PDT 24
Peak memory 204380 kb
Host smart-f72bc461-5986-4e10-9ed0-234de1376eda
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965301161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.965301161
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.441367438
Short name T617
Test name
Test status
Simulation time 1152833555 ps
CPU time 18.74 seconds
Started Jul 27 04:24:07 PM PDT 24
Finished Jul 27 04:24:26 PM PDT 24
Peak memory 203816 kb
Host smart-0a75d463-3497-4606-b6d1-276c421ece82
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=441367438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.441367438
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.1219820987
Short name T170
Test name
Test status
Simulation time 142646315 ps
CPU time 3.78 seconds
Started Jul 27 04:24:03 PM PDT 24
Finished Jul 27 04:24:07 PM PDT 24
Peak memory 203248 kb
Host smart-4b0c6590-3d44-4b29-8eb3-5b9fd1867ffe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1219820987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1219820987
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1307284971
Short name T552
Test name
Test status
Simulation time 18769541824 ps
CPU time 33.51 seconds
Started Jul 27 04:24:07 PM PDT 24
Finished Jul 27 04:24:41 PM PDT 24
Peak memory 203364 kb
Host smart-27570b3b-a63f-444c-b73d-a4055734129a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307284971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1307284971
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1447135052
Short name T445
Test name
Test status
Simulation time 4151925808 ps
CPU time 22.7 seconds
Started Jul 27 04:24:05 PM PDT 24
Finished Jul 27 04:24:28 PM PDT 24
Peak memory 203360 kb
Host smart-4c5e5eee-88b1-4a84-b4c2-f2a0e33b6435
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1447135052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1447135052
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3725261419
Short name T794
Test name
Test status
Simulation time 58238107 ps
CPU time 2.44 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:24:09 PM PDT 24
Peak memory 203248 kb
Host smart-4bfe35d4-13d0-43c6-8f03-ea70c54ab266
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725261419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3725261419
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.908799744
Short name T203
Test name
Test status
Simulation time 320785567 ps
CPU time 7.02 seconds
Started Jul 27 04:24:10 PM PDT 24
Finished Jul 27 04:24:18 PM PDT 24
Peak memory 204988 kb
Host smart-3e0ea9f6-1c51-4417-9db0-c073bc7ae29c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=908799744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.908799744
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.3628062002
Short name T158
Test name
Test status
Simulation time 8211276024 ps
CPU time 206.78 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:27:33 PM PDT 24
Peak memory 209596 kb
Host smart-9a69047f-ab1c-45a6-a1b1-46573eb9b9a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3628062002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3628062002
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1028985241
Short name T805
Test name
Test status
Simulation time 328614178 ps
CPU time 167.55 seconds
Started Jul 27 04:24:07 PM PDT 24
Finished Jul 27 04:26:55 PM PDT 24
Peak memory 208432 kb
Host smart-a2093d91-6503-4cd3-afbc-1151aaafa03c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1028985241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran
d_reset.1028985241
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.3710825880
Short name T613
Test name
Test status
Simulation time 159498041 ps
CPU time 77.82 seconds
Started Jul 27 04:24:09 PM PDT 24
Finished Jul 27 04:25:27 PM PDT 24
Peak memory 208524 kb
Host smart-0fd57bae-b131-456d-8c4c-10e699866347
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3710825880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re
set_error.3710825880
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.4246856243
Short name T334
Test name
Test status
Simulation time 648596097 ps
CPU time 17.96 seconds
Started Jul 27 04:24:06 PM PDT 24
Finished Jul 27 04:24:24 PM PDT 24
Peak memory 211488 kb
Host smart-99a03632-8dc4-49e9-bbcc-1b93f04799f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4246856243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.4246856243
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.3238313550
Short name T485
Test name
Test status
Simulation time 621779916 ps
CPU time 22.81 seconds
Started Jul 27 04:19:33 PM PDT 24
Finished Jul 27 04:19:56 PM PDT 24
Peak memory 204444 kb
Host smart-6c2168ca-61c2-4ff2-997c-741036a71ea0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3238313550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3238313550
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.185417267
Short name T65
Test name
Test status
Simulation time 122643262230 ps
CPU time 530.33 seconds
Started Jul 27 04:17:44 PM PDT 24
Finished Jul 27 04:26:35 PM PDT 24
Peak memory 207156 kb
Host smart-c9d06564-8658-4459-9c93-af1596939269
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=185417267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow
_rsp.185417267
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.446333955
Short name T565
Test name
Test status
Simulation time 458586239 ps
CPU time 13.75 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:22:20 PM PDT 24
Peak memory 203312 kb
Host smart-b569897e-0e52-4a2c-aa6b-f712f42b2392
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=446333955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.446333955
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.1853712014
Short name T403
Test name
Test status
Simulation time 268400086 ps
CPU time 2.64 seconds
Started Jul 27 04:22:05 PM PDT 24
Finished Jul 27 04:22:08 PM PDT 24
Peak memory 202288 kb
Host smart-80ad3214-1082-4138-a7a3-6fb7e9f12923
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1853712014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1853712014
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.3320796479
Short name T722
Test name
Test status
Simulation time 67013796 ps
CPU time 2.78 seconds
Started Jul 27 04:23:42 PM PDT 24
Finished Jul 27 04:23:45 PM PDT 24
Peak memory 203032 kb
Host smart-171fc354-d137-43b4-83cd-204ec8122469
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3320796479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.3320796479
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.4034760950
Short name T200
Test name
Test status
Simulation time 33812053692 ps
CPU time 209.05 seconds
Started Jul 27 04:23:41 PM PDT 24
Finished Jul 27 04:27:10 PM PDT 24
Peak memory 211292 kb
Host smart-4e50fe42-2d26-41c3-8aed-1fc001cf6bca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034760950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.4034760950
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.2502630538
Short name T452
Test name
Test status
Simulation time 31340003627 ps
CPU time 106.34 seconds
Started Jul 27 04:18:36 PM PDT 24
Finished Jul 27 04:20:22 PM PDT 24
Peak memory 211556 kb
Host smart-e5e1feac-c420-4c8b-9654-d50694d498b2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2502630538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2502630538
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.3476992103
Short name T493
Test name
Test status
Simulation time 36630047 ps
CPU time 4.25 seconds
Started Jul 27 04:23:42 PM PDT 24
Finished Jul 27 04:23:47 PM PDT 24
Peak memory 203076 kb
Host smart-648b21e6-687e-4d84-ae80-bd45d49cdc5f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476992103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3476992103
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.2563703427
Short name T167
Test name
Test status
Simulation time 1210966546 ps
CPU time 23.76 seconds
Started Jul 27 04:19:30 PM PDT 24
Finished Jul 27 04:19:54 PM PDT 24
Peak memory 203868 kb
Host smart-fcf956d5-35b7-4da0-845b-9074e8a966d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2563703427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2563703427
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.1449071623
Short name T168
Test name
Test status
Simulation time 194399939 ps
CPU time 3.33 seconds
Started Jul 27 04:17:57 PM PDT 24
Finished Jul 27 04:18:00 PM PDT 24
Peak memory 203076 kb
Host smart-6a95fc21-c1af-4f5c-9e0c-cb68839b543d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1449071623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1449071623
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.4151019964
Short name T836
Test name
Test status
Simulation time 7220410006 ps
CPU time 24.18 seconds
Started Jul 27 04:23:05 PM PDT 24
Finished Jul 27 04:23:30 PM PDT 24
Peak memory 201948 kb
Host smart-fc8351ef-85b0-4f8e-b460-03e17d321ac4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151019964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.4151019964
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.2361420102
Short name T808
Test name
Test status
Simulation time 3591528012 ps
CPU time 30.39 seconds
Started Jul 27 04:23:50 PM PDT 24
Finished Jul 27 04:24:20 PM PDT 24
Peak memory 203372 kb
Host smart-f61b7980-61bc-4eca-a6b5-6eb8be72113d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2361420102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2361420102
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.2028968489
Short name T390
Test name
Test status
Simulation time 29938780 ps
CPU time 2.17 seconds
Started Jul 27 04:17:56 PM PDT 24
Finished Jul 27 04:17:58 PM PDT 24
Peak memory 203028 kb
Host smart-7c0416d1-6808-45ed-a0c1-754ad019b69a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028968489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.2028968489
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.2706921940
Short name T834
Test name
Test status
Simulation time 10813963442 ps
CPU time 159.81 seconds
Started Jul 27 04:18:22 PM PDT 24
Finished Jul 27 04:21:02 PM PDT 24
Peak memory 209416 kb
Host smart-e2f45da9-8d84-4c47-9f23-7ba0a849cecd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2706921940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2706921940
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.3992113570
Short name T755
Test name
Test status
Simulation time 410434677 ps
CPU time 40.47 seconds
Started Jul 27 04:19:32 PM PDT 24
Finished Jul 27 04:20:13 PM PDT 24
Peak memory 204736 kb
Host smart-f1893a0b-5559-4dc6-9df1-c552c6975318
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3992113570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3992113570
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.2867784491
Short name T453
Test name
Test status
Simulation time 5844050525 ps
CPU time 408.31 seconds
Started Jul 27 04:22:21 PM PDT 24
Finished Jul 27 04:29:09 PM PDT 24
Peak memory 210768 kb
Host smart-73733bf0-7d24-4894-9adf-3c3b376a4517
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2867784491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand
_reset.2867784491
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.393591994
Short name T23
Test name
Test status
Simulation time 470842815 ps
CPU time 66.9 seconds
Started Jul 27 04:22:51 PM PDT 24
Finished Jul 27 04:23:58 PM PDT 24
Peak memory 208236 kb
Host smart-68eca1df-907f-429a-a4be-b29704a0947b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=393591994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rese
t_error.393591994
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.4031074344
Short name T478
Test name
Test status
Simulation time 82639854 ps
CPU time 8.42 seconds
Started Jul 27 04:19:30 PM PDT 24
Finished Jul 27 04:19:38 PM PDT 24
Peak memory 204772 kb
Host smart-caf07b74-d1bf-4cb6-9a18-614538617911
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4031074344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.4031074344
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.3933950555
Short name T96
Test name
Test status
Simulation time 332565919 ps
CPU time 7.27 seconds
Started Jul 27 04:18:14 PM PDT 24
Finished Jul 27 04:18:21 PM PDT 24
Peak memory 203384 kb
Host smart-25e33dad-d5b7-40ec-aa8a-43a544373512
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3933950555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.3933950555
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.2387611318
Short name T629
Test name
Test status
Simulation time 36004117047 ps
CPU time 325.29 seconds
Started Jul 27 04:19:16 PM PDT 24
Finished Jul 27 04:24:41 PM PDT 24
Peak memory 211948 kb
Host smart-32670b63-246d-4b14-a5f3-7e6a0aada151
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2387611318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo
w_rsp.2387611318
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.1968910653
Short name T683
Test name
Test status
Simulation time 529831312 ps
CPU time 10.61 seconds
Started Jul 27 04:19:56 PM PDT 24
Finished Jul 27 04:20:06 PM PDT 24
Peak memory 203504 kb
Host smart-c5ea0581-26e2-4fdf-973e-04762ebde60f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1968910653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.1968910653
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.1645190705
Short name T435
Test name
Test status
Simulation time 497795236 ps
CPU time 8.83 seconds
Started Jul 27 04:19:09 PM PDT 24
Finished Jul 27 04:19:17 PM PDT 24
Peak memory 203572 kb
Host smart-74d5a169-5ae2-4b24-b4d3-4970aab1ccdf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1645190705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1645190705
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.3597264380
Short name T48
Test name
Test status
Simulation time 873380387 ps
CPU time 8.04 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:22:14 PM PDT 24
Peak memory 210748 kb
Host smart-563d4f30-8b99-428f-a892-2d5f8ad4a5c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3597264380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.3597264380
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.1902844869
Short name T298
Test name
Test status
Simulation time 5275812442 ps
CPU time 29.54 seconds
Started Jul 27 04:22:49 PM PDT 24
Finished Jul 27 04:23:19 PM PDT 24
Peak memory 203896 kb
Host smart-727bf6aa-6265-4fad-b182-0ee9e50cd7f4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902844869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1902844869
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.4220898241
Short name T640
Test name
Test status
Simulation time 40918745258 ps
CPU time 144.28 seconds
Started Jul 27 04:20:59 PM PDT 24
Finished Jul 27 04:23:24 PM PDT 24
Peak memory 211556 kb
Host smart-903899ef-f57e-4038-9e0d-ae9e6ddadfb9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4220898241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.4220898241
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.4100269433
Short name T818
Test name
Test status
Simulation time 152758328 ps
CPU time 19.81 seconds
Started Jul 27 04:23:16 PM PDT 24
Finished Jul 27 04:23:36 PM PDT 24
Peak memory 211404 kb
Host smart-29ea233f-18a6-43ed-a703-8ce2c5abf5a4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100269433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.4100269433
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.899490106
Short name T574
Test name
Test status
Simulation time 191684782 ps
CPU time 15.2 seconds
Started Jul 27 04:18:56 PM PDT 24
Finished Jul 27 04:19:11 PM PDT 24
Peak memory 211560 kb
Host smart-29d30194-c218-4c99-a85f-76cb85384e02
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=899490106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.899490106
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.4042870033
Short name T270
Test name
Test status
Simulation time 42581056 ps
CPU time 2.51 seconds
Started Jul 27 04:20:51 PM PDT 24
Finished Jul 27 04:20:54 PM PDT 24
Peak memory 203188 kb
Host smart-775afb00-f9e1-4d73-8041-91614315b54f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4042870033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.4042870033
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.454139656
Short name T279
Test name
Test status
Simulation time 26253841015 ps
CPU time 37.1 seconds
Started Jul 27 04:19:43 PM PDT 24
Finished Jul 27 04:20:20 PM PDT 24
Peak memory 203752 kb
Host smart-58d6e4f0-0c51-44c0-8339-7c9b021fe1b9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=454139656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.454139656
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.1292414526
Short name T150
Test name
Test status
Simulation time 5747930678 ps
CPU time 19.57 seconds
Started Jul 27 04:22:07 PM PDT 24
Finished Jul 27 04:22:27 PM PDT 24
Peak memory 203080 kb
Host smart-48f2c3cb-7048-423a-85b0-0e0dc692d889
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1292414526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1292414526
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.3674155481
Short name T503
Test name
Test status
Simulation time 31647205 ps
CPU time 2.47 seconds
Started Jul 27 04:19:40 PM PDT 24
Finished Jul 27 04:19:43 PM PDT 24
Peak memory 203332 kb
Host smart-e99523f6-3f04-458b-bc0b-dca2852b472f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674155481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.3674155481
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.2038955179
Short name T110
Test name
Test status
Simulation time 23681345738 ps
CPU time 159.5 seconds
Started Jul 27 04:18:07 PM PDT 24
Finished Jul 27 04:20:47 PM PDT 24
Peak memory 209212 kb
Host smart-676e4df3-e6fa-49eb-8148-6abd28817aa3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2038955179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2038955179
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.3828018011
Short name T323
Test name
Test status
Simulation time 422449569 ps
CPU time 28.42 seconds
Started Jul 27 04:22:31 PM PDT 24
Finished Jul 27 04:23:00 PM PDT 24
Peak memory 211188 kb
Host smart-dc056896-38f2-4661-9c39-0e61f2f6c3e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3828018011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3828018011
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.4102876346
Short name T817
Test name
Test status
Simulation time 242483202 ps
CPU time 85.15 seconds
Started Jul 27 04:18:08 PM PDT 24
Finished Jul 27 04:19:33 PM PDT 24
Peak memory 207072 kb
Host smart-edd3421f-ba3f-4dd6-a22e-4558da66c07b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4102876346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand
_reset.4102876346
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1289008495
Short name T36
Test name
Test status
Simulation time 409689156 ps
CPU time 176.31 seconds
Started Jul 27 04:22:09 PM PDT 24
Finished Jul 27 04:25:05 PM PDT 24
Peak memory 211220 kb
Host smart-7ee66121-1b9b-4675-a18c-4d7f909b0a59
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1289008495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res
et_error.1289008495
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.3146743815
Short name T622
Test name
Test status
Simulation time 1900238312 ps
CPU time 10.81 seconds
Started Jul 27 04:22:28 PM PDT 24
Finished Jul 27 04:22:39 PM PDT 24
Peak memory 211240 kb
Host smart-a107ab1b-6c25-44f7-b7ab-0c26428cc704
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3146743815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3146743815
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.4037017530
Short name T318
Test name
Test status
Simulation time 427811400 ps
CPU time 11.61 seconds
Started Jul 27 04:22:40 PM PDT 24
Finished Jul 27 04:22:52 PM PDT 24
Peak memory 205244 kb
Host smart-6af8278a-d172-42b0-9432-908a1b7ea85e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4037017530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.4037017530
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.4070950540
Short name T623
Test name
Test status
Simulation time 16708954836 ps
CPU time 69.79 seconds
Started Jul 27 04:18:07 PM PDT 24
Finished Jul 27 04:19:17 PM PDT 24
Peak memory 211564 kb
Host smart-868b43b6-65f3-4bdb-824d-1df62ee54ab3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4070950540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo
w_rsp.4070950540
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.2631252725
Short name T851
Test name
Test status
Simulation time 331095093 ps
CPU time 9.66 seconds
Started Jul 27 04:22:34 PM PDT 24
Finished Jul 27 04:22:43 PM PDT 24
Peak memory 203648 kb
Host smart-980bc63a-5434-450f-aeac-854935412e94
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2631252725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.2631252725
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.3624975270
Short name T569
Test name
Test status
Simulation time 85965095 ps
CPU time 7.51 seconds
Started Jul 27 04:22:40 PM PDT 24
Finished Jul 27 04:22:48 PM PDT 24
Peak memory 203308 kb
Host smart-aa2bbacd-e34b-46de-81e0-29c2575f6836
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3624975270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3624975270
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.2952800452
Short name T253
Test name
Test status
Simulation time 3263482298 ps
CPU time 35.64 seconds
Started Jul 27 04:22:35 PM PDT 24
Finished Jul 27 04:23:11 PM PDT 24
Peak memory 211324 kb
Host smart-25d03108-ffbb-442a-b0bb-67bf909f7257
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2952800452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.2952800452
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.1849974713
Short name T595
Test name
Test status
Simulation time 24884660215 ps
CPU time 128.06 seconds
Started Jul 27 04:19:30 PM PDT 24
Finished Jul 27 04:21:38 PM PDT 24
Peak memory 211544 kb
Host smart-82ff7e13-79d8-4182-9be8-6c88dec258f2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849974713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1849974713
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.137133921
Short name T744
Test name
Test status
Simulation time 35509822073 ps
CPU time 191.44 seconds
Started Jul 27 04:22:34 PM PDT 24
Finished Jul 27 04:25:46 PM PDT 24
Peak memory 211308 kb
Host smart-048c93d4-fed2-49eb-97bd-d71bf1905096
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=137133921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.137133921
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.3588421808
Short name T409
Test name
Test status
Simulation time 231731620 ps
CPU time 23.7 seconds
Started Jul 27 04:17:57 PM PDT 24
Finished Jul 27 04:18:21 PM PDT 24
Peak memory 210888 kb
Host smart-73021811-965d-43be-8485-80226549b850
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588421808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3588421808
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.2502946404
Short name T284
Test name
Test status
Simulation time 45306611 ps
CPU time 4.36 seconds
Started Jul 27 04:22:25 PM PDT 24
Finished Jul 27 04:22:29 PM PDT 24
Peak memory 201740 kb
Host smart-192ad034-39e9-4958-b23f-f0e399c427aa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2502946404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2502946404
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.54111644
Short name T169
Test name
Test status
Simulation time 259232359 ps
CPU time 3.89 seconds
Started Jul 27 04:19:30 PM PDT 24
Finished Jul 27 04:19:34 PM PDT 24
Peak memory 203236 kb
Host smart-1b07ed33-47cd-4ada-9f62-4bc4ad5295d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=54111644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.54111644
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2068633215
Short name T380
Test name
Test status
Simulation time 31725848665 ps
CPU time 52.49 seconds
Started Jul 27 04:19:21 PM PDT 24
Finished Jul 27 04:20:13 PM PDT 24
Peak memory 203372 kb
Host smart-dab9834a-1e3f-4870-be33-f47ab272ef6b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068633215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2068633215
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.1657627222
Short name T823
Test name
Test status
Simulation time 3288348897 ps
CPU time 25.32 seconds
Started Jul 27 04:22:34 PM PDT 24
Finished Jul 27 04:23:00 PM PDT 24
Peak memory 203108 kb
Host smart-2b6489d1-f8f0-4be7-b604-ebd2d0504ac3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1657627222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1657627222
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2109902425
Short name T830
Test name
Test status
Simulation time 27593200 ps
CPU time 2.3 seconds
Started Jul 27 04:22:07 PM PDT 24
Finished Jul 27 04:22:10 PM PDT 24
Peak memory 202704 kb
Host smart-1577037d-e1fe-43f1-b88f-c421b9717597
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109902425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2109902425
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.988942928
Short name T242
Test name
Test status
Simulation time 4038441390 ps
CPU time 111.35 seconds
Started Jul 27 04:18:07 PM PDT 24
Finished Jul 27 04:19:59 PM PDT 24
Peak memory 206128 kb
Host smart-edf16ef3-f894-4725-a1ce-b2f5ca214288
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=988942928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.988942928
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3966780584
Short name T313
Test name
Test status
Simulation time 5411016129 ps
CPU time 167.55 seconds
Started Jul 27 04:19:41 PM PDT 24
Finished Jul 27 04:22:28 PM PDT 24
Peak memory 211432 kb
Host smart-5e3f8b6a-051b-4638-9e1f-c9cc1cc860b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3966780584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3966780584
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.689963692
Short name T483
Test name
Test status
Simulation time 443140601 ps
CPU time 116.22 seconds
Started Jul 27 04:18:07 PM PDT 24
Finished Jul 27 04:20:03 PM PDT 24
Peak memory 208488 kb
Host smart-446868cf-0dcb-42b1-9cf7-cf2a3ecf4335
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=689963692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_
reset.689963692
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2511632095
Short name T820
Test name
Test status
Simulation time 294555737 ps
CPU time 95.37 seconds
Started Jul 27 04:22:35 PM PDT 24
Finished Jul 27 04:24:11 PM PDT 24
Peak memory 209852 kb
Host smart-4320ef9a-78a0-419e-bb30-66ff20c6f9a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2511632095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res
et_error.2511632095
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.3258977880
Short name T559
Test name
Test status
Simulation time 16222760 ps
CPU time 2.88 seconds
Started Jul 27 04:22:34 PM PDT 24
Finished Jul 27 04:22:38 PM PDT 24
Peak memory 211208 kb
Host smart-86ef7c0f-2b32-42b5-96a8-3ce315d6f934
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3258977880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3258977880
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.1827475047
Short name T107
Test name
Test status
Simulation time 8243936361 ps
CPU time 67.74 seconds
Started Jul 27 04:22:20 PM PDT 24
Finished Jul 27 04:23:27 PM PDT 24
Peak memory 205700 kb
Host smart-b64659a8-8c7d-4d24-b299-b2a0f70941d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1827475047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1827475047
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.2273483613
Short name T182
Test name
Test status
Simulation time 47506724668 ps
CPU time 296.22 seconds
Started Jul 27 04:20:57 PM PDT 24
Finished Jul 27 04:25:54 PM PDT 24
Peak memory 211444 kb
Host smart-6fe87bfb-d4d3-4699-b2cc-af11648b1abf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2273483613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo
w_rsp.2273483613
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1916221392
Short name T395
Test name
Test status
Simulation time 240482621 ps
CPU time 7.35 seconds
Started Jul 27 04:22:49 PM PDT 24
Finished Jul 27 04:22:56 PM PDT 24
Peak memory 203064 kb
Host smart-a8e49b7a-e245-4df5-acc9-0de868b9e373
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1916221392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1916221392
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.1533485543
Short name T621
Test name
Test status
Simulation time 36521373 ps
CPU time 1.79 seconds
Started Jul 27 04:19:34 PM PDT 24
Finished Jul 27 04:19:36 PM PDT 24
Peak memory 203452 kb
Host smart-fb1df58f-4332-439f-83b4-de04237bddfe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1533485543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1533485543
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.3283074171
Short name T490
Test name
Test status
Simulation time 60310445 ps
CPU time 7.84 seconds
Started Jul 27 04:20:54 PM PDT 24
Finished Jul 27 04:21:02 PM PDT 24
Peak memory 211632 kb
Host smart-562bfc02-e63d-4f83-b530-638fdd7f67af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3283074171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.3283074171
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.2269074602
Short name T599
Test name
Test status
Simulation time 49568414031 ps
CPU time 134.21 seconds
Started Jul 27 04:21:26 PM PDT 24
Finished Jul 27 04:23:41 PM PDT 24
Peak memory 211548 kb
Host smart-7ba4cbf0-f420-4d8b-8ec0-5e1bbc4c6661
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269074602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2269074602
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.845290978
Short name T147
Test name
Test status
Simulation time 18513388192 ps
CPU time 99.08 seconds
Started Jul 27 04:22:39 PM PDT 24
Finished Jul 27 04:24:19 PM PDT 24
Peak memory 211476 kb
Host smart-960cdd07-193b-498a-b8fe-4e84a6985e92
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=845290978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.845290978
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.3515365681
Short name T802
Test name
Test status
Simulation time 137762183 ps
CPU time 23.83 seconds
Started Jul 27 04:21:06 PM PDT 24
Finished Jul 27 04:21:30 PM PDT 24
Peak memory 211516 kb
Host smart-b6ea063c-675a-4af5-adfa-c95743987726
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515365681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.3515365681
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.2709123717
Short name T236
Test name
Test status
Simulation time 1800721468 ps
CPU time 21.49 seconds
Started Jul 27 04:18:16 PM PDT 24
Finished Jul 27 04:18:37 PM PDT 24
Peak memory 203368 kb
Host smart-f8baaedf-1d17-4b73-b2f1-9c7e1982dfb8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2709123717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2709123717
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.1867864486
Short name T55
Test name
Test status
Simulation time 145805777 ps
CPU time 3.51 seconds
Started Jul 27 04:22:52 PM PDT 24
Finished Jul 27 04:22:56 PM PDT 24
Peak memory 203312 kb
Host smart-6d845dd5-e859-4cc3-a45c-d665b4bc2149
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1867864486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1867864486
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.2423011309
Short name T528
Test name
Test status
Simulation time 6717050714 ps
CPU time 33.92 seconds
Started Jul 27 04:21:05 PM PDT 24
Finished Jul 27 04:21:39 PM PDT 24
Peak memory 203512 kb
Host smart-7c0f2113-e7bd-4765-a365-1dccdc134fdc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423011309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2423011309
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2060634366
Short name T444
Test name
Test status
Simulation time 7800743944 ps
CPU time 35.11 seconds
Started Jul 27 04:22:52 PM PDT 24
Finished Jul 27 04:23:27 PM PDT 24
Peak memory 202692 kb
Host smart-5fc11419-bb50-46de-b337-10b2370c6c33
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2060634366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2060634366
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.3259619905
Short name T425
Test name
Test status
Simulation time 101389411 ps
CPU time 2.35 seconds
Started Jul 27 04:22:38 PM PDT 24
Finished Jul 27 04:22:41 PM PDT 24
Peak memory 202476 kb
Host smart-0f015bec-8b3b-4546-9dc5-ac9108bc35f1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259619905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3259619905
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.853721740
Short name T109
Test name
Test status
Simulation time 16451261577 ps
CPU time 208.47 seconds
Started Jul 27 04:22:44 PM PDT 24
Finished Jul 27 04:26:13 PM PDT 24
Peak memory 210240 kb
Host smart-20204d0a-12f1-4162-a9f9-4eb888a776e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=853721740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.853721740
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.679586941
Short name T798
Test name
Test status
Simulation time 726876779 ps
CPU time 57.81 seconds
Started Jul 27 04:22:38 PM PDT 24
Finished Jul 27 04:23:36 PM PDT 24
Peak memory 204892 kb
Host smart-feecbf52-08d5-4f29-a691-d6224dff5b02
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=679586941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.679586941
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.1552702563
Short name T265
Test name
Test status
Simulation time 2033941440 ps
CPU time 291.57 seconds
Started Jul 27 04:22:49 PM PDT 24
Finished Jul 27 04:27:41 PM PDT 24
Peak memory 225176 kb
Host smart-4db5e41f-a546-4bda-a9ee-2b0cd5ccdf77
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1552702563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res
et_error.1552702563
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.394726001
Short name T251
Test name
Test status
Simulation time 164710518 ps
CPU time 6.19 seconds
Started Jul 27 04:22:44 PM PDT 24
Finished Jul 27 04:22:50 PM PDT 24
Peak memory 209908 kb
Host smart-e7bcec84-5991-4e41-af1d-46a006b52b0f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=394726001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.394726001
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.268672388
Short name T212
Test name
Test status
Simulation time 589237509 ps
CPU time 42.79 seconds
Started Jul 27 04:22:10 PM PDT 24
Finished Jul 27 04:22:53 PM PDT 24
Peak memory 204412 kb
Host smart-1c7193b1-c8a1-47f5-8f43-a007818b4875
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=268672388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.268672388
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.1908203680
Short name T108
Test name
Test status
Simulation time 71040169551 ps
CPU time 523.03 seconds
Started Jul 27 04:22:18 PM PDT 24
Finished Jul 27 04:31:02 PM PDT 24
Peak memory 211432 kb
Host smart-102366af-4d18-40ac-bfe5-1054ec2cec9e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1908203680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo
w_rsp.1908203680
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1836502654
Short name T870
Test name
Test status
Simulation time 1509206297 ps
CPU time 14.22 seconds
Started Jul 27 04:22:11 PM PDT 24
Finished Jul 27 04:22:25 PM PDT 24
Peak memory 203084 kb
Host smart-c36a923c-f2eb-457e-8358-6edd078f57ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1836502654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1836502654
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.2381867942
Short name T778
Test name
Test status
Simulation time 1628852876 ps
CPU time 32.41 seconds
Started Jul 27 04:19:38 PM PDT 24
Finished Jul 27 04:20:10 PM PDT 24
Peak memory 203460 kb
Host smart-10f6c724-0dc6-4a59-8908-c44b6130a9dd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2381867942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2381867942
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.2347316986
Short name T695
Test name
Test status
Simulation time 2215065904 ps
CPU time 37.17 seconds
Started Jul 27 04:22:47 PM PDT 24
Finished Jul 27 04:23:25 PM PDT 24
Peak memory 204268 kb
Host smart-22265319-a836-4bd6-9802-1cb8dc2a3260
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2347316986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.2347316986
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.3377645194
Short name T173
Test name
Test status
Simulation time 45221314627 ps
CPU time 125.5 seconds
Started Jul 27 04:23:15 PM PDT 24
Finished Jul 27 04:25:21 PM PDT 24
Peak memory 211396 kb
Host smart-c426b93e-1dcf-4ae9-b140-7b733a8a7a1c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377645194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3377645194
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1316632125
Short name T879
Test name
Test status
Simulation time 47943588976 ps
CPU time 196.06 seconds
Started Jul 27 04:22:47 PM PDT 24
Finished Jul 27 04:26:04 PM PDT 24
Peak memory 211328 kb
Host smart-9388313c-47d0-4f67-b20c-33742bfea0c7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1316632125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1316632125
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.2446154319
Short name T194
Test name
Test status
Simulation time 140810995 ps
CPU time 7.32 seconds
Started Jul 27 04:18:21 PM PDT 24
Finished Jul 27 04:18:28 PM PDT 24
Peak memory 204384 kb
Host smart-d6368c8a-1306-45fb-9588-f21e878fdcdd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446154319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.2446154319
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.3591850815
Short name T80
Test name
Test status
Simulation time 545438713 ps
CPU time 12.1 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:22:18 PM PDT 24
Peak memory 203296 kb
Host smart-87f01185-b271-4396-a169-a8652e336ad8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3591850815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3591850815
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.3447178599
Short name T262
Test name
Test status
Simulation time 388362546 ps
CPU time 3.31 seconds
Started Jul 27 04:18:32 PM PDT 24
Finished Jul 27 04:18:35 PM PDT 24
Peak memory 203684 kb
Host smart-169e41ce-6cbd-49d3-84d3-60ee0eace18b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3447178599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3447178599
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3761275596
Short name T273
Test name
Test status
Simulation time 18853373314 ps
CPU time 35.38 seconds
Started Jul 27 04:18:31 PM PDT 24
Finished Jul 27 04:19:07 PM PDT 24
Peak memory 203748 kb
Host smart-58852ccb-9f9b-42b0-9529-e7f5b4ec9fcd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761275596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3761275596
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2297985728
Short name T754
Test name
Test status
Simulation time 6724477419 ps
CPU time 29.9 seconds
Started Jul 27 04:22:44 PM PDT 24
Finished Jul 27 04:23:14 PM PDT 24
Peak memory 203080 kb
Host smart-63fb03d8-cee2-4ab7-9327-b886efe670c6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2297985728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2297985728
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.2137511783
Short name T47
Test name
Test status
Simulation time 30923589 ps
CPU time 2.05 seconds
Started Jul 27 04:22:21 PM PDT 24
Finished Jul 27 04:22:24 PM PDT 24
Peak memory 202020 kb
Host smart-332a1ec2-1293-41ce-8e32-05fe1a27f9fd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137511783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2137511783
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.180722895
Short name T76
Test name
Test status
Simulation time 5162944046 ps
CPU time 29.78 seconds
Started Jul 27 04:22:07 PM PDT 24
Finished Jul 27 04:22:37 PM PDT 24
Peak memory 211236 kb
Host smart-dd7197eb-1bf0-43b6-b2e3-aa302509f5cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=180722895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.180722895
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.871676223
Short name T394
Test name
Test status
Simulation time 282172575 ps
CPU time 25.95 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:22:32 PM PDT 24
Peak memory 202376 kb
Host smart-96ed0d17-24d0-4556-8a46-6dcf71dd1517
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=871676223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.871676223
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.1918792806
Short name T889
Test name
Test status
Simulation time 413801919 ps
CPU time 86.61 seconds
Started Jul 27 04:20:44 PM PDT 24
Finished Jul 27 04:22:11 PM PDT 24
Peak memory 207648 kb
Host smart-05ba742c-a61e-412e-af00-8c65dfd34583
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1918792806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res
et_error.1918792806
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.452458584
Short name T470
Test name
Test status
Simulation time 2583532629 ps
CPU time 25.77 seconds
Started Jul 27 04:18:41 PM PDT 24
Finished Jul 27 04:19:07 PM PDT 24
Peak memory 211544 kb
Host smart-62609083-aeb9-4074-a3b2-10de56862349
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=452458584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.452458584
Directory /workspace/9.xbar_unmapped_addr/latest
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