Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1650	1			T23	36		T47	6		T17	22
all_values[1]	1657	1			T23	26		T47	5		T17	30
all_values[2]	1725	1			T23	25		T47	9		T17	18
all_values[3]	1675	1			T23	16		T47	6		T17	23
all_values[4]	1677	1			T23	20		T47	2		T17	20
all_values[5]	1648	1			T23	19		T47	6		T17	16
all_values[6]	1640	1			T23	12		T47	4		T17	17
all_values[7]	1715	1			T23	21		T47	3		T17	22
all_values[8]	1675	1			T23	22		T47	6		T17	18
all_values[9]	1712	1			T23	25		T47	6		T17	37
all_values[10]	1757	1			T23	23		T47	8		T17	28
all_values[11]	1728	1			T23	20		T47	11		T17	24
all_values[12]	1715	1			T23	27		T47	2		T17	33
all_values[13]	1708	1			T23	17		T47	8		T17	20
all_values[14]	1656	1			T23	25		T47	6		T17	24
all_values[15]	1581	1			T23	15		T47	11		T17	24
all_values[16]	1715	1			T23	12		T47	7		T17	25
all_values[17]	1683	1			T23	19		T47	11		T17	27
all_values[18]	1689	1			T23	27		T47	8		T17	19
all_values[19]	1682	1			T23	26		T47	10		T17	22
all_values[20]	1621	1			T23	16		T47	6		T17	20
all_values[21]	1727	1			T23	31		T47	9		T17	21
all_values[22]	1723	1			T23	23		T47	6		T17	29
all_values[23]	1690	1			T23	21		T47	4		T17	22
all_values[24]	1611	1			T23	26		T47	3		T17	24
all_values[25]	1650	1			T23	26		T47	8		T17	23
all_values[26]	1619	1			T23	22		T47	3		T17	23
all_values[27]	1683	1			T23	18		T47	9		T17	20
all_values[28]	1658	1			T23	18		T47	5		T17	23
all_values[29]	1667	1			T23	21		T47	7		T17	21
all_values[30]	1639	1			T23	31		T47	9		T17	27
all_values[31]	1712	1			T23	26		T47	2		T17	27
all_values[32]	1711	1			T23	23		T47	5		T17	16
all_values[33]	1636	1			T23	28		T47	6		T17	14
all_values[34]	1679	1			T23	20		T47	4		T17	30
all_values[35]	1681	1			T23	24		T47	3		T17	22
all_values[36]	1682	1			T23	24		T47	4		T17	25
all_values[37]	1716	1			T23	24		T47	7		T17	24
all_values[38]	1697	1			T23	9		T47	6		T17	21
all_values[39]	1640	1			T23	20		T47	5		T17	19
all_values[40]	1712	1			T23	14		T47	3		T17	22
all_values[41]	1707	1			T23	17		T47	5		T17	24
all_values[42]	1702	1			T23	20		T47	6		T17	21
all_values[43]	1667	1			T23	14		T47	4		T17	18
all_values[44]	1554	1			T23	21		T47	5		T17	22
all_values[45]	1616	1			T23	20		T47	1		T17	24
all_values[46]	1666	1			T23	17		T47	3		T17	26
all_values[47]	1610	1			T23	22		T47	3		T17	25
all_values[48]	1698	1			T23	15		T47	5		T17	17
all_values[49]	1686	1			T23	21		T47	6		T17	20
all_values[50]	1677	1			T23	20		T47	8		T17	19
all_values[51]	1679	1			T23	16		T47	5		T17	29
all_values[52]	1675	1			T23	17		T47	9		T17	26
all_values[53]	1681	1			T23	20		T47	6		T17	27
all_values[54]	1562	1			T23	22		T47	8		T17	15
all_values[55]	1693	1			T23	26		T47	10		T17	22
all_values[56]	1740	1			T23	19		T47	2		T17	33
all_values[57]	1716	1			T23	27		T47	9		T17	23
all_values[58]	1716	1			T23	23		T47	8		T17	22
all_values[59]	1615	1			T23	27		T47	7		T17	20
all_values[60]	1645	1			T23	24		T47	7		T17	21
all_values[61]	1691	1			T23	26		T47	3		T17	31
all_values[62]	1709	1			T23	25		T47	4		T17	25
all_values[63]	1640	1			T23	15		T47	5		T17	25