Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 492 1 T3 4 T7 5 T20 2
all_values[1] 498 1 T2 2 T3 3 T7 10
all_values[2] 499 1 T2 3 T3 6 T7 8
all_values[3] 531 1 T3 2 T7 9 T20 4
all_values[4] 510 1 T2 1 T3 4 T7 11
all_values[5] 468 1 T3 6 T7 7 T17 7
all_values[6] 519 1 T2 1 T3 5 T7 7
all_values[7] 491 1 T3 4 T7 10 T20 1
all_values[8] 471 1 T3 3 T7 3 T10 1
all_values[9] 492 1 T2 2 T3 3 T7 8
all_values[10] 506 1 T3 6 T7 10 T20 1
all_values[11] 506 1 T2 2 T3 2 T7 11
all_values[12] 523 1 T2 1 T3 3 T7 5
all_values[13] 458 1 T3 5 T7 9 T20 2
all_values[14] 492 1 T2 1 T3 1 T7 5
all_values[15] 481 1 T3 6 T7 6 T20 1
all_values[16] 500 1 T3 3 T7 8 T17 9
all_values[17] 502 1 T2 2 T7 12 T17 6
all_values[18] 471 1 T2 1 T7 9 T10 1
all_values[19] 515 1 T2 1 T3 2 T7 9
all_values[20] 476 1 T7 2 T20 1 T17 8
all_values[21] 496 1 T2 1 T3 3 T7 7
all_values[22] 453 1 T3 3 T7 4 T20 1
all_values[23] 495 1 T3 2 T7 6 T10 1

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