Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1718	1			T2	3		T3	12		T7	23
all_values[1]	1673	1			T3	24		T7	23		T16	1
all_values[2]	1797	1			T3	29		T7	32		T16	1
all_values[3]	1664	1			T2	4		T3	18		T7	30
all_values[4]	1764	1			T3	21		T7	34		T17	16
all_values[5]	1728	1			T2	1		T3	15		T7	19
all_values[6]	1750	1			T2	4		T3	23		T7	25
all_values[7]	1644	1			T2	3		T3	16		T7	24
all_values[8]	1729	1			T2	1		T3	20		T7	17
all_values[9]	1694	1			T2	1		T3	14		T7	23
all_values[10]	1681	1			T2	3		T3	18		T7	28
all_values[11]	1765	1			T2	1		T3	11		T7	24
all_values[12]	1713	1			T2	2		T3	12		T7	34
all_values[13]	1751	1			T3	11		T7	26		T16	2
all_values[14]	1728	1			T2	3		T3	19		T7	30
all_values[15]	1649	1			T3	19		T7	27		T17	11
all_values[16]	1675	1			T3	12		T7	24		T16	1
all_values[17]	1684	1			T2	2		T3	11		T7	24
all_values[18]	1654	1			T2	1		T3	12		T7	31
all_values[19]	1720	1			T2	2		T3	18		T7	29
all_values[20]	1699	1			T2	2		T3	16		T7	18
all_values[21]	1664	1			T3	17		T7	26		T16	1
all_values[22]	1730	1			T2	4		T3	13		T7	23
all_values[23]	1671	1			T2	2		T3	17		T7	28
all_values[24]	1684	1			T2	1		T3	9		T7	24
all_values[25]	1669	1			T2	4		T3	12		T7	25
all_values[26]	1805	1			T2	2		T3	10		T7	23
all_values[27]	1684	1			T2	1		T3	9		T7	22
all_values[28]	1702	1			T2	2		T3	13		T7	27
all_values[29]	1687	1			T3	22		T7	32		T16	1
all_values[30]	1740	1			T2	2		T3	18		T7	27
all_values[31]	1613	1			T2	2		T3	15		T7	32
all_values[32]	1723	1			T2	3		T3	16		T7	33
all_values[33]	1742	1			T2	1		T3	15		T7	36
all_values[34]	1678	1			T2	1		T3	12		T7	24
all_values[35]	1684	1			T3	16		T7	22		T17	15
all_values[36]	1688	1			T2	3		T3	15		T7	25
all_values[37]	1715	1			T2	2		T3	18		T7	29
all_values[38]	1749	1			T2	3		T3	15		T7	26
all_values[39]	1665	1			T2	1		T3	18		T7	24
all_values[40]	1653	1			T3	16		T7	19		T16	2
all_values[41]	1704	1			T2	3		T3	12		T7	28
all_values[42]	1681	1			T3	16		T7	19		T16	2
all_values[43]	1743	1			T2	1		T3	23		T7	28
all_values[44]	1709	1			T2	1		T3	16		T7	25
all_values[45]	1674	1			T2	2		T3	12		T7	33
all_values[46]	1678	1			T2	4		T3	17		T7	34
all_values[47]	1670	1			T2	1		T3	13		T7	28
all_values[48]	1703	1			T2	1		T3	10		T7	18
all_values[49]	1758	1			T2	1		T3	18		T7	23
all_values[50]	1697	1			T2	1		T3	22		T7	22
all_values[51]	1719	1			T3	9		T7	22		T16	1
all_values[52]	1730	1			T2	1		T3	19		T7	36
all_values[53]	1670	1			T2	2		T3	19		T7	28
all_values[54]	1746	1			T2	2		T3	11		T7	41
all_values[55]	1698	1			T2	1		T3	19		T7	28
all_values[56]	1655	1			T2	4		T3	20		T7	40
all_values[57]	1735	1			T2	3		T3	18		T7	24
all_values[58]	1667	1			T2	2		T3	19		T7	29
all_values[59]	1743	1			T2	2		T3	14		T7	23
all_values[60]	1727	1			T2	1		T3	10		T7	24
all_values[61]	1678	1			T2	4		T3	19		T7	35
all_values[62]	1744	1			T2	1		T3	19		T7	35
all_values[63]	1769	1			T2	3		T3	13		T7	28