Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1909	1			T1	3		T9	4		T8	3
all_values[1]	1900	1			T1	3		T9	3		T8	6
all_values[2]	2004	1			T1	5		T9	6		T8	5
all_values[3]	1904	1			T1	3		T9	1		T8	5
all_values[4]	1919	1			T1	5		T8	6		T18	2
all_values[5]	1897	1			T1	3		T9	3		T8	4
all_values[6]	1927	1			T1	2		T9	6		T8	6
all_values[7]	1875	1			T1	6		T9	1		T8	3
all_values[8]	1993	1			T1	3		T9	3		T8	6
all_values[9]	1909	1			T1	7		T9	2		T18	4
all_values[10]	1948	1			T1	2		T9	2		T8	2
all_values[11]	1924	1			T1	1		T9	7		T8	1
all_values[12]	1928	1			T1	8		T8	6		T18	1
all_values[13]	1796	1			T1	9		T9	6		T8	4
all_values[14]	1902	1			T1	4		T9	2		T8	7
all_values[15]	1915	1			T1	5		T9	4		T8	1
all_values[16]	1902	1			T1	1		T9	4		T8	4
all_values[17]	1941	1			T1	2		T9	4		T8	6
all_values[18]	1832	1			T1	5		T9	4		T8	5
all_values[19]	1999	1			T1	1		T9	6		T8	2
all_values[20]	1886	1			T1	7		T9	1		T8	4
all_values[21]	1860	1			T1	3		T9	4		T8	7
all_values[22]	1885	1			T1	3		T9	4		T8	6
all_values[23]	1924	1			T1	4		T9	3		T8	3
all_values[24]	1885	1			T1	1		T9	4		T8	9
all_values[25]	1883	1			T9	2		T8	4		T18	2
all_values[26]	1931	1			T1	4		T8	3		T18	1
all_values[27]	1981	1			T1	5		T8	5		T18	2
all_values[28]	1879	1			T1	4		T9	2		T8	7
all_values[29]	1926	1			T1	4		T9	2		T8	3
all_values[30]	1903	1			T1	4		T9	2		T8	10
all_values[31]	1902	1			T1	2		T9	1		T8	2
all_values[32]	1891	1			T1	2		T9	2		T8	3
all_values[33]	1901	1			T1	2		T9	6		T8	3
all_values[34]	1953	1			T1	3		T9	3		T8	4
all_values[35]	1965	1			T1	4		T9	1		T8	2
all_values[36]	1950	1			T1	3		T9	4		T8	4
all_values[37]	1868	1			T1	3		T8	5		T65	22
all_values[38]	1923	1			T1	4		T9	1		T8	9
all_values[39]	1869	1			T1	3		T9	2		T8	3
all_values[40]	1910	1			T1	4		T9	4		T8	3
all_values[41]	1916	1			T1	3		T9	2		T8	3
all_values[42]	1909	1			T1	1		T9	3		T8	4
all_values[43]	1887	1			T1	4		T9	3		T8	2
all_values[44]	1861	1			T1	4		T9	5		T8	3
all_values[45]	1883	1			T1	4		T9	7		T8	3
all_values[46]	1858	1			T1	3		T9	2		T8	5
all_values[47]	1869	1			T1	3		T9	2		T8	4
all_values[48]	1871	1			T1	3		T9	3		T8	9
all_values[49]	1924	1			T1	2		T9	3		T8	4
all_values[50]	1940	1			T1	3		T9	1		T8	5
all_values[51]	1899	1			T1	6		T9	2		T8	8
all_values[52]	1840	1			T1	5		T9	4		T8	2
all_values[53]	1889	1			T1	11		T9	2		T8	3
all_values[54]	1964	1			T1	6		T9	3		T8	3
all_values[55]	1960	1			T1	6		T9	3		T8	6
all_values[56]	1878	1			T1	3		T9	2		T8	1
all_values[57]	1991	1			T1	2		T9	1		T8	3
all_values[58]	1971	1			T1	6		T9	3		T8	8
all_values[59]	1902	1			T1	4		T9	3		T8	2
all_values[60]	1945	1			T1	3		T9	3		T8	3
all_values[61]	1994	1			T1	4		T9	3		T8	2
all_values[62]	1843	1			T1	2		T9	4		T8	1
all_values[63]	1915	1			T1	3		T9	3		T8	3