Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1774	1			T5	2		T22	3		T79	2
all_values[1]	1728	1			T5	1		T79	1		T25	34
all_values[2]	1784	1			T5	4		T22	2		T21	3
all_values[3]	1785	1			T5	6		T22	1		T21	2
all_values[4]	1798	1			T5	4		T22	1		T21	1
all_values[5]	1711	1			T5	5		T22	2		T79	1
all_values[6]	1841	1			T5	2		T22	2		T79	1
all_values[7]	1818	1			T5	1		T21	1		T79	4
all_values[8]	1796	1			T5	5		T21	3		T25	29
all_values[9]	1700	1			T22	4		T21	1		T79	2
all_values[10]	1763	1			T5	2		T22	2		T21	3
all_values[11]	1758	1			T22	2		T21	2		T79	2
all_values[12]	1807	1			T5	3		T22	3		T21	4
all_values[13]	1687	1			T5	2		T21	2		T25	36
all_values[14]	1746	1			T5	3		T22	5		T25	42
all_values[15]	1762	1			T5	4		T22	3		T21	2
all_values[16]	1804	1			T5	4		T22	1		T21	3
all_values[17]	1793	1			T5	4		T22	1		T21	1
all_values[18]	1800	1			T5	1		T22	3		T25	43
all_values[19]	1786	1			T5	4		T22	3		T79	1
all_values[20]	1822	1			T5	2		T22	1		T21	3
all_values[21]	1825	1			T5	1		T22	4		T21	2
all_values[22]	1737	1			T5	4		T21	1		T25	27
all_values[23]	1796	1			T5	5		T22	1		T79	2
all_values[24]	1728	1			T5	6		T22	2		T79	1
all_values[25]	1783	1			T5	1		T79	1		T25	25
all_values[26]	1739	1			T5	3		T22	5		T79	3
all_values[27]	1777	1			T5	2		T22	2		T21	1
all_values[28]	1820	1			T5	4		T22	1		T21	4
all_values[29]	1837	1			T5	1		T22	3		T79	2
all_values[30]	1738	1			T5	6		T22	2		T21	1
all_values[31]	1738	1			T5	4		T22	1		T79	1
all_values[32]	1807	1			T5	6		T22	1		T21	1
all_values[33]	1857	1			T5	2		T22	4		T21	2
all_values[34]	1704	1			T5	2		T22	2		T21	2
all_values[35]	1843	1			T5	3		T21	3		T79	1
all_values[36]	1828	1			T5	4		T22	1		T21	3
all_values[37]	1800	1			T5	4		T22	2		T79	2
all_values[38]	1868	1			T5	4		T22	1		T21	2
all_values[39]	1795	1			T5	3		T21	2		T79	1
all_values[40]	1730	1			T5	4		T22	3		T21	2
all_values[41]	1788	1			T5	3		T22	3		T21	1
all_values[42]	1713	1			T5	5		T25	24		T201	1
all_values[43]	1802	1			T5	3		T22	2		T21	1
all_values[44]	1809	1			T5	6		T22	4		T21	1
all_values[45]	1830	1			T5	5		T21	1		T25	41
all_values[46]	1779	1			T5	6		T22	4		T21	2
all_values[47]	1774	1			T5	2		T22	4		T21	2
all_values[48]	1772	1			T5	3		T22	3		T21	2
all_values[49]	1779	1			T5	2		T22	1		T21	2
all_values[50]	1781	1			T5	4		T22	4		T21	1
all_values[51]	1779	1			T5	1		T22	4		T79	2
all_values[52]	1828	1			T5	5		T22	4		T21	1
all_values[53]	1768	1			T5	2		T22	4		T21	3
all_values[54]	1789	1			T5	3		T22	1		T79	2
all_values[55]	1786	1			T5	3		T22	5		T25	36
all_values[56]	1786	1			T5	3		T22	1		T21	3
all_values[57]	1803	1			T5	2		T22	1		T21	1
all_values[58]	1762	1			T5	2		T22	1		T21	1
all_values[59]	1822	1			T5	4		T22	2		T21	2
all_values[60]	1835	1			T5	7		T22	4		T21	3
all_values[61]	1807	1			T5	4		T22	2		T21	2
all_values[62]	1796	1			T5	3		T22	2		T21	1
all_values[63]	1815	1			T5	1		T22	3		T21	1