Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 515 1 T7 1 T12 8 T43 3
all_values[1] 539 1 T14 1 T43 4 T65 1
all_values[2] 512 1 T7 1 T12 3 T14 1
all_values[3] 512 1 T7 2 T12 3 T14 2
all_values[4] 556 1 T12 4 T14 1 T43 4
all_values[5] 522 1 T7 1 T12 6 T14 2
all_values[6] 564 1 T12 5 T14 2 T43 5
all_values[7] 505 1 T12 4 T14 1 T43 4
all_values[8] 536 1 T12 5 T14 2 T43 7
all_values[9] 520 1 T7 1 T12 2 T43 6
all_values[10] 534 1 T7 1 T12 2 T43 3
all_values[11] 512 1 T7 1 T12 2 T14 1
all_values[12] 495 1 T7 1 T12 4 T43 4
all_values[13] 558 1 T12 7 T43 9 T15 1
all_values[14] 545 1 T7 1 T12 6 T43 2
all_values[15] 509 1 T12 3 T14 3 T43 10
all_values[16] 525 1 T7 1 T12 7 T43 6
all_values[17] 535 1 T7 1 T12 5 T43 5
all_values[18] 576 1 T12 4 T14 2 T43 5
all_values[19] 535 1 T12 3 T14 3 T43 1
all_values[20] 571 1 T7 1 T12 10 T14 1
all_values[21] 502 1 T12 9 T43 2 T15 3
all_values[22] 531 1 T7 1 T12 4 T43 5
all_values[23] 537 1 T7 5 T12 7 T14 1

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