Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1736	1			T12	12		T14	3		T43	18
all_values[1]	1869	1			T12	10		T14	10		T43	17
all_values[2]	1874	1			T12	16		T14	4		T43	17
all_values[3]	1855	1			T12	10		T14	12		T43	16
all_values[4]	1786	1			T12	6		T14	3		T43	11
all_values[5]	1766	1			T12	4		T14	12		T43	18
all_values[6]	1832	1			T12	7		T14	5		T43	20
all_values[7]	1847	1			T12	11		T14	6		T43	13
all_values[8]	1851	1			T12	14		T14	7		T43	19
all_values[9]	1872	1			T12	11		T14	7		T43	22
all_values[10]	1779	1			T12	4		T14	9		T43	21
all_values[11]	1849	1			T12	8		T14	7		T43	16
all_values[12]	1809	1			T12	14		T14	5		T43	19
all_values[13]	1764	1			T12	15		T14	5		T43	21
all_values[14]	1837	1			T12	6		T14	12		T43	18
all_values[15]	1846	1			T12	11		T14	6		T43	17
all_values[16]	1797	1			T12	13		T14	3		T43	24
all_values[17]	1863	1			T12	16		T14	3		T43	21
all_values[18]	1914	1			T12	11		T14	6		T43	17
all_values[19]	1828	1			T12	13		T14	7		T43	21
all_values[20]	1821	1			T12	4		T14	8		T43	23
all_values[21]	1816	1			T12	8		T14	4		T43	26
all_values[22]	1878	1			T12	14		T14	1		T43	16
all_values[23]	1771	1			T12	11		T14	6		T43	21
all_values[24]	1838	1			T12	11		T14	7		T43	16
all_values[25]	1837	1			T12	3		T14	6		T43	17
all_values[26]	1855	1			T12	12		T14	4		T43	18
all_values[27]	1878	1			T12	13		T14	6		T43	24
all_values[28]	1852	1			T12	11		T14	6		T43	15
all_values[29]	1821	1			T12	13		T14	9		T43	17
all_values[30]	1797	1			T12	9		T14	5		T43	21
all_values[31]	1910	1			T12	12		T14	6		T43	11
all_values[32]	1727	1			T12	14		T14	9		T43	12
all_values[33]	1776	1			T12	6		T14	8		T43	18
all_values[34]	1791	1			T12	11		T14	8		T43	15
all_values[35]	1790	1			T12	12		T14	7		T43	16
all_values[36]	1841	1			T12	5		T14	8		T43	21
all_values[37]	1891	1			T12	10		T14	10		T43	23
all_values[38]	1930	1			T12	6		T14	6		T43	16
all_values[39]	1862	1			T12	11		T14	2		T43	20
all_values[40]	1872	1			T12	12		T14	8		T43	18
all_values[41]	1800	1			T12	10		T14	7		T43	27
all_values[42]	1823	1			T12	13		T14	7		T43	11
all_values[43]	1825	1			T12	11		T14	10		T43	23
all_values[44]	1802	1			T12	13		T14	4		T43	15
all_values[45]	1898	1			T12	10		T14	7		T43	26
all_values[46]	1799	1			T12	11		T14	4		T43	25
all_values[47]	1818	1			T12	8		T14	10		T43	16
all_values[48]	1852	1			T12	14		T14	6		T43	19
all_values[49]	1835	1			T12	11		T14	6		T43	27
all_values[50]	1814	1			T12	11		T14	3		T43	21
all_values[51]	1833	1			T12	6		T14	4		T43	11
all_values[52]	1892	1			T12	10		T14	8		T43	19
all_values[53]	1915	1			T12	10		T14	3		T43	28
all_values[54]	1836	1			T12	6		T14	5		T43	18
all_values[55]	1827	1			T12	10		T14	1		T43	19
all_values[56]	1865	1			T12	8		T14	7		T43	14
all_values[57]	1881	1			T12	11		T14	10		T43	20
all_values[58]	1822	1			T12	12		T14	9		T43	16
all_values[59]	1864	1			T12	8		T14	6		T43	21
all_values[60]	1840	1			T12	10		T14	4		T43	22
all_values[61]	1803	1			T12	10		T14	7		T43	15
all_values[62]	1738	1			T12	17		T14	8		T43	24
all_values[63]	1813	1			T12	11		T14	4		T43	15