Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.02 99.26 88.92 98.80 95.88 99.26 100.00


Total test records in report: 900
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T147 /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.3633688351 Aug 01 05:36:26 PM PDT 24 Aug 01 05:43:05 PM PDT 24 6914479026 ps
T170 /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1900137804 Aug 01 05:39:35 PM PDT 24 Aug 01 05:42:40 PM PDT 24 53278867535 ps
T767 /workspace/coverage/xbar_build_mode/5.xbar_stress_all.2036132841 Aug 01 05:36:33 PM PDT 24 Aug 01 05:38:48 PM PDT 24 4584412822 ps
T768 /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.1156917464 Aug 01 05:37:01 PM PDT 24 Aug 01 05:37:25 PM PDT 24 437900141 ps
T128 /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1174945766 Aug 01 05:37:59 PM PDT 24 Aug 01 05:42:18 PM PDT 24 5600916275 ps
T769 /workspace/coverage/xbar_build_mode/16.xbar_random.1673515709 Aug 01 05:37:06 PM PDT 24 Aug 01 05:37:46 PM PDT 24 6512131394 ps
T770 /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.3118442017 Aug 01 05:38:00 PM PDT 24 Aug 01 05:38:30 PM PDT 24 247469863 ps
T771 /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2028249240 Aug 01 05:36:58 PM PDT 24 Aug 01 05:37:30 PM PDT 24 786642551 ps
T772 /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.1935198482 Aug 01 05:37:59 PM PDT 24 Aug 01 05:39:01 PM PDT 24 2075524565 ps
T773 /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.2590702593 Aug 01 05:36:21 PM PDT 24 Aug 01 05:39:21 PM PDT 24 7240422649 ps
T774 /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.2191408633 Aug 01 05:39:39 PM PDT 24 Aug 01 05:40:15 PM PDT 24 4880403424 ps
T775 /workspace/coverage/xbar_build_mode/44.xbar_same_source.3532236374 Aug 01 05:39:19 PM PDT 24 Aug 01 05:39:23 PM PDT 24 41163615 ps
T776 /workspace/coverage/xbar_build_mode/22.xbar_random.2217163882 Aug 01 05:37:26 PM PDT 24 Aug 01 05:37:30 PM PDT 24 24302525 ps
T777 /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.4185417160 Aug 01 05:36:33 PM PDT 24 Aug 01 05:37:05 PM PDT 24 6039249820 ps
T778 /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.333820602 Aug 01 05:37:02 PM PDT 24 Aug 01 05:40:20 PM PDT 24 484856914 ps
T779 /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.2553063079 Aug 01 05:36:42 PM PDT 24 Aug 01 05:39:06 PM PDT 24 26495607559 ps
T780 /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.797017314 Aug 01 05:36:20 PM PDT 24 Aug 01 05:37:21 PM PDT 24 6481205410 ps
T781 /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.309142798 Aug 01 05:36:21 PM PDT 24 Aug 01 05:36:28 PM PDT 24 33893098 ps
T782 /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.2206313197 Aug 01 05:37:13 PM PDT 24 Aug 01 05:38:16 PM PDT 24 538945206 ps
T783 /workspace/coverage/xbar_build_mode/11.xbar_same_source.1274240883 Aug 01 05:36:54 PM PDT 24 Aug 01 05:37:11 PM PDT 24 546579387 ps
T784 /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.3746477791 Aug 01 05:37:02 PM PDT 24 Aug 01 05:39:38 PM PDT 24 68567854687 ps
T262 /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3387275033 Aug 01 05:39:33 PM PDT 24 Aug 01 05:40:01 PM PDT 24 132548521 ps
T785 /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.422063671 Aug 01 05:39:18 PM PDT 24 Aug 01 05:39:21 PM PDT 24 98611756 ps
T786 /workspace/coverage/xbar_build_mode/6.xbar_stress_all.2937628034 Aug 01 05:36:42 PM PDT 24 Aug 01 05:37:10 PM PDT 24 1480599746 ps
T787 /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.2656848661 Aug 01 05:37:12 PM PDT 24 Aug 01 05:37:24 PM PDT 24 287008635 ps
T788 /workspace/coverage/xbar_build_mode/24.xbar_smoke.3816190567 Aug 01 05:37:41 PM PDT 24 Aug 01 05:37:44 PM PDT 24 191914485 ps
T789 /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.3078187906 Aug 01 05:36:33 PM PDT 24 Aug 01 05:38:12 PM PDT 24 8986973327 ps
T790 /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3173323239 Aug 01 05:38:21 PM PDT 24 Aug 01 05:38:50 PM PDT 24 6197442060 ps
T194 /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1447836427 Aug 01 05:36:59 PM PDT 24 Aug 01 05:38:24 PM PDT 24 18775432970 ps
T791 /workspace/coverage/xbar_build_mode/7.xbar_error_random.889915715 Aug 01 05:36:47 PM PDT 24 Aug 01 05:37:09 PM PDT 24 642850237 ps
T792 /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3853570704 Aug 01 05:37:28 PM PDT 24 Aug 01 05:39:02 PM PDT 24 3200922350 ps
T263 /workspace/coverage/xbar_build_mode/2.xbar_stress_all.1206019043 Aug 01 05:36:22 PM PDT 24 Aug 01 05:38:42 PM PDT 24 2324083237 ps
T37 /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3511758666 Aug 01 05:37:19 PM PDT 24 Aug 01 05:42:26 PM PDT 24 1787548914 ps
T793 /workspace/coverage/xbar_build_mode/38.xbar_random.2726776379 Aug 01 05:38:34 PM PDT 24 Aug 01 05:38:56 PM PDT 24 3235155635 ps
T794 /workspace/coverage/xbar_build_mode/20.xbar_random.1391772558 Aug 01 05:37:17 PM PDT 24 Aug 01 05:37:54 PM PDT 24 3304494183 ps
T795 /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.2285660411 Aug 01 05:36:23 PM PDT 24 Aug 01 05:37:05 PM PDT 24 186765563 ps
T155 /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.716724220 Aug 01 05:37:18 PM PDT 24 Aug 01 05:37:49 PM PDT 24 3772457797 ps
T796 /workspace/coverage/xbar_build_mode/29.xbar_same_source.3337318774 Aug 01 05:38:10 PM PDT 24 Aug 01 05:38:30 PM PDT 24 241206851 ps
T797 /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.3677767721 Aug 01 05:36:29 PM PDT 24 Aug 01 05:36:40 PM PDT 24 1179049769 ps
T798 /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.2747480512 Aug 01 05:39:21 PM PDT 24 Aug 01 05:39:42 PM PDT 24 213717096 ps
T799 /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.1401263895 Aug 01 05:37:12 PM PDT 24 Aug 01 05:37:22 PM PDT 24 117756194 ps
T800 /workspace/coverage/xbar_build_mode/17.xbar_same_source.3544390570 Aug 01 05:37:14 PM PDT 24 Aug 01 05:37:29 PM PDT 24 713465893 ps
T801 /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.1038235202 Aug 01 05:37:07 PM PDT 24 Aug 01 05:37:39 PM PDT 24 5652180435 ps
T802 /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.661471792 Aug 01 05:36:25 PM PDT 24 Aug 01 05:40:59 PM PDT 24 46414023049 ps
T803 /workspace/coverage/xbar_build_mode/36.xbar_same_source.1261011439 Aug 01 05:38:34 PM PDT 24 Aug 01 05:38:45 PM PDT 24 184672126 ps
T804 /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2107519610 Aug 01 05:38:48 PM PDT 24 Aug 01 05:38:50 PM PDT 24 54711604 ps
T805 /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.1914870659 Aug 01 05:37:01 PM PDT 24 Aug 01 05:37:03 PM PDT 24 30606503 ps
T806 /workspace/coverage/xbar_build_mode/38.xbar_same_source.2148998100 Aug 01 05:38:33 PM PDT 24 Aug 01 05:38:47 PM PDT 24 712594083 ps
T807 /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2103537290 Aug 01 05:37:27 PM PDT 24 Aug 01 05:37:29 PM PDT 24 56372053 ps
T808 /workspace/coverage/xbar_build_mode/9.xbar_smoke.3024277544 Aug 01 05:36:44 PM PDT 24 Aug 01 05:36:48 PM PDT 24 145149187 ps
T809 /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2238279303 Aug 01 05:37:03 PM PDT 24 Aug 01 05:37:12 PM PDT 24 53148128 ps
T810 /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.3183623751 Aug 01 05:36:24 PM PDT 24 Aug 01 05:36:41 PM PDT 24 266485827 ps
T811 /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2686405816 Aug 01 05:38:23 PM PDT 24 Aug 01 05:38:31 PM PDT 24 230862805 ps
T812 /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.4066653640 Aug 01 05:36:21 PM PDT 24 Aug 01 05:36:56 PM PDT 24 14497282004 ps
T813 /workspace/coverage/xbar_build_mode/2.xbar_smoke.860288615 Aug 01 05:36:19 PM PDT 24 Aug 01 05:36:21 PM PDT 24 128242907 ps
T814 /workspace/coverage/xbar_build_mode/19.xbar_same_source.3598840981 Aug 01 05:37:18 PM PDT 24 Aug 01 05:37:30 PM PDT 24 320682841 ps
T815 /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.321667550 Aug 01 05:37:40 PM PDT 24 Aug 01 05:41:03 PM PDT 24 649299205 ps
T816 /workspace/coverage/xbar_build_mode/26.xbar_smoke.2856010380 Aug 01 05:37:39 PM PDT 24 Aug 01 05:37:42 PM PDT 24 69015477 ps
T817 /workspace/coverage/xbar_build_mode/44.xbar_smoke.3880200843 Aug 01 05:39:02 PM PDT 24 Aug 01 05:39:06 PM PDT 24 354652062 ps
T818 /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1016867410 Aug 01 05:37:32 PM PDT 24 Aug 01 05:37:34 PM PDT 24 28288866 ps
T819 /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.928234778 Aug 01 05:37:18 PM PDT 24 Aug 01 05:37:43 PM PDT 24 1683392033 ps
T820 /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3364031341 Aug 01 05:36:49 PM PDT 24 Aug 01 05:38:48 PM PDT 24 2148024705 ps
T821 /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1287776466 Aug 01 05:38:16 PM PDT 24 Aug 01 05:38:40 PM PDT 24 3460057267 ps
T822 /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.429675328 Aug 01 05:37:16 PM PDT 24 Aug 01 05:41:49 PM PDT 24 151270752456 ps
T823 /workspace/coverage/xbar_build_mode/32.xbar_error_random.1059211677 Aug 01 05:38:14 PM PDT 24 Aug 01 05:38:21 PM PDT 24 53761020 ps
T824 /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3989656013 Aug 01 05:39:33 PM PDT 24 Aug 01 05:40:34 PM PDT 24 8565336234 ps
T825 /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.45334179 Aug 01 05:39:00 PM PDT 24 Aug 01 05:46:46 PM PDT 24 2022680586 ps
T826 /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.3036734331 Aug 01 05:36:57 PM PDT 24 Aug 01 05:38:14 PM PDT 24 23625770999 ps
T827 /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.2108530126 Aug 01 05:37:29 PM PDT 24 Aug 01 05:40:13 PM PDT 24 2895907397 ps
T828 /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.3715535893 Aug 01 05:37:38 PM PDT 24 Aug 01 05:37:45 PM PDT 24 42448388 ps
T829 /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.766991735 Aug 01 05:37:28 PM PDT 24 Aug 01 05:38:12 PM PDT 24 21519709270 ps
T830 /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.1032284913 Aug 01 05:39:33 PM PDT 24 Aug 01 05:39:56 PM PDT 24 161509406 ps
T831 /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.3061660758 Aug 01 05:37:04 PM PDT 24 Aug 01 05:37:37 PM PDT 24 4102688726 ps
T832 /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.108893973 Aug 01 05:37:07 PM PDT 24 Aug 01 05:40:40 PM PDT 24 26115928678 ps
T833 /workspace/coverage/xbar_build_mode/28.xbar_stress_all.4231971436 Aug 01 05:37:57 PM PDT 24 Aug 01 05:39:33 PM PDT 24 5380130563 ps
T834 /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3326021864 Aug 01 05:36:22 PM PDT 24 Aug 01 05:36:24 PM PDT 24 34902386 ps
T835 /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.3937504888 Aug 01 05:38:22 PM PDT 24 Aug 01 05:42:05 PM PDT 24 45659450483 ps
T836 /workspace/coverage/xbar_build_mode/11.xbar_stress_all.2824532090 Aug 01 05:36:57 PM PDT 24 Aug 01 05:39:05 PM PDT 24 4634577060 ps
T837 /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.3154547090 Aug 01 05:39:33 PM PDT 24 Aug 01 05:40:49 PM PDT 24 14103299535 ps
T838 /workspace/coverage/xbar_build_mode/9.xbar_stress_all.4184724139 Aug 01 05:36:51 PM PDT 24 Aug 01 05:38:53 PM PDT 24 2786305282 ps
T275 /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.3919288730 Aug 01 05:37:57 PM PDT 24 Aug 01 05:40:25 PM PDT 24 40126199261 ps
T839 /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.2498505241 Aug 01 05:39:19 PM PDT 24 Aug 01 05:39:59 PM PDT 24 7335283514 ps
T840 /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3798417983 Aug 01 05:38:33 PM PDT 24 Aug 01 05:38:55 PM PDT 24 2604711473 ps
T841 /workspace/coverage/xbar_build_mode/19.xbar_stress_all.1752871293 Aug 01 05:37:15 PM PDT 24 Aug 01 05:40:15 PM PDT 24 7098329055 ps
T842 /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.4230090244 Aug 01 05:36:48 PM PDT 24 Aug 01 05:36:59 PM PDT 24 1584015218 ps
T129 /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3907150584 Aug 01 05:39:20 PM PDT 24 Aug 01 05:46:28 PM PDT 24 50028069130 ps
T843 /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.629089479 Aug 01 05:37:18 PM PDT 24 Aug 01 05:37:49 PM PDT 24 11766579364 ps
T844 /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.3553463484 Aug 01 05:38:32 PM PDT 24 Aug 01 05:38:35 PM PDT 24 32601024 ps
T845 /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.4183710757 Aug 01 05:36:26 PM PDT 24 Aug 01 05:38:34 PM PDT 24 997630161 ps
T846 /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2934933937 Aug 01 05:38:59 PM PDT 24 Aug 01 05:39:49 PM PDT 24 559204680 ps
T255 /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.4215058120 Aug 01 05:38:13 PM PDT 24 Aug 01 05:44:44 PM PDT 24 3793954570 ps
T847 /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.3876287780 Aug 01 05:38:47 PM PDT 24 Aug 01 05:38:50 PM PDT 24 40624050 ps
T848 /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.3238764166 Aug 01 05:38:25 PM PDT 24 Aug 01 05:38:52 PM PDT 24 363323122 ps
T849 /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.2339680422 Aug 01 05:36:18 PM PDT 24 Aug 01 05:37:03 PM PDT 24 5520931317 ps
T850 /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.1189996062 Aug 01 05:38:26 PM PDT 24 Aug 01 05:40:28 PM PDT 24 83143471691 ps
T851 /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.3966885114 Aug 01 05:37:16 PM PDT 24 Aug 01 05:37:43 PM PDT 24 193018995 ps
T852 /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1856949161 Aug 01 05:38:13 PM PDT 24 Aug 01 05:42:57 PM PDT 24 35924104939 ps
T853 /workspace/coverage/xbar_build_mode/41.xbar_random.3258139812 Aug 01 05:38:48 PM PDT 24 Aug 01 05:39:04 PM PDT 24 205800287 ps
T854 /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2568922905 Aug 01 05:39:36 PM PDT 24 Aug 01 05:45:24 PM PDT 24 5162817959 ps
T855 /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.2617890897 Aug 01 05:38:29 PM PDT 24 Aug 01 05:38:46 PM PDT 24 1833879886 ps
T856 /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.473851860 Aug 01 05:39:17 PM PDT 24 Aug 01 05:39:40 PM PDT 24 3929552929 ps
T857 /workspace/coverage/xbar_build_mode/25.xbar_same_source.1924800501 Aug 01 05:37:39 PM PDT 24 Aug 01 05:37:47 PM PDT 24 125848668 ps
T858 /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.1983958190 Aug 01 05:37:12 PM PDT 24 Aug 01 05:40:16 PM PDT 24 534742562 ps
T859 /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.1601372339 Aug 01 05:36:54 PM PDT 24 Aug 01 05:38:04 PM PDT 24 220836185 ps
T860 /workspace/coverage/xbar_build_mode/26.xbar_random.1857853065 Aug 01 05:37:41 PM PDT 24 Aug 01 05:38:01 PM PDT 24 135307112 ps
T861 /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3842188731 Aug 01 05:36:49 PM PDT 24 Aug 01 05:37:06 PM PDT 24 2260167617 ps
T862 /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.222085786 Aug 01 05:39:35 PM PDT 24 Aug 01 05:39:52 PM PDT 24 145616396 ps
T863 /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2259684205 Aug 01 05:36:58 PM PDT 24 Aug 01 05:40:48 PM PDT 24 17886509640 ps
T864 /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.1675821979 Aug 01 05:39:21 PM PDT 24 Aug 01 05:42:21 PM PDT 24 54885227132 ps
T865 /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1842567362 Aug 01 05:36:30 PM PDT 24 Aug 01 05:39:34 PM PDT 24 55443940319 ps
T866 /workspace/coverage/xbar_build_mode/28.xbar_smoke.4281628430 Aug 01 05:37:57 PM PDT 24 Aug 01 05:38:00 PM PDT 24 86730460 ps
T867 /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.964605690 Aug 01 05:37:57 PM PDT 24 Aug 01 05:38:12 PM PDT 24 613507970 ps
T868 /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1278081013 Aug 01 05:39:35 PM PDT 24 Aug 01 05:39:37 PM PDT 24 29387534 ps
T869 /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.3937630242 Aug 01 05:36:22 PM PDT 24 Aug 01 05:36:43 PM PDT 24 201035443 ps
T870 /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.3245051537 Aug 01 05:37:27 PM PDT 24 Aug 01 05:38:06 PM PDT 24 1776311529 ps
T871 /workspace/coverage/xbar_build_mode/15.xbar_smoke.3134395093 Aug 01 05:37:04 PM PDT 24 Aug 01 05:37:06 PM PDT 24 30848166 ps
T872 /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.3749733851 Aug 01 05:38:23 PM PDT 24 Aug 01 05:38:34 PM PDT 24 141642480 ps
T873 /workspace/coverage/xbar_build_mode/28.xbar_error_random.1107783936 Aug 01 05:37:59 PM PDT 24 Aug 01 05:38:02 PM PDT 24 174253561 ps
T874 /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2949225640 Aug 01 05:38:35 PM PDT 24 Aug 01 05:47:12 PM PDT 24 14444198681 ps
T875 /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1571250079 Aug 01 05:38:34 PM PDT 24 Aug 01 05:45:45 PM PDT 24 48368612770 ps
T876 /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.3776017311 Aug 01 05:39:36 PM PDT 24 Aug 01 05:39:50 PM PDT 24 133951580 ps
T877 /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.1002513979 Aug 01 05:37:03 PM PDT 24 Aug 01 05:37:21 PM PDT 24 386952145 ps
T878 /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.866382534 Aug 01 05:37:01 PM PDT 24 Aug 01 05:37:24 PM PDT 24 679804786 ps
T879 /workspace/coverage/xbar_build_mode/33.xbar_error_random.756830460 Aug 01 05:38:18 PM PDT 24 Aug 01 05:38:23 PM PDT 24 162194933 ps
T41 /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.3067520109 Aug 01 05:38:47 PM PDT 24 Aug 01 05:46:30 PM PDT 24 9871924885 ps
T880 /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.3055744391 Aug 01 05:39:19 PM PDT 24 Aug 01 05:39:51 PM PDT 24 5672930278 ps
T881 /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.1435077104 Aug 01 05:38:09 PM PDT 24 Aug 01 05:38:42 PM PDT 24 774964863 ps
T882 /workspace/coverage/xbar_build_mode/4.xbar_same_source.3165417120 Aug 01 05:36:31 PM PDT 24 Aug 01 05:36:33 PM PDT 24 34503255 ps
T195 /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2123000381 Aug 01 05:38:12 PM PDT 24 Aug 01 05:40:47 PM PDT 24 37240570664 ps
T883 /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1133410926 Aug 01 05:36:44 PM PDT 24 Aug 01 05:36:47 PM PDT 24 36814262 ps
T884 /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1002639439 Aug 01 05:36:50 PM PDT 24 Aug 01 05:36:52 PM PDT 24 25915229 ps
T885 /workspace/coverage/xbar_build_mode/47.xbar_stress_all.3137476034 Aug 01 05:39:32 PM PDT 24 Aug 01 05:40:13 PM PDT 24 2862647920 ps
T886 /workspace/coverage/xbar_build_mode/45.xbar_same_source.3454269203 Aug 01 05:39:18 PM PDT 24 Aug 01 05:39:23 PM PDT 24 148036153 ps
T171 /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1398557445 Aug 01 05:37:18 PM PDT 24 Aug 01 05:37:40 PM PDT 24 7259450746 ps
T887 /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.1672069218 Aug 01 05:38:32 PM PDT 24 Aug 01 05:39:04 PM PDT 24 872054272 ps
T888 /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.1863574645 Aug 01 05:37:01 PM PDT 24 Aug 01 05:40:42 PM PDT 24 1650138349 ps
T889 /workspace/coverage/xbar_build_mode/48.xbar_error_random.595691395 Aug 01 05:39:35 PM PDT 24 Aug 01 05:40:03 PM PDT 24 1103603704 ps
T890 /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.3182931301 Aug 01 05:37:07 PM PDT 24 Aug 01 05:37:37 PM PDT 24 217459004 ps
T130 /workspace/coverage/xbar_build_mode/14.xbar_same_source.2139141708 Aug 01 05:37:02 PM PDT 24 Aug 01 05:37:29 PM PDT 24 2322872732 ps
T891 /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.351917501 Aug 01 05:38:48 PM PDT 24 Aug 01 05:43:20 PM PDT 24 4769498950 ps
T892 /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.3487780718 Aug 01 05:36:59 PM PDT 24 Aug 01 05:37:02 PM PDT 24 50008650 ps
T893 /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.627273433 Aug 01 05:39:33 PM PDT 24 Aug 01 05:40:15 PM PDT 24 302104724 ps
T894 /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2249446501 Aug 01 05:39:35 PM PDT 24 Aug 01 05:40:03 PM PDT 24 3904014940 ps
T895 /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.499982699 Aug 01 05:38:28 PM PDT 24 Aug 01 05:38:35 PM PDT 24 62349961 ps
T896 /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.3826118662 Aug 01 05:39:34 PM PDT 24 Aug 01 05:39:57 PM PDT 24 3015062411 ps
T897 /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.4263632496 Aug 01 05:39:20 PM PDT 24 Aug 01 05:42:47 PM PDT 24 32643472486 ps
T898 /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.3132918685 Aug 01 05:36:42 PM PDT 24 Aug 01 05:39:58 PM PDT 24 35203770482 ps
T899 /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.412883910 Aug 01 05:38:23 PM PDT 24 Aug 01 05:38:46 PM PDT 24 557378360 ps
T900 /workspace/coverage/xbar_build_mode/10.xbar_random.1973673258 Aug 01 05:36:46 PM PDT 24 Aug 01 05:37:04 PM PDT 24 226866145 ps
T190 /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.2587087060 Aug 01 05:36:32 PM PDT 24 Aug 01 05:44:49 PM PDT 24 12422892785 ps

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.759924677
Short name T12
Test name
Test status
Simulation time 1614287020 ps
CPU time 238.22 seconds
Started Aug 01 05:37:08 PM PDT 24
Finished Aug 01 05:41:06 PM PDT 24
Peak memory 219408 kb
Host smart-dc9cd36b-6522-45c7-88ed-898b9d68c148
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=759924677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_res
et_error.759924677
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.1152821332
Short name T7
Test name
Test status
Simulation time 87976151817 ps
CPU time 678.34 seconds
Started Aug 01 05:39:32 PM PDT 24
Finished Aug 01 05:50:50 PM PDT 24
Peak memory 211756 kb
Host smart-76495f9f-acb7-4fd3-aa66-03ea2199820f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1152821332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl
ow_rsp.1152821332
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.713334339
Short name T25
Test name
Test status
Simulation time 98328457576 ps
CPU time 667.91 seconds
Started Aug 01 05:37:20 PM PDT 24
Finished Aug 01 05:48:28 PM PDT 24
Peak memory 211704 kb
Host smart-88865624-6eb3-46dc-a258-e6330f68d900
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=713334339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slo
w_rsp.713334339
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2293911626
Short name T89
Test name
Test status
Simulation time 4078365932 ps
CPU time 134.58 seconds
Started Aug 01 05:38:33 PM PDT 24
Finished Aug 01 05:40:48 PM PDT 24
Peak memory 208264 kb
Host smart-985e5a91-016f-4853-bc3f-d64780fb5998
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2293911626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2293911626
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.4117158748
Short name T144
Test name
Test status
Simulation time 1411711593 ps
CPU time 140.32 seconds
Started Aug 01 05:38:12 PM PDT 24
Finished Aug 01 05:40:33 PM PDT 24
Peak memory 209420 kb
Host smart-1061adb4-34f0-4b9c-961a-5ddc497790cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4117158748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.4117158748
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.3475522942
Short name T9
Test name
Test status
Simulation time 53939128559 ps
CPU time 248.63 seconds
Started Aug 01 05:36:44 PM PDT 24
Finished Aug 01 05:40:52 PM PDT 24
Peak memory 204872 kb
Host smart-19609437-b8c5-4ee7-8d10-6a08f9d8ef72
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475522942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3475522942
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.173380260
Short name T93
Test name
Test status
Simulation time 183517921740 ps
CPU time 527.71 seconds
Started Aug 01 05:37:38 PM PDT 24
Finished Aug 01 05:46:26 PM PDT 24
Peak memory 206908 kb
Host smart-cfac6a01-dadd-4f87-834d-ad5426827119
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=173380260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slo
w_rsp.173380260
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3323764568
Short name T81
Test name
Test status
Simulation time 135798024149 ps
CPU time 544.69 seconds
Started Aug 01 05:38:46 PM PDT 24
Finished Aug 01 05:47:51 PM PDT 24
Peak memory 211692 kb
Host smart-6e399c20-6926-4f90-bc61-f82a936f3e39
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3323764568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl
ow_rsp.3323764568
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.3330549920
Short name T43
Test name
Test status
Simulation time 1934037924 ps
CPU time 202.99 seconds
Started Aug 01 05:37:42 PM PDT 24
Finished Aug 01 05:41:05 PM PDT 24
Peak memory 208456 kb
Host smart-a2ed0727-7894-4ce6-ba44-cca3e32ce460
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3330549920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran
d_reset.3330549920
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.2255213882
Short name T121
Test name
Test status
Simulation time 11420266510 ps
CPU time 367.41 seconds
Started Aug 01 05:37:09 PM PDT 24
Finished Aug 01 05:43:17 PM PDT 24
Peak memory 211636 kb
Host smart-f1871c9d-32f5-430e-94fc-d64a1c7411a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2255213882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2255213882
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1680612664
Short name T36
Test name
Test status
Simulation time 720710585 ps
CPU time 207.28 seconds
Started Aug 01 05:37:01 PM PDT 24
Finished Aug 01 05:40:28 PM PDT 24
Peak memory 208372 kb
Host smart-2e82f401-c0d4-4e5a-a8d5-2abda82cd632
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1680612664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran
d_reset.1680612664
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.3236867801
Short name T4
Test name
Test status
Simulation time 5166391593 ps
CPU time 150.38 seconds
Started Aug 01 05:38:49 PM PDT 24
Finished Aug 01 05:41:19 PM PDT 24
Peak memory 209940 kb
Host smart-de2675ce-88f8-45d3-a508-f70455d71445
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3236867801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3236867801
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.2848694882
Short name T32
Test name
Test status
Simulation time 4724886916 ps
CPU time 290.34 seconds
Started Aug 01 05:36:23 PM PDT 24
Finished Aug 01 05:41:13 PM PDT 24
Peak memory 209764 kb
Host smart-2a6b67ce-03f7-4af7-8e80-c5ebc2c79084
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2848694882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand
_reset.2848694882
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.2599743772
Short name T91
Test name
Test status
Simulation time 11380920101 ps
CPU time 106.64 seconds
Started Aug 01 05:36:58 PM PDT 24
Finished Aug 01 05:38:45 PM PDT 24
Peak memory 211696 kb
Host smart-15a37417-d376-40b2-bbe1-9401fbaa94c1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2599743772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.2599743772
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.394453796
Short name T26
Test name
Test status
Simulation time 458763116 ps
CPU time 195.95 seconds
Started Aug 01 05:39:00 PM PDT 24
Finished Aug 01 05:42:16 PM PDT 24
Peak memory 208640 kb
Host smart-4b5b1100-0e77-4e53-8901-46f7f10939e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=394453796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand
_reset.394453796
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.502908611
Short name T122
Test name
Test status
Simulation time 113009704620 ps
CPU time 645.57 seconds
Started Aug 01 05:38:22 PM PDT 24
Finished Aug 01 05:49:07 PM PDT 24
Peak memory 211696 kb
Host smart-d8da5f20-e611-400c-991d-93fd2da374eb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=502908611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slo
w_rsp.502908611
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2886999509
Short name T34
Test name
Test status
Simulation time 6764680256 ps
CPU time 452.8 seconds
Started Aug 01 05:36:55 PM PDT 24
Finished Aug 01 05:44:28 PM PDT 24
Peak memory 208712 kb
Host smart-c0c6926b-0f09-4cc3-94de-d882aed7f304
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2886999509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran
d_reset.2886999509
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.4203068386
Short name T20
Test name
Test status
Simulation time 2295839132 ps
CPU time 240.88 seconds
Started Aug 01 05:39:02 PM PDT 24
Finished Aug 01 05:43:03 PM PDT 24
Peak memory 211744 kb
Host smart-bf98bae6-7ce2-4bc8-b13f-f3dcabcec1ca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4203068386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re
set_error.4203068386
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3907150584
Short name T129
Test name
Test status
Simulation time 50028069130 ps
CPU time 427.47 seconds
Started Aug 01 05:39:20 PM PDT 24
Finished Aug 01 05:46:28 PM PDT 24
Peak memory 206976 kb
Host smart-50e10682-8e6d-4aea-84f0-43e5dee33024
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3907150584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl
ow_rsp.3907150584
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.1325718225
Short name T198
Test name
Test status
Simulation time 1357626516 ps
CPU time 366.67 seconds
Started Aug 01 05:37:57 PM PDT 24
Finished Aug 01 05:44:04 PM PDT 24
Peak memory 208692 kb
Host smart-3c2375a1-d340-4b9b-b948-81a73e12dacc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1325718225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran
d_reset.1325718225
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3245689124
Short name T126
Test name
Test status
Simulation time 3555604890 ps
CPU time 269.04 seconds
Started Aug 01 05:37:23 PM PDT 24
Finished Aug 01 05:41:52 PM PDT 24
Peak memory 208292 kb
Host smart-9eea9130-37ff-43e2-8f6c-2d7f7439698d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3245689124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran
d_reset.3245689124
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.3099978165
Short name T556
Test name
Test status
Simulation time 6132904845 ps
CPU time 65.4 seconds
Started Aug 01 05:36:22 PM PDT 24
Finished Aug 01 05:37:28 PM PDT 24
Peak memory 211748 kb
Host smart-795048b0-1f78-4359-8b04-d6482053e43b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3099978165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3099978165
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.3664414589
Short name T209
Test name
Test status
Simulation time 90315259986 ps
CPU time 462.55 seconds
Started Aug 01 05:36:21 PM PDT 24
Finished Aug 01 05:44:04 PM PDT 24
Peak memory 211660 kb
Host smart-7c1f5691-ce2c-4e00-ad8c-920d8e75093c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3664414589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo
w_rsp.3664414589
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.2181290929
Short name T698
Test name
Test status
Simulation time 331512535 ps
CPU time 18.6 seconds
Started Aug 01 05:36:22 PM PDT 24
Finished Aug 01 05:36:41 PM PDT 24
Peak memory 204040 kb
Host smart-4c54babc-c74d-4e73-9594-14dcc3dd9177
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2181290929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.2181290929
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.3712889755
Short name T442
Test name
Test status
Simulation time 150202038 ps
CPU time 9.87 seconds
Started Aug 01 05:36:23 PM PDT 24
Finished Aug 01 05:36:33 PM PDT 24
Peak memory 203460 kb
Host smart-c2ab1e01-20df-49c1-8c5e-bc2eb243676e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3712889755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3712889755
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.1795260198
Short name T721
Test name
Test status
Simulation time 3561549205 ps
CPU time 33.42 seconds
Started Aug 01 05:36:22 PM PDT 24
Finished Aug 01 05:36:55 PM PDT 24
Peak memory 211708 kb
Host smart-c4c41a25-7f67-437c-b5d9-bbe185167ecc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1795260198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.1795260198
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.3306000472
Short name T169
Test name
Test status
Simulation time 13154533646 ps
CPU time 81.77 seconds
Started Aug 01 05:36:21 PM PDT 24
Finished Aug 01 05:37:43 PM PDT 24
Peak memory 211552 kb
Host smart-4195c059-bae2-4c54-9d77-3ba5084a7816
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306000472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3306000472
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1760994300
Short name T455
Test name
Test status
Simulation time 16575719699 ps
CPU time 129.37 seconds
Started Aug 01 05:36:22 PM PDT 24
Finished Aug 01 05:38:32 PM PDT 24
Peak memory 205108 kb
Host smart-26b298a4-0350-4b97-9519-a65a708f64a5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1760994300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1760994300
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.3899883251
Short name T351
Test name
Test status
Simulation time 186771519 ps
CPU time 26.67 seconds
Started Aug 01 05:36:24 PM PDT 24
Finished Aug 01 05:36:50 PM PDT 24
Peak memory 211680 kb
Host smart-86a1d45c-ef11-4044-a511-2265124d1433
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899883251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3899883251
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.4040434735
Short name T460
Test name
Test status
Simulation time 3597410080 ps
CPU time 27.28 seconds
Started Aug 01 05:36:22 PM PDT 24
Finished Aug 01 05:36:50 PM PDT 24
Peak memory 204212 kb
Host smart-7a886364-2048-4154-b551-d167108a151a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4040434735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.4040434735
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.3697042754
Short name T689
Test name
Test status
Simulation time 296097858 ps
CPU time 3.06 seconds
Started Aug 01 05:36:10 PM PDT 24
Finished Aug 01 05:36:14 PM PDT 24
Peak memory 203448 kb
Host smart-933ec5ca-0881-4335-b775-ce6150b9ae17
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3697042754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3697042754
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.282676276
Short name T571
Test name
Test status
Simulation time 27484995368 ps
CPU time 43.38 seconds
Started Aug 01 05:36:20 PM PDT 24
Finished Aug 01 05:37:04 PM PDT 24
Peak memory 203568 kb
Host smart-137acf9d-54c8-4be0-81bf-7cbc729f78be
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=282676276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.282676276
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1718891747
Short name T514
Test name
Test status
Simulation time 7408348431 ps
CPU time 28.42 seconds
Started Aug 01 05:36:23 PM PDT 24
Finished Aug 01 05:36:52 PM PDT 24
Peak memory 203468 kb
Host smart-fb8f3106-fe49-4d9f-b768-baa6ffa6dd71
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1718891747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1718891747
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.1593621510
Short name T414
Test name
Test status
Simulation time 116909755 ps
CPU time 1.84 seconds
Started Aug 01 05:36:12 PM PDT 24
Finished Aug 01 05:36:15 PM PDT 24
Peak memory 203384 kb
Host smart-272c5c9d-e510-46f5-8cd1-64164546e7ce
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593621510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1593621510
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.766742388
Short name T14
Test name
Test status
Simulation time 5866475364 ps
CPU time 196.49 seconds
Started Aug 01 05:36:21 PM PDT 24
Finished Aug 01 05:39:38 PM PDT 24
Peak memory 209272 kb
Host smart-d121030a-148d-4eea-9910-64f2ece8482f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=766742388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.766742388
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.2590702593
Short name T773
Test name
Test status
Simulation time 7240422649 ps
CPU time 179.84 seconds
Started Aug 01 05:36:21 PM PDT 24
Finished Aug 01 05:39:21 PM PDT 24
Peak memory 211672 kb
Host smart-1147e055-ce8d-4396-92d6-d8a39756354e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2590702593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.2590702593
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1964200607
Short name T165
Test name
Test status
Simulation time 1738902848 ps
CPU time 154.44 seconds
Started Aug 01 05:36:21 PM PDT 24
Finished Aug 01 05:38:56 PM PDT 24
Peak memory 208372 kb
Host smart-b75f0f5b-cfb8-4519-9ead-69d4a8871c7d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1964200607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand
_reset.1964200607
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.438071464
Short name T725
Test name
Test status
Simulation time 3481465951 ps
CPU time 202.55 seconds
Started Aug 01 05:36:23 PM PDT 24
Finished Aug 01 05:39:46 PM PDT 24
Peak memory 219900 kb
Host smart-f20a84d6-68dd-497d-8c95-cd3cd93759be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=438071464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rese
t_error.438071464
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.2109476540
Short name T440
Test name
Test status
Simulation time 313910438 ps
CPU time 3.89 seconds
Started Aug 01 05:36:21 PM PDT 24
Finished Aug 01 05:36:25 PM PDT 24
Peak memory 204212 kb
Host smart-f9d2a287-a7ac-4fa5-88c3-d50d13fe8560
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2109476540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2109476540
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.797017314
Short name T780
Test name
Test status
Simulation time 6481205410 ps
CPU time 61.22 seconds
Started Aug 01 05:36:20 PM PDT 24
Finished Aug 01 05:37:21 PM PDT 24
Peak memory 205828 kb
Host smart-596e879a-63c1-401e-ad92-cebc6cf6eb5b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=797017314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.797017314
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1646673136
Short name T97
Test name
Test status
Simulation time 107689081831 ps
CPU time 539.33 seconds
Started Aug 01 05:36:20 PM PDT 24
Finished Aug 01 05:45:20 PM PDT 24
Peak memory 207524 kb
Host smart-c692de23-3149-4780-86fc-facdf004a96a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1646673136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo
w_rsp.1646673136
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2582649452
Short name T382
Test name
Test status
Simulation time 21482026 ps
CPU time 3.28 seconds
Started Aug 01 05:36:20 PM PDT 24
Finished Aug 01 05:36:24 PM PDT 24
Peak memory 203476 kb
Host smart-dc455cba-ea6f-4e8e-8560-59889dfc1997
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2582649452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2582649452
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.2379029137
Short name T617
Test name
Test status
Simulation time 4393485846 ps
CPU time 30.73 seconds
Started Aug 01 05:36:23 PM PDT 24
Finished Aug 01 05:36:54 PM PDT 24
Peak memory 203516 kb
Host smart-f8e63539-053b-4f65-b2d8-78e43129c8bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2379029137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2379029137
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.4208755390
Short name T345
Test name
Test status
Simulation time 534022419 ps
CPU time 14.83 seconds
Started Aug 01 05:36:19 PM PDT 24
Finished Aug 01 05:36:34 PM PDT 24
Peak memory 211656 kb
Host smart-8b2d7902-0a27-4374-b5d0-08e4f71e5f4a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4208755390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.4208755390
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.3768302017
Short name T656
Test name
Test status
Simulation time 41771744039 ps
CPU time 203.04 seconds
Started Aug 01 05:36:22 PM PDT 24
Finished Aug 01 05:39:45 PM PDT 24
Peak memory 205216 kb
Host smart-55482e25-f740-4ec0-84cc-20d6e368bee2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768302017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3768302017
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.633720528
Short name T522
Test name
Test status
Simulation time 55328032298 ps
CPU time 199.85 seconds
Started Aug 01 05:36:22 PM PDT 24
Finished Aug 01 05:39:42 PM PDT 24
Peak memory 211800 kb
Host smart-0078c10a-888e-4ec0-9e9a-56bea18cbc38
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=633720528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.633720528
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.478848613
Short name T253
Test name
Test status
Simulation time 79376578 ps
CPU time 4.85 seconds
Started Aug 01 05:36:22 PM PDT 24
Finished Aug 01 05:36:27 PM PDT 24
Peak memory 204596 kb
Host smart-ff2937dd-c671-4c0f-8790-25c436ef6c85
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478848613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.478848613
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.3065688446
Short name T260
Test name
Test status
Simulation time 386149109 ps
CPU time 18.14 seconds
Started Aug 01 05:36:23 PM PDT 24
Finished Aug 01 05:36:41 PM PDT 24
Peak memory 204108 kb
Host smart-0cad3d4c-2890-47f5-8023-2e5bb6db0ab4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3065688446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3065688446
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.49335301
Short name T666
Test name
Test status
Simulation time 75773553 ps
CPU time 2.42 seconds
Started Aug 01 05:36:20 PM PDT 24
Finished Aug 01 05:36:22 PM PDT 24
Peak memory 203328 kb
Host smart-fefa0e4b-f379-4570-9205-dd2283656b59
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=49335301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.49335301
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1718230985
Short name T45
Test name
Test status
Simulation time 4347262588 ps
CPU time 23.69 seconds
Started Aug 01 05:36:23 PM PDT 24
Finished Aug 01 05:36:47 PM PDT 24
Peak memory 203480 kb
Host smart-4924b8f5-f3a5-47c1-a56c-cb9cc8baacfd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718230985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1718230985
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1864711310
Short name T214
Test name
Test status
Simulation time 7673843227 ps
CPU time 27.65 seconds
Started Aug 01 05:36:19 PM PDT 24
Finished Aug 01 05:36:47 PM PDT 24
Peak memory 203536 kb
Host smart-76bb13f4-67d7-4cfb-bd79-8e84eb30af18
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1864711310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1864711310
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.4136604331
Short name T471
Test name
Test status
Simulation time 57714767 ps
CPU time 2.28 seconds
Started Aug 01 05:36:24 PM PDT 24
Finished Aug 01 05:36:27 PM PDT 24
Peak memory 203452 kb
Host smart-354fc846-a718-4685-aa63-0da3a82f64c4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136604331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.4136604331
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.3995038236
Short name T301
Test name
Test status
Simulation time 89132004 ps
CPU time 2.21 seconds
Started Aug 01 05:36:20 PM PDT 24
Finished Aug 01 05:36:22 PM PDT 24
Peak memory 203416 kb
Host smart-8cf24343-00ae-47c5-a690-ef361bea394d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3995038236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3995038236
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2808547231
Short name T431
Test name
Test status
Simulation time 3272268154 ps
CPU time 113.93 seconds
Started Aug 01 05:36:24 PM PDT 24
Finished Aug 01 05:38:18 PM PDT 24
Peak memory 206400 kb
Host smart-3390460e-65b6-4188-8633-74adefa86e08
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2808547231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2808547231
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.3633688351
Short name T147
Test name
Test status
Simulation time 6914479026 ps
CPU time 399.43 seconds
Started Aug 01 05:36:26 PM PDT 24
Finished Aug 01 05:43:05 PM PDT 24
Peak memory 208620 kb
Host smart-d772314a-e360-404a-af8e-4a6916deae46
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3633688351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand
_reset.3633688351
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.1008789064
Short name T30
Test name
Test status
Simulation time 3890514812 ps
CPU time 389.48 seconds
Started Aug 01 05:36:22 PM PDT 24
Finished Aug 01 05:42:52 PM PDT 24
Peak memory 219932 kb
Host smart-eae97022-ca0e-4186-a76d-1f01b122c74f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1008789064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res
et_error.1008789064
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.3937630242
Short name T869
Test name
Test status
Simulation time 201035443 ps
CPU time 20.61 seconds
Started Aug 01 05:36:22 PM PDT 24
Finished Aug 01 05:36:43 PM PDT 24
Peak memory 205648 kb
Host smart-0d6a23bd-b415-41be-b81d-cf8557a1c0da
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3937630242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3937630242
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.3153437679
Short name T715
Test name
Test status
Simulation time 1238564748 ps
CPU time 17.76 seconds
Started Aug 01 05:36:53 PM PDT 24
Finished Aug 01 05:37:11 PM PDT 24
Peak memory 211668 kb
Host smart-bd0b26e0-12a9-47d6-bfe0-46ab34cef843
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3153437679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3153437679
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1447836427
Short name T194
Test name
Test status
Simulation time 18775432970 ps
CPU time 84.8 seconds
Started Aug 01 05:36:59 PM PDT 24
Finished Aug 01 05:38:24 PM PDT 24
Peak memory 211700 kb
Host smart-10a0a3cf-8f59-4fd2-80fa-0efc5ebfcd60
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1447836427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl
ow_rsp.1447836427
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.278938745
Short name T700
Test name
Test status
Simulation time 156760317 ps
CPU time 12.93 seconds
Started Aug 01 05:36:58 PM PDT 24
Finished Aug 01 05:37:11 PM PDT 24
Peak memory 203972 kb
Host smart-d33d37e2-a374-4800-93ba-91567eb43ad5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=278938745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.278938745
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.2940758936
Short name T350
Test name
Test status
Simulation time 3162747705 ps
CPU time 24.61 seconds
Started Aug 01 05:36:55 PM PDT 24
Finished Aug 01 05:37:20 PM PDT 24
Peak memory 203524 kb
Host smart-dc389636-9c6d-4e9d-8836-da5188d3788d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2940758936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2940758936
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.1973673258
Short name T900
Test name
Test status
Simulation time 226866145 ps
CPU time 17.61 seconds
Started Aug 01 05:36:46 PM PDT 24
Finished Aug 01 05:37:04 PM PDT 24
Peak memory 211684 kb
Host smart-f0ffac65-e352-4271-9e7a-84ea26a993a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1973673258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.1973673258
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.3070905534
Short name T2
Test name
Test status
Simulation time 8125196326 ps
CPU time 50.35 seconds
Started Aug 01 05:36:54 PM PDT 24
Finished Aug 01 05:37:45 PM PDT 24
Peak memory 204828 kb
Host smart-a496faa6-0a1d-40dd-bc88-8a52852964e1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070905534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3070905534
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.4187484608
Short name T610
Test name
Test status
Simulation time 22640052639 ps
CPU time 169.96 seconds
Started Aug 01 05:36:56 PM PDT 24
Finished Aug 01 05:39:47 PM PDT 24
Peak memory 204716 kb
Host smart-1cccf59c-a3ba-445e-8ac7-46f1064739d2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4187484608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.4187484608
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.414891775
Short name T399
Test name
Test status
Simulation time 194296702 ps
CPU time 25.67 seconds
Started Aug 01 05:36:58 PM PDT 24
Finished Aug 01 05:37:24 PM PDT 24
Peak memory 204528 kb
Host smart-90bd0b12-3843-42df-b672-bff2f0831857
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414891775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.414891775
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.510295360
Short name T481
Test name
Test status
Simulation time 4199545552 ps
CPU time 26.11 seconds
Started Aug 01 05:36:56 PM PDT 24
Finished Aug 01 05:37:23 PM PDT 24
Peak memory 203476 kb
Host smart-a6cf4614-d364-4b22-8b0a-8ad7f2808989
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=510295360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.510295360
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.3496222104
Short name T99
Test name
Test status
Simulation time 187344250 ps
CPU time 3.67 seconds
Started Aug 01 05:36:44 PM PDT 24
Finished Aug 01 05:36:48 PM PDT 24
Peak memory 203548 kb
Host smart-558b09ba-3201-491f-95b7-56e9ac2da07d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3496222104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3496222104
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.2528730849
Short name T110
Test name
Test status
Simulation time 7714482443 ps
CPU time 37.18 seconds
Started Aug 01 05:36:48 PM PDT 24
Finished Aug 01 05:37:26 PM PDT 24
Peak memory 203504 kb
Host smart-2e6d234b-d6bd-44c7-8dbf-e450462c23ed
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528730849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2528730849
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3842188731
Short name T861
Test name
Test status
Simulation time 2260167617 ps
CPU time 17.52 seconds
Started Aug 01 05:36:49 PM PDT 24
Finished Aug 01 05:37:06 PM PDT 24
Peak memory 203604 kb
Host smart-f54f006e-31ad-4231-9ae0-e3bfd1fc30bc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3842188731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3842188731
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1133410926
Short name T883
Test name
Test status
Simulation time 36814262 ps
CPU time 2.76 seconds
Started Aug 01 05:36:44 PM PDT 24
Finished Aug 01 05:36:47 PM PDT 24
Peak memory 203476 kb
Host smart-5b2f94c6-3602-4f8b-8747-67360e50d6c5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133410926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.1133410926
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.1663601786
Short name T591
Test name
Test status
Simulation time 1164428040 ps
CPU time 109.05 seconds
Started Aug 01 05:36:57 PM PDT 24
Finished Aug 01 05:38:46 PM PDT 24
Peak memory 206856 kb
Host smart-26b5af5a-e983-4cf4-87ac-57c0641e82a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1663601786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1663601786
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.2737629914
Short name T751
Test name
Test status
Simulation time 301008103 ps
CPU time 55.11 seconds
Started Aug 01 05:36:58 PM PDT 24
Finished Aug 01 05:37:53 PM PDT 24
Peak memory 204640 kb
Host smart-d3c58cd5-4def-4708-a9d6-0fda5e8e4266
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2737629914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2737629914
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.333820602
Short name T778
Test name
Test status
Simulation time 484856914 ps
CPU time 198.66 seconds
Started Aug 01 05:37:02 PM PDT 24
Finished Aug 01 05:40:20 PM PDT 24
Peak memory 209172 kb
Host smart-c58ecbac-95af-46b6-9546-53e88e5c956c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=333820602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand
_reset.333820602
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.4206933545
Short name T313
Test name
Test status
Simulation time 1220007959 ps
CPU time 198.28 seconds
Started Aug 01 05:36:57 PM PDT 24
Finished Aug 01 05:40:16 PM PDT 24
Peak memory 211504 kb
Host smart-0e84e6c8-ff85-4a52-8c95-795f51fd4415
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4206933545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re
set_error.4206933545
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.1028703099
Short name T593
Test name
Test status
Simulation time 260758743 ps
CPU time 18.03 seconds
Started Aug 01 05:36:56 PM PDT 24
Finished Aug 01 05:37:14 PM PDT 24
Peak memory 204988 kb
Host smart-a91167c0-386b-4ff9-81eb-2bd52957a150
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1028703099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1028703099
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.866382534
Short name T878
Test name
Test status
Simulation time 679804786 ps
CPU time 22.21 seconds
Started Aug 01 05:37:01 PM PDT 24
Finished Aug 01 05:37:24 PM PDT 24
Peak memory 211656 kb
Host smart-3c4060e6-91d9-4fc8-8dbe-9345c5f981c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=866382534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.866382534
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.2933322253
Short name T241
Test name
Test status
Simulation time 62308647953 ps
CPU time 118.15 seconds
Started Aug 01 05:36:56 PM PDT 24
Finished Aug 01 05:38:54 PM PDT 24
Peak memory 211724 kb
Host smart-20de6c5a-d499-48f3-b0e5-41e9f61cbbde
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2933322253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl
ow_rsp.2933322253
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.1002513979
Short name T877
Test name
Test status
Simulation time 386952145 ps
CPU time 18.21 seconds
Started Aug 01 05:37:03 PM PDT 24
Finished Aug 01 05:37:21 PM PDT 24
Peak memory 203472 kb
Host smart-b8389e88-5cf0-46cb-a6dc-7fd43e68d69b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1002513979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.1002513979
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.3478896672
Short name T321
Test name
Test status
Simulation time 1109155498 ps
CPU time 8.82 seconds
Started Aug 01 05:36:57 PM PDT 24
Finished Aug 01 05:37:06 PM PDT 24
Peak memory 203456 kb
Host smart-f2e53490-a71c-493d-9fd1-82a0ba13e22f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3478896672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3478896672
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.2439433050
Short name T47
Test name
Test status
Simulation time 502883479 ps
CPU time 22.53 seconds
Started Aug 01 05:36:55 PM PDT 24
Finished Aug 01 05:37:18 PM PDT 24
Peak memory 211656 kb
Host smart-cd278de8-8351-4524-bbe8-f664b266a15f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2439433050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.2439433050
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.908141343
Short name T517
Test name
Test status
Simulation time 26161847839 ps
CPU time 148.15 seconds
Started Aug 01 05:36:55 PM PDT 24
Finished Aug 01 05:39:24 PM PDT 24
Peak memory 211704 kb
Host smart-4d2d767d-1430-4248-8c10-613cb2f04552
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=908141343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.908141343
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.1039978419
Short name T395
Test name
Test status
Simulation time 28296460233 ps
CPU time 86.07 seconds
Started Aug 01 05:36:58 PM PDT 24
Finished Aug 01 05:38:24 PM PDT 24
Peak memory 211740 kb
Host smart-1fbd98d0-6a32-490e-b1c0-52d0a8186f56
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1039978419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1039978419
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.935474214
Short name T731
Test name
Test status
Simulation time 253278052 ps
CPU time 23.33 seconds
Started Aug 01 05:36:56 PM PDT 24
Finished Aug 01 05:37:20 PM PDT 24
Peak memory 211644 kb
Host smart-4ca784c8-65f3-4afa-a17c-ae5460ebd37b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935474214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.935474214
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.1274240883
Short name T783
Test name
Test status
Simulation time 546579387 ps
CPU time 17.58 seconds
Started Aug 01 05:36:54 PM PDT 24
Finished Aug 01 05:37:11 PM PDT 24
Peak memory 204052 kb
Host smart-3baaa7c9-8879-4141-bbc6-1d2810111255
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1274240883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1274240883
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.3422247264
Short name T732
Test name
Test status
Simulation time 389403971 ps
CPU time 3.49 seconds
Started Aug 01 05:37:01 PM PDT 24
Finished Aug 01 05:37:05 PM PDT 24
Peak memory 203488 kb
Host smart-99bbecd3-d2f1-4667-94a7-34999357fcae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3422247264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3422247264
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.2722229451
Short name T160
Test name
Test status
Simulation time 10536752928 ps
CPU time 33.35 seconds
Started Aug 01 05:36:56 PM PDT 24
Finished Aug 01 05:37:29 PM PDT 24
Peak memory 203560 kb
Host smart-c7093fba-1509-40a7-9c06-f83e9dab25dc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722229451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2722229451
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3717811490
Short name T374
Test name
Test status
Simulation time 4489590470 ps
CPU time 28.26 seconds
Started Aug 01 05:36:57 PM PDT 24
Finished Aug 01 05:37:25 PM PDT 24
Peak memory 203492 kb
Host smart-750fc7aa-7ab5-4a35-b071-37be222c4469
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3717811490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3717811490
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.1152306258
Short name T678
Test name
Test status
Simulation time 29276000 ps
CPU time 2.37 seconds
Started Aug 01 05:37:01 PM PDT 24
Finished Aug 01 05:37:04 PM PDT 24
Peak memory 203488 kb
Host smart-e7c08085-b0fe-4827-9560-1e772040550c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152306258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.1152306258
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.2824532090
Short name T836
Test name
Test status
Simulation time 4634577060 ps
CPU time 128.24 seconds
Started Aug 01 05:36:57 PM PDT 24
Finished Aug 01 05:39:05 PM PDT 24
Peak memory 207284 kb
Host smart-51b5d808-2154-44c8-a475-73efe38cd71c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2824532090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2824532090
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1357517649
Short name T272
Test name
Test status
Simulation time 1005785982 ps
CPU time 100.57 seconds
Started Aug 01 05:37:01 PM PDT 24
Finished Aug 01 05:38:42 PM PDT 24
Peak memory 207188 kb
Host smart-07f6909a-3c99-44cd-9a16-8db51a9e819c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1357517649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1357517649
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.1714118969
Short name T432
Test name
Test status
Simulation time 60180281 ps
CPU time 23.71 seconds
Started Aug 01 05:36:55 PM PDT 24
Finished Aug 01 05:37:19 PM PDT 24
Peak memory 206500 kb
Host smart-445d0fb4-81a3-4552-b142-01c806f4d9d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1714118969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran
d_reset.1714118969
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.2311579876
Short name T423
Test name
Test status
Simulation time 108123146 ps
CPU time 42.76 seconds
Started Aug 01 05:36:54 PM PDT 24
Finished Aug 01 05:37:37 PM PDT 24
Peak memory 206580 kb
Host smart-5d9a060c-8f80-4c92-aa05-d0e602e9a4a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2311579876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re
set_error.2311579876
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2028249240
Short name T771
Test name
Test status
Simulation time 786642551 ps
CPU time 32.22 seconds
Started Aug 01 05:36:58 PM PDT 24
Finished Aug 01 05:37:30 PM PDT 24
Peak memory 211660 kb
Host smart-50308b13-15dd-4a1a-ae2a-5238591eb251
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2028249240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2028249240
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.2457082191
Short name T465
Test name
Test status
Simulation time 1163380483 ps
CPU time 32.99 seconds
Started Aug 01 05:36:55 PM PDT 24
Finished Aug 01 05:37:29 PM PDT 24
Peak memory 211688 kb
Host smart-9e2d6360-67dd-4764-b1ad-bec89cba2e9a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2457082191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2457082191
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.4271969889
Short name T569
Test name
Test status
Simulation time 125717656466 ps
CPU time 492.66 seconds
Started Aug 01 05:36:59 PM PDT 24
Finished Aug 01 05:45:12 PM PDT 24
Peak memory 211664 kb
Host smart-bc3f359b-8643-47b4-86b6-7e525a7d7c11
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4271969889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl
ow_rsp.4271969889
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.1625484165
Short name T650
Test name
Test status
Simulation time 551408153 ps
CPU time 9.64 seconds
Started Aug 01 05:36:55 PM PDT 24
Finished Aug 01 05:37:05 PM PDT 24
Peak memory 203456 kb
Host smart-23570fc2-2632-4833-9e19-804f10f0314c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1625484165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.1625484165
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.4167881950
Short name T159
Test name
Test status
Simulation time 1571656772 ps
CPU time 26.68 seconds
Started Aug 01 05:36:58 PM PDT 24
Finished Aug 01 05:37:25 PM PDT 24
Peak memory 203500 kb
Host smart-c2af29c5-fac0-4baf-8cee-8dcd6514e7f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4167881950 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.4167881950
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.3270461262
Short name T653
Test name
Test status
Simulation time 636339864 ps
CPU time 22.99 seconds
Started Aug 01 05:36:54 PM PDT 24
Finished Aug 01 05:37:17 PM PDT 24
Peak memory 211588 kb
Host smart-02a1b9d9-997e-41bb-b3e6-a1adf4e5516d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3270461262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3270461262
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.3036734331
Short name T826
Test name
Test status
Simulation time 23625770999 ps
CPU time 76.58 seconds
Started Aug 01 05:36:57 PM PDT 24
Finished Aug 01 05:38:14 PM PDT 24
Peak memory 211784 kb
Host smart-bba12b73-e04f-4172-8e22-1c234588f910
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036734331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3036734331
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3916486827
Short name T31
Test name
Test status
Simulation time 21103376085 ps
CPU time 184.88 seconds
Started Aug 01 05:36:53 PM PDT 24
Finished Aug 01 05:39:58 PM PDT 24
Peak memory 211640 kb
Host smart-5d1c7cd5-4a1d-4cc3-86b1-ec865b45284d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3916486827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3916486827
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.32451866
Short name T204
Test name
Test status
Simulation time 134105487 ps
CPU time 11.78 seconds
Started Aug 01 05:36:59 PM PDT 24
Finished Aug 01 05:37:11 PM PDT 24
Peak memory 204564 kb
Host smart-c0235fc6-7edf-4f78-a75b-fdf463eaf02c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32451866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.32451866
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.4254812714
Short name T223
Test name
Test status
Simulation time 5495625376 ps
CPU time 19.72 seconds
Started Aug 01 05:37:00 PM PDT 24
Finished Aug 01 05:37:20 PM PDT 24
Peak memory 204628 kb
Host smart-8d16072d-ce4a-4bc8-96d4-14f3589e04b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4254812714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.4254812714
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.919842572
Short name T428
Test name
Test status
Simulation time 58539104 ps
CPU time 2.57 seconds
Started Aug 01 05:36:59 PM PDT 24
Finished Aug 01 05:37:02 PM PDT 24
Peak memory 203492 kb
Host smart-8ba4813e-393d-4f45-a036-179848e6ee29
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=919842572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.919842572
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.2410056136
Short name T696
Test name
Test status
Simulation time 15973863254 ps
CPU time 31.37 seconds
Started Aug 01 05:36:55 PM PDT 24
Finished Aug 01 05:37:26 PM PDT 24
Peak memory 203532 kb
Host smart-80519eba-d479-4548-ab0b-6ff8e27af8be
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410056136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2410056136
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1095804512
Short name T168
Test name
Test status
Simulation time 3100037220 ps
CPU time 20.17 seconds
Started Aug 01 05:36:58 PM PDT 24
Finished Aug 01 05:37:18 PM PDT 24
Peak memory 203536 kb
Host smart-fea041c3-1d3a-4ad7-8bb8-015fe1f96d5c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1095804512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1095804512
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.552390752
Short name T164
Test name
Test status
Simulation time 49056624 ps
CPU time 2.39 seconds
Started Aug 01 05:36:58 PM PDT 24
Finished Aug 01 05:37:01 PM PDT 24
Peak memory 203472 kb
Host smart-f6dfba2b-856c-49c2-af3d-6a5004526707
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552390752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.552390752
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.1698605898
Short name T88
Test name
Test status
Simulation time 1534873430 ps
CPU time 189.02 seconds
Started Aug 01 05:37:00 PM PDT 24
Finished Aug 01 05:40:09 PM PDT 24
Peak memory 210320 kb
Host smart-47d6122c-4899-4602-a81c-81cd90cafcc7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1698605898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1698605898
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2259684205
Short name T863
Test name
Test status
Simulation time 17886509640 ps
CPU time 230.14 seconds
Started Aug 01 05:36:58 PM PDT 24
Finished Aug 01 05:40:48 PM PDT 24
Peak memory 211176 kb
Host smart-9c9c8dd9-3694-40b6-8050-bb1a00ecbfb5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2259684205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2259684205
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.1601372339
Short name T859
Test name
Test status
Simulation time 220836185 ps
CPU time 69.54 seconds
Started Aug 01 05:36:54 PM PDT 24
Finished Aug 01 05:38:04 PM PDT 24
Peak memory 208164 kb
Host smart-e317be42-ef85-4351-ad49-d0d785d30c8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1601372339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re
set_error.1601372339
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1243116299
Short name T513
Test name
Test status
Simulation time 747963490 ps
CPU time 29.55 seconds
Started Aug 01 05:36:59 PM PDT 24
Finished Aug 01 05:37:28 PM PDT 24
Peak memory 211572 kb
Host smart-a766dcd2-2c73-4dfb-a3e6-16c34ef42d33
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1243116299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1243116299
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.2887107630
Short name T146
Test name
Test status
Simulation time 436306528 ps
CPU time 28.93 seconds
Started Aug 01 05:36:58 PM PDT 24
Finished Aug 01 05:37:27 PM PDT 24
Peak memory 205924 kb
Host smart-8caa255f-23fd-428f-b21a-46137314e2ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2887107630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2887107630
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.2459120795
Short name T528
Test name
Test status
Simulation time 69432723495 ps
CPU time 546.95 seconds
Started Aug 01 05:36:58 PM PDT 24
Finished Aug 01 05:46:05 PM PDT 24
Peak memory 211700 kb
Host smart-7e63fdd6-6ddc-4587-8d2a-1638b6814279
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2459120795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl
ow_rsp.2459120795
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2833363757
Short name T70
Test name
Test status
Simulation time 794539502 ps
CPU time 23.45 seconds
Started Aug 01 05:37:03 PM PDT 24
Finished Aug 01 05:37:26 PM PDT 24
Peak memory 203468 kb
Host smart-4286b832-c489-4b35-9241-a3405544c8dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2833363757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2833363757
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.3524382748
Short name T646
Test name
Test status
Simulation time 99352723 ps
CPU time 10.19 seconds
Started Aug 01 05:36:58 PM PDT 24
Finished Aug 01 05:37:09 PM PDT 24
Peak memory 203452 kb
Host smart-a98f15e9-054b-49d3-828f-f27d980b06d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3524382748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3524382748
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.529439224
Short name T714
Test name
Test status
Simulation time 1021254560 ps
CPU time 24.88 seconds
Started Aug 01 05:36:57 PM PDT 24
Finished Aug 01 05:37:22 PM PDT 24
Peak memory 211672 kb
Host smart-ba83c2c5-a0fa-402c-8d12-fc1b73b5ab7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=529439224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.529439224
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.2659960675
Short name T529
Test name
Test status
Simulation time 35683949907 ps
CPU time 208.81 seconds
Started Aug 01 05:37:01 PM PDT 24
Finished Aug 01 05:40:30 PM PDT 24
Peak memory 204808 kb
Host smart-4e69d91b-1391-4e10-8d22-e89d181432b3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659960675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2659960675
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2087762221
Short name T742
Test name
Test status
Simulation time 37378591524 ps
CPU time 229.44 seconds
Started Aug 01 05:37:13 PM PDT 24
Finished Aug 01 05:41:02 PM PDT 24
Peak memory 211672 kb
Host smart-85846df8-f86f-478e-a314-2238a900acc5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2087762221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2087762221
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.3222147258
Short name T48
Test name
Test status
Simulation time 49071820 ps
CPU time 6.48 seconds
Started Aug 01 05:36:58 PM PDT 24
Finished Aug 01 05:37:05 PM PDT 24
Peak memory 211676 kb
Host smart-1395b8d6-ec23-4869-81a4-30ade8048149
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222147258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3222147258
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.1820799168
Short name T621
Test name
Test status
Simulation time 829502451 ps
CPU time 18.5 seconds
Started Aug 01 05:37:02 PM PDT 24
Finished Aug 01 05:37:20 PM PDT 24
Peak memory 204032 kb
Host smart-651e62d6-9a7a-4a62-8bba-627b45b64d46
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1820799168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1820799168
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.1232812107
Short name T530
Test name
Test status
Simulation time 158169181 ps
CPU time 3.98 seconds
Started Aug 01 05:37:02 PM PDT 24
Finished Aug 01 05:37:06 PM PDT 24
Peak memory 203484 kb
Host smart-876a4756-a886-4cff-aaf2-5568c24d0f2e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1232812107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1232812107
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2022929176
Short name T363
Test name
Test status
Simulation time 5126715174 ps
CPU time 30.76 seconds
Started Aug 01 05:36:58 PM PDT 24
Finished Aug 01 05:37:29 PM PDT 24
Peak memory 203592 kb
Host smart-cc7ed58c-5e62-478c-9f3e-a0224c596c53
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022929176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2022929176
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.1000463830
Short name T625
Test name
Test status
Simulation time 4679323323 ps
CPU time 30.49 seconds
Started Aug 01 05:37:01 PM PDT 24
Finished Aug 01 05:37:32 PM PDT 24
Peak memory 203500 kb
Host smart-e0419fec-cc54-4f9c-ae56-7fbddc4b6a39
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1000463830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1000463830
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.758935010
Short name T554
Test name
Test status
Simulation time 28728452 ps
CPU time 2.02 seconds
Started Aug 01 05:36:59 PM PDT 24
Finished Aug 01 05:37:01 PM PDT 24
Peak memory 203500 kb
Host smart-e752245e-4d94-4585-a79c-dd1400c00c76
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758935010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.758935010
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.603762819
Short name T257
Test name
Test status
Simulation time 764467761 ps
CPU time 28.01 seconds
Started Aug 01 05:36:59 PM PDT 24
Finished Aug 01 05:37:27 PM PDT 24
Peak memory 205860 kb
Host smart-9559e68f-56cd-4248-bf34-3c089b10fb1c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=603762819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.603762819
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.1863574645
Short name T888
Test name
Test status
Simulation time 1650138349 ps
CPU time 220.44 seconds
Started Aug 01 05:37:01 PM PDT 24
Finished Aug 01 05:40:42 PM PDT 24
Peak memory 212064 kb
Host smart-494fb637-3c47-42e4-ae53-6d172bb4643e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1863574645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1863574645
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.3800832005
Short name T447
Test name
Test status
Simulation time 4527262331 ps
CPU time 353.59 seconds
Started Aug 01 05:36:58 PM PDT 24
Finished Aug 01 05:42:52 PM PDT 24
Peak memory 224676 kb
Host smart-5469e72d-79ac-40c1-80f7-d07c2327c33b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3800832005 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re
set_error.3800832005
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.1156917464
Short name T768
Test name
Test status
Simulation time 437900141 ps
CPU time 23.48 seconds
Started Aug 01 05:37:01 PM PDT 24
Finished Aug 01 05:37:25 PM PDT 24
Peak memory 205312 kb
Host smart-0564d312-78dc-4741-956c-810bd8f2af79
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1156917464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1156917464
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.3894098798
Short name T80
Test name
Test status
Simulation time 2390564394 ps
CPU time 62.83 seconds
Started Aug 01 05:37:01 PM PDT 24
Finished Aug 01 05:38:04 PM PDT 24
Peak memory 205696 kb
Host smart-255509f6-ec8b-4969-be70-2f615c7d3079
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3894098798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.3894098798
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.2998745084
Short name T139
Test name
Test status
Simulation time 9201100806 ps
CPU time 58.35 seconds
Started Aug 01 05:37:02 PM PDT 24
Finished Aug 01 05:38:00 PM PDT 24
Peak memory 211712 kb
Host smart-8240a49a-650e-4b4e-915a-31541ac2956f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2998745084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl
ow_rsp.2998745084
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2238279303
Short name T809
Test name
Test status
Simulation time 53148128 ps
CPU time 8.19 seconds
Started Aug 01 05:37:03 PM PDT 24
Finished Aug 01 05:37:12 PM PDT 24
Peak memory 203504 kb
Host smart-f201865f-70a4-406d-9d06-f0308b77b09f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2238279303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2238279303
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.3867574505
Short name T766
Test name
Test status
Simulation time 519864276 ps
CPU time 9.32 seconds
Started Aug 01 05:37:03 PM PDT 24
Finished Aug 01 05:37:12 PM PDT 24
Peak memory 203372 kb
Host smart-1b01298d-f2e3-428d-8c92-6786a008fcff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3867574505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3867574505
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.173017827
Short name T761
Test name
Test status
Simulation time 84593851 ps
CPU time 6.68 seconds
Started Aug 01 05:37:01 PM PDT 24
Finished Aug 01 05:37:08 PM PDT 24
Peak memory 204552 kb
Host smart-7f6111b1-3032-43b7-affd-3d899717a2e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=173017827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.173017827
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.3746477791
Short name T784
Test name
Test status
Simulation time 68567854687 ps
CPU time 155.9 seconds
Started Aug 01 05:37:02 PM PDT 24
Finished Aug 01 05:39:38 PM PDT 24
Peak memory 205096 kb
Host smart-851ce16d-4051-4cb3-a840-979d55c478a9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746477791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3746477791
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.1691021627
Short name T461
Test name
Test status
Simulation time 2530813217 ps
CPU time 22.97 seconds
Started Aug 01 05:36:57 PM PDT 24
Finished Aug 01 05:37:21 PM PDT 24
Peak memory 203580 kb
Host smart-4576b2e3-e055-4826-9ba4-73c1542043b8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1691021627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1691021627
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.4250018861
Short name T335
Test name
Test status
Simulation time 83494693 ps
CPU time 6.13 seconds
Started Aug 01 05:37:01 PM PDT 24
Finished Aug 01 05:37:08 PM PDT 24
Peak memory 204600 kb
Host smart-34df00e0-d67d-4773-abc9-3b66b7a60c91
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250018861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.4250018861
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.2139141708
Short name T130
Test name
Test status
Simulation time 2322872732 ps
CPU time 26.83 seconds
Started Aug 01 05:37:02 PM PDT 24
Finished Aug 01 05:37:29 PM PDT 24
Peak memory 204204 kb
Host smart-5c489a2d-7f73-4d7d-b5a2-52fce948f5fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2139141708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2139141708
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke.1668747667
Short name T179
Test name
Test status
Simulation time 137007697 ps
CPU time 3.28 seconds
Started Aug 01 05:37:00 PM PDT 24
Finished Aug 01 05:37:03 PM PDT 24
Peak memory 203496 kb
Host smart-1c7a7a76-4b17-41ee-b4e4-9b3b5159dc2f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1668747667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1668747667
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3794872055
Short name T406
Test name
Test status
Simulation time 10631217087 ps
CPU time 33.62 seconds
Started Aug 01 05:36:56 PM PDT 24
Finished Aug 01 05:37:30 PM PDT 24
Peak memory 203540 kb
Host smart-8353c80b-9b3d-431c-b642-cbbf1585d898
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794872055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3794872055
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.936779939
Short name T282
Test name
Test status
Simulation time 3144006668 ps
CPU time 20.76 seconds
Started Aug 01 05:37:00 PM PDT 24
Finished Aug 01 05:37:21 PM PDT 24
Peak memory 203572 kb
Host smart-8f51be97-febd-40e6-8ac9-2cb156e7e5d6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=936779939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.936779939
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.3487780718
Short name T892
Test name
Test status
Simulation time 50008650 ps
CPU time 2.36 seconds
Started Aug 01 05:36:59 PM PDT 24
Finished Aug 01 05:37:02 PM PDT 24
Peak memory 203484 kb
Host smart-ee7b6b83-130b-40a7-8dad-51a80a510f69
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487780718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.3487780718
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.2673533284
Short name T347
Test name
Test status
Simulation time 1481658910 ps
CPU time 104.99 seconds
Started Aug 01 05:37:01 PM PDT 24
Finished Aug 01 05:38:46 PM PDT 24
Peak memory 208368 kb
Host smart-f741a365-fec3-48f0-926d-9184ea5b4e70
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2673533284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2673533284
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.2115520545
Short name T597
Test name
Test status
Simulation time 748376617 ps
CPU time 72.42 seconds
Started Aug 01 05:36:58 PM PDT 24
Finished Aug 01 05:38:11 PM PDT 24
Peak memory 208428 kb
Host smart-a60256ac-10b7-4cd6-b586-cf9e63232a1d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2115520545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2115520545
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.3260101572
Short name T38
Test name
Test status
Simulation time 7351316598 ps
CPU time 305.46 seconds
Started Aug 01 05:37:01 PM PDT 24
Finished Aug 01 05:42:07 PM PDT 24
Peak memory 221188 kb
Host smart-39fc8420-fe5c-4425-bbc0-7788b925e872
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3260101572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran
d_reset.3260101572
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.525501263
Short name T548
Test name
Test status
Simulation time 2056382976 ps
CPU time 152.7 seconds
Started Aug 01 05:37:02 PM PDT 24
Finished Aug 01 05:39:35 PM PDT 24
Peak memory 210728 kb
Host smart-7fd2b184-1d8a-4d51-850f-5d9aa703e739
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=525501263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_res
et_error.525501263
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.1959587509
Short name T759
Test name
Test status
Simulation time 304787065 ps
CPU time 8.63 seconds
Started Aug 01 05:36:59 PM PDT 24
Finished Aug 01 05:37:08 PM PDT 24
Peak memory 211660 kb
Host smart-fe28f4cf-337f-4f3f-8952-5460e4ed03d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1959587509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1959587509
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.2722917384
Short name T302
Test name
Test status
Simulation time 781445129 ps
CPU time 23.54 seconds
Started Aug 01 05:36:56 PM PDT 24
Finished Aug 01 05:37:20 PM PDT 24
Peak memory 211660 kb
Host smart-4ddf465b-edbf-4f9d-92a9-bc850e5f5e00
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2722917384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2722917384
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1370641124
Short name T566
Test name
Test status
Simulation time 186258218058 ps
CPU time 419.46 seconds
Started Aug 01 05:37:01 PM PDT 24
Finished Aug 01 05:44:00 PM PDT 24
Peak memory 211552 kb
Host smart-3096aed9-6a37-4352-b39b-5b13857c2574
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1370641124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl
ow_rsp.1370641124
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.1471945321
Short name T683
Test name
Test status
Simulation time 1403700259 ps
CPU time 21.92 seconds
Started Aug 01 05:37:13 PM PDT 24
Finished Aug 01 05:37:35 PM PDT 24
Peak memory 203476 kb
Host smart-e455d6f7-ef2c-4b8e-84b1-563a59e2b9f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1471945321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.1471945321
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.2735448786
Short name T319
Test name
Test status
Simulation time 244169787 ps
CPU time 11.08 seconds
Started Aug 01 05:37:07 PM PDT 24
Finished Aug 01 05:37:18 PM PDT 24
Peak memory 203352 kb
Host smart-beb382bc-d1e6-48df-ab3c-08b0cf07a874
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2735448786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2735448786
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.2386994767
Short name T381
Test name
Test status
Simulation time 1091218162 ps
CPU time 37.05 seconds
Started Aug 01 05:37:06 PM PDT 24
Finished Aug 01 05:37:43 PM PDT 24
Peak memory 211644 kb
Host smart-e000c488-d0a6-4bd5-b5f2-572aad62f37c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2386994767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2386994767
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.493879849
Short name T57
Test name
Test status
Simulation time 41170548754 ps
CPU time 196.67 seconds
Started Aug 01 05:37:01 PM PDT 24
Finished Aug 01 05:40:18 PM PDT 24
Peak memory 211728 kb
Host smart-acb9a083-9aee-4da9-a9fe-b19fda0ca182
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=493879849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.493879849
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.2487797122
Short name T574
Test name
Test status
Simulation time 156361506 ps
CPU time 8.18 seconds
Started Aug 01 05:37:00 PM PDT 24
Finished Aug 01 05:37:08 PM PDT 24
Peak memory 211436 kb
Host smart-15edb52a-daaa-4020-94e2-4b8fef36ae21
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487797122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.2487797122
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.2301295383
Short name T456
Test name
Test status
Simulation time 1548151438 ps
CPU time 34.78 seconds
Started Aug 01 05:37:00 PM PDT 24
Finished Aug 01 05:37:34 PM PDT 24
Peak memory 203464 kb
Host smart-f5354a73-ccb8-40e6-ad64-897366557c9a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2301295383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2301295383
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.3134395093
Short name T871
Test name
Test status
Simulation time 30848166 ps
CPU time 2.06 seconds
Started Aug 01 05:37:04 PM PDT 24
Finished Aug 01 05:37:06 PM PDT 24
Peak memory 203472 kb
Host smart-757e2062-79b6-4bbe-8aac-995cf6c303d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3134395093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3134395093
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3175673450
Short name T269
Test name
Test status
Simulation time 5913714698 ps
CPU time 30.55 seconds
Started Aug 01 05:36:50 PM PDT 24
Finished Aug 01 05:37:21 PM PDT 24
Peak memory 203552 kb
Host smart-1f92a9a0-ee0b-46a9-b50b-8744eb4eccb7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175673450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3175673450
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.3061660758
Short name T831
Test name
Test status
Simulation time 4102688726 ps
CPU time 33.48 seconds
Started Aug 01 05:37:04 PM PDT 24
Finished Aug 01 05:37:37 PM PDT 24
Peak memory 203548 kb
Host smart-2f5fd9eb-b080-4952-8efe-948e118cf971
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3061660758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3061660758
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.1914870659
Short name T805
Test name
Test status
Simulation time 30606503 ps
CPU time 2.65 seconds
Started Aug 01 05:37:01 PM PDT 24
Finished Aug 01 05:37:03 PM PDT 24
Peak memory 203376 kb
Host smart-17e3e536-9997-47b1-b80b-d3214f734eb2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914870659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1914870659
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.133427111
Short name T415
Test name
Test status
Simulation time 651901342 ps
CPU time 53.59 seconds
Started Aug 01 05:37:16 PM PDT 24
Finished Aug 01 05:38:10 PM PDT 24
Peak memory 206048 kb
Host smart-8fc8de26-a78b-435f-ac13-bd36572da5cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=133427111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.133427111
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.983436717
Short name T336
Test name
Test status
Simulation time 10310645302 ps
CPU time 141.71 seconds
Started Aug 01 05:37:07 PM PDT 24
Finished Aug 01 05:39:29 PM PDT 24
Peak memory 206592 kb
Host smart-14b696d7-517d-4328-9630-7d2148629f51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=983436717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.983436717
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.4157279627
Short name T738
Test name
Test status
Simulation time 391601145 ps
CPU time 151.37 seconds
Started Aug 01 05:37:08 PM PDT 24
Finished Aug 01 05:39:39 PM PDT 24
Peak memory 208440 kb
Host smart-65ae8a6d-63ad-44a0-9472-e9dde57086e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4157279627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran
d_reset.4157279627
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.1983958190
Short name T858
Test name
Test status
Simulation time 534742562 ps
CPU time 183.19 seconds
Started Aug 01 05:37:12 PM PDT 24
Finished Aug 01 05:40:16 PM PDT 24
Peak memory 211656 kb
Host smart-3e2e7c72-5fcd-42c0-882d-103cb418a847
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1983958190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re
set_error.1983958190
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.177114364
Short name T703
Test name
Test status
Simulation time 393693167 ps
CPU time 16.24 seconds
Started Aug 01 05:37:13 PM PDT 24
Finished Aug 01 05:37:30 PM PDT 24
Peak memory 211668 kb
Host smart-0c40ea70-ee22-40a5-ac94-920729d48f16
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=177114364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.177114364
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2269736579
Short name T418
Test name
Test status
Simulation time 3352872764 ps
CPU time 27.72 seconds
Started Aug 01 05:37:10 PM PDT 24
Finished Aug 01 05:37:38 PM PDT 24
Peak memory 210988 kb
Host smart-23698a36-ae96-4250-ad08-50ee944ff0bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2269736579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2269736579
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.15792846
Short name T462
Test name
Test status
Simulation time 207534480694 ps
CPU time 461.26 seconds
Started Aug 01 05:37:10 PM PDT 24
Finished Aug 01 05:44:51 PM PDT 24
Peak memory 211004 kb
Host smart-b66e5cc1-59cd-4360-b483-bc4392ffc268
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=15792846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow
_rsp.15792846
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.3073915031
Short name T628
Test name
Test status
Simulation time 157010109 ps
CPU time 18 seconds
Started Aug 01 05:37:23 PM PDT 24
Finished Aug 01 05:37:41 PM PDT 24
Peak memory 203812 kb
Host smart-457e4fb4-380a-47d4-9fe1-1d9e97a3183f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3073915031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.3073915031
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_random.359832834
Short name T536
Test name
Test status
Simulation time 256236692 ps
CPU time 20.43 seconds
Started Aug 01 05:37:09 PM PDT 24
Finished Aug 01 05:37:29 PM PDT 24
Peak memory 203464 kb
Host smart-ea5007e6-5079-4dcd-9d32-29f23b7fab12
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=359832834 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.359832834
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.1673515709
Short name T769
Test name
Test status
Simulation time 6512131394 ps
CPU time 40.63 seconds
Started Aug 01 05:37:06 PM PDT 24
Finished Aug 01 05:37:46 PM PDT 24
Peak memory 211648 kb
Host smart-94f6aba0-968c-4021-801d-e8586ef25274
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1673515709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1673515709
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.429675328
Short name T822
Test name
Test status
Simulation time 151270752456 ps
CPU time 272.12 seconds
Started Aug 01 05:37:16 PM PDT 24
Finished Aug 01 05:41:49 PM PDT 24
Peak memory 205272 kb
Host smart-5d3ee470-7cfe-4881-a4cf-a400baea6fbd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=429675328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.429675328
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.108893973
Short name T832
Test name
Test status
Simulation time 26115928678 ps
CPU time 212.89 seconds
Started Aug 01 05:37:07 PM PDT 24
Finished Aug 01 05:40:40 PM PDT 24
Peak memory 204980 kb
Host smart-f1a205cd-2a7f-4413-9791-97cec0a112aa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=108893973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.108893973
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.1401263895
Short name T799
Test name
Test status
Simulation time 117756194 ps
CPU time 9.79 seconds
Started Aug 01 05:37:12 PM PDT 24
Finished Aug 01 05:37:22 PM PDT 24
Peak memory 211644 kb
Host smart-417ad89c-86bb-41fb-b221-d00171aa02df
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401263895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.1401263895
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.2048201171
Short name T606
Test name
Test status
Simulation time 2179018799 ps
CPU time 20.71 seconds
Started Aug 01 05:37:10 PM PDT 24
Finished Aug 01 05:37:30 PM PDT 24
Peak memory 210964 kb
Host smart-e3d5a7d0-7dfd-47fc-b0aa-e01cb1b86ce4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2048201171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2048201171
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.2699512805
Short name T60
Test name
Test status
Simulation time 332329380 ps
CPU time 3.56 seconds
Started Aug 01 05:37:13 PM PDT 24
Finished Aug 01 05:37:17 PM PDT 24
Peak memory 203488 kb
Host smart-c896bf4f-7953-437e-9407-68fae82b490d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2699512805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2699512805
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3865964553
Short name T685
Test name
Test status
Simulation time 42476854032 ps
CPU time 50.4 seconds
Started Aug 01 05:37:24 PM PDT 24
Finished Aug 01 05:38:15 PM PDT 24
Peak memory 203452 kb
Host smart-ce25e079-de7a-4e37-8026-d68d89051dbc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865964553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3865964553
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.4200244654
Short name T192
Test name
Test status
Simulation time 5064978696 ps
CPU time 35.63 seconds
Started Aug 01 05:37:14 PM PDT 24
Finished Aug 01 05:37:49 PM PDT 24
Peak memory 203544 kb
Host smart-9301efac-6d50-40c7-a9e2-91618eebfb9e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4200244654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.4200244654
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2775940235
Short name T437
Test name
Test status
Simulation time 90584589 ps
CPU time 2.43 seconds
Started Aug 01 05:37:07 PM PDT 24
Finished Aug 01 05:37:10 PM PDT 24
Peak memory 203448 kb
Host smart-669318e2-0a59-4238-9407-b73a25411592
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775940235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2775940235
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.3489140188
Short name T173
Test name
Test status
Simulation time 4366416440 ps
CPU time 145.61 seconds
Started Aug 01 05:37:09 PM PDT 24
Finished Aug 01 05:39:34 PM PDT 24
Peak memory 207440 kb
Host smart-32aaa734-a669-4ebc-86f9-55aa761dfed1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3489140188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3489140188
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.2206313197
Short name T782
Test name
Test status
Simulation time 538945206 ps
CPU time 62.49 seconds
Started Aug 01 05:37:13 PM PDT 24
Finished Aug 01 05:38:16 PM PDT 24
Peak memory 204704 kb
Host smart-a3472e0e-87f2-4d24-9c10-aca932a86464
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2206313197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2206313197
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.306729614
Short name T601
Test name
Test status
Simulation time 2095469613 ps
CPU time 113.88 seconds
Started Aug 01 05:37:13 PM PDT 24
Finished Aug 01 05:39:07 PM PDT 24
Peak memory 208340 kb
Host smart-3de5f3b1-9735-4efb-977e-21f48621a9be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=306729614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand
_reset.306729614
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.429487220
Short name T68
Test name
Test status
Simulation time 977765089 ps
CPU time 15.6 seconds
Started Aug 01 05:37:24 PM PDT 24
Finished Aug 01 05:37:40 PM PDT 24
Peak memory 204676 kb
Host smart-7b4d4fd9-89a2-4db6-91b7-281fe1a1352a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=429487220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.429487220
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.3182931301
Short name T890
Test name
Test status
Simulation time 217459004 ps
CPU time 29.68 seconds
Started Aug 01 05:37:07 PM PDT 24
Finished Aug 01 05:37:37 PM PDT 24
Peak memory 205892 kb
Host smart-0682cf5c-bf2d-4335-819c-13c2b87ce6a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3182931301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.3182931301
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.4293959487
Short name T309
Test name
Test status
Simulation time 117573859714 ps
CPU time 446.69 seconds
Started Aug 01 05:37:23 PM PDT 24
Finished Aug 01 05:44:50 PM PDT 24
Peak memory 211652 kb
Host smart-fc42c65b-10c2-4bbe-bb90-67c484d9bdc5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4293959487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl
ow_rsp.4293959487
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.534727015
Short name T405
Test name
Test status
Simulation time 22239252 ps
CPU time 2.66 seconds
Started Aug 01 05:37:06 PM PDT 24
Finished Aug 01 05:37:09 PM PDT 24
Peak memory 203496 kb
Host smart-eff52a59-0e1c-4ef1-ac46-38e5d271f63e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=534727015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.534727015
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.3324963806
Short name T736
Test name
Test status
Simulation time 773637374 ps
CPU time 20.98 seconds
Started Aug 01 05:37:09 PM PDT 24
Finished Aug 01 05:37:30 PM PDT 24
Peak memory 203468 kb
Host smart-88a1e4a1-4821-4b9f-93ce-e19436ad0ce9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3324963806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3324963806
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.2836183494
Short name T11
Test name
Test status
Simulation time 128745370 ps
CPU time 4.65 seconds
Started Aug 01 05:37:09 PM PDT 24
Finished Aug 01 05:37:14 PM PDT 24
Peak memory 203408 kb
Host smart-8824ebaf-6a92-4607-9f3e-94df1cdc0a8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2836183494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.2836183494
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.1265774153
Short name T59
Test name
Test status
Simulation time 80516707578 ps
CPU time 127.47 seconds
Started Aug 01 05:37:10 PM PDT 24
Finished Aug 01 05:39:17 PM PDT 24
Peak memory 210980 kb
Host smart-6e57db79-5b78-47c0-a7e1-fbe2ae0b3635
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265774153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.1265774153
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2086094940
Short name T340
Test name
Test status
Simulation time 31690146459 ps
CPU time 94.74 seconds
Started Aug 01 05:37:10 PM PDT 24
Finished Aug 01 05:38:45 PM PDT 24
Peak memory 204916 kb
Host smart-bf2fa4eb-cdea-49ec-85ad-1985f381e79e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2086094940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2086094940
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.2517598138
Short name T398
Test name
Test status
Simulation time 218555471 ps
CPU time 30.59 seconds
Started Aug 01 05:37:13 PM PDT 24
Finished Aug 01 05:37:43 PM PDT 24
Peak memory 211580 kb
Host smart-4f5386af-cf56-4436-9a96-8ca022b9e575
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517598138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.2517598138
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.3544390570
Short name T800
Test name
Test status
Simulation time 713465893 ps
CPU time 14.07 seconds
Started Aug 01 05:37:14 PM PDT 24
Finished Aug 01 05:37:29 PM PDT 24
Peak memory 204072 kb
Host smart-5e6d365f-2084-4bed-968e-7d258bdd2967
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3544390570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3544390570
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.1705433131
Short name T427
Test name
Test status
Simulation time 191357222 ps
CPU time 3.13 seconds
Started Aug 01 05:37:05 PM PDT 24
Finished Aug 01 05:37:08 PM PDT 24
Peak memory 203468 kb
Host smart-940f907e-a743-479e-bf1d-178d1212901a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1705433131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1705433131
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1150240561
Short name T412
Test name
Test status
Simulation time 6289146044 ps
CPU time 25.17 seconds
Started Aug 01 05:37:23 PM PDT 24
Finished Aug 01 05:37:48 PM PDT 24
Peak memory 203452 kb
Host smart-87a8ea37-019d-4744-8914-ac43d3d0a87b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150240561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1150240561
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.1223902857
Short name T404
Test name
Test status
Simulation time 3178933221 ps
CPU time 27.93 seconds
Started Aug 01 05:37:13 PM PDT 24
Finished Aug 01 05:37:41 PM PDT 24
Peak memory 203564 kb
Host smart-31fcccc2-f708-4211-bde6-0ed87e388165
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1223902857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1223902857
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.1487153662
Short name T629
Test name
Test status
Simulation time 45074800 ps
CPU time 1.86 seconds
Started Aug 01 05:37:23 PM PDT 24
Finished Aug 01 05:37:25 PM PDT 24
Peak memory 203372 kb
Host smart-8bd9f286-1ebb-4b4b-a1c4-7b7763501bd9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487153662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.1487153662
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.1911320729
Short name T558
Test name
Test status
Simulation time 9259930801 ps
CPU time 175.55 seconds
Started Aug 01 05:37:22 PM PDT 24
Finished Aug 01 05:40:18 PM PDT 24
Peak memory 209844 kb
Host smart-e89c232e-f0e6-4bb8-aa37-a689e4f956b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1911320729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1911320729
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.1872452316
Short name T39
Test name
Test status
Simulation time 5039621930 ps
CPU time 157.35 seconds
Started Aug 01 05:37:15 PM PDT 24
Finished Aug 01 05:39:52 PM PDT 24
Peak memory 208776 kb
Host smart-aa582d81-40c8-486e-97e6-9ca0d772f733
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1872452316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1872452316
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.4045484521
Short name T393
Test name
Test status
Simulation time 2926354783 ps
CPU time 253.36 seconds
Started Aug 01 05:37:23 PM PDT 24
Finished Aug 01 05:41:37 PM PDT 24
Peak memory 223996 kb
Host smart-0e032604-45f8-4732-ae47-20ae19dc76f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4045484521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re
set_error.4045484521
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.1276486299
Short name T645
Test name
Test status
Simulation time 316867261 ps
CPU time 12.41 seconds
Started Aug 01 05:37:26 PM PDT 24
Finished Aug 01 05:37:39 PM PDT 24
Peak memory 204992 kb
Host smart-de10c4d8-b4c9-4eaa-bcdf-4fb9e8368154
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1276486299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1276486299
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.2656848661
Short name T787
Test name
Test status
Simulation time 287008635 ps
CPU time 12.66 seconds
Started Aug 01 05:37:12 PM PDT 24
Finished Aug 01 05:37:24 PM PDT 24
Peak memory 211644 kb
Host smart-68b43e8a-4d81-492f-8e1a-c9d4510bc0f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2656848661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.2656848661
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.2542669821
Short name T706
Test name
Test status
Simulation time 9249680036 ps
CPU time 78.27 seconds
Started Aug 01 05:37:14 PM PDT 24
Finished Aug 01 05:38:33 PM PDT 24
Peak memory 211788 kb
Host smart-d076adaf-09ff-4bcb-9d07-5fa58e9768ba
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2542669821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl
ow_rsp.2542669821
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.4167885690
Short name T295
Test name
Test status
Simulation time 65893213 ps
CPU time 10.44 seconds
Started Aug 01 05:37:14 PM PDT 24
Finished Aug 01 05:37:25 PM PDT 24
Peak memory 203800 kb
Host smart-25f2c967-62a8-4836-8c0d-5350cc8d0609
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4167885690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.4167885690
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.1883549818
Short name T720
Test name
Test status
Simulation time 55474972 ps
CPU time 4.66 seconds
Started Aug 01 05:37:10 PM PDT 24
Finished Aug 01 05:37:15 PM PDT 24
Peak memory 203472 kb
Host smart-7bb6f4e8-b964-4aef-80fc-fa2a13aac7a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1883549818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1883549818
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.1151775300
Short name T85
Test name
Test status
Simulation time 785376237 ps
CPU time 14.97 seconds
Started Aug 01 05:37:15 PM PDT 24
Finished Aug 01 05:37:31 PM PDT 24
Peak memory 204568 kb
Host smart-2c7e719f-730c-4106-83fa-6fae86f294b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1151775300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.1151775300
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.2905240303
Short name T232
Test name
Test status
Simulation time 162725415024 ps
CPU time 308.52 seconds
Started Aug 01 05:37:08 PM PDT 24
Finished Aug 01 05:42:17 PM PDT 24
Peak memory 205120 kb
Host smart-a565de13-1806-4ff0-82ca-e5072edf1b11
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905240303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2905240303
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.577502433
Short name T331
Test name
Test status
Simulation time 125456161507 ps
CPU time 297.18 seconds
Started Aug 01 05:37:15 PM PDT 24
Finished Aug 01 05:42:13 PM PDT 24
Peak memory 211620 kb
Host smart-534ad7fa-11cc-47e9-a602-8220aa3c7e84
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=577502433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.577502433
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.3790038422
Short name T479
Test name
Test status
Simulation time 134732174 ps
CPU time 9.67 seconds
Started Aug 01 05:37:11 PM PDT 24
Finished Aug 01 05:37:21 PM PDT 24
Peak memory 204596 kb
Host smart-f77d5b82-01c9-4237-b668-d4775afc1644
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790038422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3790038422
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.3818933100
Short name T176
Test name
Test status
Simulation time 355384627 ps
CPU time 13.55 seconds
Started Aug 01 05:37:15 PM PDT 24
Finished Aug 01 05:37:29 PM PDT 24
Peak memory 203440 kb
Host smart-6ff5f2e4-8f50-4e1f-95b3-7e48aa5a1153
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3818933100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3818933100
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.597386239
Short name T630
Test name
Test status
Simulation time 304952861 ps
CPU time 3.06 seconds
Started Aug 01 05:37:08 PM PDT 24
Finished Aug 01 05:37:11 PM PDT 24
Peak memory 203020 kb
Host smart-734280b5-d25a-4500-ac55-c389cf4bab84
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=597386239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.597386239
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1883484156
Short name T136
Test name
Test status
Simulation time 12152556347 ps
CPU time 35.1 seconds
Started Aug 01 05:37:06 PM PDT 24
Finished Aug 01 05:37:41 PM PDT 24
Peak memory 203460 kb
Host smart-c9a30287-48f0-4143-9391-0e69960b656c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883484156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1883484156
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.879638877
Short name T632
Test name
Test status
Simulation time 2960662475 ps
CPU time 25.92 seconds
Started Aug 01 05:37:14 PM PDT 24
Finished Aug 01 05:37:41 PM PDT 24
Peak memory 203564 kb
Host smart-e893897c-d886-4abd-bc9b-ddbd734dfb43
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=879638877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.879638877
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.754544350
Short name T322
Test name
Test status
Simulation time 49731692 ps
CPU time 1.78 seconds
Started Aug 01 05:37:22 PM PDT 24
Finished Aug 01 05:37:24 PM PDT 24
Peak memory 203368 kb
Host smart-0aeb3d4a-58b7-4b02-86e4-fe0f18f3cd6e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754544350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.754544350
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.2309259752
Short name T357
Test name
Test status
Simulation time 2373686367 ps
CPU time 121.08 seconds
Started Aug 01 05:37:15 PM PDT 24
Finished Aug 01 05:39:16 PM PDT 24
Peak memory 209184 kb
Host smart-345d5b96-3e56-4a8c-8f7e-c05bcfabc6ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2309259752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2309259752
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.3589892353
Short name T679
Test name
Test status
Simulation time 1310700165 ps
CPU time 168.72 seconds
Started Aug 01 05:37:10 PM PDT 24
Finished Aug 01 05:39:59 PM PDT 24
Peak memory 208416 kb
Host smart-e9d3157d-cf85-4975-b2ce-c4a87905b466
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3589892353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran
d_reset.3589892353
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.3665855546
Short name T221
Test name
Test status
Simulation time 7405363 ps
CPU time 5.87 seconds
Started Aug 01 05:37:14 PM PDT 24
Finished Aug 01 05:37:21 PM PDT 24
Peak memory 203516 kb
Host smart-10562b77-2f70-4bd3-868d-a7b7cd943856
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3665855546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re
set_error.3665855546
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.1038235202
Short name T801
Test name
Test status
Simulation time 5652180435 ps
CPU time 31.5 seconds
Started Aug 01 05:37:07 PM PDT 24
Finished Aug 01 05:37:39 PM PDT 24
Peak memory 205700 kb
Host smart-3b0c95ad-2b05-40d5-8cc0-7b03b8d0fb07
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1038235202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1038235202
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.1447884476
Short name T334
Test name
Test status
Simulation time 616771870 ps
CPU time 33.18 seconds
Started Aug 01 05:37:18 PM PDT 24
Finished Aug 01 05:37:52 PM PDT 24
Peak memory 204588 kb
Host smart-80eec56d-0a5d-45a7-8ab7-5cc35772151b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1447884476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1447884476
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2471422264
Short name T61
Test name
Test status
Simulation time 147980954501 ps
CPU time 640.97 seconds
Started Aug 01 05:37:28 PM PDT 24
Finished Aug 01 05:48:09 PM PDT 24
Peak memory 206048 kb
Host smart-21c731cc-2c92-4864-8bf1-083b298a1883
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2471422264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl
ow_rsp.2471422264
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.1882276200
Short name T746
Test name
Test status
Simulation time 213636371 ps
CPU time 8.37 seconds
Started Aug 01 05:37:20 PM PDT 24
Finished Aug 01 05:37:29 PM PDT 24
Peak memory 203588 kb
Host smart-6897a4c8-757a-4031-a037-e49574107c03
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1882276200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.1882276200
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.681376404
Short name T365
Test name
Test status
Simulation time 63673558 ps
CPU time 9.18 seconds
Started Aug 01 05:37:17 PM PDT 24
Finished Aug 01 05:37:26 PM PDT 24
Peak memory 203380 kb
Host smart-b1e13e61-4047-4899-b927-6f639b970f6b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=681376404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.681376404
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.3381702930
Short name T573
Test name
Test status
Simulation time 246881114 ps
CPU time 6.91 seconds
Started Aug 01 05:37:17 PM PDT 24
Finished Aug 01 05:37:24 PM PDT 24
Peak memory 211664 kb
Host smart-861af436-e5e3-46fb-9c1d-0515fd9c50ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3381702930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.3381702930
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.2387333680
Short name T92
Test name
Test status
Simulation time 70821971004 ps
CPU time 137.33 seconds
Started Aug 01 05:37:22 PM PDT 24
Finished Aug 01 05:39:40 PM PDT 24
Peak memory 210992 kb
Host smart-39a0e883-d4b3-4482-a3bd-4a223557bb7e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387333680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2387333680
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.857874741
Short name T659
Test name
Test status
Simulation time 10935899900 ps
CPU time 77.28 seconds
Started Aug 01 05:37:16 PM PDT 24
Finished Aug 01 05:38:34 PM PDT 24
Peak memory 211696 kb
Host smart-2be52b1a-acd2-4f38-bad3-d11c1700356d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=857874741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.857874741
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.798202240
Short name T315
Test name
Test status
Simulation time 37029764 ps
CPU time 3.72 seconds
Started Aug 01 05:37:28 PM PDT 24
Finished Aug 01 05:37:32 PM PDT 24
Peak memory 204156 kb
Host smart-6aec3aa8-6d53-486b-8d74-8b81e7f1c7d1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798202240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.798202240
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.3598840981
Short name T814
Test name
Test status
Simulation time 320682841 ps
CPU time 11.56 seconds
Started Aug 01 05:37:18 PM PDT 24
Finished Aug 01 05:37:30 PM PDT 24
Peak memory 203508 kb
Host smart-14820c3b-3d1e-43ee-be2f-9e0fcc9f55a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3598840981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3598840981
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.2079963319
Short name T713
Test name
Test status
Simulation time 48130856 ps
CPU time 2.27 seconds
Started Aug 01 05:37:28 PM PDT 24
Finished Aug 01 05:37:31 PM PDT 24
Peak memory 203464 kb
Host smart-a42628cd-917a-4c17-b7a1-3099f13046bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2079963319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2079963319
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.629089479
Short name T843
Test name
Test status
Simulation time 11766579364 ps
CPU time 30.13 seconds
Started Aug 01 05:37:18 PM PDT 24
Finished Aug 01 05:37:49 PM PDT 24
Peak memory 203456 kb
Host smart-59fbef14-1c3c-4331-a75c-707ec1a6af84
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=629089479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.629089479
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1398557445
Short name T171
Test name
Test status
Simulation time 7259450746 ps
CPU time 22.33 seconds
Started Aug 01 05:37:18 PM PDT 24
Finished Aug 01 05:37:40 PM PDT 24
Peak memory 203500 kb
Host smart-29b5efcb-6a21-4e63-a932-febe32def8a2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1398557445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1398557445
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.573264007
Short name T247
Test name
Test status
Simulation time 29637105 ps
CPU time 2.19 seconds
Started Aug 01 05:37:17 PM PDT 24
Finished Aug 01 05:37:19 PM PDT 24
Peak memory 203472 kb
Host smart-5acc02d8-1d45-4a8e-8354-760c64f3fb66
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573264007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.573264007
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.1752871293
Short name T841
Test name
Test status
Simulation time 7098329055 ps
CPU time 179.71 seconds
Started Aug 01 05:37:15 PM PDT 24
Finished Aug 01 05:40:15 PM PDT 24
Peak memory 209748 kb
Host smart-1980f222-0658-40a1-9b18-81d2ff550787
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1752871293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1752871293
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1382286793
Short name T733
Test name
Test status
Simulation time 478787721 ps
CPU time 54.71 seconds
Started Aug 01 05:37:19 PM PDT 24
Finished Aug 01 05:38:14 PM PDT 24
Peak memory 206104 kb
Host smart-092f44b0-1373-44cf-a706-5c0e1beb1be0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1382286793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1382286793
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.1448186590
Short name T304
Test name
Test status
Simulation time 4129075677 ps
CPU time 176.12 seconds
Started Aug 01 05:37:18 PM PDT 24
Finished Aug 01 05:40:15 PM PDT 24
Peak memory 208892 kb
Host smart-241562d0-46a8-4e10-80fe-28f54ed9e335
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1448186590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran
d_reset.1448186590
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3511758666
Short name T37
Test name
Test status
Simulation time 1787548914 ps
CPU time 306.65 seconds
Started Aug 01 05:37:19 PM PDT 24
Finished Aug 01 05:42:26 PM PDT 24
Peak memory 219884 kb
Host smart-dab483db-aa8a-406e-8985-d2423566d274
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3511758666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re
set_error.3511758666
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.3490027728
Short name T292
Test name
Test status
Simulation time 247146501 ps
CPU time 5.85 seconds
Started Aug 01 05:37:16 PM PDT 24
Finished Aug 01 05:37:22 PM PDT 24
Peak memory 211692 kb
Host smart-2d1b063f-922c-476f-8480-e37f706d4646
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3490027728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3490027728
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.309142798
Short name T781
Test name
Test status
Simulation time 33893098 ps
CPU time 6.35 seconds
Started Aug 01 05:36:21 PM PDT 24
Finished Aug 01 05:36:28 PM PDT 24
Peak memory 203516 kb
Host smart-85efc0df-1c52-4e66-af73-d50dbd1bd032
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=309142798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.309142798
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.661471792
Short name T802
Test name
Test status
Simulation time 46414023049 ps
CPU time 274.5 seconds
Started Aug 01 05:36:25 PM PDT 24
Finished Aug 01 05:40:59 PM PDT 24
Peak memory 206764 kb
Host smart-b3cb59f7-4a7f-4a67-adbe-bf5d349037be
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=661471792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow
_rsp.661471792
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3510080570
Short name T576
Test name
Test status
Simulation time 163648882 ps
CPU time 9.51 seconds
Started Aug 01 05:36:19 PM PDT 24
Finished Aug 01 05:36:28 PM PDT 24
Peak memory 203512 kb
Host smart-f5f1fa2b-1746-4cd2-922f-09e746d9b85a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3510080570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3510080570
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.2699581496
Short name T400
Test name
Test status
Simulation time 181662925 ps
CPU time 7.57 seconds
Started Aug 01 05:36:22 PM PDT 24
Finished Aug 01 05:36:30 PM PDT 24
Peak memory 203508 kb
Host smart-6ed426dc-6449-4934-9048-fa9c366f4f93
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2699581496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2699581496
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.1959732520
Short name T429
Test name
Test status
Simulation time 1006375566 ps
CPU time 30.68 seconds
Started Aug 01 05:36:22 PM PDT 24
Finished Aug 01 05:36:52 PM PDT 24
Peak memory 204908 kb
Host smart-5b94bf6a-4205-491f-8fdc-0f9c83bd4719
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1959732520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.1959732520
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.2423085568
Short name T757
Test name
Test status
Simulation time 48641909506 ps
CPU time 192.71 seconds
Started Aug 01 05:36:22 PM PDT 24
Finished Aug 01 05:39:35 PM PDT 24
Peak memory 211748 kb
Host smart-54ae48ff-9c62-4811-b942-2bdb72665b8c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423085568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2423085568
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.2339680422
Short name T849
Test name
Test status
Simulation time 5520931317 ps
CPU time 44.45 seconds
Started Aug 01 05:36:18 PM PDT 24
Finished Aug 01 05:37:03 PM PDT 24
Peak memory 211912 kb
Host smart-f1bb98a6-3bf5-48e0-9d28-89bb17ca40f2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2339680422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2339680422
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.2862359858
Short name T756
Test name
Test status
Simulation time 95103188 ps
CPU time 11.92 seconds
Started Aug 01 05:36:20 PM PDT 24
Finished Aug 01 05:36:32 PM PDT 24
Peak memory 204468 kb
Host smart-7bd36a1a-c4a2-4540-9168-906870b7eb32
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862359858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.2862359858
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.513601477
Short name T373
Test name
Test status
Simulation time 1239150678 ps
CPU time 10.01 seconds
Started Aug 01 05:36:23 PM PDT 24
Finished Aug 01 05:36:34 PM PDT 24
Peak memory 203460 kb
Host smart-8fcd1130-ec8d-4637-b23c-a74274e6f4ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=513601477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.513601477
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.860288615
Short name T813
Test name
Test status
Simulation time 128242907 ps
CPU time 1.9 seconds
Started Aug 01 05:36:19 PM PDT 24
Finished Aug 01 05:36:21 PM PDT 24
Peak memory 203460 kb
Host smart-b60c78d3-b4c4-4b55-b8ac-8aae449df01c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=860288615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.860288615
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.881385618
Short name T565
Test name
Test status
Simulation time 4272925270 ps
CPU time 23.94 seconds
Started Aug 01 05:36:29 PM PDT 24
Finished Aug 01 05:36:53 PM PDT 24
Peak memory 203520 kb
Host smart-1027100e-ff30-4151-af9e-60627b431be3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=881385618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.881385618
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.4066653640
Short name T812
Test name
Test status
Simulation time 14497282004 ps
CPU time 35.19 seconds
Started Aug 01 05:36:21 PM PDT 24
Finished Aug 01 05:36:56 PM PDT 24
Peak memory 203536 kb
Host smart-3b9361df-8420-4459-a646-1fd1ece5d0a8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4066653640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.4066653640
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.1796789187
Short name T482
Test name
Test status
Simulation time 32543603 ps
CPU time 2.3 seconds
Started Aug 01 05:36:24 PM PDT 24
Finished Aug 01 05:36:27 PM PDT 24
Peak memory 203344 kb
Host smart-4e7057c2-5a48-4ff9-8e44-3c7100ab5413
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796789187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.1796789187
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.1206019043
Short name T263
Test name
Test status
Simulation time 2324083237 ps
CPU time 139.76 seconds
Started Aug 01 05:36:22 PM PDT 24
Finished Aug 01 05:38:42 PM PDT 24
Peak memory 207244 kb
Host smart-c2bd3889-9cc7-437a-84cf-c96e2f83640e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1206019043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.1206019043
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.4183710757
Short name T845
Test name
Test status
Simulation time 997630161 ps
CPU time 127.72 seconds
Started Aug 01 05:36:26 PM PDT 24
Finished Aug 01 05:38:34 PM PDT 24
Peak memory 210140 kb
Host smart-f18f4bb9-fef3-405a-89a0-1bee8d87d546
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4183710757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.4183710757
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.2285660411
Short name T795
Test name
Test status
Simulation time 186765563 ps
CPU time 41.84 seconds
Started Aug 01 05:36:23 PM PDT 24
Finished Aug 01 05:37:05 PM PDT 24
Peak memory 207540 kb
Host smart-29390282-a9ba-4a3c-9be5-0de9153ccf85
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2285660411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res
et_error.2285660411
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.173516800
Short name T624
Test name
Test status
Simulation time 216331255 ps
CPU time 18.91 seconds
Started Aug 01 05:36:23 PM PDT 24
Finished Aug 01 05:36:42 PM PDT 24
Peak memory 211672 kb
Host smart-1b64a3d7-ecb2-4e69-b023-3ac29b710c45
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=173516800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.173516800
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.500612653
Short name T249
Test name
Test status
Simulation time 3486020150 ps
CPU time 61.18 seconds
Started Aug 01 05:37:16 PM PDT 24
Finished Aug 01 05:38:17 PM PDT 24
Peak memory 211680 kb
Host smart-f4efc41f-4745-4f25-bd8f-bca0ec89c9f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=500612653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.500612653
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.3434790665
Short name T515
Test name
Test status
Simulation time 45478088 ps
CPU time 7.06 seconds
Started Aug 01 05:37:19 PM PDT 24
Finished Aug 01 05:37:26 PM PDT 24
Peak memory 203432 kb
Host smart-f78eea7e-7841-49da-92a1-6bcf542447cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3434790665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.3434790665
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.1126339472
Short name T588
Test name
Test status
Simulation time 145807243 ps
CPU time 19.26 seconds
Started Aug 01 05:37:22 PM PDT 24
Finished Aug 01 05:37:42 PM PDT 24
Peak memory 202688 kb
Host smart-18ded3a3-b535-4ff0-a105-be312fef0acd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1126339472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.1126339472
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.1391772558
Short name T794
Test name
Test status
Simulation time 3304494183 ps
CPU time 36.87 seconds
Started Aug 01 05:37:17 PM PDT 24
Finished Aug 01 05:37:54 PM PDT 24
Peak memory 204832 kb
Host smart-d3133587-23a2-4916-a9fa-48e50d4fb86a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1391772558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.1391772558
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.267242131
Short name T142
Test name
Test status
Simulation time 19102665194 ps
CPU time 48.47 seconds
Started Aug 01 05:37:18 PM PDT 24
Finished Aug 01 05:38:06 PM PDT 24
Peak memory 211632 kb
Host smart-8924181a-cd7f-4312-8e63-659ab61d8250
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=267242131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.267242131
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1094120355
Short name T764
Test name
Test status
Simulation time 17234441936 ps
CPU time 77.27 seconds
Started Aug 01 05:37:27 PM PDT 24
Finished Aug 01 05:38:45 PM PDT 24
Peak memory 204796 kb
Host smart-048fd63e-8f6a-4069-b53a-7d30299ac9e1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1094120355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1094120355
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.3966885114
Short name T851
Test name
Test status
Simulation time 193018995 ps
CPU time 27.2 seconds
Started Aug 01 05:37:16 PM PDT 24
Finished Aug 01 05:37:43 PM PDT 24
Peak memory 204992 kb
Host smart-693bb5a1-d0db-4e86-a31e-3c35e35d1b90
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966885114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.3966885114
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.3033220937
Short name T394
Test name
Test status
Simulation time 778748129 ps
CPU time 9.82 seconds
Started Aug 01 05:37:15 PM PDT 24
Finished Aug 01 05:37:25 PM PDT 24
Peak memory 203800 kb
Host smart-c7da5135-f0c7-48aa-b0cc-643ca5f52330
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3033220937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3033220937
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.2850888739
Short name T297
Test name
Test status
Simulation time 129330195 ps
CPU time 3.17 seconds
Started Aug 01 05:37:17 PM PDT 24
Finished Aug 01 05:37:21 PM PDT 24
Peak memory 203448 kb
Host smart-a53e40e2-d89f-4bd1-b96a-0b91ccce6b4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2850888739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2850888739
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.1148861221
Short name T274
Test name
Test status
Simulation time 13347375612 ps
CPU time 30.23 seconds
Started Aug 01 05:37:27 PM PDT 24
Finished Aug 01 05:37:58 PM PDT 24
Peak memory 203528 kb
Host smart-7cf7ec0d-80ba-43f0-8003-40fca1ab1d0b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148861221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1148861221
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.2668752907
Short name T62
Test name
Test status
Simulation time 4364760094 ps
CPU time 34.77 seconds
Started Aug 01 05:37:19 PM PDT 24
Finished Aug 01 05:37:54 PM PDT 24
Peak memory 203544 kb
Host smart-47bff777-d3f1-452e-96ec-aa96871cebe4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2668752907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2668752907
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.3626293963
Short name T151
Test name
Test status
Simulation time 35477801 ps
CPU time 2.44 seconds
Started Aug 01 05:37:16 PM PDT 24
Finished Aug 01 05:37:19 PM PDT 24
Peak memory 203344 kb
Host smart-4aae72c9-39ee-405e-96fd-a584d0ceb339
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626293963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3626293963
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.3114650553
Short name T290
Test name
Test status
Simulation time 4004702721 ps
CPU time 61.7 seconds
Started Aug 01 05:37:18 PM PDT 24
Finished Aug 01 05:38:20 PM PDT 24
Peak memory 206024 kb
Host smart-763e3424-515a-4172-a912-16cac6385d34
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3114650553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3114650553
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.1092900339
Short name T238
Test name
Test status
Simulation time 1756974814 ps
CPU time 29.82 seconds
Started Aug 01 05:37:19 PM PDT 24
Finished Aug 01 05:37:49 PM PDT 24
Peak memory 204660 kb
Host smart-db637285-116c-4892-aa96-7267da9e36cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1092900339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1092900339
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.785214966
Short name T143
Test name
Test status
Simulation time 2112747626 ps
CPU time 191.96 seconds
Started Aug 01 05:37:17 PM PDT 24
Finished Aug 01 05:40:29 PM PDT 24
Peak memory 209344 kb
Host smart-9f7c1b48-05a6-4810-934d-7497e413128a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=785214966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand
_reset.785214966
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.2161749687
Short name T150
Test name
Test status
Simulation time 548878547 ps
CPU time 134.99 seconds
Started Aug 01 05:37:15 PM PDT 24
Finished Aug 01 05:39:30 PM PDT 24
Peak memory 211360 kb
Host smart-7a312857-49e3-43a3-a889-c8e5d8b2f7b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2161749687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re
set_error.2161749687
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.928234778
Short name T819
Test name
Test status
Simulation time 1683392033 ps
CPU time 25.21 seconds
Started Aug 01 05:37:18 PM PDT 24
Finished Aug 01 05:37:43 PM PDT 24
Peak memory 211528 kb
Host smart-5508edd8-4a3e-4e2b-852d-50ce12c752d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=928234778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.928234778
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.1921647745
Short name T172
Test name
Test status
Simulation time 544112001 ps
CPU time 9.94 seconds
Started Aug 01 05:37:17 PM PDT 24
Finished Aug 01 05:37:27 PM PDT 24
Peak memory 204536 kb
Host smart-5ad4702b-7a37-4907-bdf8-87ddaa979beb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1921647745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.1921647745
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.4148403867
Short name T284
Test name
Test status
Simulation time 2709402221 ps
CPU time 25.43 seconds
Started Aug 01 05:37:27 PM PDT 24
Finished Aug 01 05:37:52 PM PDT 24
Peak memory 203508 kb
Host smart-38d3867e-65f3-4232-b1f9-cabc27a076b9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4148403867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl
ow_rsp.4148403867
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.4067795778
Short name T497
Test name
Test status
Simulation time 350190211 ps
CPU time 15.9 seconds
Started Aug 01 05:37:28 PM PDT 24
Finished Aug 01 05:37:44 PM PDT 24
Peak memory 203476 kb
Host smart-2ef7f744-e577-48d3-914f-18ec6e348b5e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4067795778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.4067795778
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.3141571030
Short name T71
Test name
Test status
Simulation time 571423206 ps
CPU time 19.54 seconds
Started Aug 01 05:37:19 PM PDT 24
Finished Aug 01 05:37:39 PM PDT 24
Peak memory 203472 kb
Host smart-79e03adf-2b64-42b4-9e53-580e1386725b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3141571030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3141571030
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.1610281812
Short name T426
Test name
Test status
Simulation time 1251515897 ps
CPU time 33.26 seconds
Started Aug 01 05:37:16 PM PDT 24
Finished Aug 01 05:37:50 PM PDT 24
Peak memory 211652 kb
Host smart-b921ed10-dc2f-485d-8ffd-c91cd44866ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1610281812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.1610281812
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.2588178774
Short name T622
Test name
Test status
Simulation time 62990178996 ps
CPU time 186.2 seconds
Started Aug 01 05:37:18 PM PDT 24
Finished Aug 01 05:40:24 PM PDT 24
Peak memory 211724 kb
Host smart-34266756-4ee7-47b4-8c21-2b9f4ce1a440
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588178774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2588178774
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.421441044
Short name T639
Test name
Test status
Simulation time 60475591553 ps
CPU time 223.64 seconds
Started Aug 01 05:37:17 PM PDT 24
Finished Aug 01 05:41:01 PM PDT 24
Peak memory 204712 kb
Host smart-5b452c1c-2fcb-4a8e-816f-9e8bdb132913
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=421441044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.421441044
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.3840657608
Short name T535
Test name
Test status
Simulation time 87968612 ps
CPU time 7.09 seconds
Started Aug 01 05:37:18 PM PDT 24
Finished Aug 01 05:37:25 PM PDT 24
Peak memory 211672 kb
Host smart-559ccf77-9111-4a1d-8978-48c25615c8a0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840657608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.3840657608
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.2086797643
Short name T750
Test name
Test status
Simulation time 566806676 ps
CPU time 8.88 seconds
Started Aug 01 05:37:17 PM PDT 24
Finished Aug 01 05:37:26 PM PDT 24
Peak memory 204104 kb
Host smart-f8f6ef2c-a9b9-47c7-87a4-19d0dcf400d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2086797643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2086797643
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.687612297
Short name T259
Test name
Test status
Simulation time 33470483 ps
CPU time 2.33 seconds
Started Aug 01 05:37:17 PM PDT 24
Finished Aug 01 05:37:20 PM PDT 24
Peak memory 203484 kb
Host smart-9577577b-8fdd-419e-9543-c5fcd5b3d30e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=687612297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.687612297
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2811988594
Short name T250
Test name
Test status
Simulation time 8911839638 ps
CPU time 28.1 seconds
Started Aug 01 05:37:20 PM PDT 24
Finished Aug 01 05:37:48 PM PDT 24
Peak memory 203528 kb
Host smart-a72e3ad2-53a9-40b3-98c3-998b98894913
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811988594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2811988594
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.716724220
Short name T155
Test name
Test status
Simulation time 3772457797 ps
CPU time 30.64 seconds
Started Aug 01 05:37:18 PM PDT 24
Finished Aug 01 05:37:49 PM PDT 24
Peak memory 203444 kb
Host smart-9b2fb2c7-4d2b-4d6f-9e79-191f097d1181
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=716724220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.716724220
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2103537290
Short name T807
Test name
Test status
Simulation time 56372053 ps
CPU time 2.32 seconds
Started Aug 01 05:37:27 PM PDT 24
Finished Aug 01 05:37:29 PM PDT 24
Peak memory 203428 kb
Host smart-1c521d26-46db-4544-9874-48aa237b0492
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103537290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.2103537290
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.4095709428
Short name T6
Test name
Test status
Simulation time 1100426969 ps
CPU time 100.11 seconds
Started Aug 01 05:37:28 PM PDT 24
Finished Aug 01 05:39:09 PM PDT 24
Peak memory 205968 kb
Host smart-1d01dca1-0e37-4cc3-9e0b-d1f1e7c2ae5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4095709428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.4095709428
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3853570704
Short name T792
Test name
Test status
Simulation time 3200922350 ps
CPU time 93.39 seconds
Started Aug 01 05:37:28 PM PDT 24
Finished Aug 01 05:39:02 PM PDT 24
Peak memory 205148 kb
Host smart-a211319a-770d-46c3-8184-2b1c8c9068fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3853570704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3853570704
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.1499692197
Short name T67
Test name
Test status
Simulation time 8228128610 ps
CPU time 325.98 seconds
Started Aug 01 05:37:28 PM PDT 24
Finished Aug 01 05:42:54 PM PDT 24
Peak memory 219944 kb
Host smart-5920740f-274c-4aee-979a-39bfeb3f443d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1499692197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran
d_reset.1499692197
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.2108530126
Short name T827
Test name
Test status
Simulation time 2895907397 ps
CPU time 163.37 seconds
Started Aug 01 05:37:29 PM PDT 24
Finished Aug 01 05:40:13 PM PDT 24
Peak memory 207576 kb
Host smart-5f3addda-4b8b-442b-95d8-f4bf0e552fe4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2108530126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re
set_error.2108530126
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.1869684735
Short name T723
Test name
Test status
Simulation time 545667874 ps
CPU time 23.58 seconds
Started Aug 01 05:37:27 PM PDT 24
Finished Aug 01 05:37:51 PM PDT 24
Peak memory 211656 kb
Host smart-150a47ed-d3aa-41d9-a209-876d29664233
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1869684735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1869684735
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.2219571610
Short name T256
Test name
Test status
Simulation time 264516062 ps
CPU time 19.56 seconds
Started Aug 01 05:37:26 PM PDT 24
Finished Aug 01 05:37:46 PM PDT 24
Peak memory 211652 kb
Host smart-1164d841-b333-47e7-86c5-ce852af9fe1a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2219571610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.2219571610
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3868872467
Short name T575
Test name
Test status
Simulation time 121055286284 ps
CPU time 668.01 seconds
Started Aug 01 05:37:31 PM PDT 24
Finished Aug 01 05:48:40 PM PDT 24
Peak memory 207440 kb
Host smart-b8bab6a4-51c7-428b-8223-32335ba7ac66
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3868872467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl
ow_rsp.3868872467
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2566773875
Short name T695
Test name
Test status
Simulation time 131704957 ps
CPU time 3.64 seconds
Started Aug 01 05:37:33 PM PDT 24
Finished Aug 01 05:37:37 PM PDT 24
Peak memory 203568 kb
Host smart-d5210c5d-e869-4620-b7f1-2669a610e395
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2566773875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.2566773875
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.3734809052
Short name T332
Test name
Test status
Simulation time 24472703 ps
CPU time 3.21 seconds
Started Aug 01 05:37:28 PM PDT 24
Finished Aug 01 05:37:32 PM PDT 24
Peak memory 203464 kb
Host smart-2a03e250-0641-402f-8f61-e57997fcd335
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3734809052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3734809052
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.2217163882
Short name T776
Test name
Test status
Simulation time 24302525 ps
CPU time 3.26 seconds
Started Aug 01 05:37:26 PM PDT 24
Finished Aug 01 05:37:30 PM PDT 24
Peak memory 203564 kb
Host smart-d43f28ef-cc8e-4750-838d-1c293ba8ca44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2217163882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.2217163882
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.766991735
Short name T829
Test name
Test status
Simulation time 21519709270 ps
CPU time 43.93 seconds
Started Aug 01 05:37:28 PM PDT 24
Finished Aug 01 05:38:12 PM PDT 24
Peak memory 211696 kb
Host smart-fde6f25f-a5e6-4ecf-bb86-2d3b6b64463f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=766991735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.766991735
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1003821597
Short name T603
Test name
Test status
Simulation time 22690492324 ps
CPU time 185.87 seconds
Started Aug 01 05:37:26 PM PDT 24
Finished Aug 01 05:40:32 PM PDT 24
Peak memory 211696 kb
Host smart-ba15156e-8eb1-4e69-9b83-2498400501d2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1003821597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1003821597
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.3161662819
Short name T203
Test name
Test status
Simulation time 334548420 ps
CPU time 15.49 seconds
Started Aug 01 05:37:25 PM PDT 24
Finished Aug 01 05:37:41 PM PDT 24
Peak memory 211640 kb
Host smart-98149e0e-1a2c-44c3-9bec-c4b76891938f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161662819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.3161662819
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.3380579386
Short name T237
Test name
Test status
Simulation time 825898411 ps
CPU time 13.61 seconds
Started Aug 01 05:37:28 PM PDT 24
Finished Aug 01 05:37:41 PM PDT 24
Peak memory 203872 kb
Host smart-d1bb9af1-2800-48cc-94e5-179634a5caf2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3380579386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3380579386
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.2249943122
Short name T512
Test name
Test status
Simulation time 253203806 ps
CPU time 3.1 seconds
Started Aug 01 05:37:29 PM PDT 24
Finished Aug 01 05:37:32 PM PDT 24
Peak memory 203492 kb
Host smart-01bc8d42-50af-4b49-9d60-4c9282809019
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2249943122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2249943122
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.216075848
Short name T421
Test name
Test status
Simulation time 12433513993 ps
CPU time 35.96 seconds
Started Aug 01 05:37:28 PM PDT 24
Finished Aug 01 05:38:05 PM PDT 24
Peak memory 203464 kb
Host smart-2ac85a36-63be-4719-8190-5a9ec84e2438
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=216075848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.216075848
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1658540232
Short name T140
Test name
Test status
Simulation time 4157243024 ps
CPU time 33.58 seconds
Started Aug 01 05:37:27 PM PDT 24
Finished Aug 01 05:38:01 PM PDT 24
Peak memory 203540 kb
Host smart-9082a498-a972-456d-b4ec-6cb1f61cabee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1658540232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1658540232
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.657005601
Short name T667
Test name
Test status
Simulation time 27841591 ps
CPU time 2.26 seconds
Started Aug 01 05:37:26 PM PDT 24
Finished Aug 01 05:37:28 PM PDT 24
Peak memory 203464 kb
Host smart-449777bb-43e5-47dc-bd5c-ef53d3cdc9c1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657005601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.657005601
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.3127022091
Short name T76
Test name
Test status
Simulation time 1176402977 ps
CPU time 38.27 seconds
Started Aug 01 05:37:28 PM PDT 24
Finished Aug 01 05:38:07 PM PDT 24
Peak memory 205924 kb
Host smart-3f4919bb-0151-4150-bbd8-d5c2add42d47
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3127022091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3127022091
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.2978569347
Short name T436
Test name
Test status
Simulation time 622166070 ps
CPU time 89.11 seconds
Started Aug 01 05:37:26 PM PDT 24
Finished Aug 01 05:38:56 PM PDT 24
Peak memory 206808 kb
Host smart-5346c660-f71a-46ba-9dd5-5ca0df5c11a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2978569347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2978569347
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.812875983
Short name T370
Test name
Test status
Simulation time 22081440 ps
CPU time 28.78 seconds
Started Aug 01 05:37:26 PM PDT 24
Finished Aug 01 05:37:55 PM PDT 24
Peak memory 206044 kb
Host smart-80e7739c-aa60-457a-882f-0e6385418858
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=812875983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand
_reset.812875983
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.1034235687
Short name T65
Test name
Test status
Simulation time 7229678342 ps
CPU time 107.69 seconds
Started Aug 01 05:37:27 PM PDT 24
Finished Aug 01 05:39:15 PM PDT 24
Peak memory 207668 kb
Host smart-99feae7f-66c4-4a1d-8aa1-da40ccb85c61
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1034235687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re
set_error.1034235687
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.4121147003
Short name T727
Test name
Test status
Simulation time 391230669 ps
CPU time 9.32 seconds
Started Aug 01 05:37:28 PM PDT 24
Finished Aug 01 05:37:38 PM PDT 24
Peak memory 211668 kb
Host smart-144885bc-58a6-4643-8585-a4c253752989
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4121147003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.4121147003
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.3245051537
Short name T870
Test name
Test status
Simulation time 1776311529 ps
CPU time 38.64 seconds
Started Aug 01 05:37:27 PM PDT 24
Finished Aug 01 05:38:06 PM PDT 24
Peak memory 204584 kb
Host smart-ecfad0ec-dd0d-4c84-adef-9feffd9f2627
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3245051537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.3245051537
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.3580287649
Short name T491
Test name
Test status
Simulation time 51652073588 ps
CPU time 472.35 seconds
Started Aug 01 05:37:28 PM PDT 24
Finished Aug 01 05:45:21 PM PDT 24
Peak memory 211636 kb
Host smart-06e2a6d2-aa20-4620-9d58-0932508bb9da
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3580287649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl
ow_rsp.3580287649
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.4050110609
Short name T490
Test name
Test status
Simulation time 811326394 ps
CPU time 5.9 seconds
Started Aug 01 05:37:27 PM PDT 24
Finished Aug 01 05:37:33 PM PDT 24
Peak memory 203468 kb
Host smart-a14a74d3-62be-484f-935e-e4b4c46c5fe5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4050110609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.4050110609
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.1861336793
Short name T520
Test name
Test status
Simulation time 27934315 ps
CPU time 3.19 seconds
Started Aug 01 05:37:27 PM PDT 24
Finished Aug 01 05:37:30 PM PDT 24
Peak memory 203488 kb
Host smart-20af8b4c-a989-4055-81fb-e24139c5e8ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1861336793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1861336793
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.1747828851
Short name T531
Test name
Test status
Simulation time 570752583 ps
CPU time 20.45 seconds
Started Aug 01 05:37:27 PM PDT 24
Finished Aug 01 05:37:48 PM PDT 24
Peak memory 211676 kb
Host smart-c086a840-8ba8-488b-8c0d-da28f0c0a6c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1747828851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1747828851
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.515805940
Short name T547
Test name
Test status
Simulation time 21661757611 ps
CPU time 98.42 seconds
Started Aug 01 05:37:26 PM PDT 24
Finished Aug 01 05:39:05 PM PDT 24
Peak memory 211736 kb
Host smart-4ea29d0a-720e-4d48-8ac3-79f3018cb47e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=515805940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.515805940
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.611385123
Short name T273
Test name
Test status
Simulation time 1291875877 ps
CPU time 10.27 seconds
Started Aug 01 05:37:28 PM PDT 24
Finished Aug 01 05:37:38 PM PDT 24
Peak memory 203512 kb
Host smart-3b9ce2fc-7b36-4ab4-ab47-88f565d99e35
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=611385123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.611385123
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.992761118
Short name T49
Test name
Test status
Simulation time 59572619 ps
CPU time 5.13 seconds
Started Aug 01 05:37:26 PM PDT 24
Finished Aug 01 05:37:32 PM PDT 24
Peak memory 204580 kb
Host smart-ba10fe25-6f34-413f-8df4-fee92ba6481a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992761118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.992761118
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.3164375221
Short name T466
Test name
Test status
Simulation time 706786652 ps
CPU time 12.58 seconds
Started Aug 01 05:37:34 PM PDT 24
Finished Aug 01 05:37:46 PM PDT 24
Peak memory 203624 kb
Host smart-abb2db9d-2b88-42b3-a084-8cb20b06c967
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3164375221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3164375221
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.2132057064
Short name T361
Test name
Test status
Simulation time 30739543 ps
CPU time 2.52 seconds
Started Aug 01 05:37:29 PM PDT 24
Finished Aug 01 05:37:31 PM PDT 24
Peak memory 203388 kb
Host smart-04931ad2-f8eb-4b7c-a46d-bc3e61c65e18
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2132057064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2132057064
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.447185969
Short name T584
Test name
Test status
Simulation time 4828807285 ps
CPU time 30.59 seconds
Started Aug 01 05:37:29 PM PDT 24
Finished Aug 01 05:38:00 PM PDT 24
Peak memory 203564 kb
Host smart-333ebbaa-58f2-498d-b1b9-b076fc4c3256
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=447185969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.447185969
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.1267134929
Short name T174
Test name
Test status
Simulation time 5043843485 ps
CPU time 28.6 seconds
Started Aug 01 05:37:26 PM PDT 24
Finished Aug 01 05:37:55 PM PDT 24
Peak memory 203428 kb
Host smart-d79381b0-f736-4417-a66d-93f7be8c174f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1267134929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1267134929
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1016867410
Short name T818
Test name
Test status
Simulation time 28288866 ps
CPU time 2.08 seconds
Started Aug 01 05:37:32 PM PDT 24
Finished Aug 01 05:37:34 PM PDT 24
Peak memory 203408 kb
Host smart-24d5d041-a4cf-4881-9e12-1bf17e91e07c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016867410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1016867410
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.1754591200
Short name T316
Test name
Test status
Simulation time 1991345366 ps
CPU time 103.67 seconds
Started Aug 01 05:37:28 PM PDT 24
Finished Aug 01 05:39:12 PM PDT 24
Peak memory 205836 kb
Host smart-7d770eb2-f4db-45c7-a493-cfd9d0bcbe5e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1754591200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1754591200
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.257225323
Short name T708
Test name
Test status
Simulation time 6151694502 ps
CPU time 131.95 seconds
Started Aug 01 05:37:40 PM PDT 24
Finished Aug 01 05:39:53 PM PDT 24
Peak memory 206608 kb
Host smart-f522313b-39b7-4287-85dd-e092a4736bde
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=257225323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.257225323
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.894445575
Short name T184
Test name
Test status
Simulation time 50726413 ps
CPU time 11.96 seconds
Started Aug 01 05:37:39 PM PDT 24
Finished Aug 01 05:37:51 PM PDT 24
Peak memory 206036 kb
Host smart-f91b57c0-5669-4b54-8e2a-2e02e764f667
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=894445575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand
_reset.894445575
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.4097288408
Short name T507
Test name
Test status
Simulation time 6788246879 ps
CPU time 251.42 seconds
Started Aug 01 05:37:37 PM PDT 24
Finished Aug 01 05:41:49 PM PDT 24
Peak memory 219912 kb
Host smart-c298e48e-493b-4904-9dc8-8f9bee92887b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4097288408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re
set_error.4097288408
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.2855579525
Short name T112
Test name
Test status
Simulation time 411183157 ps
CPU time 13.47 seconds
Started Aug 01 05:37:28 PM PDT 24
Finished Aug 01 05:37:41 PM PDT 24
Peak memory 211684 kb
Host smart-7efdcde2-fd75-49f4-a832-b4d794b859ca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2855579525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2855579525
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.926077574
Short name T199
Test name
Test status
Simulation time 346926448 ps
CPU time 31.99 seconds
Started Aug 01 05:37:42 PM PDT 24
Finished Aug 01 05:38:14 PM PDT 24
Peak memory 211692 kb
Host smart-aa2b3700-2aad-409f-9da5-c5e402323acd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=926077574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.926077574
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1876358621
Short name T684
Test name
Test status
Simulation time 20572754170 ps
CPU time 105.6 seconds
Started Aug 01 05:37:40 PM PDT 24
Finished Aug 01 05:39:26 PM PDT 24
Peak memory 211720 kb
Host smart-9bcddaa2-a3bb-4f1a-a8a7-ffc69e264316
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1876358621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl
ow_rsp.1876358621
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.3715535893
Short name T828
Test name
Test status
Simulation time 42448388 ps
CPU time 6.42 seconds
Started Aug 01 05:37:38 PM PDT 24
Finished Aug 01 05:37:45 PM PDT 24
Peak memory 203916 kb
Host smart-2af67cf5-10db-4e38-9600-d2daee4bf638
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3715535893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.3715535893
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.1277354420
Short name T486
Test name
Test status
Simulation time 468389391 ps
CPU time 13.42 seconds
Started Aug 01 05:37:41 PM PDT 24
Finished Aug 01 05:37:55 PM PDT 24
Peak memory 203700 kb
Host smart-1a42185c-b2c6-4e2b-8eca-d142fe407f80
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1277354420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1277354420
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.3877230992
Short name T19
Test name
Test status
Simulation time 27657071 ps
CPU time 3.65 seconds
Started Aug 01 05:37:40 PM PDT 24
Finished Aug 01 05:37:44 PM PDT 24
Peak memory 204036 kb
Host smart-2f9fd61d-0857-418e-a728-10edcb05c1a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3877230992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.3877230992
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.1588409767
Short name T692
Test name
Test status
Simulation time 127286708694 ps
CPU time 186.67 seconds
Started Aug 01 05:37:40 PM PDT 24
Finished Aug 01 05:40:47 PM PDT 24
Peak memory 211732 kb
Host smart-46f0cbfc-b1dd-4c75-9940-df276d3911f5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588409767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1588409767
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.3825448092
Short name T744
Test name
Test status
Simulation time 26692908242 ps
CPU time 190.29 seconds
Started Aug 01 05:37:38 PM PDT 24
Finished Aug 01 05:40:49 PM PDT 24
Peak memory 205120 kb
Host smart-63900d83-b386-45f3-9a8c-e6ccd06ff460
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3825448092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3825448092
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.121742786
Short name T546
Test name
Test status
Simulation time 228469837 ps
CPU time 19.08 seconds
Started Aug 01 05:37:38 PM PDT 24
Finished Aug 01 05:37:57 PM PDT 24
Peak memory 204672 kb
Host smart-68ed4360-9faa-445f-98db-8aeda3946394
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121742786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.121742786
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.4177912987
Short name T443
Test name
Test status
Simulation time 438758959 ps
CPU time 8.85 seconds
Started Aug 01 05:37:38 PM PDT 24
Finished Aug 01 05:37:47 PM PDT 24
Peak memory 203456 kb
Host smart-e50137f0-46d2-4a02-b697-c49da4622285
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4177912987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.4177912987
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.3816190567
Short name T788
Test name
Test status
Simulation time 191914485 ps
CPU time 3.31 seconds
Started Aug 01 05:37:41 PM PDT 24
Finished Aug 01 05:37:44 PM PDT 24
Peak memory 203484 kb
Host smart-793c83aa-a93e-404f-924b-df79aade74ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3816190567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3816190567
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3351169837
Short name T231
Test name
Test status
Simulation time 5851116846 ps
CPU time 34.36 seconds
Started Aug 01 05:37:38 PM PDT 24
Finished Aug 01 05:38:13 PM PDT 24
Peak memory 203460 kb
Host smart-d1cb683e-90b7-45cd-bc4d-e0f81a2427af
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351169837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3351169837
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2540651044
Short name T233
Test name
Test status
Simulation time 5543102501 ps
CPU time 30.06 seconds
Started Aug 01 05:37:41 PM PDT 24
Finished Aug 01 05:38:12 PM PDT 24
Peak memory 203544 kb
Host smart-9852bbdf-4197-4aaa-bc31-7e5a5f03b728
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2540651044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2540651044
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1100784879
Short name T758
Test name
Test status
Simulation time 61734806 ps
CPU time 2.63 seconds
Started Aug 01 05:37:41 PM PDT 24
Finished Aug 01 05:37:44 PM PDT 24
Peak memory 203448 kb
Host smart-c4baa2f8-4438-41a9-a7b9-38f3c32118c3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100784879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1100784879
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.1960611131
Short name T354
Test name
Test status
Simulation time 1819668721 ps
CPU time 46.46 seconds
Started Aug 01 05:37:41 PM PDT 24
Finished Aug 01 05:38:28 PM PDT 24
Peak memory 205964 kb
Host smart-c3392cfe-e5ab-47cc-9acd-496fab3073d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1960611131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1960611131
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.813973684
Short name T605
Test name
Test status
Simulation time 8811648268 ps
CPU time 147.57 seconds
Started Aug 01 05:37:39 PM PDT 24
Finished Aug 01 05:40:07 PM PDT 24
Peak memory 206716 kb
Host smart-2e4926ca-2cb0-4186-aa0f-976c13de3f62
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=813973684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.813973684
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.321667550
Short name T815
Test name
Test status
Simulation time 649299205 ps
CPU time 201.76 seconds
Started Aug 01 05:37:40 PM PDT 24
Finished Aug 01 05:41:03 PM PDT 24
Peak memory 209264 kb
Host smart-b6ca3f90-ea39-4487-9762-b92847b01365
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=321667550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand
_reset.321667550
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.1691663189
Short name T28
Test name
Test status
Simulation time 4140710987 ps
CPU time 423.51 seconds
Started Aug 01 05:37:40 PM PDT 24
Finished Aug 01 05:44:44 PM PDT 24
Peak memory 226344 kb
Host smart-52a57eca-db4a-4704-8805-fb671824240b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1691663189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re
set_error.1691663189
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.3462183706
Short name T484
Test name
Test status
Simulation time 1437744060 ps
CPU time 19.87 seconds
Started Aug 01 05:37:40 PM PDT 24
Finished Aug 01 05:38:00 PM PDT 24
Peak memory 211680 kb
Host smart-24ecfcfb-f70c-4135-a3c7-189adf4920eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3462183706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3462183706
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.1158260608
Short name T213
Test name
Test status
Simulation time 1784000792 ps
CPU time 73.84 seconds
Started Aug 01 05:37:42 PM PDT 24
Finished Aug 01 05:38:56 PM PDT 24
Peak memory 211664 kb
Host smart-6fd1b4de-1f77-4e38-a1dd-5daabb0eef8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1158260608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.1158260608
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.277091710
Short name T219
Test name
Test status
Simulation time 320672157 ps
CPU time 11.21 seconds
Started Aug 01 05:37:41 PM PDT 24
Finished Aug 01 05:37:52 PM PDT 24
Peak memory 203508 kb
Host smart-b0a76aab-c40a-42b1-baea-040995bbd54a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=277091710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.277091710
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.3593401937
Short name T537
Test name
Test status
Simulation time 408403258 ps
CPU time 12.97 seconds
Started Aug 01 05:37:39 PM PDT 24
Finished Aug 01 05:37:52 PM PDT 24
Peak memory 203468 kb
Host smart-83774c5c-7a4b-4f6c-9dfb-3feac2a8a420
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3593401937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3593401937
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.1757722024
Short name T78
Test name
Test status
Simulation time 1757973169 ps
CPU time 33.1 seconds
Started Aug 01 05:37:42 PM PDT 24
Finished Aug 01 05:38:15 PM PDT 24
Peak memory 211536 kb
Host smart-d0b0d5bd-0205-41e0-a24a-3dbbf89472a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1757722024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.1757722024
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.3324882379
Short name T665
Test name
Test status
Simulation time 9446213133 ps
CPU time 58.57 seconds
Started Aug 01 05:37:40 PM PDT 24
Finished Aug 01 05:38:38 PM PDT 24
Peak memory 211728 kb
Host smart-15c45e05-ca50-42ef-9cda-85d43a93c65b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324882379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3324882379
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1501085041
Short name T493
Test name
Test status
Simulation time 5351138249 ps
CPU time 31.67 seconds
Started Aug 01 05:37:37 PM PDT 24
Finished Aug 01 05:38:09 PM PDT 24
Peak memory 211756 kb
Host smart-c4235e54-8f87-422c-ae1c-c24d7bbfbd0a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1501085041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1501085041
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.2438205133
Short name T760
Test name
Test status
Simulation time 103283683 ps
CPU time 13.88 seconds
Started Aug 01 05:37:39 PM PDT 24
Finished Aug 01 05:37:53 PM PDT 24
Peak memory 211572 kb
Host smart-83be48eb-b0bd-4f93-becf-1cfd4b3c2df6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438205133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2438205133
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.1924800501
Short name T857
Test name
Test status
Simulation time 125848668 ps
CPU time 8.42 seconds
Started Aug 01 05:37:39 PM PDT 24
Finished Aug 01 05:37:47 PM PDT 24
Peak memory 204116 kb
Host smart-e8075e5b-2bfd-4501-9e8f-a083b32bb21b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1924800501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1924800501
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.2573544924
Short name T543
Test name
Test status
Simulation time 40153194 ps
CPU time 2.67 seconds
Started Aug 01 05:37:41 PM PDT 24
Finished Aug 01 05:37:44 PM PDT 24
Peak memory 203344 kb
Host smart-959f8a48-7e2b-4bdf-b570-e0e241502531
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2573544924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2573544924
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.364186912
Short name T258
Test name
Test status
Simulation time 8192623079 ps
CPU time 27.19 seconds
Started Aug 01 05:37:38 PM PDT 24
Finished Aug 01 05:38:06 PM PDT 24
Peak memory 203536 kb
Host smart-aa89ddf9-fd15-428d-9a94-6bbe10645a7a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=364186912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.364186912
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.2454816803
Short name T138
Test name
Test status
Simulation time 8546906448 ps
CPU time 29.06 seconds
Started Aug 01 05:37:38 PM PDT 24
Finished Aug 01 05:38:08 PM PDT 24
Peak memory 203468 kb
Host smart-dfa79886-2be6-4766-bce1-8bcc3c558cc1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2454816803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2454816803
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2028965238
Short name T131
Test name
Test status
Simulation time 46845372 ps
CPU time 2.47 seconds
Started Aug 01 05:37:41 PM PDT 24
Finished Aug 01 05:37:43 PM PDT 24
Peak memory 203496 kb
Host smart-8be0d169-07a3-4e52-9912-e3ccc1233d46
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028965238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2028965238
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.734233376
Short name T487
Test name
Test status
Simulation time 801266926 ps
CPU time 80.33 seconds
Started Aug 01 05:37:38 PM PDT 24
Finished Aug 01 05:38:59 PM PDT 24
Peak memory 207380 kb
Host smart-5f883fe2-1f47-4184-ad1f-e6a96c678810
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=734233376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.734233376
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.160360147
Short name T449
Test name
Test status
Simulation time 9089480466 ps
CPU time 78.8 seconds
Started Aug 01 05:37:38 PM PDT 24
Finished Aug 01 05:38:58 PM PDT 24
Peak memory 206252 kb
Host smart-9ac54859-6937-4a11-a753-6b3b7b5d079a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=160360147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.160360147
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.1889733972
Short name T103
Test name
Test status
Simulation time 5522924907 ps
CPU time 87.4 seconds
Started Aug 01 05:37:41 PM PDT 24
Finished Aug 01 05:39:09 PM PDT 24
Peak memory 208748 kb
Host smart-e7a31b57-f035-4c2e-a043-5c3bd4019448
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1889733972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re
set_error.1889733972
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.950185072
Short name T229
Test name
Test status
Simulation time 867163520 ps
CPU time 25.06 seconds
Started Aug 01 05:37:39 PM PDT 24
Finished Aug 01 05:38:04 PM PDT 24
Peak memory 211656 kb
Host smart-1aa6e0ef-97bb-4318-a21e-887d27860725
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=950185072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.950185072
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.3781732153
Short name T117
Test name
Test status
Simulation time 648437681 ps
CPU time 23.54 seconds
Started Aug 01 05:37:58 PM PDT 24
Finished Aug 01 05:38:22 PM PDT 24
Peak memory 211660 kb
Host smart-488f3c00-0053-487a-ab64-2914aef2fc91
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3781732153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.3781732153
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.2200482578
Short name T511
Test name
Test status
Simulation time 2982453523 ps
CPU time 29.31 seconds
Started Aug 01 05:37:56 PM PDT 24
Finished Aug 01 05:38:26 PM PDT 24
Peak memory 203548 kb
Host smart-7fbae95b-d519-4a81-9ec3-ca4771fd50c7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2200482578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl
ow_rsp.2200482578
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.139607637
Short name T66
Test name
Test status
Simulation time 422740484 ps
CPU time 12.97 seconds
Started Aug 01 05:37:58 PM PDT 24
Finished Aug 01 05:38:12 PM PDT 24
Peak memory 203476 kb
Host smart-170fa827-5537-407b-b0e8-d13058b661b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=139607637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.139607637
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.898145517
Short name T177
Test name
Test status
Simulation time 784874214 ps
CPU time 23.48 seconds
Started Aug 01 05:37:56 PM PDT 24
Finished Aug 01 05:38:19 PM PDT 24
Peak memory 203452 kb
Host smart-757aa88f-690e-4a4b-a943-f2f0e62d6a4f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=898145517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.898145517
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.1857853065
Short name T860
Test name
Test status
Simulation time 135307112 ps
CPU time 19.9 seconds
Started Aug 01 05:37:41 PM PDT 24
Finished Aug 01 05:38:01 PM PDT 24
Peak memory 211660 kb
Host smart-801bc235-074c-4e22-a82b-d2d8d15a30e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1857853065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.1857853065
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.1756517922
Short name T464
Test name
Test status
Simulation time 28737473228 ps
CPU time 58.9 seconds
Started Aug 01 05:37:38 PM PDT 24
Finished Aug 01 05:38:37 PM PDT 24
Peak memory 211680 kb
Host smart-85880b5f-ab42-4020-8c65-b0c0aa3e82c9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756517922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1756517922
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.247444681
Short name T620
Test name
Test status
Simulation time 27549158620 ps
CPU time 100.56 seconds
Started Aug 01 05:37:59 PM PDT 24
Finished Aug 01 05:39:39 PM PDT 24
Peak memory 204776 kb
Host smart-38900f41-6207-48c2-aa7a-cfdd1020b693
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=247444681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.247444681
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.176630196
Short name T459
Test name
Test status
Simulation time 42209957 ps
CPU time 3.99 seconds
Started Aug 01 05:37:40 PM PDT 24
Finished Aug 01 05:37:45 PM PDT 24
Peak memory 211648 kb
Host smart-34639038-13c5-45ba-ab84-5a0d6e5e95f3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176630196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.176630196
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.2150299905
Short name T102
Test name
Test status
Simulation time 2129473357 ps
CPU time 13.67 seconds
Started Aug 01 05:37:58 PM PDT 24
Finished Aug 01 05:38:12 PM PDT 24
Peak memory 203736 kb
Host smart-87974af6-2049-49e2-8b20-1d3f2ef3da4e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2150299905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2150299905
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.2856010380
Short name T816
Test name
Test status
Simulation time 69015477 ps
CPU time 2.13 seconds
Started Aug 01 05:37:39 PM PDT 24
Finished Aug 01 05:37:42 PM PDT 24
Peak memory 203448 kb
Host smart-cadd64dc-ba4b-4d06-af58-50d47b07d426
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2856010380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2856010380
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.112459964
Short name T222
Test name
Test status
Simulation time 5405381343 ps
CPU time 29 seconds
Started Aug 01 05:37:40 PM PDT 24
Finished Aug 01 05:38:09 PM PDT 24
Peak memory 203548 kb
Host smart-71962b7e-d6b6-485b-bc82-3ea158ad5e9a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=112459964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.112459964
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.735027673
Short name T745
Test name
Test status
Simulation time 2882652968 ps
CPU time 26.74 seconds
Started Aug 01 05:37:37 PM PDT 24
Finished Aug 01 05:38:04 PM PDT 24
Peak memory 203464 kb
Host smart-b7194fa1-a7b1-432f-b319-c8d6b00b5279
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=735027673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.735027673
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1856800287
Short name T116
Test name
Test status
Simulation time 43748884 ps
CPU time 2.27 seconds
Started Aug 01 05:37:41 PM PDT 24
Finished Aug 01 05:37:43 PM PDT 24
Peak memory 203480 kb
Host smart-72400437-d554-4cf8-ba65-733bf53b17d8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856800287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1856800287
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.3077780631
Short name T101
Test name
Test status
Simulation time 13589773127 ps
CPU time 182.85 seconds
Started Aug 01 05:37:57 PM PDT 24
Finished Aug 01 05:41:00 PM PDT 24
Peak memory 209660 kb
Host smart-fcea5b38-0c9c-4b77-92e8-c451f9a362e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3077780631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3077780631
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.2206973967
Short name T380
Test name
Test status
Simulation time 1327273958 ps
CPU time 146.09 seconds
Started Aug 01 05:37:57 PM PDT 24
Finished Aug 01 05:40:24 PM PDT 24
Peak memory 206960 kb
Host smart-cca8d28b-0b9a-48eb-bc44-3cc0842790ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2206973967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2206973967
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1174945766
Short name T128
Test name
Test status
Simulation time 5600916275 ps
CPU time 258.93 seconds
Started Aug 01 05:37:59 PM PDT 24
Finished Aug 01 05:42:18 PM PDT 24
Peak memory 209808 kb
Host smart-aef722a3-9171-45f0-b0b6-e57032437c4a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1174945766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran
d_reset.1174945766
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2945370625
Short name T279
Test name
Test status
Simulation time 8485760 ps
CPU time 12.53 seconds
Started Aug 01 05:37:57 PM PDT 24
Finished Aug 01 05:38:10 PM PDT 24
Peak memory 203928 kb
Host smart-9a1f98ff-5cac-494d-99e3-b7dc3e2f948f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2945370625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re
set_error.2945370625
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.917019484
Short name T687
Test name
Test status
Simulation time 860864812 ps
CPU time 33.04 seconds
Started Aug 01 05:37:58 PM PDT 24
Finished Aug 01 05:38:31 PM PDT 24
Peak memory 211664 kb
Host smart-36f4dd6d-39bd-446c-a81e-14b47984b147
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=917019484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.917019484
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.1935198482
Short name T772
Test name
Test status
Simulation time 2075524565 ps
CPU time 62.68 seconds
Started Aug 01 05:37:59 PM PDT 24
Finished Aug 01 05:39:01 PM PDT 24
Peak memory 211648 kb
Host smart-3a086e11-7545-4b48-801b-c68334162a02
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1935198482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1935198482
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.1454082057
Short name T636
Test name
Test status
Simulation time 74587633056 ps
CPU time 402.99 seconds
Started Aug 01 05:37:59 PM PDT 24
Finished Aug 01 05:44:42 PM PDT 24
Peak memory 211636 kb
Host smart-158b9a41-94f7-45f8-b5c1-64d9e76e6a2a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1454082057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl
ow_rsp.1454082057
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.964605690
Short name T867
Test name
Test status
Simulation time 613507970 ps
CPU time 14.99 seconds
Started Aug 01 05:37:57 PM PDT 24
Finished Aug 01 05:38:12 PM PDT 24
Peak memory 203844 kb
Host smart-497cca20-579e-461f-a42e-1ba6be40425a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=964605690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.964605690
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.892141947
Short name T185
Test name
Test status
Simulation time 166100721 ps
CPU time 5.51 seconds
Started Aug 01 05:37:57 PM PDT 24
Finished Aug 01 05:38:03 PM PDT 24
Peak memory 203444 kb
Host smart-48f8c79b-ece1-4603-a377-2cf10c05e138
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=892141947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.892141947
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.3845169615
Short name T141
Test name
Test status
Simulation time 1896908611 ps
CPU time 34.67 seconds
Started Aug 01 05:37:57 PM PDT 24
Finished Aug 01 05:38:32 PM PDT 24
Peak memory 211668 kb
Host smart-d92122c0-3be3-46ee-957c-ebb5f623993b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3845169615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.3845169615
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.408595133
Short name T670
Test name
Test status
Simulation time 34311106721 ps
CPU time 111.93 seconds
Started Aug 01 05:37:58 PM PDT 24
Finished Aug 01 05:39:51 PM PDT 24
Peak memory 211728 kb
Host smart-b2eb396b-e417-4535-897b-3194c731df1e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=408595133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.408595133
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3751660810
Short name T3
Test name
Test status
Simulation time 1444430906 ps
CPU time 13.65 seconds
Started Aug 01 05:37:59 PM PDT 24
Finished Aug 01 05:38:13 PM PDT 24
Peak memory 203424 kb
Host smart-032603f8-e4d7-4cf7-82a9-23312e8c6087
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3751660810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3751660810
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.2383799820
Short name T457
Test name
Test status
Simulation time 222360680 ps
CPU time 28.99 seconds
Started Aug 01 05:37:56 PM PDT 24
Finished Aug 01 05:38:25 PM PDT 24
Peak memory 211688 kb
Host smart-0f32357c-e9cd-4635-b7f9-c268a5f55c1e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383799820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2383799820
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.2575837754
Short name T16
Test name
Test status
Simulation time 3556742219 ps
CPU time 34.08 seconds
Started Aug 01 05:37:55 PM PDT 24
Finished Aug 01 05:38:30 PM PDT 24
Peak memory 211684 kb
Host smart-326701e3-9c12-4b8a-9e00-b13bd8526434
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2575837754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2575837754
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.1049141275
Short name T604
Test name
Test status
Simulation time 461504583 ps
CPU time 3.58 seconds
Started Aug 01 05:37:58 PM PDT 24
Finished Aug 01 05:38:02 PM PDT 24
Peak memory 203488 kb
Host smart-d3116ed3-17d3-4c0a-b05b-30f81b8cdd62
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1049141275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1049141275
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.756311727
Short name T225
Test name
Test status
Simulation time 9130026199 ps
CPU time 27.43 seconds
Started Aug 01 05:37:58 PM PDT 24
Finished Aug 01 05:38:26 PM PDT 24
Peak memory 203552 kb
Host smart-461ec8b5-12d9-4919-9fde-b43084b8c867
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=756311727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.756311727
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3527048726
Short name T472
Test name
Test status
Simulation time 16060222721 ps
CPU time 32.73 seconds
Started Aug 01 05:37:56 PM PDT 24
Finished Aug 01 05:38:29 PM PDT 24
Peak memory 203520 kb
Host smart-e5a6d503-db58-4f16-b9c0-70b6492f617a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3527048726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3527048726
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.232531650
Short name T114
Test name
Test status
Simulation time 28317921 ps
CPU time 2.28 seconds
Started Aug 01 05:38:00 PM PDT 24
Finished Aug 01 05:38:03 PM PDT 24
Peak memory 203448 kb
Host smart-dd379eea-e92d-437d-a114-329047ea855a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232531650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.232531650
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.454025211
Short name T410
Test name
Test status
Simulation time 1850404282 ps
CPU time 181.54 seconds
Started Aug 01 05:37:58 PM PDT 24
Finished Aug 01 05:40:59 PM PDT 24
Peak memory 209376 kb
Host smart-45a49327-a826-4fe8-9439-9411260e2187
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=454025211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.454025211
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2475288205
Short name T379
Test name
Test status
Simulation time 1843493735 ps
CPU time 183.19 seconds
Started Aug 01 05:37:56 PM PDT 24
Finished Aug 01 05:40:59 PM PDT 24
Peak memory 210808 kb
Host smart-3d8ba5bf-ad1d-4c0c-ba94-be10434d0089
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2475288205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2475288205
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.3003588044
Short name T468
Test name
Test status
Simulation time 12758400 ps
CPU time 2.64 seconds
Started Aug 01 05:37:58 PM PDT 24
Finished Aug 01 05:38:01 PM PDT 24
Peak memory 203484 kb
Host smart-b5bc5ab5-c158-4122-a1fb-c54af78df395
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3003588044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re
set_error.3003588044
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.3854097029
Short name T590
Test name
Test status
Simulation time 155204869 ps
CPU time 12.18 seconds
Started Aug 01 05:37:57 PM PDT 24
Finished Aug 01 05:38:09 PM PDT 24
Peak memory 211656 kb
Host smart-f4c2e7aa-677a-4e16-a447-2e8f4522f705
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3854097029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3854097029
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.1497851567
Short name T207
Test name
Test status
Simulation time 1649179960 ps
CPU time 49.48 seconds
Started Aug 01 05:37:57 PM PDT 24
Finished Aug 01 05:38:46 PM PDT 24
Peak memory 211684 kb
Host smart-b7642789-ef00-4a32-b6e8-0eb015def811
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1497851567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1497851567
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.951227671
Short name T504
Test name
Test status
Simulation time 10557598382 ps
CPU time 74.9 seconds
Started Aug 01 05:37:57 PM PDT 24
Finished Aug 01 05:39:12 PM PDT 24
Peak memory 205532 kb
Host smart-0e6e349a-e86d-418e-b2ad-22ea96e7915e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=951227671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slo
w_rsp.951227671
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2600134980
Short name T153
Test name
Test status
Simulation time 914931311 ps
CPU time 19.22 seconds
Started Aug 01 05:38:00 PM PDT 24
Finished Aug 01 05:38:19 PM PDT 24
Peak memory 203512 kb
Host smart-9b82bb49-9c62-4c37-aeb6-ec636a73b7ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2600134980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2600134980
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.1107783936
Short name T873
Test name
Test status
Simulation time 174253561 ps
CPU time 2.66 seconds
Started Aug 01 05:37:59 PM PDT 24
Finished Aug 01 05:38:02 PM PDT 24
Peak memory 203456 kb
Host smart-2d5bb181-8ea2-438b-b066-f510ca911b1b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1107783936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1107783936
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.3692365355
Short name T21
Test name
Test status
Simulation time 1617118678 ps
CPU time 39.1 seconds
Started Aug 01 05:37:58 PM PDT 24
Finished Aug 01 05:38:37 PM PDT 24
Peak memory 205068 kb
Host smart-dc7dd059-9463-4ee0-8618-2becd3c4155d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3692365355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.3692365355
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1807455492
Short name T668
Test name
Test status
Simulation time 167435324352 ps
CPU time 224.26 seconds
Started Aug 01 05:37:59 PM PDT 24
Finished Aug 01 05:41:43 PM PDT 24
Peak memory 211692 kb
Host smart-57ad0d20-f49f-4cef-9831-80815eeb7feb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807455492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1807455492
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.3919288730
Short name T275
Test name
Test status
Simulation time 40126199261 ps
CPU time 147.84 seconds
Started Aug 01 05:37:57 PM PDT 24
Finished Aug 01 05:40:25 PM PDT 24
Peak memory 211708 kb
Host smart-eadc20c4-bfa6-4411-a84e-cc93608f1342
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3919288730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3919288730
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.3449221664
Short name T53
Test name
Test status
Simulation time 136314972 ps
CPU time 21.34 seconds
Started Aug 01 05:37:59 PM PDT 24
Finished Aug 01 05:38:21 PM PDT 24
Peak memory 211640 kb
Host smart-f9e4b0fc-2712-400f-9667-63a57597a0d4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449221664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3449221664
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.413406433
Short name T635
Test name
Test status
Simulation time 934236044 ps
CPU time 21.37 seconds
Started Aug 01 05:37:59 PM PDT 24
Finished Aug 01 05:38:21 PM PDT 24
Peak memory 204112 kb
Host smart-16c42023-e6f3-465a-8cee-9243934eb515
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=413406433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.413406433
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.4281628430
Short name T866
Test name
Test status
Simulation time 86730460 ps
CPU time 2.18 seconds
Started Aug 01 05:37:57 PM PDT 24
Finished Aug 01 05:38:00 PM PDT 24
Peak memory 203548 kb
Host smart-ec4de964-8907-44c2-a24f-53cdb35b61a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4281628430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.4281628430
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.4276154724
Short name T324
Test name
Test status
Simulation time 24479801712 ps
CPU time 40.59 seconds
Started Aug 01 05:37:59 PM PDT 24
Finished Aug 01 05:38:40 PM PDT 24
Peak memory 203552 kb
Host smart-9ca990a5-5c1e-46c1-952f-41733d5c393f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276154724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.4276154724
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.2248677618
Short name T600
Test name
Test status
Simulation time 4623329296 ps
CPU time 36.1 seconds
Started Aug 01 05:37:57 PM PDT 24
Finished Aug 01 05:38:33 PM PDT 24
Peak memory 203460 kb
Host smart-e505e53f-8107-4ba5-895c-6140873598d5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2248677618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2248677618
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.3741665656
Short name T235
Test name
Test status
Simulation time 69625695 ps
CPU time 2.6 seconds
Started Aug 01 05:37:58 PM PDT 24
Finished Aug 01 05:38:01 PM PDT 24
Peak memory 203448 kb
Host smart-9c6631cb-3a53-49ac-a540-4818bbf7a530
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741665656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3741665656
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.4231971436
Short name T833
Test name
Test status
Simulation time 5380130563 ps
CPU time 95.41 seconds
Started Aug 01 05:37:57 PM PDT 24
Finished Aug 01 05:39:33 PM PDT 24
Peak memory 206240 kb
Host smart-d3854c99-bd70-4ab9-86c8-9571992768fc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4231971436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.4231971436
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.2111460305
Short name T133
Test name
Test status
Simulation time 7967303310 ps
CPU time 157.94 seconds
Started Aug 01 05:37:57 PM PDT 24
Finished Aug 01 05:40:35 PM PDT 24
Peak memory 205476 kb
Host smart-76fcc7c8-a7f9-4635-ba74-085787c03c89
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2111460305 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2111460305
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.3087435465
Short name T644
Test name
Test status
Simulation time 3825412840 ps
CPU time 328.35 seconds
Started Aug 01 05:37:58 PM PDT 24
Finished Aug 01 05:43:26 PM PDT 24
Peak memory 210720 kb
Host smart-233baef4-211e-4c3a-98b7-3b74a6191448
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3087435465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran
d_reset.3087435465
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.2192389711
Short name T505
Test name
Test status
Simulation time 1766328111 ps
CPU time 239.4 seconds
Started Aug 01 05:37:56 PM PDT 24
Finished Aug 01 05:41:56 PM PDT 24
Peak memory 212356 kb
Host smart-af935306-b7b4-4a88-b26a-51d367c3a35a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2192389711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re
set_error.2192389711
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.2583844459
Short name T615
Test name
Test status
Simulation time 34497994 ps
CPU time 4.73 seconds
Started Aug 01 05:37:58 PM PDT 24
Finished Aug 01 05:38:03 PM PDT 24
Peak memory 211648 kb
Host smart-ea3988d2-80c3-4de5-9f32-e6a1f17e7962
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2583844459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2583844459
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.4290851152
Short name T458
Test name
Test status
Simulation time 1013536689 ps
CPU time 24.64 seconds
Started Aug 01 05:38:12 PM PDT 24
Finished Aug 01 05:38:36 PM PDT 24
Peak memory 211680 kb
Host smart-20f00fc3-6b3f-44e0-8a2f-7becda9d2457
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4290851152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.4290851152
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1856949161
Short name T852
Test name
Test status
Simulation time 35924104939 ps
CPU time 283.64 seconds
Started Aug 01 05:38:13 PM PDT 24
Finished Aug 01 05:42:57 PM PDT 24
Peak memory 206604 kb
Host smart-607b3730-9f35-425e-9a03-460f7adee0f2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1856949161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl
ow_rsp.1856949161
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.854185212
Short name T570
Test name
Test status
Simulation time 205965524 ps
CPU time 6.72 seconds
Started Aug 01 05:38:12 PM PDT 24
Finished Aug 01 05:38:19 PM PDT 24
Peak memory 203460 kb
Host smart-8569e4b4-4c1a-465c-86c7-7eda599198ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=854185212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.854185212
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.1250370068
Short name T608
Test name
Test status
Simulation time 18107187 ps
CPU time 2.23 seconds
Started Aug 01 05:38:10 PM PDT 24
Finished Aug 01 05:38:13 PM PDT 24
Peak memory 203372 kb
Host smart-3a2a3ca0-118f-46a3-b681-3017ace9e539
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1250370068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1250370068
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.3870938665
Short name T516
Test name
Test status
Simulation time 247343963 ps
CPU time 14.15 seconds
Started Aug 01 05:37:58 PM PDT 24
Finished Aug 01 05:38:12 PM PDT 24
Peak memory 211688 kb
Host smart-aa6a01d0-210b-4e8c-9ffd-b2618fb53100
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3870938665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.3870938665
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2123000381
Short name T195
Test name
Test status
Simulation time 37240570664 ps
CPU time 154.42 seconds
Started Aug 01 05:38:12 PM PDT 24
Finished Aug 01 05:40:47 PM PDT 24
Peak memory 211704 kb
Host smart-e6878ba9-70de-47f9-9c87-36a688c97bc8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123000381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2123000381
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1098626743
Short name T485
Test name
Test status
Simulation time 20709559474 ps
CPU time 150.16 seconds
Started Aug 01 05:38:10 PM PDT 24
Finished Aug 01 05:40:41 PM PDT 24
Peak memory 211800 kb
Host smart-483e2891-20ab-4fc2-9a5d-f19fd6b629d5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1098626743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1098626743
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.3118442017
Short name T770
Test name
Test status
Simulation time 247469863 ps
CPU time 29.52 seconds
Started Aug 01 05:38:00 PM PDT 24
Finished Aug 01 05:38:30 PM PDT 24
Peak memory 211676 kb
Host smart-38689d95-53c5-4d44-8a75-419e239d6819
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118442017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.3118442017
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.3337318774
Short name T796
Test name
Test status
Simulation time 241206851 ps
CPU time 19.62 seconds
Started Aug 01 05:38:10 PM PDT 24
Finished Aug 01 05:38:30 PM PDT 24
Peak memory 204164 kb
Host smart-8da209cc-5196-4460-88a6-494b58a1d812
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3337318774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3337318774
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.759464097
Short name T359
Test name
Test status
Simulation time 23424918 ps
CPU time 2.08 seconds
Started Aug 01 05:37:57 PM PDT 24
Finished Aug 01 05:37:59 PM PDT 24
Peak memory 203332 kb
Host smart-f515eee8-37a3-472c-8ca7-9851d852d073
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=759464097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.759464097
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3604322930
Short name T120
Test name
Test status
Simulation time 7097953919 ps
CPU time 37.37 seconds
Started Aug 01 05:37:58 PM PDT 24
Finished Aug 01 05:38:35 PM PDT 24
Peak memory 203556 kb
Host smart-99fb2f4c-0423-4f4e-bc73-c2e9a82e21e9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604322930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3604322930
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.556662848
Short name T227
Test name
Test status
Simulation time 5104103117 ps
CPU time 31.27 seconds
Started Aug 01 05:37:57 PM PDT 24
Finished Aug 01 05:38:29 PM PDT 24
Peak memory 203564 kb
Host smart-84d09f04-c611-4712-af4b-25dab12dc1f4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=556662848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.556662848
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.3223796907
Short name T422
Test name
Test status
Simulation time 42390066 ps
CPU time 2.53 seconds
Started Aug 01 05:37:57 PM PDT 24
Finished Aug 01 05:38:00 PM PDT 24
Peak memory 203428 kb
Host smart-abc3d62a-4f81-416c-ae8a-bbf45c52fd6c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223796907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.3223796907
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.600542021
Short name T218
Test name
Test status
Simulation time 2028731415 ps
CPU time 34.02 seconds
Started Aug 01 05:38:14 PM PDT 24
Finished Aug 01 05:38:48 PM PDT 24
Peak memory 204908 kb
Host smart-e2a137f1-edbc-40b5-98df-c2b6043cfc99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=600542021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.600542021
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1265432787
Short name T148
Test name
Test status
Simulation time 6387878767 ps
CPU time 107.19 seconds
Started Aug 01 05:38:12 PM PDT 24
Finished Aug 01 05:39:59 PM PDT 24
Peak memory 206944 kb
Host smart-e4de31a2-5437-483d-9395-38af62d72611
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1265432787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1265432787
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.4215058120
Short name T255
Test name
Test status
Simulation time 3793954570 ps
CPU time 391.18 seconds
Started Aug 01 05:38:13 PM PDT 24
Finished Aug 01 05:44:44 PM PDT 24
Peak memory 210328 kb
Host smart-f5e31e17-3d8f-4d53-bb56-2ffbd3866c37
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4215058120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran
d_reset.4215058120
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3219112469
Short name T618
Test name
Test status
Simulation time 2906039371 ps
CPU time 290.24 seconds
Started Aug 01 05:38:09 PM PDT 24
Finished Aug 01 05:43:00 PM PDT 24
Peak memory 211584 kb
Host smart-2649e355-8697-4a6c-879f-46c4bfd2d8c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3219112469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re
set_error.3219112469
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.3474354163
Short name T688
Test name
Test status
Simulation time 108028941 ps
CPU time 17.02 seconds
Started Aug 01 05:38:13 PM PDT 24
Finished Aug 01 05:38:30 PM PDT 24
Peak memory 211644 kb
Host smart-48717b6b-0717-4ef2-8f93-7ef533e0954c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3474354163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3474354163
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.3839213616
Short name T568
Test name
Test status
Simulation time 98497452 ps
CPU time 12.82 seconds
Started Aug 01 05:36:20 PM PDT 24
Finished Aug 01 05:36:33 PM PDT 24
Peak memory 211660 kb
Host smart-b6e6e45e-b65f-4822-ad47-bcfe7144ec69
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3839213616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.3839213616
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1716863938
Short name T724
Test name
Test status
Simulation time 11404950652 ps
CPU time 61.18 seconds
Started Aug 01 05:36:25 PM PDT 24
Finished Aug 01 05:37:26 PM PDT 24
Peak memory 211752 kb
Host smart-8ad7b0d4-32dc-4d50-8686-8a7383511632
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1716863938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo
w_rsp.1716863938
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.3677767721
Short name T797
Test name
Test status
Simulation time 1179049769 ps
CPU time 10.54 seconds
Started Aug 01 05:36:29 PM PDT 24
Finished Aug 01 05:36:40 PM PDT 24
Peak memory 203436 kb
Host smart-51f15d06-5364-463f-8091-843532e67298
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3677767721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.3677767721
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.4223703660
Short name T396
Test name
Test status
Simulation time 425355546 ps
CPU time 13.39 seconds
Started Aug 01 05:36:31 PM PDT 24
Finished Aug 01 05:36:45 PM PDT 24
Peak memory 203336 kb
Host smart-dec9b98d-2211-4801-9eaf-de88ac661729
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4223703660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.4223703660
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.1688550216
Short name T424
Test name
Test status
Simulation time 133135377 ps
CPU time 22.07 seconds
Started Aug 01 05:36:24 PM PDT 24
Finished Aug 01 05:36:47 PM PDT 24
Peak memory 211552 kb
Host smart-76ebe71a-e7a7-4adf-a40c-b59f215bfc62
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1688550216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.1688550216
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.1828397736
Short name T100
Test name
Test status
Simulation time 63275068901 ps
CPU time 113.06 seconds
Started Aug 01 05:36:23 PM PDT 24
Finished Aug 01 05:38:16 PM PDT 24
Peak memory 211680 kb
Host smart-9fd6e245-ce18-460d-8f4c-e6b964e746f1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828397736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1828397736
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.3262715473
Short name T163
Test name
Test status
Simulation time 32454489696 ps
CPU time 219.84 seconds
Started Aug 01 05:36:27 PM PDT 24
Finished Aug 01 05:40:07 PM PDT 24
Peak memory 211688 kb
Host smart-62d4fcc3-9764-48f9-b536-45b941e2086b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3262715473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3262715473
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.3183623751
Short name T810
Test name
Test status
Simulation time 266485827 ps
CPU time 16.65 seconds
Started Aug 01 05:36:24 PM PDT 24
Finished Aug 01 05:36:41 PM PDT 24
Peak memory 204708 kb
Host smart-af420c22-82f6-4681-b354-0b946869c948
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183623751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.3183623751
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.3044177862
Short name T452
Test name
Test status
Simulation time 1296377864 ps
CPU time 19.05 seconds
Started Aug 01 05:36:22 PM PDT 24
Finished Aug 01 05:36:41 PM PDT 24
Peak memory 203504 kb
Host smart-fe273b38-f867-4f2a-83c3-f8171a342aaa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3044177862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3044177862
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.533830382
Short name T175
Test name
Test status
Simulation time 88424577 ps
CPU time 1.91 seconds
Started Aug 01 05:36:19 PM PDT 24
Finished Aug 01 05:36:22 PM PDT 24
Peak memory 203488 kb
Host smart-c64424ac-a141-4756-afee-0ab1a60f03e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=533830382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.533830382
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.2245463171
Short name T403
Test name
Test status
Simulation time 9296211388 ps
CPU time 33.6 seconds
Started Aug 01 05:36:23 PM PDT 24
Finished Aug 01 05:36:57 PM PDT 24
Peak memory 203508 kb
Host smart-a95ae880-50e3-4480-9ef2-f21ba6eb2e24
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245463171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2245463171
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3321579530
Short name T640
Test name
Test status
Simulation time 5087297823 ps
CPU time 28.96 seconds
Started Aug 01 05:36:24 PM PDT 24
Finished Aug 01 05:36:53 PM PDT 24
Peak memory 203468 kb
Host smart-980b7ed5-8c85-4f6a-ad7b-2b6bd3e8786b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3321579530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3321579530
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3326021864
Short name T834
Test name
Test status
Simulation time 34902386 ps
CPU time 2.15 seconds
Started Aug 01 05:36:22 PM PDT 24
Finished Aug 01 05:36:24 PM PDT 24
Peak memory 203432 kb
Host smart-65134bd3-64de-4b3c-927f-2aca9557148c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326021864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3326021864
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.2804636482
Short name T77
Test name
Test status
Simulation time 3711619457 ps
CPU time 115.37 seconds
Started Aug 01 05:36:34 PM PDT 24
Finished Aug 01 05:38:30 PM PDT 24
Peak memory 208360 kb
Host smart-1e66e6ba-343c-429a-838d-f21dffbdf393
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2804636482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2804636482
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.485329180
Short name T559
Test name
Test status
Simulation time 1327555121 ps
CPU time 163.4 seconds
Started Aug 01 05:36:34 PM PDT 24
Finished Aug 01 05:39:17 PM PDT 24
Peak memory 205612 kb
Host smart-e4c83375-ade8-4e46-ab8f-6217ed9a3cd2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=485329180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.485329180
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.877092197
Short name T488
Test name
Test status
Simulation time 90032787 ps
CPU time 32.83 seconds
Started Aug 01 05:36:30 PM PDT 24
Finished Aug 01 05:37:03 PM PDT 24
Peak memory 205992 kb
Host smart-376ac25a-4e7f-4cd2-9e61-2e877cbcdca0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=877092197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_
reset.877092197
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1137943808
Short name T681
Test name
Test status
Simulation time 321694951 ps
CPU time 75.9 seconds
Started Aug 01 05:36:32 PM PDT 24
Finished Aug 01 05:37:48 PM PDT 24
Peak memory 208660 kb
Host smart-bfacb2c3-2110-4b4d-9bae-cb47afd6a109
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1137943808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res
et_error.1137943808
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.242692310
Short name T675
Test name
Test status
Simulation time 1300182583 ps
CPU time 9.16 seconds
Started Aug 01 05:36:31 PM PDT 24
Finished Aug 01 05:36:40 PM PDT 24
Peak memory 211660 kb
Host smart-f3dbf759-841f-4f86-9b17-48e388be9e33
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=242692310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.242692310
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.1759151393
Short name T716
Test name
Test status
Simulation time 3924255324 ps
CPU time 37 seconds
Started Aug 01 05:38:15 PM PDT 24
Finished Aug 01 05:38:52 PM PDT 24
Peak memory 211728 kb
Host smart-ce798858-19c8-4676-94d2-ab897a126436
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1759151393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1759151393
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.1860226611
Short name T454
Test name
Test status
Simulation time 85511514819 ps
CPU time 603.52 seconds
Started Aug 01 05:38:13 PM PDT 24
Finished Aug 01 05:48:17 PM PDT 24
Peak memory 211764 kb
Host smart-f1bfae3e-7c4f-4af6-8bf6-85fccd6d844f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1860226611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl
ow_rsp.1860226611
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3808968179
Short name T318
Test name
Test status
Simulation time 404185583 ps
CPU time 11.01 seconds
Started Aug 01 05:38:14 PM PDT 24
Finished Aug 01 05:38:25 PM PDT 24
Peak memory 203508 kb
Host smart-79b3c827-76fc-4771-bbcf-6c01e0f605ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3808968179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3808968179
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.1398355733
Short name T682
Test name
Test status
Simulation time 780787197 ps
CPU time 15.68 seconds
Started Aug 01 05:38:12 PM PDT 24
Finished Aug 01 05:38:28 PM PDT 24
Peak memory 203488 kb
Host smart-1c169758-fdaf-43f3-853d-d8d698f52d35
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1398355733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1398355733
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.378987310
Short name T82
Test name
Test status
Simulation time 2384467498 ps
CPU time 42.82 seconds
Started Aug 01 05:38:12 PM PDT 24
Finished Aug 01 05:38:55 PM PDT 24
Peak memory 211700 kb
Host smart-ced4185e-5a68-4331-99b6-a88fcd177702
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=378987310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.378987310
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.694981928
Short name T69
Test name
Test status
Simulation time 105383352540 ps
CPU time 233.85 seconds
Started Aug 01 05:38:10 PM PDT 24
Finished Aug 01 05:42:04 PM PDT 24
Peak memory 211672 kb
Host smart-4bf9328e-eaf7-42e5-a9ed-5b0cd63e60cd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=694981928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.694981928
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3246511257
Short name T680
Test name
Test status
Simulation time 123831830433 ps
CPU time 232.15 seconds
Started Aug 01 05:38:11 PM PDT 24
Finished Aug 01 05:42:04 PM PDT 24
Peak memory 211636 kb
Host smart-a1fff43f-20c1-411e-8cc5-c5135698507e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3246511257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3246511257
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.2797159037
Short name T362
Test name
Test status
Simulation time 14201691 ps
CPU time 2.08 seconds
Started Aug 01 05:38:11 PM PDT 24
Finished Aug 01 05:38:14 PM PDT 24
Peak memory 203488 kb
Host smart-0d60e310-d3d3-40ba-bca0-acfe1fe645f7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797159037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.2797159037
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.3388894851
Short name T106
Test name
Test status
Simulation time 297419246 ps
CPU time 10.77 seconds
Started Aug 01 05:38:12 PM PDT 24
Finished Aug 01 05:38:23 PM PDT 24
Peak memory 204060 kb
Host smart-eabd3b3e-1cdf-4527-81a5-ce87a73b0b78
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3388894851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3388894851
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.1255275450
Short name T495
Test name
Test status
Simulation time 33451156 ps
CPU time 2.52 seconds
Started Aug 01 05:38:13 PM PDT 24
Finished Aug 01 05:38:16 PM PDT 24
Peak memory 203464 kb
Host smart-4edc7d99-7a3e-44c8-8166-6e71017b316d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1255275450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1255275450
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.2824101891
Short name T580
Test name
Test status
Simulation time 10105575157 ps
CPU time 30.25 seconds
Started Aug 01 05:38:13 PM PDT 24
Finished Aug 01 05:38:43 PM PDT 24
Peak memory 203528 kb
Host smart-08fdc4d8-09a2-4c5e-8276-76f7bd06501b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824101891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2824101891
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.1201702413
Short name T298
Test name
Test status
Simulation time 20026041658 ps
CPU time 47.68 seconds
Started Aug 01 05:38:11 PM PDT 24
Finished Aug 01 05:38:59 PM PDT 24
Peak memory 203444 kb
Host smart-af5f181c-2e6e-4b97-9b1d-6a61e5614a13
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1201702413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1201702413
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.530139447
Short name T647
Test name
Test status
Simulation time 120137407 ps
CPU time 2 seconds
Started Aug 01 05:38:13 PM PDT 24
Finished Aug 01 05:38:15 PM PDT 24
Peak memory 203468 kb
Host smart-47bdeb50-ee67-4aed-8c7e-09eb6170daab
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530139447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.530139447
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all.328797329
Short name T626
Test name
Test status
Simulation time 826897003 ps
CPU time 28.94 seconds
Started Aug 01 05:38:13 PM PDT 24
Finished Aug 01 05:38:42 PM PDT 24
Peak memory 205084 kb
Host smart-41b7327b-636d-4ae4-a9cd-35d828bc8d1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=328797329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.328797329
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3658245034
Short name T527
Test name
Test status
Simulation time 12876852596 ps
CPU time 177.66 seconds
Started Aug 01 05:38:13 PM PDT 24
Finished Aug 01 05:41:11 PM PDT 24
Peak memory 208652 kb
Host smart-e3a46092-fb08-4d46-ad0c-616b52f566f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3658245034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3658245034
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.178756533
Short name T40
Test name
Test status
Simulation time 2916824577 ps
CPU time 364.47 seconds
Started Aug 01 05:38:12 PM PDT 24
Finished Aug 01 05:44:17 PM PDT 24
Peak memory 212736 kb
Host smart-5898968c-84bc-4f7a-a2c1-19285d6adbb5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=178756533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand
_reset.178756533
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.3025770396
Short name T747
Test name
Test status
Simulation time 694474971 ps
CPU time 175.05 seconds
Started Aug 01 05:38:13 PM PDT 24
Finished Aug 01 05:41:09 PM PDT 24
Peak memory 211636 kb
Host smart-b5008844-6cf1-47b0-8e69-8e6a6d5ae376
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3025770396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re
set_error.3025770396
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.1435077104
Short name T881
Test name
Test status
Simulation time 774964863 ps
CPU time 32.38 seconds
Started Aug 01 05:38:09 PM PDT 24
Finished Aug 01 05:38:42 PM PDT 24
Peak memory 211636 kb
Host smart-8cdf8c26-529c-4f9e-9b53-0fee04b1a477
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1435077104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1435077104
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.2711685474
Short name T125
Test name
Test status
Simulation time 1946653925 ps
CPU time 68.73 seconds
Started Aug 01 05:38:12 PM PDT 24
Finished Aug 01 05:39:21 PM PDT 24
Peak memory 211740 kb
Host smart-2835fbc4-895d-49a4-96a8-1c545d2b5223
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2711685474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2711685474
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1782762652
Short name T327
Test name
Test status
Simulation time 4030261361 ps
CPU time 27.56 seconds
Started Aug 01 05:38:12 PM PDT 24
Finished Aug 01 05:38:40 PM PDT 24
Peak memory 203768 kb
Host smart-3ccf93d2-1b6c-4ebb-830f-0895ad8b33dd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1782762652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl
ow_rsp.1782762652
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.528007631
Short name T397
Test name
Test status
Simulation time 44204964 ps
CPU time 2.18 seconds
Started Aug 01 05:38:11 PM PDT 24
Finished Aug 01 05:38:13 PM PDT 24
Peak memory 203456 kb
Host smart-33a3db5e-8823-4433-a58f-774b482546b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=528007631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.528007631
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.2720164279
Short name T375
Test name
Test status
Simulation time 826950861 ps
CPU time 22.53 seconds
Started Aug 01 05:38:16 PM PDT 24
Finished Aug 01 05:38:39 PM PDT 24
Peak memory 203580 kb
Host smart-2f8243f1-55f5-4279-b5bb-20f68bcaf305
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2720164279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2720164279
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.502399465
Short name T323
Test name
Test status
Simulation time 89475759 ps
CPU time 4.35 seconds
Started Aug 01 05:38:14 PM PDT 24
Finished Aug 01 05:38:18 PM PDT 24
Peak memory 211664 kb
Host smart-4c96a009-e1ab-454b-aea7-fd3e958c499f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=502399465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.502399465
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.1480363527
Short name T614
Test name
Test status
Simulation time 12913455138 ps
CPU time 27.49 seconds
Started Aug 01 05:38:12 PM PDT 24
Finished Aug 01 05:38:40 PM PDT 24
Peak memory 204592 kb
Host smart-9d471e38-ff2c-4d87-a51f-96668b304458
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480363527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1480363527
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.2945726926
Short name T188
Test name
Test status
Simulation time 26022509367 ps
CPU time 168.74 seconds
Started Aug 01 05:38:14 PM PDT 24
Finished Aug 01 05:41:03 PM PDT 24
Peak memory 211696 kb
Host smart-c2ddae28-7217-41fa-9415-f61127420639
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2945726926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2945726926
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.3920016817
Short name T149
Test name
Test status
Simulation time 735884392 ps
CPU time 24.2 seconds
Started Aug 01 05:38:13 PM PDT 24
Finished Aug 01 05:38:38 PM PDT 24
Peak memory 211552 kb
Host smart-989625a0-a0d0-4116-84cb-da7893ff3e56
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920016817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3920016817
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.222576519
Short name T401
Test name
Test status
Simulation time 213833914 ps
CPU time 16.36 seconds
Started Aug 01 05:38:13 PM PDT 24
Finished Aug 01 05:38:29 PM PDT 24
Peak memory 203516 kb
Host smart-a6fbd1ac-be84-4fb7-942e-682dd7842e06
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=222576519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.222576519
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.3555538314
Short name T450
Test name
Test status
Simulation time 305663273 ps
CPU time 3.58 seconds
Started Aug 01 05:38:15 PM PDT 24
Finished Aug 01 05:38:19 PM PDT 24
Peak memory 203384 kb
Host smart-a8e07460-0eb0-4206-b332-d5120e975266
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3555538314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3555538314
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.131464326
Short name T749
Test name
Test status
Simulation time 6913588314 ps
CPU time 33.11 seconds
Started Aug 01 05:38:14 PM PDT 24
Finished Aug 01 05:38:47 PM PDT 24
Peak memory 202588 kb
Host smart-21baa387-d1a7-47cc-a94f-381bd5659c79
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=131464326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.131464326
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.3873226269
Short name T655
Test name
Test status
Simulation time 8367573311 ps
CPU time 30.76 seconds
Started Aug 01 05:38:12 PM PDT 24
Finished Aug 01 05:38:43 PM PDT 24
Peak memory 203512 kb
Host smart-48625467-b9ea-4ec1-bde5-ade41d288103
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3873226269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3873226269
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1648876122
Short name T251
Test name
Test status
Simulation time 30768921 ps
CPU time 2.31 seconds
Started Aug 01 05:38:12 PM PDT 24
Finished Aug 01 05:38:14 PM PDT 24
Peak memory 203476 kb
Host smart-b9dac3cd-472b-4e1a-bf45-609e49911df3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648876122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1648876122
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3339116651
Short name T245
Test name
Test status
Simulation time 5726074541 ps
CPU time 98.67 seconds
Started Aug 01 05:38:13 PM PDT 24
Finished Aug 01 05:39:52 PM PDT 24
Peak memory 207656 kb
Host smart-e6342d86-ffd5-4414-9c36-8f6782b8443b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3339116651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3339116651
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.535442125
Short name T248
Test name
Test status
Simulation time 1501430851 ps
CPU time 231.82 seconds
Started Aug 01 05:38:15 PM PDT 24
Finished Aug 01 05:42:07 PM PDT 24
Peak memory 211564 kb
Host smart-fc62ea9b-50c0-4439-bb9d-c8c715a27f55
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=535442125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand
_reset.535442125
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.312080127
Short name T737
Test name
Test status
Simulation time 1789554410 ps
CPU time 435.35 seconds
Started Aug 01 05:38:12 PM PDT 24
Finished Aug 01 05:45:27 PM PDT 24
Peak memory 219768 kb
Host smart-d0f92492-9a7a-4f8c-93cd-00d52eced89d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=312080127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_res
et_error.312080127
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1987449012
Short name T8
Test name
Test status
Simulation time 444071327 ps
CPU time 15.13 seconds
Started Aug 01 05:38:13 PM PDT 24
Finished Aug 01 05:38:28 PM PDT 24
Peak memory 211636 kb
Host smart-5064eeea-17cf-41c4-ba4b-8cb09a78b617
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1987449012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1987449012
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.1847340659
Short name T690
Test name
Test status
Simulation time 1026708255 ps
CPU time 35.75 seconds
Started Aug 01 05:38:13 PM PDT 24
Finished Aug 01 05:38:49 PM PDT 24
Peak memory 211588 kb
Host smart-0dc429c8-ffa2-413a-863f-82fd06b3217a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1847340659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.1847340659
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.755583029
Short name T555
Test name
Test status
Simulation time 48536508963 ps
CPU time 188.67 seconds
Started Aug 01 05:38:14 PM PDT 24
Finished Aug 01 05:41:23 PM PDT 24
Peak memory 211040 kb
Host smart-80475640-d1cb-4944-bc60-1f1d02de65f7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=755583029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slo
w_rsp.755583029
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3064631439
Short name T296
Test name
Test status
Simulation time 491609780 ps
CPU time 18.85 seconds
Started Aug 01 05:38:15 PM PDT 24
Finished Aug 01 05:38:34 PM PDT 24
Peak memory 203368 kb
Host smart-97590524-9c07-4c42-a98d-9a6888823136
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3064631439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3064631439
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.1059211677
Short name T823
Test name
Test status
Simulation time 53761020 ps
CPU time 6.39 seconds
Started Aug 01 05:38:14 PM PDT 24
Finished Aug 01 05:38:21 PM PDT 24
Peak memory 203480 kb
Host smart-2a0b7626-3bd7-442e-b7f2-66be9afba85e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1059211677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1059211677
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.2120256598
Short name T353
Test name
Test status
Simulation time 1885192136 ps
CPU time 15.52 seconds
Started Aug 01 05:38:14 PM PDT 24
Finished Aug 01 05:38:30 PM PDT 24
Peak memory 211640 kb
Host smart-dd5e04e0-b5fe-4585-be23-603bdf7ee56d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2120256598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.2120256598
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.2648121464
Short name T264
Test name
Test status
Simulation time 228755995385 ps
CPU time 350.9 seconds
Started Aug 01 05:38:13 PM PDT 24
Finished Aug 01 05:44:04 PM PDT 24
Peak memory 204664 kb
Host smart-6e65197f-d2e6-4434-a9ce-fe5874daa031
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648121464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2648121464
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3502101080
Short name T44
Test name
Test status
Simulation time 16835621364 ps
CPU time 95.37 seconds
Started Aug 01 05:38:14 PM PDT 24
Finished Aug 01 05:39:49 PM PDT 24
Peak memory 211712 kb
Host smart-2c7bb1ba-38d7-450e-9ba3-08a9e54cfb7b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3502101080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3502101080
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1050259385
Short name T265
Test name
Test status
Simulation time 214678308 ps
CPU time 23.37 seconds
Started Aug 01 05:38:12 PM PDT 24
Finished Aug 01 05:38:35 PM PDT 24
Peak memory 204808 kb
Host smart-d802d39a-c664-43ba-9f29-6e1a9292333c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050259385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1050259385
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.3840427028
Short name T523
Test name
Test status
Simulation time 312744036 ps
CPU time 19.59 seconds
Started Aug 01 05:38:14 PM PDT 24
Finished Aug 01 05:38:33 PM PDT 24
Peak memory 204196 kb
Host smart-293f652c-bc5a-4b44-97ff-911b10755a8d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3840427028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3840427028
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.833818636
Short name T579
Test name
Test status
Simulation time 57982006 ps
CPU time 2.49 seconds
Started Aug 01 05:38:13 PM PDT 24
Finished Aug 01 05:38:16 PM PDT 24
Peak memory 203488 kb
Host smart-c863bc21-e884-460b-928a-53ba2ba52f01
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=833818636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.833818636
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.2084487428
Short name T407
Test name
Test status
Simulation time 11898638650 ps
CPU time 36.55 seconds
Started Aug 01 05:38:15 PM PDT 24
Finished Aug 01 05:38:52 PM PDT 24
Peak memory 203556 kb
Host smart-f7544361-4c04-4105-b63a-60fe19c421e0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084487428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2084487428
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.1781829654
Short name T739
Test name
Test status
Simulation time 6786828663 ps
CPU time 32.42 seconds
Started Aug 01 05:38:13 PM PDT 24
Finished Aug 01 05:38:46 PM PDT 24
Peak memory 203472 kb
Host smart-2ca45f96-eb7a-4511-925f-94904effd2fe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1781829654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1781829654
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2425343681
Short name T87
Test name
Test status
Simulation time 46238821 ps
CPU time 2.33 seconds
Started Aug 01 05:38:12 PM PDT 24
Finished Aug 01 05:38:14 PM PDT 24
Peak memory 203488 kb
Host smart-20217be7-d17f-43f2-8c8c-d61b7a258a33
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425343681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2425343681
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.4143865319
Short name T206
Test name
Test status
Simulation time 1360980634 ps
CPU time 44.5 seconds
Started Aug 01 05:38:12 PM PDT 24
Finished Aug 01 05:38:57 PM PDT 24
Peak memory 205748 kb
Host smart-5fd33478-6c54-4e03-b639-431eda2c6393
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4143865319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.4143865319
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.2885976348
Short name T338
Test name
Test status
Simulation time 876692469 ps
CPU time 81.89 seconds
Started Aug 01 05:38:14 PM PDT 24
Finished Aug 01 05:39:36 PM PDT 24
Peak memory 211636 kb
Host smart-9d18a09f-59d5-4cb6-8aab-624d8809b10c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2885976348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2885976348
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3609694399
Short name T29
Test name
Test status
Simulation time 571951397 ps
CPU time 169.53 seconds
Started Aug 01 05:38:14 PM PDT 24
Finished Aug 01 05:41:04 PM PDT 24
Peak memory 208568 kb
Host smart-9650eb71-f5d5-4f57-8e61-0aac5e9182dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3609694399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran
d_reset.3609694399
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.1722300404
Short name T710
Test name
Test status
Simulation time 1562742613 ps
CPU time 321 seconds
Started Aug 01 05:38:17 PM PDT 24
Finished Aug 01 05:43:38 PM PDT 24
Peak memory 219888 kb
Host smart-389848a1-dee2-4adf-8521-a388daeff700
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1722300404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re
set_error.1722300404
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.3084742786
Short name T637
Test name
Test status
Simulation time 76152095 ps
CPU time 6.79 seconds
Started Aug 01 05:38:14 PM PDT 24
Finished Aug 01 05:38:21 PM PDT 24
Peak memory 211616 kb
Host smart-1196d1d9-bcbd-4736-a007-a48a491534ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3084742786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3084742786
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.3749733851
Short name T872
Test name
Test status
Simulation time 141642480 ps
CPU time 10.38 seconds
Started Aug 01 05:38:23 PM PDT 24
Finished Aug 01 05:38:34 PM PDT 24
Peak memory 204516 kb
Host smart-4e9118d4-af6a-4f41-a107-1db2b28abe23
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3749733851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3749733851
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2549720894
Short name T178
Test name
Test status
Simulation time 70411962521 ps
CPU time 221 seconds
Started Aug 01 05:38:23 PM PDT 24
Finished Aug 01 05:42:04 PM PDT 24
Peak memory 211708 kb
Host smart-a300426e-2c18-41fc-a46f-0e5c34f1baf9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2549720894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl
ow_rsp.2549720894
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.2069251008
Short name T633
Test name
Test status
Simulation time 6440704623 ps
CPU time 28.06 seconds
Started Aug 01 05:38:21 PM PDT 24
Finished Aug 01 05:38:49 PM PDT 24
Peak memory 211568 kb
Host smart-ea23df5a-e6cd-48f6-ba83-1f9c8a175e4e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2069251008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2069251008
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.756830460
Short name T879
Test name
Test status
Simulation time 162194933 ps
CPU time 5.21 seconds
Started Aug 01 05:38:18 PM PDT 24
Finished Aug 01 05:38:23 PM PDT 24
Peak memory 203384 kb
Host smart-e289de64-7795-4f04-84b3-59b4755d4a30
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=756830460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.756830460
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.1313514032
Short name T506
Test name
Test status
Simulation time 334439524 ps
CPU time 15.65 seconds
Started Aug 01 05:38:23 PM PDT 24
Finished Aug 01 05:38:39 PM PDT 24
Peak memory 211652 kb
Host smart-dd2639f9-f7fe-4322-a016-52350191f67b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1313514032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.1313514032
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.2153667147
Short name T123
Test name
Test status
Simulation time 13995415671 ps
CPU time 47.5 seconds
Started Aug 01 05:38:17 PM PDT 24
Finished Aug 01 05:39:04 PM PDT 24
Peak memory 211708 kb
Host smart-d24f9b81-2d3a-41d4-b307-a7fddea423f0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153667147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2153667147
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3405564106
Short name T90
Test name
Test status
Simulation time 59917160582 ps
CPU time 215.59 seconds
Started Aug 01 05:38:23 PM PDT 24
Finished Aug 01 05:41:59 PM PDT 24
Peak memory 211708 kb
Host smart-accd7055-916c-44eb-87e9-fb05d6c2ebb5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3405564106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3405564106
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2686405816
Short name T811
Test name
Test status
Simulation time 230862805 ps
CPU time 7.96 seconds
Started Aug 01 05:38:23 PM PDT 24
Finished Aug 01 05:38:31 PM PDT 24
Peak memory 204572 kb
Host smart-ef2d7c49-def7-449d-a866-e65ec212006a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686405816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2686405816
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.3449612011
Short name T230
Test name
Test status
Simulation time 107538492 ps
CPU time 8.95 seconds
Started Aug 01 05:38:19 PM PDT 24
Finished Aug 01 05:38:28 PM PDT 24
Peak memory 203524 kb
Host smart-4037704b-4083-48bc-9b64-416486616158
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3449612011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3449612011
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.2232431416
Short name T384
Test name
Test status
Simulation time 139688517 ps
CPU time 3.2 seconds
Started Aug 01 05:38:11 PM PDT 24
Finished Aug 01 05:38:14 PM PDT 24
Peak memory 203420 kb
Host smart-04a245d6-0e72-4c7c-bbc9-95e81cdea805
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2232431416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2232431416
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.4014878460
Short name T55
Test name
Test status
Simulation time 5465703471 ps
CPU time 26.6 seconds
Started Aug 01 05:38:16 PM PDT 24
Finished Aug 01 05:38:43 PM PDT 24
Peak memory 203556 kb
Host smart-57a35e4a-7b40-460f-bdcc-b20987c02cec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014878460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.4014878460
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1287776466
Short name T821
Test name
Test status
Simulation time 3460057267 ps
CPU time 23.39 seconds
Started Aug 01 05:38:16 PM PDT 24
Finished Aug 01 05:38:40 PM PDT 24
Peak memory 203544 kb
Host smart-56e1dc7d-a1a1-4b51-96b4-643126c36dab
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1287776466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1287776466
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.829823582
Short name T180
Test name
Test status
Simulation time 28982955 ps
CPU time 2.07 seconds
Started Aug 01 05:38:14 PM PDT 24
Finished Aug 01 05:38:16 PM PDT 24
Peak memory 203452 kb
Host smart-d44544a9-06d3-45be-b053-b6099b4d8224
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829823582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.829823582
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.3236603892
Short name T453
Test name
Test status
Simulation time 1307541180 ps
CPU time 140.34 seconds
Started Aug 01 05:38:19 PM PDT 24
Finished Aug 01 05:40:39 PM PDT 24
Peak memory 207084 kb
Host smart-a6b5881b-261e-437f-8d6f-63b1c788f3ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3236603892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3236603892
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3490662781
Short name T308
Test name
Test status
Simulation time 3333741821 ps
CPU time 90.4 seconds
Started Aug 01 05:38:23 PM PDT 24
Finished Aug 01 05:39:54 PM PDT 24
Peak memory 205972 kb
Host smart-a1e56979-f907-4c50-be17-4465d3444dbc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3490662781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3490662781
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1834744088
Short name T598
Test name
Test status
Simulation time 3095671250 ps
CPU time 115.18 seconds
Started Aug 01 05:38:21 PM PDT 24
Finished Aug 01 05:40:16 PM PDT 24
Peak memory 206644 kb
Host smart-3eec3807-af07-4a51-a838-f19ce59a27e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1834744088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran
d_reset.1834744088
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2978324115
Short name T662
Test name
Test status
Simulation time 1432112579 ps
CPU time 166.76 seconds
Started Aug 01 05:38:23 PM PDT 24
Finished Aug 01 05:41:10 PM PDT 24
Peak memory 211424 kb
Host smart-f2c4b2db-a2e8-46d2-96e3-931ca9b788c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2978324115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re
set_error.2978324115
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.380218556
Short name T444
Test name
Test status
Simulation time 596027620 ps
CPU time 10.83 seconds
Started Aug 01 05:38:23 PM PDT 24
Finished Aug 01 05:38:34 PM PDT 24
Peak memory 211636 kb
Host smart-6a1acfef-933d-42cf-bb7a-8f127763b613
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=380218556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.380218556
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.3406307199
Short name T366
Test name
Test status
Simulation time 279834457 ps
CPU time 35.44 seconds
Started Aug 01 05:38:19 PM PDT 24
Finished Aug 01 05:38:55 PM PDT 24
Peak memory 211744 kb
Host smart-0f26100e-73fa-450b-babc-b122d03a7842
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3406307199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.3406307199
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.3771330509
Short name T519
Test name
Test status
Simulation time 728994524 ps
CPU time 26.91 seconds
Started Aug 01 05:38:22 PM PDT 24
Finished Aug 01 05:38:49 PM PDT 24
Peak memory 203508 kb
Host smart-01a39f9f-080c-460a-a96e-feecb648cd2b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3771330509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.3771330509
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.1220468320
Short name T741
Test name
Test status
Simulation time 992794702 ps
CPU time 14.01 seconds
Started Aug 01 05:38:33 PM PDT 24
Finished Aug 01 05:38:47 PM PDT 24
Peak memory 203404 kb
Host smart-485e3f72-fc83-41db-b8aa-0a03ae2cba49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1220468320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1220468320
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.480983169
Short name T594
Test name
Test status
Simulation time 1295929707 ps
CPU time 35.21 seconds
Started Aug 01 05:38:21 PM PDT 24
Finished Aug 01 05:38:56 PM PDT 24
Peak memory 211504 kb
Host smart-2847d454-6782-4ff7-b0e6-9d7d0be9ad87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=480983169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.480983169
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.3512103026
Short name T109
Test name
Test status
Simulation time 42781800530 ps
CPU time 195.86 seconds
Started Aug 01 05:38:24 PM PDT 24
Finished Aug 01 05:41:40 PM PDT 24
Peak memory 211704 kb
Host smart-c27ae4ac-a17a-4aab-a6a7-ce0a9fc80f99
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512103026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3512103026
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.795590709
Short name T417
Test name
Test status
Simulation time 51552636239 ps
CPU time 235.7 seconds
Started Aug 01 05:38:24 PM PDT 24
Finished Aug 01 05:42:20 PM PDT 24
Peak memory 211660 kb
Host smart-6a5d110f-9b21-4629-b034-da910706c94e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=795590709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.795590709
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.1057550010
Short name T595
Test name
Test status
Simulation time 108942666 ps
CPU time 13.1 seconds
Started Aug 01 05:38:28 PM PDT 24
Finished Aug 01 05:38:41 PM PDT 24
Peak memory 211500 kb
Host smart-0d0de992-c00b-435d-b6d3-9f595ff94e75
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057550010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.1057550010
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.3243742091
Short name T470
Test name
Test status
Simulation time 1195927230 ps
CPU time 19 seconds
Started Aug 01 05:38:29 PM PDT 24
Finished Aug 01 05:38:48 PM PDT 24
Peak memory 203564 kb
Host smart-a6c7738c-a775-4f8d-b0e7-1e122b02207b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3243742091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3243742091
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.3935814596
Short name T271
Test name
Test status
Simulation time 28667872 ps
CPU time 2.04 seconds
Started Aug 01 05:38:30 PM PDT 24
Finished Aug 01 05:38:32 PM PDT 24
Peak memory 203388 kb
Host smart-04552ad1-beb0-49c3-a97c-18c4a4a5dece
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3935814596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3935814596
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.2996410481
Short name T734
Test name
Test status
Simulation time 6294491657 ps
CPU time 28.88 seconds
Started Aug 01 05:38:32 PM PDT 24
Finished Aug 01 05:39:01 PM PDT 24
Peak memory 203452 kb
Host smart-c6bde924-6f2c-4e16-bf02-170076e62c61
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996410481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2996410481
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.2670814246
Short name T341
Test name
Test status
Simulation time 11803667160 ps
CPU time 33.9 seconds
Started Aug 01 05:38:28 PM PDT 24
Finished Aug 01 05:39:02 PM PDT 24
Peak memory 203500 kb
Host smart-954d9b16-e0dc-4889-af07-4a6847ef799f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2670814246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2670814246
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.958248388
Short name T411
Test name
Test status
Simulation time 32474990 ps
CPU time 2.11 seconds
Started Aug 01 05:38:21 PM PDT 24
Finished Aug 01 05:38:23 PM PDT 24
Peak memory 203476 kb
Host smart-f4739aa7-5022-456e-9f34-c3fdec89a813
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958248388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.958248388
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.1632168570
Short name T261
Test name
Test status
Simulation time 803941829 ps
CPU time 47.43 seconds
Started Aug 01 05:38:25 PM PDT 24
Finished Aug 01 05:39:13 PM PDT 24
Peak memory 207476 kb
Host smart-857f3bae-6f49-4ad9-8097-68061d8e90bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1632168570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1632168570
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1341553846
Short name T182
Test name
Test status
Simulation time 580189942 ps
CPU time 7.86 seconds
Started Aug 01 05:38:23 PM PDT 24
Finished Aug 01 05:38:31 PM PDT 24
Peak memory 203484 kb
Host smart-40d74b27-6ef6-46db-b1a7-919dc011c272
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1341553846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1341553846
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3265051241
Short name T84
Test name
Test status
Simulation time 1058729339 ps
CPU time 95.67 seconds
Started Aug 01 05:38:23 PM PDT 24
Finished Aug 01 05:39:59 PM PDT 24
Peak memory 208180 kb
Host smart-fa661858-f3a6-41fe-9ddf-eb05776d7d4a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3265051241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran
d_reset.3265051241
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.2040159417
Short name T508
Test name
Test status
Simulation time 658036841 ps
CPU time 138.01 seconds
Started Aug 01 05:38:28 PM PDT 24
Finished Aug 01 05:40:47 PM PDT 24
Peak memory 210476 kb
Host smart-3042a46d-a51a-4c14-9bc4-9c8cfe74b5b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2040159417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re
set_error.2040159417
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.3075592045
Short name T289
Test name
Test status
Simulation time 1094177072 ps
CPU time 25.82 seconds
Started Aug 01 05:38:20 PM PDT 24
Finished Aug 01 05:38:46 PM PDT 24
Peak memory 211660 kb
Host smart-8f93f8dc-df06-4ed1-b861-9b872f5cd2d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3075592045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3075592045
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.4024242340
Short name T79
Test name
Test status
Simulation time 1533013454 ps
CPU time 34.53 seconds
Started Aug 01 05:38:25 PM PDT 24
Finished Aug 01 05:39:00 PM PDT 24
Peak memory 211648 kb
Host smart-3ee94e1b-193a-4609-ab11-90a30fca4f6b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4024242340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.4024242340
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.774878037
Short name T538
Test name
Test status
Simulation time 102266516171 ps
CPU time 321.52 seconds
Started Aug 01 05:38:28 PM PDT 24
Finished Aug 01 05:43:49 PM PDT 24
Peak memory 206048 kb
Host smart-8baa50f4-e968-484a-ad46-8e91ae6d1d1e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=774878037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slo
w_rsp.774878037
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.3427060686
Short name T607
Test name
Test status
Simulation time 1481876660 ps
CPU time 12.95 seconds
Started Aug 01 05:38:28 PM PDT 24
Finished Aug 01 05:38:41 PM PDT 24
Peak memory 203512 kb
Host smart-57943a4f-2d48-49b1-bf4c-2c7ea67ea31b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3427060686 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.3427060686
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.1903119292
Short name T348
Test name
Test status
Simulation time 47860977 ps
CPU time 4.28 seconds
Started Aug 01 05:38:21 PM PDT 24
Finished Aug 01 05:38:26 PM PDT 24
Peak memory 203480 kb
Host smart-c7ce6113-56fd-4806-97d0-ac9709cb416b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1903119292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1903119292
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.572514598
Short name T389
Test name
Test status
Simulation time 554273186 ps
CPU time 10.38 seconds
Started Aug 01 05:38:23 PM PDT 24
Finished Aug 01 05:38:33 PM PDT 24
Peak memory 204616 kb
Host smart-66199998-9fbc-4ca3-81e7-202f2a10b0c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=572514598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.572514598
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.1189996062
Short name T850
Test name
Test status
Simulation time 83143471691 ps
CPU time 121.9 seconds
Started Aug 01 05:38:26 PM PDT 24
Finished Aug 01 05:40:28 PM PDT 24
Peak memory 211704 kb
Host smart-7641f4f5-fff4-42e9-a2c0-8b2d7e8a11fe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189996062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1189996062
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2851982500
Short name T416
Test name
Test status
Simulation time 47973342821 ps
CPU time 144.61 seconds
Started Aug 01 05:38:35 PM PDT 24
Finished Aug 01 05:41:00 PM PDT 24
Peak memory 204616 kb
Host smart-d17fe35c-f13c-4dda-9ebb-f7543abf88c1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2851982500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2851982500
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.412883910
Short name T899
Test name
Test status
Simulation time 557378360 ps
CPU time 23.48 seconds
Started Aug 01 05:38:23 PM PDT 24
Finished Aug 01 05:38:46 PM PDT 24
Peak memory 204528 kb
Host smart-6a57a75b-b088-4749-bf13-1d80ba4504f9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412883910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.412883910
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.3821670897
Short name T585
Test name
Test status
Simulation time 49261704 ps
CPU time 4.63 seconds
Started Aug 01 05:38:26 PM PDT 24
Finished Aug 01 05:38:31 PM PDT 24
Peak memory 203472 kb
Host smart-5547c40b-0a9c-47e5-ad76-9db50890d5db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3821670897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3821670897
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.361359944
Short name T502
Test name
Test status
Simulation time 35380320 ps
CPU time 2.37 seconds
Started Aug 01 05:38:21 PM PDT 24
Finished Aug 01 05:38:23 PM PDT 24
Peak memory 203440 kb
Host smart-e15b4926-5e5e-42b8-90b9-2a2de36ef660
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=361359944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.361359944
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.2652233334
Short name T661
Test name
Test status
Simulation time 11324546028 ps
CPU time 35.85 seconds
Started Aug 01 05:38:22 PM PDT 24
Finished Aug 01 05:38:58 PM PDT 24
Peak memory 203600 kb
Host smart-7511cca6-781f-4a16-bff4-445bdb768793
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652233334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2652233334
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3173323239
Short name T790
Test name
Test status
Simulation time 6197442060 ps
CPU time 29.16 seconds
Started Aug 01 05:38:21 PM PDT 24
Finished Aug 01 05:38:50 PM PDT 24
Peak memory 203564 kb
Host smart-96f8011a-c1ab-4f5e-ad0b-643b179ad31d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3173323239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3173323239
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.656815784
Short name T283
Test name
Test status
Simulation time 34709055 ps
CPU time 2.11 seconds
Started Aug 01 05:38:28 PM PDT 24
Finished Aug 01 05:38:31 PM PDT 24
Peak memory 203476 kb
Host smart-604096e1-e279-426f-b318-dcd014b7fc8f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656815784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.656815784
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.514911307
Short name T72
Test name
Test status
Simulation time 317826853 ps
CPU time 7.87 seconds
Started Aug 01 05:38:24 PM PDT 24
Finished Aug 01 05:38:32 PM PDT 24
Peak memory 211640 kb
Host smart-093e134e-4ded-4e36-bfbe-132ff0a09606
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=514911307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.514911307
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.64413067
Short name T730
Test name
Test status
Simulation time 27349855857 ps
CPU time 229.73 seconds
Started Aug 01 05:38:29 PM PDT 24
Finished Aug 01 05:42:19 PM PDT 24
Peak memory 210256 kb
Host smart-15f6d430-99bb-4d2d-a252-ea1161f3f131
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=64413067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.64413067
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1537862563
Short name T240
Test name
Test status
Simulation time 654712279 ps
CPU time 289.49 seconds
Started Aug 01 05:38:20 PM PDT 24
Finished Aug 01 05:43:10 PM PDT 24
Peak memory 208312 kb
Host smart-a248b96f-28ce-4188-be22-2c341401ca99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1537862563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran
d_reset.1537862563
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.510201011
Short name T307
Test name
Test status
Simulation time 14839064350 ps
CPU time 430.72 seconds
Started Aug 01 05:38:23 PM PDT 24
Finished Aug 01 05:45:34 PM PDT 24
Peak memory 220072 kb
Host smart-412a1177-9a90-42b2-be84-51319a8fd125
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=510201011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_res
et_error.510201011
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.4082207062
Short name T33
Test name
Test status
Simulation time 836509914 ps
CPU time 28.52 seconds
Started Aug 01 05:38:23 PM PDT 24
Finished Aug 01 05:38:51 PM PDT 24
Peak memory 211600 kb
Host smart-88a8e04b-e5c4-4468-b0cb-2fe9f73d4465
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4082207062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.4082207062
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.3511889317
Short name T267
Test name
Test status
Simulation time 91191611 ps
CPU time 7.07 seconds
Started Aug 01 05:38:33 PM PDT 24
Finished Aug 01 05:38:40 PM PDT 24
Peak memory 204512 kb
Host smart-fa640f80-e1ba-4c40-852d-177f18a4617c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3511889317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.3511889317
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3915660950
Short name T705
Test name
Test status
Simulation time 26072090226 ps
CPU time 78.09 seconds
Started Aug 01 05:38:27 PM PDT 24
Finished Aug 01 05:39:46 PM PDT 24
Peak memory 211684 kb
Host smart-6c562041-987a-41a8-b9a7-e680a85f218e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3915660950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl
ow_rsp.3915660950
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.3558720171
Short name T314
Test name
Test status
Simulation time 414301607 ps
CPU time 10.4 seconds
Started Aug 01 05:38:29 PM PDT 24
Finished Aug 01 05:38:39 PM PDT 24
Peak memory 203352 kb
Host smart-23669d41-f8da-4d17-bf0e-8cbe8f22631b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3558720171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.3558720171
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.2092276228
Short name T762
Test name
Test status
Simulation time 559585142 ps
CPU time 17.27 seconds
Started Aug 01 05:38:27 PM PDT 24
Finished Aug 01 05:38:44 PM PDT 24
Peak memory 203348 kb
Host smart-357bd8e0-6900-459f-8202-f824812143f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2092276228 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2092276228
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.4235925545
Short name T701
Test name
Test status
Simulation time 519308117 ps
CPU time 19.62 seconds
Started Aug 01 05:38:34 PM PDT 24
Finished Aug 01 05:38:54 PM PDT 24
Peak memory 211560 kb
Host smart-564f9259-6fb8-429f-9320-7cb1e99845e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4235925545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.4235925545
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.3937504888
Short name T835
Test name
Test status
Simulation time 45659450483 ps
CPU time 223.09 seconds
Started Aug 01 05:38:22 PM PDT 24
Finished Aug 01 05:42:05 PM PDT 24
Peak memory 211652 kb
Host smart-0c13e5dd-0d75-4616-961a-0a3ff2e1ab54
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937504888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3937504888
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.3319177212
Short name T376
Test name
Test status
Simulation time 1804646602 ps
CPU time 15.67 seconds
Started Aug 01 05:38:29 PM PDT 24
Finished Aug 01 05:38:44 PM PDT 24
Peak memory 203928 kb
Host smart-36d8e66a-bb9b-4912-bd33-f2b319573095
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3319177212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3319177212
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.3378591918
Short name T542
Test name
Test status
Simulation time 163326948 ps
CPU time 17.28 seconds
Started Aug 01 05:38:25 PM PDT 24
Finished Aug 01 05:38:42 PM PDT 24
Peak memory 211564 kb
Host smart-9640adb2-10af-479c-b23e-5449dbfdddd5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378591918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.3378591918
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.1261011439
Short name T803
Test name
Test status
Simulation time 184672126 ps
CPU time 10.48 seconds
Started Aug 01 05:38:34 PM PDT 24
Finished Aug 01 05:38:45 PM PDT 24
Peak memory 204000 kb
Host smart-f0b8bb7b-7a7c-4829-809a-2d1fe9ba3d7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1261011439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.1261011439
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.1434942179
Short name T391
Test name
Test status
Simulation time 26158120 ps
CPU time 2.41 seconds
Started Aug 01 05:38:25 PM PDT 24
Finished Aug 01 05:38:27 PM PDT 24
Peak memory 203384 kb
Host smart-09a5019b-cddd-4203-bb4a-07f294d73594
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1434942179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1434942179
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.242606036
Short name T467
Test name
Test status
Simulation time 10115636389 ps
CPU time 27.92 seconds
Started Aug 01 05:38:26 PM PDT 24
Finished Aug 01 05:38:54 PM PDT 24
Peak memory 203460 kb
Host smart-efc811d2-ade2-4af8-a4e9-7aded3666150
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=242606036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.242606036
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.578929480
Short name T276
Test name
Test status
Simulation time 6740685003 ps
CPU time 26.56 seconds
Started Aug 01 05:38:24 PM PDT 24
Finished Aug 01 05:38:51 PM PDT 24
Peak memory 203548 kb
Host smart-5a567cfd-a4b8-4c88-849b-714871ef02bf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=578929480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.578929480
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.2385791396
Short name T215
Test name
Test status
Simulation time 26423957 ps
CPU time 2.15 seconds
Started Aug 01 05:38:29 PM PDT 24
Finished Aug 01 05:38:31 PM PDT 24
Peak memory 203376 kb
Host smart-425acbd0-2527-421a-8ccc-38d191f86a70
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385791396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.2385791396
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.2810900173
Short name T657
Test name
Test status
Simulation time 787036359 ps
CPU time 20.57 seconds
Started Aug 01 05:38:35 PM PDT 24
Finished Aug 01 05:38:55 PM PDT 24
Peak memory 205464 kb
Host smart-9905b72d-0853-4a97-b446-0c1ba4b790eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2810900173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2810900173
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.3486709547
Short name T15
Test name
Test status
Simulation time 7401573832 ps
CPU time 128.65 seconds
Started Aug 01 05:38:30 PM PDT 24
Finished Aug 01 05:40:39 PM PDT 24
Peak memory 208720 kb
Host smart-10697cb6-b326-4ed4-924a-6e1f778a6201
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3486709547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3486709547
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.4079337157
Short name T166
Test name
Test status
Simulation time 1975430734 ps
CPU time 311.11 seconds
Started Aug 01 05:38:30 PM PDT 24
Finished Aug 01 05:43:41 PM PDT 24
Peak memory 209296 kb
Host smart-d2def607-a51f-41d7-930f-5659c257189c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4079337157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran
d_reset.4079337157
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.1025094223
Short name T660
Test name
Test status
Simulation time 656892629 ps
CPU time 193.78 seconds
Started Aug 01 05:38:34 PM PDT 24
Finished Aug 01 05:41:48 PM PDT 24
Peak memory 211248 kb
Host smart-968d64ef-c8ae-43c8-ae63-5bba54b2a337
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1025094223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re
set_error.1025094223
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.2617890897
Short name T855
Test name
Test status
Simulation time 1833879886 ps
CPU time 16.72 seconds
Started Aug 01 05:38:29 PM PDT 24
Finished Aug 01 05:38:46 PM PDT 24
Peak memory 211568 kb
Host smart-d8ca60bf-2766-498c-a73d-1e3f88f9fb3d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2617890897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2617890897
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.3238764166
Short name T848
Test name
Test status
Simulation time 363323122 ps
CPU time 26.81 seconds
Started Aug 01 05:38:25 PM PDT 24
Finished Aug 01 05:38:52 PM PDT 24
Peak memory 211680 kb
Host smart-9c2c5a2b-f3cf-40ca-9baf-0783dcb0b6b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3238764166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.3238764166
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1283847174
Short name T98
Test name
Test status
Simulation time 123646520390 ps
CPU time 636.05 seconds
Started Aug 01 05:38:35 PM PDT 24
Finished Aug 01 05:49:11 PM PDT 24
Peak memory 211700 kb
Host smart-3dbb3a4e-3007-4557-9635-085220882bb9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1283847174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl
ow_rsp.1283847174
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.231577013
Short name T753
Test name
Test status
Simulation time 118894622 ps
CPU time 13.06 seconds
Started Aug 01 05:38:39 PM PDT 24
Finished Aug 01 05:38:53 PM PDT 24
Peak memory 203500 kb
Host smart-e3144d0d-1f23-42ee-b94c-b049525aa9ad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=231577013 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.231577013
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.2343761912
Short name T337
Test name
Test status
Simulation time 479033871 ps
CPU time 15.33 seconds
Started Aug 01 05:38:35 PM PDT 24
Finished Aug 01 05:38:50 PM PDT 24
Peak memory 203472 kb
Host smart-e682d1f4-1464-4d4e-a3c1-e3dcd47ecab7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2343761912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2343761912
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.1668126751
Short name T541
Test name
Test status
Simulation time 1074066067 ps
CPU time 29.28 seconds
Started Aug 01 05:38:34 PM PDT 24
Finished Aug 01 05:39:04 PM PDT 24
Peak memory 204508 kb
Host smart-d8263c5e-9c22-4b80-81d8-4da3e79767f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1668126751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1668126751
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.2414710115
Short name T300
Test name
Test status
Simulation time 41694145210 ps
CPU time 228.89 seconds
Started Aug 01 05:38:28 PM PDT 24
Finished Aug 01 05:42:17 PM PDT 24
Peak memory 211604 kb
Host smart-e2049938-d573-4661-ac4d-b2b8d366447c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414710115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2414710115
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.661509471
Short name T52
Test name
Test status
Simulation time 12068558818 ps
CPU time 93.62 seconds
Started Aug 01 05:38:22 PM PDT 24
Finished Aug 01 05:39:56 PM PDT 24
Peak memory 204800 kb
Host smart-28982632-af59-4e77-a479-0d5dfa044128
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=661509471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.661509471
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.499982699
Short name T895
Test name
Test status
Simulation time 62349961 ps
CPU time 7.43 seconds
Started Aug 01 05:38:28 PM PDT 24
Finished Aug 01 05:38:35 PM PDT 24
Peak memory 204548 kb
Host smart-d52cc7d2-0898-4ae3-8631-0c2b94e8abc7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499982699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.499982699
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.2518888095
Short name T498
Test name
Test status
Simulation time 48437051 ps
CPU time 2.09 seconds
Started Aug 01 05:38:34 PM PDT 24
Finished Aug 01 05:38:36 PM PDT 24
Peak memory 203548 kb
Host smart-16c30244-d57f-4552-ab46-34439d2165f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2518888095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2518888095
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.3959844628
Short name T611
Test name
Test status
Simulation time 144768543 ps
CPU time 3.18 seconds
Started Aug 01 05:38:28 PM PDT 24
Finished Aug 01 05:38:32 PM PDT 24
Peak memory 203340 kb
Host smart-35705cab-231d-4f53-9ee9-50888dd3bd17
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3959844628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3959844628
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2497824116
Short name T563
Test name
Test status
Simulation time 17920961283 ps
CPU time 37.17 seconds
Started Aug 01 05:38:24 PM PDT 24
Finished Aug 01 05:39:01 PM PDT 24
Peak memory 203540 kb
Host smart-28929430-67dc-4ddb-bca1-5b0c8510a69d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497824116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2497824116
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.2183897381
Short name T23
Test name
Test status
Simulation time 3109837218 ps
CPU time 26.08 seconds
Started Aug 01 05:38:23 PM PDT 24
Finished Aug 01 05:38:49 PM PDT 24
Peak memory 203532 kb
Host smart-34d3dc82-85d7-461a-8888-92bfa0f03f6f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2183897381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2183897381
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3393234821
Short name T641
Test name
Test status
Simulation time 104681441 ps
CPU time 2.64 seconds
Started Aug 01 05:38:23 PM PDT 24
Finished Aug 01 05:38:26 PM PDT 24
Peak memory 203448 kb
Host smart-81428d7e-0f5e-4593-84f6-1b0fbb947d9f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393234821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3393234821
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.796007795
Short name T463
Test name
Test status
Simulation time 2133417672 ps
CPU time 81.66 seconds
Started Aug 01 05:38:33 PM PDT 24
Finished Aug 01 05:39:55 PM PDT 24
Peak memory 205792 kb
Host smart-6624a150-22fd-49c1-8bf3-aa5aaa03352c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=796007795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.796007795
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2435838030
Short name T356
Test name
Test status
Simulation time 72727143 ps
CPU time 6.48 seconds
Started Aug 01 05:38:34 PM PDT 24
Finished Aug 01 05:38:40 PM PDT 24
Peak memory 203448 kb
Host smart-f654bb82-21ad-45b3-a8eb-328abec93c67
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2435838030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2435838030
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.1604431499
Short name T119
Test name
Test status
Simulation time 4179989351 ps
CPU time 257.28 seconds
Started Aug 01 05:38:33 PM PDT 24
Finished Aug 01 05:42:51 PM PDT 24
Peak memory 211036 kb
Host smart-1f5638ba-353a-42db-9e8c-284934ee0943
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1604431499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran
d_reset.1604431499
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3661211593
Short name T352
Test name
Test status
Simulation time 3124448546 ps
CPU time 248.16 seconds
Started Aug 01 05:38:32 PM PDT 24
Finished Aug 01 05:42:40 PM PDT 24
Peak memory 210056 kb
Host smart-9d65b1d4-5149-454d-ba0e-56acacf44283
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3661211593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re
set_error.3661211593
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.3571845487
Short name T208
Test name
Test status
Simulation time 1048984374 ps
CPU time 17.67 seconds
Started Aug 01 05:38:38 PM PDT 24
Finished Aug 01 05:38:56 PM PDT 24
Peak memory 211652 kb
Host smart-84164ea0-312b-4692-bf9e-7a3b4569ea56
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3571845487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3571845487
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.4140756124
Short name T270
Test name
Test status
Simulation time 371118577 ps
CPU time 39.7 seconds
Started Aug 01 05:38:34 PM PDT 24
Finished Aug 01 05:39:14 PM PDT 24
Peak memory 205176 kb
Host smart-5d657d53-24e2-4b98-b271-df6f1ca16d2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4140756124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.4140756124
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1571250079
Short name T875
Test name
Test status
Simulation time 48368612770 ps
CPU time 431.02 seconds
Started Aug 01 05:38:34 PM PDT 24
Finished Aug 01 05:45:45 PM PDT 24
Peak memory 211708 kb
Host smart-6554a91b-a470-4b6a-97d5-4871c035651e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1571250079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl
ow_rsp.1571250079
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.853890368
Short name T562
Test name
Test status
Simulation time 383121044 ps
CPU time 14.6 seconds
Started Aug 01 05:38:34 PM PDT 24
Finished Aug 01 05:38:49 PM PDT 24
Peak memory 203368 kb
Host smart-8ef1c0a9-bb1b-4b5c-bbd1-8955db17271f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=853890368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.853890368
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.3701051877
Short name T430
Test name
Test status
Simulation time 171681145 ps
CPU time 9.39 seconds
Started Aug 01 05:38:38 PM PDT 24
Finished Aug 01 05:38:47 PM PDT 24
Peak memory 203476 kb
Host smart-cd015869-0ae9-4c12-b967-34b9b810e775
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3701051877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3701051877
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.2726776379
Short name T793
Test name
Test status
Simulation time 3235155635 ps
CPU time 21.81 seconds
Started Aug 01 05:38:34 PM PDT 24
Finished Aug 01 05:38:56 PM PDT 24
Peak memory 211800 kb
Host smart-b756a525-18b1-4b7e-8e4f-1ca4552f11f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2726776379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.2726776379
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.946559734
Short name T205
Test name
Test status
Simulation time 81593297022 ps
CPU time 167.33 seconds
Started Aug 01 05:38:34 PM PDT 24
Finished Aug 01 05:41:21 PM PDT 24
Peak memory 211712 kb
Host smart-e09ff440-4890-41d6-b44c-580bcffd2842
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=946559734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.946559734
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.56166491
Short name T58
Test name
Test status
Simulation time 29680038075 ps
CPU time 229.73 seconds
Started Aug 01 05:38:32 PM PDT 24
Finished Aug 01 05:42:22 PM PDT 24
Peak memory 211716 kb
Host smart-e034c829-be2b-44cf-96a5-f1bedbf5eeb8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=56166491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.56166491
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.2866894010
Short name T719
Test name
Test status
Simulation time 139674542 ps
CPU time 20.76 seconds
Started Aug 01 05:38:34 PM PDT 24
Finished Aug 01 05:38:54 PM PDT 24
Peak memory 211616 kb
Host smart-5d1a2fbb-1563-4ac3-a1af-14ad14c13fb8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866894010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.2866894010
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.2148998100
Short name T806
Test name
Test status
Simulation time 712594083 ps
CPU time 14.21 seconds
Started Aug 01 05:38:33 PM PDT 24
Finished Aug 01 05:38:47 PM PDT 24
Peak memory 204200 kb
Host smart-a41e9ea7-7b80-4564-9770-aff7c13776a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2148998100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.2148998100
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.3610688575
Short name T158
Test name
Test status
Simulation time 162257292 ps
CPU time 3.78 seconds
Started Aug 01 05:38:32 PM PDT 24
Finished Aug 01 05:38:36 PM PDT 24
Peak memory 203412 kb
Host smart-3e4f8001-2e03-4395-bf34-6e27172f0332
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3610688575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3610688575
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.2037121936
Short name T553
Test name
Test status
Simulation time 18369450124 ps
CPU time 40.69 seconds
Started Aug 01 05:38:40 PM PDT 24
Finished Aug 01 05:39:20 PM PDT 24
Peak memory 203520 kb
Host smart-3698dd09-e44a-4b81-837d-d5f1936dd772
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037121936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2037121936
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1338939498
Short name T211
Test name
Test status
Simulation time 11258414861 ps
CPU time 35.58 seconds
Started Aug 01 05:38:34 PM PDT 24
Finished Aug 01 05:39:09 PM PDT 24
Peak memory 203444 kb
Host smart-a4330571-5eaa-4282-a23f-90c2239a5299
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1338939498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1338939498
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.983045179
Short name T325
Test name
Test status
Simulation time 85728111 ps
CPU time 2.61 seconds
Started Aug 01 05:38:43 PM PDT 24
Finished Aug 01 05:38:46 PM PDT 24
Peak memory 203468 kb
Host smart-0c9cbce2-861d-4717-ae06-2a75b28146ee
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983045179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.983045179
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.2533715339
Short name T224
Test name
Test status
Simulation time 786003911 ps
CPU time 32.32 seconds
Started Aug 01 05:38:33 PM PDT 24
Finished Aug 01 05:39:06 PM PDT 24
Peak memory 205760 kb
Host smart-1f48428c-eacb-468d-9a7f-f2dd72e30826
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2533715339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2533715339
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2949225640
Short name T874
Test name
Test status
Simulation time 14444198681 ps
CPU time 516.76 seconds
Started Aug 01 05:38:35 PM PDT 24
Finished Aug 01 05:47:12 PM PDT 24
Peak memory 219932 kb
Host smart-31652936-2eb5-4fa3-9eff-83f9081204d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2949225640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran
d_reset.2949225640
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3315256114
Short name T663
Test name
Test status
Simulation time 799324942 ps
CPU time 81.5 seconds
Started Aug 01 05:38:34 PM PDT 24
Finished Aug 01 05:39:56 PM PDT 24
Peak memory 207580 kb
Host smart-9a6f6531-e3ba-4276-b076-dfceca621533
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3315256114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re
set_error.3315256114
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1205873803
Short name T196
Test name
Test status
Simulation time 444794764 ps
CPU time 15.26 seconds
Started Aug 01 05:38:35 PM PDT 24
Finished Aug 01 05:38:51 PM PDT 24
Peak memory 211656 kb
Host smart-36ba2eaa-a5a5-4482-b403-fe939bfcaecc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1205873803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1205873803
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.1672069218
Short name T887
Test name
Test status
Simulation time 872054272 ps
CPU time 31.98 seconds
Started Aug 01 05:38:32 PM PDT 24
Finished Aug 01 05:39:04 PM PDT 24
Peak memory 211668 kb
Host smart-46006621-acd9-4ba6-b710-d102ad18f690
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1672069218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.1672069218
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.449236461
Short name T113
Test name
Test status
Simulation time 18443437688 ps
CPU time 135.9 seconds
Started Aug 01 05:38:39 PM PDT 24
Finished Aug 01 05:40:55 PM PDT 24
Peak memory 211748 kb
Host smart-f54e49f9-a538-43b6-bef6-3469966a4f75
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=449236461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slo
w_rsp.449236461
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.1098803398
Short name T583
Test name
Test status
Simulation time 108866460 ps
CPU time 10.19 seconds
Started Aug 01 05:38:48 PM PDT 24
Finished Aug 01 05:38:58 PM PDT 24
Peak memory 203468 kb
Host smart-6c28d90b-766f-4a83-9538-8546534c7d93
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1098803398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.1098803398
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.2853746864
Short name T510
Test name
Test status
Simulation time 83321999 ps
CPU time 9.12 seconds
Started Aug 01 05:38:33 PM PDT 24
Finished Aug 01 05:38:42 PM PDT 24
Peak memory 203468 kb
Host smart-89205730-ea82-438e-a9cb-7778969a4fc9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2853746864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2853746864
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.1500611129
Short name T386
Test name
Test status
Simulation time 245403630 ps
CPU time 8.32 seconds
Started Aug 01 05:38:40 PM PDT 24
Finished Aug 01 05:38:49 PM PDT 24
Peak memory 204604 kb
Host smart-9b2e8070-db2d-4273-9d8a-3f5c94db21e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1500611129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1500611129
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.3929979173
Short name T433
Test name
Test status
Simulation time 43245733991 ps
CPU time 171.83 seconds
Started Aug 01 05:38:34 PM PDT 24
Finished Aug 01 05:41:26 PM PDT 24
Peak memory 211740 kb
Host smart-f52f68cd-f06d-4b6d-a1f7-552cc1f556ec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929979173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3929979173
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.2518749347
Short name T638
Test name
Test status
Simulation time 42424985172 ps
CPU time 184.1 seconds
Started Aug 01 05:38:35 PM PDT 24
Finished Aug 01 05:41:40 PM PDT 24
Peak memory 211740 kb
Host smart-ba22be04-0827-4abb-9eca-1a17d7d71595
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2518749347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2518749347
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.862789614
Short name T469
Test name
Test status
Simulation time 42918695 ps
CPU time 5.52 seconds
Started Aug 01 05:38:43 PM PDT 24
Finished Aug 01 05:38:49 PM PDT 24
Peak memory 211644 kb
Host smart-46fef392-b248-4d5c-b076-ddca61ce7492
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862789614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.862789614
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.1057704750
Short name T651
Test name
Test status
Simulation time 1695760969 ps
CPU time 27.64 seconds
Started Aug 01 05:38:32 PM PDT 24
Finished Aug 01 05:38:59 PM PDT 24
Peak memory 204160 kb
Host smart-4cf288b4-32fe-48a8-b522-6709d7bf182b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1057704750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1057704750
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.3900106963
Short name T581
Test name
Test status
Simulation time 28834940 ps
CPU time 2.22 seconds
Started Aug 01 05:38:38 PM PDT 24
Finished Aug 01 05:38:40 PM PDT 24
Peak memory 203480 kb
Host smart-0cc9dfc7-8284-4209-a26e-7598fd76c954
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3900106963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3900106963
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3608139518
Short name T754
Test name
Test status
Simulation time 41443599759 ps
CPU time 53.52 seconds
Started Aug 01 05:38:34 PM PDT 24
Finished Aug 01 05:39:28 PM PDT 24
Peak memory 203524 kb
Host smart-76d6f70c-7601-49c3-a641-790feaddb82e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608139518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3608139518
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3798417983
Short name T840
Test name
Test status
Simulation time 2604711473 ps
CPU time 21.88 seconds
Started Aug 01 05:38:33 PM PDT 24
Finished Aug 01 05:38:55 PM PDT 24
Peak memory 203544 kb
Host smart-93489336-43e0-4e9a-8f86-1f979da25024
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3798417983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3798417983
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.3553463484
Short name T844
Test name
Test status
Simulation time 32601024 ps
CPU time 2.39 seconds
Started Aug 01 05:38:32 PM PDT 24
Finished Aug 01 05:38:35 PM PDT 24
Peak memory 203380 kb
Host smart-d300b6d1-eef3-4df5-ab7d-e142f7c5e18b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553463484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.3553463484
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.564801203
Short name T539
Test name
Test status
Simulation time 656137622 ps
CPU time 35.67 seconds
Started Aug 01 05:38:47 PM PDT 24
Finished Aug 01 05:39:23 PM PDT 24
Peak memory 205296 kb
Host smart-2bad592c-ecf0-4850-af58-6845c6e8e213
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=564801203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.564801203
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.56396418
Short name T216
Test name
Test status
Simulation time 7195866917 ps
CPU time 242.43 seconds
Started Aug 01 05:38:46 PM PDT 24
Finished Aug 01 05:42:49 PM PDT 24
Peak memory 206068 kb
Host smart-c8842b05-2d34-4c72-8640-8dbca088992c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=56396418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.56396418
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.351917501
Short name T891
Test name
Test status
Simulation time 4769498950 ps
CPU time 272.43 seconds
Started Aug 01 05:38:48 PM PDT 24
Finished Aug 01 05:43:20 PM PDT 24
Peak memory 211372 kb
Host smart-99ac003b-fc5a-476b-9859-59fbba56e543
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=351917501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand
_reset.351917501
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.1314049075
Short name T311
Test name
Test status
Simulation time 830687625 ps
CPU time 159.41 seconds
Started Aug 01 05:38:47 PM PDT 24
Finished Aug 01 05:41:26 PM PDT 24
Peak memory 211324 kb
Host smart-6bcb7e64-f92b-4028-b9ad-ebcbef05391d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1314049075 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re
set_error.1314049075
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.2918772778
Short name T413
Test name
Test status
Simulation time 139962113 ps
CPU time 19.28 seconds
Started Aug 01 05:38:47 PM PDT 24
Finished Aug 01 05:39:07 PM PDT 24
Peak memory 211600 kb
Host smart-b0e90093-1b4c-439f-9946-6d62cc3019d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2918772778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2918772778
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.3673911701
Short name T704
Test name
Test status
Simulation time 417773042 ps
CPU time 14.8 seconds
Started Aug 01 05:36:29 PM PDT 24
Finished Aug 01 05:36:44 PM PDT 24
Peak memory 204512 kb
Host smart-3c749025-2a33-46a5-8d9a-0d58d67cf5c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3673911701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.3673911701
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.535687729
Short name T268
Test name
Test status
Simulation time 46267473941 ps
CPU time 388.56 seconds
Started Aug 01 05:36:31 PM PDT 24
Finished Aug 01 05:43:00 PM PDT 24
Peak memory 206080 kb
Host smart-cee2647c-45d7-470d-950e-95aae8dd3e6c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=535687729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow
_rsp.535687729
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2347722423
Short name T748
Test name
Test status
Simulation time 102960752 ps
CPU time 14.37 seconds
Started Aug 01 05:36:33 PM PDT 24
Finished Aug 01 05:36:47 PM PDT 24
Peak memory 203488 kb
Host smart-05ceefd7-1f9b-45ae-8da3-4b6687d176c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2347722423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2347722423
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.3531769789
Short name T137
Test name
Test status
Simulation time 519376984 ps
CPU time 9.29 seconds
Started Aug 01 05:36:33 PM PDT 24
Finished Aug 01 05:36:42 PM PDT 24
Peak memory 203484 kb
Host smart-536264c1-dd93-403f-8034-ee998c93f2aa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3531769789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3531769789
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.4212963959
Short name T658
Test name
Test status
Simulation time 303680421 ps
CPU time 10.05 seconds
Started Aug 01 05:36:31 PM PDT 24
Finished Aug 01 05:36:41 PM PDT 24
Peak memory 204568 kb
Host smart-768006bd-ebdc-4777-9014-03a3f5109b46
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4212963959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.4212963959
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.491907242
Short name T755
Test name
Test status
Simulation time 40673115637 ps
CPU time 190.5 seconds
Started Aug 01 05:36:38 PM PDT 24
Finished Aug 01 05:39:48 PM PDT 24
Peak memory 211800 kb
Host smart-43c12ac0-077a-4692-afc3-e11b05801599
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=491907242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.491907242
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1842567362
Short name T865
Test name
Test status
Simulation time 55443940319 ps
CPU time 183.15 seconds
Started Aug 01 05:36:30 PM PDT 24
Finished Aug 01 05:39:34 PM PDT 24
Peak memory 211736 kb
Host smart-8d8f84ec-a854-4ac6-a79c-377e768afbf4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1842567362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1842567362
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1454212373
Short name T552
Test name
Test status
Simulation time 64778943 ps
CPU time 8.73 seconds
Started Aug 01 05:36:30 PM PDT 24
Finished Aug 01 05:36:39 PM PDT 24
Peak memory 211660 kb
Host smart-7105a734-b74e-47b2-9eda-4c9c98a233bb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454212373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1454212373
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.3165417120
Short name T882
Test name
Test status
Simulation time 34503255 ps
CPU time 1.83 seconds
Started Aug 01 05:36:31 PM PDT 24
Finished Aug 01 05:36:33 PM PDT 24
Peak memory 203388 kb
Host smart-ee5f1d12-52e2-4d3b-b940-10e6442a40e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3165417120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3165417120
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.2855140902
Short name T480
Test name
Test status
Simulation time 173374172 ps
CPU time 3.99 seconds
Started Aug 01 05:36:31 PM PDT 24
Finished Aug 01 05:36:35 PM PDT 24
Peak memory 203460 kb
Host smart-78e62387-f1c9-4a1c-b3cb-155c6ecfd7c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2855140902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2855140902
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.4185417160
Short name T777
Test name
Test status
Simulation time 6039249820 ps
CPU time 32.32 seconds
Started Aug 01 05:36:33 PM PDT 24
Finished Aug 01 05:37:05 PM PDT 24
Peak memory 203568 kb
Host smart-dab9ed5e-4d15-4cf3-9d8c-1daba489fc1e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185417160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.4185417160
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.3027617279
Short name T226
Test name
Test status
Simulation time 7727120268 ps
CPU time 31.38 seconds
Started Aug 01 05:36:36 PM PDT 24
Finished Aug 01 05:37:08 PM PDT 24
Peak memory 203552 kb
Host smart-80d604c2-de98-4bb2-a40d-d230d39c0b93
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3027617279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.3027617279
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.3568867612
Short name T402
Test name
Test status
Simulation time 26571948 ps
CPU time 2.48 seconds
Started Aug 01 05:36:39 PM PDT 24
Finished Aug 01 05:36:41 PM PDT 24
Peak memory 203464 kb
Host smart-3f01e21f-b8cf-4bd8-84c1-2b11dd6a2b98
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568867612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.3568867612
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.2949873476
Short name T243
Test name
Test status
Simulation time 4579234373 ps
CPU time 150.61 seconds
Started Aug 01 05:36:32 PM PDT 24
Finished Aug 01 05:39:03 PM PDT 24
Peak memory 206432 kb
Host smart-c11f9842-1aa4-458a-949a-0c4cc46236cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2949873476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2949873476
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.3078187906
Short name T789
Test name
Test status
Simulation time 8986973327 ps
CPU time 99.18 seconds
Started Aug 01 05:36:33 PM PDT 24
Finished Aug 01 05:38:12 PM PDT 24
Peak memory 205408 kb
Host smart-e57959b8-36e6-41fe-9e65-63819691d7f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3078187906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3078187906
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.2587087060
Short name T190
Test name
Test status
Simulation time 12422892785 ps
CPU time 496.68 seconds
Started Aug 01 05:36:32 PM PDT 24
Finished Aug 01 05:44:49 PM PDT 24
Peak memory 219904 kb
Host smart-2ec380b1-a272-4682-a626-ba29db29daa8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2587087060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand
_reset.2587087060
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.4260786213
Short name T310
Test name
Test status
Simulation time 5404958595 ps
CPU time 208.37 seconds
Started Aug 01 05:36:30 PM PDT 24
Finished Aug 01 05:39:59 PM PDT 24
Peak memory 211728 kb
Host smart-278b6b6e-53c6-4ae8-bbd9-b514a4e15dda
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4260786213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res
et_error.4260786213
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.478706126
Short name T525
Test name
Test status
Simulation time 110185881 ps
CPU time 8.28 seconds
Started Aug 01 05:36:32 PM PDT 24
Finished Aug 01 05:36:40 PM PDT 24
Peak memory 211616 kb
Host smart-4d68e75f-9fc4-4194-9fb3-8836e6fa1b26
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=478706126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.478706126
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.3369485730
Short name T627
Test name
Test status
Simulation time 4868674679 ps
CPU time 38.41 seconds
Started Aug 01 05:38:45 PM PDT 24
Finished Aug 01 05:39:24 PM PDT 24
Peak memory 211644 kb
Host smart-703aa271-fd38-4409-a690-18aa4e648b5d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3369485730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3369485730
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.268088722
Short name T252
Test name
Test status
Simulation time 273427523 ps
CPU time 9.13 seconds
Started Aug 01 05:38:47 PM PDT 24
Finished Aug 01 05:38:56 PM PDT 24
Peak memory 203468 kb
Host smart-398d5ed3-1439-40a7-bcb9-14a175be58a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=268088722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.268088722
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.567323762
Short name T673
Test name
Test status
Simulation time 54963016 ps
CPU time 5.83 seconds
Started Aug 01 05:38:47 PM PDT 24
Finished Aug 01 05:38:53 PM PDT 24
Peak memory 203456 kb
Host smart-d3678e43-a79e-48dc-9269-1a34f8dd3875
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=567323762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.567323762
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.3067256208
Short name T64
Test name
Test status
Simulation time 1050590626 ps
CPU time 33.49 seconds
Started Aug 01 05:38:47 PM PDT 24
Finished Aug 01 05:39:20 PM PDT 24
Peak memory 211660 kb
Host smart-384c7a4e-5c6b-4263-89bd-f35f71f178a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3067256208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.3067256208
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.3158047174
Short name T383
Test name
Test status
Simulation time 43667397813 ps
CPU time 259.27 seconds
Started Aug 01 05:38:47 PM PDT 24
Finished Aug 01 05:43:07 PM PDT 24
Peak memory 204800 kb
Host smart-75cdb797-d83f-4e1e-8044-5fbd1d5abd77
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158047174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3158047174
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.700514412
Short name T586
Test name
Test status
Simulation time 51168842191 ps
CPU time 293.18 seconds
Started Aug 01 05:38:46 PM PDT 24
Finished Aug 01 05:43:39 PM PDT 24
Peak memory 204760 kb
Host smart-a6f4ef14-e431-41d7-bfbb-5b2f674a302d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=700514412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.700514412
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.1981972747
Short name T474
Test name
Test status
Simulation time 257473308 ps
CPU time 10.44 seconds
Started Aug 01 05:38:46 PM PDT 24
Finished Aug 01 05:38:57 PM PDT 24
Peak memory 211636 kb
Host smart-1c79a070-1f4f-43fa-9ab8-822b965f7306
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981972747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1981972747
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.1218585949
Short name T564
Test name
Test status
Simulation time 3680953299 ps
CPU time 28.06 seconds
Started Aug 01 05:38:46 PM PDT 24
Finished Aug 01 05:39:14 PM PDT 24
Peak memory 202844 kb
Host smart-1947c0ce-7be6-496f-b00e-c405767ff577
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1218585949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1218585949
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.517410452
Short name T557
Test name
Test status
Simulation time 158666315 ps
CPU time 3.34 seconds
Started Aug 01 05:38:48 PM PDT 24
Finished Aug 01 05:38:52 PM PDT 24
Peak memory 203444 kb
Host smart-50f5b346-b369-4b81-b55f-1442c0372f8d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=517410452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.517410452
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.804958900
Short name T134
Test name
Test status
Simulation time 10365825080 ps
CPU time 33.3 seconds
Started Aug 01 05:38:46 PM PDT 24
Finished Aug 01 05:39:19 PM PDT 24
Peak memory 203432 kb
Host smart-28b8659a-7c56-423c-a920-7eb59da6d90e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=804958900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.804958900
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.3469149652
Short name T132
Test name
Test status
Simulation time 2891377541 ps
CPU time 27.24 seconds
Started Aug 01 05:38:46 PM PDT 24
Finished Aug 01 05:39:13 PM PDT 24
Peak memory 203568 kb
Host smart-137248e4-ba14-443a-a51f-3fe28297e9eb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3469149652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3469149652
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.3876287780
Short name T847
Test name
Test status
Simulation time 40624050 ps
CPU time 2.2 seconds
Started Aug 01 05:38:47 PM PDT 24
Finished Aug 01 05:38:50 PM PDT 24
Peak memory 203480 kb
Host smart-3266c52a-cc1b-4305-806a-7e045f27d18d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876287780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.3876287780
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.3628075943
Short name T722
Test name
Test status
Simulation time 2168277222 ps
CPU time 104.25 seconds
Started Aug 01 05:38:48 PM PDT 24
Finished Aug 01 05:40:32 PM PDT 24
Peak memory 207056 kb
Host smart-a1292234-8cd7-49cd-9e6d-c63cc8e10238
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3628075943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3628075943
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3991206379
Short name T623
Test name
Test status
Simulation time 1274202925 ps
CPU time 99.33 seconds
Started Aug 01 05:38:46 PM PDT 24
Finished Aug 01 05:40:26 PM PDT 24
Peak memory 205860 kb
Host smart-21441007-09f0-4ecb-abf5-8150d72cf204
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3991206379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3991206379
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.3067520109
Short name T41
Test name
Test status
Simulation time 9871924885 ps
CPU time 462.66 seconds
Started Aug 01 05:38:47 PM PDT 24
Finished Aug 01 05:46:30 PM PDT 24
Peak memory 219928 kb
Host smart-fb3ec486-50c1-4a36-9021-5f9635775035
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3067520109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran
d_reset.3067520109
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.2640342172
Short name T312
Test name
Test status
Simulation time 7097797244 ps
CPU time 223.38 seconds
Started Aug 01 05:38:49 PM PDT 24
Finished Aug 01 05:42:32 PM PDT 24
Peak memory 211608 kb
Host smart-d7b40aef-34dd-44da-855c-3caefe543b18
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2640342172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re
set_error.2640342172
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.1977621502
Short name T277
Test name
Test status
Simulation time 744513522 ps
CPU time 29.91 seconds
Started Aug 01 05:38:47 PM PDT 24
Finished Aug 01 05:39:17 PM PDT 24
Peak memory 211652 kb
Host smart-5a290e9c-67aa-45a8-9ae0-65259f2a8bb1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1977621502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1977621502
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.2365520481
Short name T368
Test name
Test status
Simulation time 751329641 ps
CPU time 21.45 seconds
Started Aug 01 05:38:46 PM PDT 24
Finished Aug 01 05:39:08 PM PDT 24
Peak memory 211660 kb
Host smart-5b5e7f81-a785-4e02-a36f-d139804854c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2365520481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.2365520481
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.187001843
Short name T145
Test name
Test status
Simulation time 33779203059 ps
CPU time 308.06 seconds
Started Aug 01 05:38:46 PM PDT 24
Finished Aug 01 05:43:55 PM PDT 24
Peak memory 206432 kb
Host smart-6d89dd4c-5294-44ca-a03b-cc98a03ffd6f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=187001843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slo
w_rsp.187001843
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.2936609681
Short name T765
Test name
Test status
Simulation time 1333649914 ps
CPU time 23.56 seconds
Started Aug 01 05:38:48 PM PDT 24
Finished Aug 01 05:39:12 PM PDT 24
Peak memory 203368 kb
Host smart-929dd49d-18cf-4c04-926a-bdbcd9d11ad5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2936609681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.2936609681
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.3781953681
Short name T364
Test name
Test status
Simulation time 1148523598 ps
CPU time 31.01 seconds
Started Aug 01 05:38:50 PM PDT 24
Finished Aug 01 05:39:21 PM PDT 24
Peak memory 203556 kb
Host smart-357e1b31-3bd1-466d-8c15-6dc2ebff7038
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3781953681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3781953681
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.3258139812
Short name T853
Test name
Test status
Simulation time 205800287 ps
CPU time 16.48 seconds
Started Aug 01 05:38:48 PM PDT 24
Finished Aug 01 05:39:04 PM PDT 24
Peak memory 211664 kb
Host smart-683580ba-16d0-438a-8b71-c4ffc8000ac0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3258139812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.3258139812
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.399458142
Short name T167
Test name
Test status
Simulation time 106647558980 ps
CPU time 266.01 seconds
Started Aug 01 05:38:46 PM PDT 24
Finished Aug 01 05:43:13 PM PDT 24
Peak memory 211776 kb
Host smart-add40737-2e1b-4963-aadb-1ecd35bebfa4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=399458142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.399458142
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2075315702
Short name T278
Test name
Test status
Simulation time 123338465229 ps
CPU time 255.12 seconds
Started Aug 01 05:38:47 PM PDT 24
Finished Aug 01 05:43:03 PM PDT 24
Peak memory 211732 kb
Host smart-7c217037-c413-429a-8b7d-ac8bbdc0a041
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2075315702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2075315702
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.3843295044
Short name T445
Test name
Test status
Simulation time 305066984 ps
CPU time 28.6 seconds
Started Aug 01 05:38:45 PM PDT 24
Finished Aug 01 05:39:14 PM PDT 24
Peak memory 211640 kb
Host smart-55c7e693-27ed-4a51-b1ca-2334de3b7c73
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843295044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.3843295044
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.100322770
Short name T726
Test name
Test status
Simulation time 400951261 ps
CPU time 6.28 seconds
Started Aug 01 05:38:47 PM PDT 24
Finished Aug 01 05:38:53 PM PDT 24
Peak memory 203640 kb
Host smart-ed3f6193-a182-49db-8430-2356a4f47ede
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=100322770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.100322770
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.1172809232
Short name T693
Test name
Test status
Simulation time 74598920 ps
CPU time 2.3 seconds
Started Aug 01 05:38:49 PM PDT 24
Finished Aug 01 05:38:52 PM PDT 24
Peak memory 203480 kb
Host smart-a365bfb3-b608-47f5-852a-f47f4e1a96bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1172809232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1172809232
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2937460216
Short name T533
Test name
Test status
Simulation time 9405285010 ps
CPU time 27.52 seconds
Started Aug 01 05:38:46 PM PDT 24
Finished Aug 01 05:39:14 PM PDT 24
Peak memory 202812 kb
Host smart-aa82abb3-e477-4d8c-955e-3454b3cce013
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937460216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2937460216
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3036729235
Short name T434
Test name
Test status
Simulation time 5447106312 ps
CPU time 27.01 seconds
Started Aug 01 05:38:48 PM PDT 24
Finished Aug 01 05:39:15 PM PDT 24
Peak memory 203420 kb
Host smart-d378ce9f-9910-4a27-9ec3-753df3cecdee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3036729235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3036729235
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2107519610
Short name T804
Test name
Test status
Simulation time 54711604 ps
CPU time 2.44 seconds
Started Aug 01 05:38:48 PM PDT 24
Finished Aug 01 05:38:50 PM PDT 24
Peak memory 203444 kb
Host smart-29b2fe8c-9ade-4d65-a147-7213e83808ec
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107519610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2107519610
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3098572404
Short name T509
Test name
Test status
Simulation time 2288608000 ps
CPU time 136.68 seconds
Started Aug 01 05:39:00 PM PDT 24
Finished Aug 01 05:41:17 PM PDT 24
Peak memory 206880 kb
Host smart-b4dae906-5687-4367-8b3d-8a8d0774ab74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3098572404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3098572404
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3197332239
Short name T212
Test name
Test status
Simulation time 6092564452 ps
CPU time 283.42 seconds
Started Aug 01 05:38:48 PM PDT 24
Finished Aug 01 05:43:31 PM PDT 24
Peak memory 209560 kb
Host smart-4c987225-31c1-4e88-86bb-b3008db45b53
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3197332239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran
d_reset.3197332239
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2934933937
Short name T846
Test name
Test status
Simulation time 559204680 ps
CPU time 50.05 seconds
Started Aug 01 05:38:59 PM PDT 24
Finished Aug 01 05:39:49 PM PDT 24
Peak memory 206680 kb
Host smart-fb08ba5e-8d2b-45c3-9cfc-82429ff733e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2934933937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re
set_error.2934933937
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.1974716804
Short name T435
Test name
Test status
Simulation time 910511438 ps
CPU time 11.77 seconds
Started Aug 01 05:38:48 PM PDT 24
Finished Aug 01 05:39:00 PM PDT 24
Peak memory 211524 kb
Host smart-200c69ba-0ddc-4589-9371-8e1cd795c064
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1974716804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1974716804
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.3415265434
Short name T303
Test name
Test status
Simulation time 2744949636 ps
CPU time 60.63 seconds
Started Aug 01 05:38:59 PM PDT 24
Finished Aug 01 05:40:00 PM PDT 24
Peak memory 206576 kb
Host smart-99b559c8-4f2b-40dc-8a03-79b983776491
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3415265434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3415265434
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2234693072
Short name T157
Test name
Test status
Simulation time 368327438100 ps
CPU time 813.76 seconds
Started Aug 01 05:38:58 PM PDT 24
Finished Aug 01 05:52:32 PM PDT 24
Peak memory 211716 kb
Host smart-bdf7399b-2ab6-4b4b-a325-e570d5e448e3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2234693072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl
ow_rsp.2234693072
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.943894843
Short name T652
Test name
Test status
Simulation time 1722946686 ps
CPU time 18.37 seconds
Started Aug 01 05:39:02 PM PDT 24
Finished Aug 01 05:39:20 PM PDT 24
Peak memory 203788 kb
Host smart-0ce67a5b-2b99-4cb7-be1a-1c19b7af16e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=943894843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.943894843
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.3885879364
Short name T545
Test name
Test status
Simulation time 339619873 ps
CPU time 28.08 seconds
Started Aug 01 05:38:58 PM PDT 24
Finished Aug 01 05:39:27 PM PDT 24
Peak memory 203372 kb
Host smart-ca9a5273-a8de-4610-8383-f09702a283eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3885879364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3885879364
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.2463972404
Short name T631
Test name
Test status
Simulation time 54107562 ps
CPU time 5.65 seconds
Started Aug 01 05:39:00 PM PDT 24
Finished Aug 01 05:39:06 PM PDT 24
Peak memory 211664 kb
Host smart-e72998e2-6f7a-48fa-98e7-a707b991e4ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2463972404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2463972404
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.429216608
Short name T643
Test name
Test status
Simulation time 18198141161 ps
CPU time 57.85 seconds
Started Aug 01 05:38:59 PM PDT 24
Finished Aug 01 05:39:57 PM PDT 24
Peak memory 211688 kb
Host smart-dcf0b643-ce61-4465-90d2-996075ad516b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=429216608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.429216608
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2748826988
Short name T96
Test name
Test status
Simulation time 2316477638 ps
CPU time 15.61 seconds
Started Aug 01 05:38:59 PM PDT 24
Finished Aug 01 05:39:15 PM PDT 24
Peak memory 203576 kb
Host smart-b0b7b66c-be1d-4987-b03b-e3826fe228ff
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2748826988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2748826988
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.1741221139
Short name T183
Test name
Test status
Simulation time 96226962 ps
CPU time 3.61 seconds
Started Aug 01 05:38:59 PM PDT 24
Finished Aug 01 05:39:03 PM PDT 24
Peak memory 203568 kb
Host smart-4583e56d-19bf-4e31-ad35-5fa5e76d653b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741221139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.1741221139
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.1941942516
Short name T587
Test name
Test status
Simulation time 336629997 ps
CPU time 7.64 seconds
Started Aug 01 05:39:01 PM PDT 24
Finished Aug 01 05:39:09 PM PDT 24
Peak memory 203504 kb
Host smart-bc3f4b5f-671f-4e28-8c05-66203f0d7092
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1941942516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1941942516
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.3062514843
Short name T409
Test name
Test status
Simulation time 72751017 ps
CPU time 2.35 seconds
Started Aug 01 05:39:00 PM PDT 24
Finished Aug 01 05:39:03 PM PDT 24
Peak memory 203460 kb
Host smart-d65c266f-ef9a-4ad5-bb87-1535d584c127
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3062514843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3062514843
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.369802463
Short name T499
Test name
Test status
Simulation time 7321781507 ps
CPU time 26.07 seconds
Started Aug 01 05:39:00 PM PDT 24
Finished Aug 01 05:39:26 PM PDT 24
Peak memory 203524 kb
Host smart-e08256f6-b532-4791-a5b3-557ac3a3e73b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=369802463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.369802463
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1336230004
Short name T161
Test name
Test status
Simulation time 24339964476 ps
CPU time 45.97 seconds
Started Aug 01 05:39:00 PM PDT 24
Finished Aug 01 05:39:46 PM PDT 24
Peak memory 203536 kb
Host smart-54d81776-42ef-4c10-a996-8787710b3b78
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1336230004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1336230004
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.1058208832
Short name T154
Test name
Test status
Simulation time 38475351 ps
CPU time 2.21 seconds
Started Aug 01 05:39:00 PM PDT 24
Finished Aug 01 05:39:03 PM PDT 24
Peak memory 203444 kb
Host smart-a46e3e3f-8996-44a3-ab1c-3318d5535949
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058208832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.1058208832
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.610914301
Short name T5
Test name
Test status
Simulation time 294940276 ps
CPU time 26.1 seconds
Started Aug 01 05:39:01 PM PDT 24
Finished Aug 01 05:39:27 PM PDT 24
Peak memory 206304 kb
Host smart-b2cd3f05-58cb-4ea0-9391-b66e029490af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=610914301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.610914301
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.2550976016
Short name T473
Test name
Test status
Simulation time 4950119339 ps
CPU time 106.68 seconds
Started Aug 01 05:39:01 PM PDT 24
Finished Aug 01 05:40:49 PM PDT 24
Peak memory 207308 kb
Host smart-f5d9eef9-ee39-4cf8-aff4-ac263d695695
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2550976016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2550976016
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.45334179
Short name T825
Test name
Test status
Simulation time 2022680586 ps
CPU time 465.89 seconds
Started Aug 01 05:39:00 PM PDT 24
Finished Aug 01 05:46:46 PM PDT 24
Peak memory 219852 kb
Host smart-573bb4d2-adc6-421e-abd0-b5a145caf978
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=45334179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_
reset.45334179
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.3701875485
Short name T709
Test name
Test status
Simulation time 448970510 ps
CPU time 15.07 seconds
Started Aug 01 05:39:00 PM PDT 24
Finished Aug 01 05:39:15 PM PDT 24
Peak memory 211520 kb
Host smart-bc07b519-fbfd-49d9-be7b-82241e675f70
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3701875485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3701875485
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.3302915535
Short name T181
Test name
Test status
Simulation time 1834745985 ps
CPU time 60.45 seconds
Started Aug 01 05:39:04 PM PDT 24
Finished Aug 01 05:40:05 PM PDT 24
Peak memory 211668 kb
Host smart-effadf86-6739-421e-acc1-507a4777c84f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3302915535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.3302915535
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1258988354
Short name T387
Test name
Test status
Simulation time 39574378302 ps
CPU time 347.12 seconds
Started Aug 01 05:38:59 PM PDT 24
Finished Aug 01 05:44:47 PM PDT 24
Peak memory 207108 kb
Host smart-934efcc0-382d-4251-9769-093099aaa729
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1258988354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl
ow_rsp.1258988354
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.4128583639
Short name T246
Test name
Test status
Simulation time 1141692601 ps
CPU time 24.72 seconds
Started Aug 01 05:39:04 PM PDT 24
Finished Aug 01 05:39:29 PM PDT 24
Peak memory 204276 kb
Host smart-09aa9af1-bd4e-49df-a4f1-4a6f6fce25cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4128583639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.4128583639
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.3774891382
Short name T197
Test name
Test status
Simulation time 596885604 ps
CPU time 19.08 seconds
Started Aug 01 05:38:59 PM PDT 24
Finished Aug 01 05:39:18 PM PDT 24
Peak memory 203464 kb
Host smart-e8033a7b-036a-4e75-bada-73921e796b90
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3774891382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3774891382
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.1156740025
Short name T676
Test name
Test status
Simulation time 1140760638 ps
CPU time 32.03 seconds
Started Aug 01 05:38:59 PM PDT 24
Finished Aug 01 05:39:32 PM PDT 24
Peak memory 204892 kb
Host smart-bfccd497-a235-47b2-9274-55ab70f8de33
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1156740025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1156740025
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.1228248892
Short name T127
Test name
Test status
Simulation time 29520254548 ps
CPU time 133.06 seconds
Started Aug 01 05:39:04 PM PDT 24
Finished Aug 01 05:41:17 PM PDT 24
Peak memory 211708 kb
Host smart-b17e953b-100e-42a9-b345-baf158fca9fd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228248892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1228248892
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3592899252
Short name T560
Test name
Test status
Simulation time 17326632028 ps
CPU time 125.12 seconds
Started Aug 01 05:39:03 PM PDT 24
Finished Aug 01 05:41:08 PM PDT 24
Peak memory 204792 kb
Host smart-56da166c-ae2f-45b2-9ca8-3412f77a9de2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3592899252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3592899252
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.473797476
Short name T254
Test name
Test status
Simulation time 51979904 ps
CPU time 5.6 seconds
Started Aug 01 05:38:59 PM PDT 24
Finished Aug 01 05:39:05 PM PDT 24
Peak memory 211632 kb
Host smart-be4d3779-fffa-437a-819e-39e997daec81
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473797476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.473797476
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.4134423607
Short name T306
Test name
Test status
Simulation time 6438522672 ps
CPU time 34.65 seconds
Started Aug 01 05:39:00 PM PDT 24
Finished Aug 01 05:39:35 PM PDT 24
Peak memory 211556 kb
Host smart-83ce1437-fd5f-4c28-94b0-5797a87fe560
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4134423607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.4134423607
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.3675847461
Short name T63
Test name
Test status
Simulation time 105167090 ps
CPU time 3.02 seconds
Started Aug 01 05:39:01 PM PDT 24
Finished Aug 01 05:39:05 PM PDT 24
Peak memory 203456 kb
Host smart-c6f08e9a-80c5-46fe-85c3-e9c874e395cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3675847461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3675847461
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2976393447
Short name T613
Test name
Test status
Simulation time 7207675637 ps
CPU time 34.14 seconds
Started Aug 01 05:39:00 PM PDT 24
Finished Aug 01 05:39:34 PM PDT 24
Peak memory 203740 kb
Host smart-c2420e66-8f9d-4940-8972-a09e7dcf9187
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976393447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2976393447
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3442090792
Short name T478
Test name
Test status
Simulation time 2675953752 ps
CPU time 22.63 seconds
Started Aug 01 05:39:02 PM PDT 24
Finished Aug 01 05:39:25 PM PDT 24
Peak memory 203492 kb
Host smart-f2de7ecb-9244-45ef-bc4d-d5e7a62f9c9f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3442090792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3442090792
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.1272451633
Short name T367
Test name
Test status
Simulation time 91776853 ps
CPU time 2.5 seconds
Started Aug 01 05:39:03 PM PDT 24
Finished Aug 01 05:39:05 PM PDT 24
Peak memory 203472 kb
Host smart-943178fc-9425-4797-ad8a-745d9998279c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272451633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.1272451633
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.1521906104
Short name T526
Test name
Test status
Simulation time 251202784 ps
CPU time 21.18 seconds
Started Aug 01 05:39:00 PM PDT 24
Finished Aug 01 05:39:21 PM PDT 24
Peak memory 211656 kb
Host smart-0d3f834b-2102-4183-8a5b-e6f91ececfb8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1521906104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.1521906104
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2879493040
Short name T344
Test name
Test status
Simulation time 113800599 ps
CPU time 11.05 seconds
Started Aug 01 05:39:01 PM PDT 24
Finished Aug 01 05:39:12 PM PDT 24
Peak memory 204152 kb
Host smart-4fc0ef9e-f732-4224-963f-d573cc9ebacd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2879493040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2879493040
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.883815373
Short name T648
Test name
Test status
Simulation time 37062651 ps
CPU time 28.8 seconds
Started Aug 01 05:39:00 PM PDT 24
Finished Aug 01 05:39:29 PM PDT 24
Peak memory 205696 kb
Host smart-d8f8c761-3d2a-4415-9e25-d20a354c83fc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=883815373 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_res
et_error.883815373
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.2548414108
Short name T54
Test name
Test status
Simulation time 1571744505 ps
CPU time 31.67 seconds
Started Aug 01 05:39:03 PM PDT 24
Finished Aug 01 05:39:34 PM PDT 24
Peak memory 211600 kb
Host smart-d9db4a0f-8c8e-4f0e-ae01-488b4f4e6696
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2548414108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2548414108
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.1604438388
Short name T561
Test name
Test status
Simulation time 1622364484 ps
CPU time 40.19 seconds
Started Aug 01 05:39:20 PM PDT 24
Finished Aug 01 05:40:01 PM PDT 24
Peak memory 205564 kb
Host smart-beb505bb-1ff6-4024-bf62-0c5645713a0b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1604438388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.1604438388
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.886482787
Short name T550
Test name
Test status
Simulation time 39935511992 ps
CPU time 346.72 seconds
Started Aug 01 05:39:19 PM PDT 24
Finished Aug 01 05:45:06 PM PDT 24
Peak memory 211656 kb
Host smart-eea273c6-35b3-4bd2-9e13-28e5bdec1652
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=886482787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slo
w_rsp.886482787
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2642766762
Short name T280
Test name
Test status
Simulation time 35118307 ps
CPU time 5.39 seconds
Started Aug 01 05:39:19 PM PDT 24
Finished Aug 01 05:39:25 PM PDT 24
Peak memory 203684 kb
Host smart-7c196c18-22c8-4c8b-976a-4d543eb5489c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2642766762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2642766762
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.3425391147
Short name T664
Test name
Test status
Simulation time 132214117 ps
CPU time 4.31 seconds
Started Aug 01 05:39:19 PM PDT 24
Finished Aug 01 05:39:24 PM PDT 24
Peak memory 203472 kb
Host smart-f98ac87b-4c66-4da3-8ed6-e2b2269230ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3425391147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3425391147
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.2188565419
Short name T408
Test name
Test status
Simulation time 1176144921 ps
CPU time 37.46 seconds
Started Aug 01 05:39:17 PM PDT 24
Finished Aug 01 05:39:55 PM PDT 24
Peak memory 204568 kb
Host smart-cc630824-a05d-4990-b089-e66a39270651
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2188565419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2188565419
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.2498505241
Short name T839
Test name
Test status
Simulation time 7335283514 ps
CPU time 39 seconds
Started Aug 01 05:39:19 PM PDT 24
Finished Aug 01 05:39:59 PM PDT 24
Peak memory 211676 kb
Host smart-91e50169-0e97-4b3f-8fb3-4d58bb5f3b46
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498505241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2498505241
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.2501789540
Short name T234
Test name
Test status
Simulation time 18748954655 ps
CPU time 164.28 seconds
Started Aug 01 05:39:18 PM PDT 24
Finished Aug 01 05:42:02 PM PDT 24
Peak memory 211732 kb
Host smart-6538870e-ae98-423f-9afc-d1a9e7a841ad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2501789540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2501789540
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.2747480512
Short name T798
Test name
Test status
Simulation time 213717096 ps
CPU time 20.82 seconds
Started Aug 01 05:39:21 PM PDT 24
Finished Aug 01 05:39:42 PM PDT 24
Peak memory 211640 kb
Host smart-e58b1a21-70e1-4235-ac46-9589af69a58e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747480512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.2747480512
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.3532236374
Short name T775
Test name
Test status
Simulation time 41163615 ps
CPU time 3.23 seconds
Started Aug 01 05:39:19 PM PDT 24
Finished Aug 01 05:39:23 PM PDT 24
Peak memory 203532 kb
Host smart-802a7591-b083-4cb8-b986-9a29eae1b929
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3532236374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3532236374
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke.3880200843
Short name T817
Test name
Test status
Simulation time 354652062 ps
CPU time 3.21 seconds
Started Aug 01 05:39:02 PM PDT 24
Finished Aug 01 05:39:06 PM PDT 24
Peak memory 203488 kb
Host smart-4fab5e4f-288a-4c93-a792-93f61410367b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3880200843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3880200843
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1867978096
Short name T51
Test name
Test status
Simulation time 6353211673 ps
CPU time 31.33 seconds
Started Aug 01 05:38:59 PM PDT 24
Finished Aug 01 05:39:31 PM PDT 24
Peak memory 203452 kb
Host smart-921b39d2-c29a-45d7-a1cd-313e73f2e7d5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867978096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1867978096
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1731463841
Short name T13
Test name
Test status
Simulation time 6199931796 ps
CPU time 26.49 seconds
Started Aug 01 05:39:04 PM PDT 24
Finished Aug 01 05:39:31 PM PDT 24
Peak memory 203560 kb
Host smart-5e8856ec-a751-4a97-8438-78720d44e770
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1731463841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1731463841
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3336307457
Short name T135
Test name
Test status
Simulation time 34899098 ps
CPU time 2.55 seconds
Started Aug 01 05:39:02 PM PDT 24
Finished Aug 01 05:39:05 PM PDT 24
Peak memory 203472 kb
Host smart-17f0be9e-b834-4436-b2b5-810b7024c693
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336307457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.3336307457
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.2153048099
Short name T669
Test name
Test status
Simulation time 24601013011 ps
CPU time 105.8 seconds
Started Aug 01 05:39:16 PM PDT 24
Finished Aug 01 05:41:02 PM PDT 24
Peak memory 206264 kb
Host smart-62b53497-4341-4216-91a8-58bf6787fe20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2153048099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.2153048099
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.138866298
Short name T115
Test name
Test status
Simulation time 2455497031 ps
CPU time 53.58 seconds
Started Aug 01 05:39:20 PM PDT 24
Finished Aug 01 05:40:14 PM PDT 24
Peak memory 206044 kb
Host smart-6b474ca7-c521-4c93-8ba3-ca67ac0920c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=138866298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.138866298
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.2521239886
Short name T186
Test name
Test status
Simulation time 1171937509 ps
CPU time 234.63 seconds
Started Aug 01 05:39:18 PM PDT 24
Finished Aug 01 05:43:13 PM PDT 24
Peak memory 209360 kb
Host smart-5fbbf900-b127-4825-958c-ea633f90182d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2521239886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran
d_reset.2521239886
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2702236295
Short name T285
Test name
Test status
Simulation time 1552732280 ps
CPU time 123.59 seconds
Started Aug 01 05:39:20 PM PDT 24
Finished Aug 01 05:41:24 PM PDT 24
Peak memory 210132 kb
Host smart-b1c64f1d-0902-46ea-9a54-895e1935a798
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2702236295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re
set_error.2702236295
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.1515060092
Short name T392
Test name
Test status
Simulation time 332861949 ps
CPU time 10.34 seconds
Started Aug 01 05:39:18 PM PDT 24
Finished Aug 01 05:39:29 PM PDT 24
Peak memory 204984 kb
Host smart-5b7071e4-0692-4535-9995-a8cc3081898b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1515060092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1515060092
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.2611488685
Short name T291
Test name
Test status
Simulation time 270521719 ps
CPU time 7.74 seconds
Started Aug 01 05:39:19 PM PDT 24
Finished Aug 01 05:39:26 PM PDT 24
Peak memory 203412 kb
Host smart-9a3fd44f-fbf5-4d6b-b297-798f5f34e274
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2611488685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.2611488685
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1377042875
Short name T287
Test name
Test status
Simulation time 119699079 ps
CPU time 9.64 seconds
Started Aug 01 05:39:19 PM PDT 24
Finished Aug 01 05:39:29 PM PDT 24
Peak memory 203500 kb
Host smart-93927b98-8588-44d5-895d-4bc48941b333
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1377042875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.1377042875
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.503128150
Short name T549
Test name
Test status
Simulation time 22769733 ps
CPU time 1.99 seconds
Started Aug 01 05:39:20 PM PDT 24
Finished Aug 01 05:39:22 PM PDT 24
Peak memory 203496 kb
Host smart-31b066c6-f842-4fe0-99d5-194f4fe36173
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=503128150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.503128150
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.4062557192
Short name T694
Test name
Test status
Simulation time 107729584 ps
CPU time 8.35 seconds
Started Aug 01 05:39:18 PM PDT 24
Finished Aug 01 05:39:27 PM PDT 24
Peak memory 211664 kb
Host smart-cddfd81c-5baa-46b3-b7c5-3f9684cfc4be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4062557192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.4062557192
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.2216347638
Short name T210
Test name
Test status
Simulation time 33774951378 ps
CPU time 179.86 seconds
Started Aug 01 05:39:18 PM PDT 24
Finished Aug 01 05:42:18 PM PDT 24
Peak memory 211780 kb
Host smart-a87e920d-ac0d-4cff-8530-0eb642872282
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216347638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2216347638
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2729959110
Short name T697
Test name
Test status
Simulation time 35639059861 ps
CPU time 145.48 seconds
Started Aug 01 05:39:18 PM PDT 24
Finished Aug 01 05:41:44 PM PDT 24
Peak memory 205292 kb
Host smart-c3d254a5-7ccb-4e64-832b-7a5bf460beda
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2729959110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2729959110
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.4034770971
Short name T346
Test name
Test status
Simulation time 182690377 ps
CPU time 24.85 seconds
Started Aug 01 05:39:27 PM PDT 24
Finished Aug 01 05:39:51 PM PDT 24
Peak memory 211652 kb
Host smart-01bd4905-4e2f-454b-84e2-444a99b140cc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034770971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.4034770971
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.3454269203
Short name T886
Test name
Test status
Simulation time 148036153 ps
CPU time 4.78 seconds
Started Aug 01 05:39:18 PM PDT 24
Finished Aug 01 05:39:23 PM PDT 24
Peak memory 203432 kb
Host smart-ea1e78ed-6717-455c-87d6-25a8ebbec0e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3454269203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3454269203
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.2736139589
Short name T193
Test name
Test status
Simulation time 435528921 ps
CPU time 3.96 seconds
Started Aug 01 05:39:22 PM PDT 24
Finished Aug 01 05:39:26 PM PDT 24
Peak memory 203356 kb
Host smart-4bf07b96-04e1-4bf7-9f3b-810bd5719d7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2736139589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2736139589
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.3055744391
Short name T880
Test name
Test status
Simulation time 5672930278 ps
CPU time 31.74 seconds
Started Aug 01 05:39:19 PM PDT 24
Finished Aug 01 05:39:51 PM PDT 24
Peak memory 203516 kb
Host smart-a32e0610-3c44-474e-b282-396f86a1bfaa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055744391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.3055744391
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.473851860
Short name T856
Test name
Test status
Simulation time 3929552929 ps
CPU time 23.62 seconds
Started Aug 01 05:39:17 PM PDT 24
Finished Aug 01 05:39:40 PM PDT 24
Peak memory 203440 kb
Host smart-0358c144-c053-4b9d-9f56-f6fe1ef8e29c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=473851860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.473851860
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.422063671
Short name T785
Test name
Test status
Simulation time 98611756 ps
CPU time 2.28 seconds
Started Aug 01 05:39:18 PM PDT 24
Finished Aug 01 05:39:21 PM PDT 24
Peak memory 203472 kb
Host smart-19b6eee3-5ef3-415b-a4dd-c9414a026c21
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422063671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.422063671
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all.3070534818
Short name T544
Test name
Test status
Simulation time 3901776175 ps
CPU time 45.49 seconds
Started Aug 01 05:39:17 PM PDT 24
Finished Aug 01 05:40:03 PM PDT 24
Peak memory 206804 kb
Host smart-854f8b70-f286-4948-bb17-a402188ac30e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3070534818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3070534818
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.4136275736
Short name T425
Test name
Test status
Simulation time 1649476109 ps
CPU time 82.02 seconds
Started Aug 01 05:39:21 PM PDT 24
Finished Aug 01 05:40:43 PM PDT 24
Peak memory 206764 kb
Host smart-cc71381b-316c-4656-9bf2-045a9b19c12d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4136275736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.4136275736
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.3670256676
Short name T17
Test name
Test status
Simulation time 2294091518 ps
CPU time 377.22 seconds
Started Aug 01 05:39:19 PM PDT 24
Finished Aug 01 05:45:36 PM PDT 24
Peak memory 211736 kb
Host smart-fe460b7d-bee3-4c59-958e-7c316a9bb7a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3670256676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran
d_reset.3670256676
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1692531333
Short name T492
Test name
Test status
Simulation time 1139872497 ps
CPU time 175.84 seconds
Started Aug 01 05:39:19 PM PDT 24
Finished Aug 01 05:42:15 PM PDT 24
Peak memory 211148 kb
Host smart-9798b9ab-e133-44d7-93e8-5dc7e5ba620b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1692531333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re
set_error.1692531333
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.3137875480
Short name T1
Test name
Test status
Simulation time 811281007 ps
CPU time 21.99 seconds
Started Aug 01 05:39:19 PM PDT 24
Finished Aug 01 05:39:41 PM PDT 24
Peak memory 211536 kb
Host smart-70d27502-199e-46f2-89d2-8ef998d947dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3137875480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3137875480
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.1363184248
Short name T567
Test name
Test status
Simulation time 1228428662 ps
CPU time 27.65 seconds
Started Aug 01 05:39:20 PM PDT 24
Finished Aug 01 05:39:48 PM PDT 24
Peak memory 205560 kb
Host smart-8f4c289b-21ca-4498-b0c5-9603a8385c8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1363184248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.1363184248
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1992911002
Short name T360
Test name
Test status
Simulation time 19235252412 ps
CPU time 186.24 seconds
Started Aug 01 05:39:18 PM PDT 24
Finished Aug 01 05:42:25 PM PDT 24
Peak memory 206220 kb
Host smart-4d7f32df-3262-417e-8be5-114a509fa6b2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1992911002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl
ow_rsp.1992911002
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2466857235
Short name T22
Test name
Test status
Simulation time 98936133 ps
CPU time 12.56 seconds
Started Aug 01 05:39:21 PM PDT 24
Finished Aug 01 05:39:33 PM PDT 24
Peak memory 203432 kb
Host smart-91b48dce-71af-4c34-9859-d12119fd2395
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2466857235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2466857235
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.1969606340
Short name T152
Test name
Test status
Simulation time 401075264 ps
CPU time 10.62 seconds
Started Aug 01 05:39:27 PM PDT 24
Finished Aug 01 05:39:38 PM PDT 24
Peak memory 203504 kb
Host smart-b72fc493-8358-46e6-9579-be8fb38013f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1969606340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1969606340
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.2127542026
Short name T372
Test name
Test status
Simulation time 67821151 ps
CPU time 7.1 seconds
Started Aug 01 05:39:19 PM PDT 24
Finished Aug 01 05:39:27 PM PDT 24
Peak memory 204528 kb
Host smart-f09a466b-a161-4485-95bd-633f2230274d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2127542026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2127542026
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.1675821979
Short name T864
Test name
Test status
Simulation time 54885227132 ps
CPU time 179.44 seconds
Started Aug 01 05:39:21 PM PDT 24
Finished Aug 01 05:42:21 PM PDT 24
Peak memory 205432 kb
Host smart-4dfe26d2-2860-4936-8fbc-884d522da103
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675821979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1675821979
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.4263632496
Short name T897
Test name
Test status
Simulation time 32643472486 ps
CPU time 206.39 seconds
Started Aug 01 05:39:20 PM PDT 24
Finished Aug 01 05:42:47 PM PDT 24
Peak memory 211740 kb
Host smart-f392d858-ef8f-4ed4-acaa-6c1e424cc335
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4263632496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.4263632496
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.1209758616
Short name T288
Test name
Test status
Simulation time 187135430 ps
CPU time 27.41 seconds
Started Aug 01 05:39:19 PM PDT 24
Finished Aug 01 05:39:47 PM PDT 24
Peak memory 211668 kb
Host smart-4b3411e9-e252-42ae-bb58-23a1565b3479
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209758616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.1209758616
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.2112778249
Short name T42
Test name
Test status
Simulation time 1152025460 ps
CPU time 27.26 seconds
Started Aug 01 05:39:19 PM PDT 24
Finished Aug 01 05:39:47 PM PDT 24
Peak memory 204052 kb
Host smart-c694c14d-a7cb-498e-9f77-40489a8d6d5b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2112778249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2112778249
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.1449455071
Short name T524
Test name
Test status
Simulation time 109315857 ps
CPU time 3.43 seconds
Started Aug 01 05:39:20 PM PDT 24
Finished Aug 01 05:39:23 PM PDT 24
Peak memory 203484 kb
Host smart-652b07eb-a9a1-4ea9-b3f7-166bfb135998
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1449455071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1449455071
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1925325822
Short name T305
Test name
Test status
Simulation time 22414767883 ps
CPU time 35.71 seconds
Started Aug 01 05:39:28 PM PDT 24
Finished Aug 01 05:40:04 PM PDT 24
Peak memory 203556 kb
Host smart-d3dedace-469b-4a86-ad33-0816d1ec6230
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925325822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1925325822
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1336195890
Short name T699
Test name
Test status
Simulation time 9188342189 ps
CPU time 35.61 seconds
Started Aug 01 05:39:17 PM PDT 24
Finished Aug 01 05:39:52 PM PDT 24
Peak memory 203540 kb
Host smart-e0e56810-6d25-4c1b-a75c-1c35f9669b07
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1336195890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1336195890
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.2843071446
Short name T24
Test name
Test status
Simulation time 39986723 ps
CPU time 2.15 seconds
Started Aug 01 05:39:20 PM PDT 24
Finished Aug 01 05:39:22 PM PDT 24
Peak memory 203452 kb
Host smart-efc390df-08e4-4855-af9e-7135df3d677e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843071446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.2843071446
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.1792971816
Short name T200
Test name
Test status
Simulation time 1726006002 ps
CPU time 101.66 seconds
Started Aug 01 05:39:28 PM PDT 24
Finished Aug 01 05:41:10 PM PDT 24
Peak memory 209244 kb
Host smart-89ae7e04-f1f4-4006-8b4f-76b619f3cdb5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1792971816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1792971816
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1023579817
Short name T489
Test name
Test status
Simulation time 29022530531 ps
CPU time 224.25 seconds
Started Aug 01 05:39:20 PM PDT 24
Finished Aug 01 05:43:05 PM PDT 24
Peak memory 206852 kb
Host smart-ce787e78-2b94-4700-95a3-bffe83fde065
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1023579817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1023579817
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.3952571886
Short name T671
Test name
Test status
Simulation time 682467826 ps
CPU time 270.81 seconds
Started Aug 01 05:39:18 PM PDT 24
Finished Aug 01 05:43:49 PM PDT 24
Peak memory 209228 kb
Host smart-78048832-92d6-46d9-be04-4714290ce704
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3952571886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran
d_reset.3952571886
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.1032284913
Short name T830
Test name
Test status
Simulation time 161509406 ps
CPU time 22.14 seconds
Started Aug 01 05:39:33 PM PDT 24
Finished Aug 01 05:39:56 PM PDT 24
Peak memory 205824 kb
Host smart-97f3700e-5e17-44e3-828a-130e2ec61f92
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1032284913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re
set_error.1032284913
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.3704101421
Short name T281
Test name
Test status
Simulation time 525157070 ps
CPU time 14.39 seconds
Started Aug 01 05:39:21 PM PDT 24
Finished Aug 01 05:39:36 PM PDT 24
Peak memory 211648 kb
Host smart-9296f5e2-fb30-4e9e-a9c9-838a7c51a26d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3704101421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.3704101421
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.1410489926
Short name T589
Test name
Test status
Simulation time 367063452 ps
CPU time 43.72 seconds
Started Aug 01 05:39:39 PM PDT 24
Finished Aug 01 05:40:23 PM PDT 24
Peak memory 205272 kb
Host smart-5970e94a-eca9-4790-b234-5a99e7df99cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1410489926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1410489926
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3749631995
Short name T86
Test name
Test status
Simulation time 55360358124 ps
CPU time 313.56 seconds
Started Aug 01 05:39:34 PM PDT 24
Finished Aug 01 05:44:47 PM PDT 24
Peak memory 211712 kb
Host smart-f7a0b011-fb82-4d7a-b7fd-147a9a88fb2e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3749631995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl
ow_rsp.3749631995
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2841333326
Short name T390
Test name
Test status
Simulation time 33119839 ps
CPU time 5.16 seconds
Started Aug 01 05:39:32 PM PDT 24
Finished Aug 01 05:39:37 PM PDT 24
Peak memory 203704 kb
Host smart-5576f1c4-6126-41be-a098-0b7d81a48818
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2841333326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2841333326
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.1392056094
Short name T320
Test name
Test status
Simulation time 775270766 ps
CPU time 19.32 seconds
Started Aug 01 05:39:33 PM PDT 24
Finished Aug 01 05:39:53 PM PDT 24
Peak memory 203384 kb
Host smart-be3fed13-b0a5-40b5-ad3d-44a6ea8bc7c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1392056094 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1392056094
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.669842871
Short name T707
Test name
Test status
Simulation time 1788148713 ps
CPU time 15.46 seconds
Started Aug 01 05:39:35 PM PDT 24
Finished Aug 01 05:39:51 PM PDT 24
Peak memory 211688 kb
Host smart-db3eba25-edb9-4404-9333-1e2d74bc0700
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=669842871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.669842871
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.3154547090
Short name T837
Test name
Test status
Simulation time 14103299535 ps
CPU time 75.93 seconds
Started Aug 01 05:39:33 PM PDT 24
Finished Aug 01 05:40:49 PM PDT 24
Peak memory 204808 kb
Host smart-e221a156-eae7-4006-ba50-d2939875e66f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154547090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3154547090
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1900137804
Short name T170
Test name
Test status
Simulation time 53278867535 ps
CPU time 184.45 seconds
Started Aug 01 05:39:35 PM PDT 24
Finished Aug 01 05:42:40 PM PDT 24
Peak memory 204996 kb
Host smart-e47d93e7-572f-40a9-bc31-ce61c69b2c26
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1900137804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1900137804
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.3776017311
Short name T876
Test name
Test status
Simulation time 133951580 ps
CPU time 13.61 seconds
Started Aug 01 05:39:36 PM PDT 24
Finished Aug 01 05:39:50 PM PDT 24
Peak memory 211648 kb
Host smart-a3a65725-c180-4aa2-a47d-9d74bc0a0ac8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776017311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.3776017311
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.3964408278
Short name T649
Test name
Test status
Simulation time 58563816 ps
CPU time 4.86 seconds
Started Aug 01 05:39:34 PM PDT 24
Finished Aug 01 05:39:39 PM PDT 24
Peak memory 204072 kb
Host smart-b1223ca8-2b91-42ef-9936-d58d8cdcdc98
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3964408278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3964408278
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.2578388528
Short name T56
Test name
Test status
Simulation time 185340584 ps
CPU time 3.96 seconds
Started Aug 01 05:39:36 PM PDT 24
Finished Aug 01 05:39:40 PM PDT 24
Peak memory 203460 kb
Host smart-9f074d46-bcb0-4c30-b2fa-9236d31491a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2578388528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2578388528
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2642470493
Short name T342
Test name
Test status
Simulation time 7548326739 ps
CPU time 31.73 seconds
Started Aug 01 05:39:34 PM PDT 24
Finished Aug 01 05:40:06 PM PDT 24
Peak memory 203532 kb
Host smart-41ac2f0d-1660-48dd-953f-d1a6cdd86b5f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642470493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2642470493
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2328905028
Short name T599
Test name
Test status
Simulation time 3842556884 ps
CPU time 23.78 seconds
Started Aug 01 05:39:31 PM PDT 24
Finished Aug 01 05:39:55 PM PDT 24
Peak memory 203492 kb
Host smart-9f706765-3bd7-4d6c-8097-ed7cc4a167f7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2328905028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2328905028
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1278081013
Short name T868
Test name
Test status
Simulation time 29387534 ps
CPU time 1.88 seconds
Started Aug 01 05:39:35 PM PDT 24
Finished Aug 01 05:39:37 PM PDT 24
Peak memory 203468 kb
Host smart-0e7e1822-1c72-410d-94bd-1535c58c9a4e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278081013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1278081013
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.3137476034
Short name T885
Test name
Test status
Simulation time 2862647920 ps
CPU time 40.69 seconds
Started Aug 01 05:39:32 PM PDT 24
Finished Aug 01 05:40:13 PM PDT 24
Peak memory 205556 kb
Host smart-1e534e6e-7e69-480e-99e1-09166fdf9627
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3137476034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3137476034
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.627273433
Short name T893
Test name
Test status
Simulation time 302104724 ps
CPU time 41.3 seconds
Started Aug 01 05:39:33 PM PDT 24
Finished Aug 01 05:40:15 PM PDT 24
Peak memory 205312 kb
Host smart-aa43f1cd-65ad-4709-a192-506e62261ace
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=627273433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.627273433
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3387275033
Short name T262
Test name
Test status
Simulation time 132548521 ps
CPU time 27.37 seconds
Started Aug 01 05:39:33 PM PDT 24
Finished Aug 01 05:40:01 PM PDT 24
Peak memory 206664 kb
Host smart-1d393926-6007-4c57-8a6b-ad2bfef00c1e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3387275033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran
d_reset.3387275033
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2568922905
Short name T854
Test name
Test status
Simulation time 5162817959 ps
CPU time 348.01 seconds
Started Aug 01 05:39:36 PM PDT 24
Finished Aug 01 05:45:24 PM PDT 24
Peak memory 211592 kb
Host smart-c40c5d6a-73f9-474f-8d17-bbcf031c9099
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2568922905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re
set_error.2568922905
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.495317246
Short name T500
Test name
Test status
Simulation time 45826052 ps
CPU time 3.87 seconds
Started Aug 01 05:39:33 PM PDT 24
Finished Aug 01 05:39:37 PM PDT 24
Peak memory 211576 kb
Host smart-baf7b763-761f-4381-a35d-87a0297ee5ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=495317246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.495317246
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.3826118662
Short name T896
Test name
Test status
Simulation time 3015062411 ps
CPU time 22.48 seconds
Started Aug 01 05:39:34 PM PDT 24
Finished Aug 01 05:39:57 PM PDT 24
Peak memory 203500 kb
Host smart-5d7c724f-eef1-4561-be87-aa801fdf39f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3826118662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3826118662
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2249446501
Short name T894
Test name
Test status
Simulation time 3904014940 ps
CPU time 26.99 seconds
Started Aug 01 05:39:35 PM PDT 24
Finished Aug 01 05:40:03 PM PDT 24
Peak memory 203548 kb
Host smart-6775cb5b-66d5-4971-818d-12a3edff6e9f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2249446501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl
ow_rsp.2249446501
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.818242418
Short name T217
Test name
Test status
Simulation time 632797729 ps
CPU time 16.75 seconds
Started Aug 01 05:39:33 PM PDT 24
Finished Aug 01 05:39:50 PM PDT 24
Peak memory 203404 kb
Host smart-b3af5f2d-3a20-4b23-bf43-a05c1a4ef6fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=818242418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.818242418
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.595691395
Short name T889
Test name
Test status
Simulation time 1103603704 ps
CPU time 28.08 seconds
Started Aug 01 05:39:35 PM PDT 24
Finished Aug 01 05:40:03 PM PDT 24
Peak memory 203512 kb
Host smart-0ade0f47-7150-4705-8b9b-15bc4893617e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=595691395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.595691395
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.3602800192
Short name T18
Test name
Test status
Simulation time 102757565 ps
CPU time 9.71 seconds
Started Aug 01 05:39:36 PM PDT 24
Finished Aug 01 05:39:46 PM PDT 24
Peak memory 204580 kb
Host smart-ce76add5-2954-43d9-b07b-aeb1611c78e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3602800192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.3602800192
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.4137081511
Short name T124
Test name
Test status
Simulation time 58674966408 ps
CPU time 210.48 seconds
Started Aug 01 05:39:32 PM PDT 24
Finished Aug 01 05:43:03 PM PDT 24
Peak memory 211728 kb
Host smart-210f1d3d-626c-4196-9c42-23f52e754149
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137081511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.4137081511
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.4071602513
Short name T191
Test name
Test status
Simulation time 55115459122 ps
CPU time 104.15 seconds
Started Aug 01 05:39:35 PM PDT 24
Finished Aug 01 05:41:20 PM PDT 24
Peak memory 211736 kb
Host smart-38e2cb89-a6d7-4cfd-bd56-f2005c33182d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4071602513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.4071602513
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.222085786
Short name T862
Test name
Test status
Simulation time 145616396 ps
CPU time 17.12 seconds
Started Aug 01 05:39:35 PM PDT 24
Finished Aug 01 05:39:52 PM PDT 24
Peak memory 211652 kb
Host smart-a095c9fd-3309-414b-8972-3338cc000f0c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222085786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.222085786
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.1470089903
Short name T378
Test name
Test status
Simulation time 2601143800 ps
CPU time 27.02 seconds
Started Aug 01 05:39:34 PM PDT 24
Finished Aug 01 05:40:01 PM PDT 24
Peak memory 203468 kb
Host smart-c789d854-60d0-4842-9c4b-f2e12fa904cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1470089903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1470089903
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.470844989
Short name T711
Test name
Test status
Simulation time 125790076 ps
CPU time 2.11 seconds
Started Aug 01 05:39:37 PM PDT 24
Finished Aug 01 05:39:40 PM PDT 24
Peak memory 203340 kb
Host smart-63edf2e9-d61d-4b57-a5ec-e03139737274
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=470844989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.470844989
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.4290066277
Short name T46
Test name
Test status
Simulation time 9155567785 ps
CPU time 30.63 seconds
Started Aug 01 05:39:39 PM PDT 24
Finished Aug 01 05:40:09 PM PDT 24
Peak memory 203540 kb
Host smart-51278845-d568-4404-b302-8555d588580d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290066277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.4290066277
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.98038951
Short name T50
Test name
Test status
Simulation time 2768601730 ps
CPU time 25.32 seconds
Started Aug 01 05:39:34 PM PDT 24
Finished Aug 01 05:39:59 PM PDT 24
Peak memory 203508 kb
Host smart-d2bab2fc-ced5-4307-956e-a3c4b38d4ecb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=98038951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.98038951
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.3804917646
Short name T388
Test name
Test status
Simulation time 58796960 ps
CPU time 2.07 seconds
Started Aug 01 05:39:35 PM PDT 24
Finished Aug 01 05:39:37 PM PDT 24
Peak memory 203480 kb
Host smart-a7c93941-fbae-46dc-ba0f-2f37a64b15d7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804917646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.3804917646
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.302863009
Short name T377
Test name
Test status
Simulation time 3074212264 ps
CPU time 111.73 seconds
Started Aug 01 05:39:33 PM PDT 24
Finished Aug 01 05:41:25 PM PDT 24
Peak memory 208688 kb
Host smart-e7f34f68-773a-414e-9145-c147715b463f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=302863009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.302863009
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.4151719304
Short name T578
Test name
Test status
Simulation time 8930448197 ps
CPU time 53.24 seconds
Started Aug 01 05:39:33 PM PDT 24
Finished Aug 01 05:40:27 PM PDT 24
Peak memory 205684 kb
Host smart-fe2c12a6-1f04-4223-90b2-19ede0a595ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4151719304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.4151719304
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2281498890
Short name T27
Test name
Test status
Simulation time 5720841237 ps
CPU time 416.17 seconds
Started Aug 01 05:39:32 PM PDT 24
Finished Aug 01 05:46:28 PM PDT 24
Peak memory 219956 kb
Host smart-00d0f979-804e-47b9-b8e8-94a3753273d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2281498890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran
d_reset.2281498890
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1045739680
Short name T518
Test name
Test status
Simulation time 8270187540 ps
CPU time 387.93 seconds
Started Aug 01 05:39:32 PM PDT 24
Finished Aug 01 05:46:00 PM PDT 24
Peak memory 220008 kb
Host smart-be5507a8-d578-4b83-a651-9ba3a871193d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1045739680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re
set_error.1045739680
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.1510147916
Short name T702
Test name
Test status
Simulation time 1410689875 ps
CPU time 20.86 seconds
Started Aug 01 05:39:39 PM PDT 24
Finished Aug 01 05:40:00 PM PDT 24
Peak memory 211664 kb
Host smart-71c88cb1-1ce2-4f8b-ab4c-1b5bceea0c39
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1510147916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.1510147916
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.2651373376
Short name T532
Test name
Test status
Simulation time 285337365 ps
CPU time 32.89 seconds
Started Aug 01 05:39:32 PM PDT 24
Finished Aug 01 05:40:05 PM PDT 24
Peak memory 211644 kb
Host smart-58329fc7-0d12-4dc3-a777-8242f3064a25
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2651373376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2651373376
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2260070658
Short name T592
Test name
Test status
Simulation time 90190490 ps
CPU time 6.76 seconds
Started Aug 01 05:39:33 PM PDT 24
Finished Aug 01 05:39:40 PM PDT 24
Peak memory 203400 kb
Host smart-af4cc700-13a8-46fd-8bed-cf52cb76644a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2260070658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.2260070658
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.2026262895
Short name T483
Test name
Test status
Simulation time 590169633 ps
CPU time 17.21 seconds
Started Aug 01 05:39:37 PM PDT 24
Finished Aug 01 05:39:55 PM PDT 24
Peak memory 203548 kb
Host smart-4de1423a-c90c-4cd7-bccb-f04a02dd3aef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2026262895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2026262895
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.2624746370
Short name T105
Test name
Test status
Simulation time 95086688 ps
CPU time 13.54 seconds
Started Aug 01 05:39:34 PM PDT 24
Finished Aug 01 05:39:48 PM PDT 24
Peak memory 204584 kb
Host smart-ddd1b01e-11f4-4c64-a06b-51c7f2ff8485
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2624746370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.2624746370
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.2235518396
Short name T118
Test name
Test status
Simulation time 47464683354 ps
CPU time 225.29 seconds
Started Aug 01 05:39:35 PM PDT 24
Finished Aug 01 05:43:20 PM PDT 24
Peak memory 211592 kb
Host smart-95e275c0-43ae-4e2a-a7fc-58a5f2c8a54e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235518396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2235518396
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3989656013
Short name T824
Test name
Test status
Simulation time 8565336234 ps
CPU time 60.89 seconds
Started Aug 01 05:39:33 PM PDT 24
Finished Aug 01 05:40:34 PM PDT 24
Peak memory 205056 kb
Host smart-c8ada958-e31f-48e2-b668-c897022cba6d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3989656013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3989656013
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.1758239689
Short name T355
Test name
Test status
Simulation time 399897628 ps
CPU time 21.79 seconds
Started Aug 01 05:39:36 PM PDT 24
Finished Aug 01 05:39:58 PM PDT 24
Peak memory 204992 kb
Host smart-9ce5f1b0-38cf-4a8f-adaa-f210dac487b7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758239689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.1758239689
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.4138903993
Short name T677
Test name
Test status
Simulation time 78480753 ps
CPU time 6.4 seconds
Started Aug 01 05:39:37 PM PDT 24
Finished Aug 01 05:39:44 PM PDT 24
Peak memory 204084 kb
Host smart-9bec6dce-d4e5-4beb-9572-34a5bc499b45
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4138903993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.4138903993
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.2257218062
Short name T239
Test name
Test status
Simulation time 72473279 ps
CPU time 2.72 seconds
Started Aug 01 05:39:33 PM PDT 24
Finished Aug 01 05:39:36 PM PDT 24
Peak memory 203332 kb
Host smart-421be40f-764f-48ca-b983-61313c6edae2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2257218062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2257218062
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1333946377
Short name T73
Test name
Test status
Simulation time 23974884740 ps
CPU time 38.91 seconds
Started Aug 01 05:39:36 PM PDT 24
Finished Aug 01 05:40:15 PM PDT 24
Peak memory 203412 kb
Host smart-211e4b36-2d18-4fd8-b1b9-a6dd080e4dc0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333946377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1333946377
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.2191408633
Short name T774
Test name
Test status
Simulation time 4880403424 ps
CPU time 35.83 seconds
Started Aug 01 05:39:39 PM PDT 24
Finished Aug 01 05:40:15 PM PDT 24
Peak memory 203548 kb
Host smart-218df7c3-1996-48fc-9c8c-e95e98bb28be
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2191408633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.2191408633
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1087992858
Short name T596
Test name
Test status
Simulation time 137193259 ps
CPU time 2.33 seconds
Started Aug 01 05:39:33 PM PDT 24
Finished Aug 01 05:39:36 PM PDT 24
Peak memory 203456 kb
Host smart-7a72c618-c21f-4fe3-850b-8d21f8d8c6ff
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087992858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1087992858
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.3531981075
Short name T476
Test name
Test status
Simulation time 31147983523 ps
CPU time 279.57 seconds
Started Aug 01 05:39:38 PM PDT 24
Finished Aug 01 05:44:18 PM PDT 24
Peak memory 211268 kb
Host smart-fb979bec-4afb-4f13-ba52-4331ec8c979f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3531981075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3531981075
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.890784478
Short name T674
Test name
Test status
Simulation time 17558860829 ps
CPU time 224.47 seconds
Started Aug 01 05:39:38 PM PDT 24
Finished Aug 01 05:43:23 PM PDT 24
Peak memory 209976 kb
Host smart-b2c98aec-4a0e-45ad-aad5-3cef39dfff8a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=890784478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.890784478
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3366665301
Short name T609
Test name
Test status
Simulation time 280524781 ps
CPU time 69.44 seconds
Started Aug 01 05:39:39 PM PDT 24
Finished Aug 01 05:40:48 PM PDT 24
Peak memory 208076 kb
Host smart-ddb1a87e-ab22-4858-9a1d-6854398802c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3366665301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran
d_reset.3366665301
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.284476654
Short name T763
Test name
Test status
Simulation time 2825423847 ps
CPU time 406.59 seconds
Started Aug 01 05:39:37 PM PDT 24
Finished Aug 01 05:46:24 PM PDT 24
Peak memory 219952 kb
Host smart-1ec193a1-a6fb-43cd-8c0e-8776c81f7e09
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=284476654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_res
et_error.284476654
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.2678596344
Short name T540
Test name
Test status
Simulation time 639730144 ps
CPU time 30.32 seconds
Started Aug 01 05:39:35 PM PDT 24
Finished Aug 01 05:40:06 PM PDT 24
Peak memory 204948 kb
Host smart-36b0e223-e49a-4de6-9718-2f5ce3c1d07e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2678596344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2678596344
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.2902984022
Short name T220
Test name
Test status
Simulation time 93002688 ps
CPU time 11.54 seconds
Started Aug 01 05:36:31 PM PDT 24
Finished Aug 01 05:36:42 PM PDT 24
Peak memory 211732 kb
Host smart-44939ad6-097c-4b2f-a335-e140123740ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2902984022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.2902984022
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3037505978
Short name T752
Test name
Test status
Simulation time 20731782453 ps
CPU time 201.06 seconds
Started Aug 01 05:36:31 PM PDT 24
Finished Aug 01 05:39:52 PM PDT 24
Peak memory 211664 kb
Host smart-db2f65aa-f066-48ed-a235-2929e21f7b75
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3037505978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo
w_rsp.3037505978
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.2350258969
Short name T672
Test name
Test status
Simulation time 143140382 ps
CPU time 4.49 seconds
Started Aug 01 05:36:31 PM PDT 24
Finished Aug 01 05:36:36 PM PDT 24
Peak memory 203692 kb
Host smart-8922018b-4f9e-4782-9ad6-1333c39d0569
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2350258969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.2350258969
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.2486868578
Short name T326
Test name
Test status
Simulation time 579315443 ps
CPU time 25.45 seconds
Started Aug 01 05:36:34 PM PDT 24
Finished Aug 01 05:37:00 PM PDT 24
Peak memory 203480 kb
Host smart-af666943-a165-4dc6-b169-550b4da07b9c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2486868578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2486868578
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.240923706
Short name T654
Test name
Test status
Simulation time 212477483 ps
CPU time 24.62 seconds
Started Aug 01 05:36:29 PM PDT 24
Finished Aug 01 05:36:54 PM PDT 24
Peak memory 211584 kb
Host smart-3c47d635-e9e5-40e7-ae0f-e6ab13d4b4dd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=240923706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.240923706
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.1678952774
Short name T438
Test name
Test status
Simulation time 9001993652 ps
CPU time 35.11 seconds
Started Aug 01 05:36:31 PM PDT 24
Finished Aug 01 05:37:07 PM PDT 24
Peak memory 211548 kb
Host smart-7efe798f-6cab-4b08-8acb-1c64e8cc877f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678952774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1678952774
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.947698212
Short name T94
Test name
Test status
Simulation time 24031724617 ps
CPU time 176.28 seconds
Started Aug 01 05:36:34 PM PDT 24
Finished Aug 01 05:39:30 PM PDT 24
Peak memory 211656 kb
Host smart-db4f4ba9-c9a6-4090-9dc0-30e1bd38bc25
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=947698212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.947698212
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.777516631
Short name T612
Test name
Test status
Simulation time 36536531 ps
CPU time 5.28 seconds
Started Aug 01 05:36:31 PM PDT 24
Finished Aug 01 05:36:37 PM PDT 24
Peak memory 211672 kb
Host smart-e345171f-3929-4179-b50e-138182b960fc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777516631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.777516631
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.1840274222
Short name T446
Test name
Test status
Simulation time 864662063 ps
CPU time 19.77 seconds
Started Aug 01 05:36:36 PM PDT 24
Finished Aug 01 05:36:56 PM PDT 24
Peak memory 203916 kb
Host smart-6b197e1e-a985-4c41-bb7c-1641175e7466
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1840274222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1840274222
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.3635702434
Short name T451
Test name
Test status
Simulation time 240002619 ps
CPU time 3.53 seconds
Started Aug 01 05:36:31 PM PDT 24
Finished Aug 01 05:36:34 PM PDT 24
Peak memory 203420 kb
Host smart-c015fd3f-3cba-4705-8011-403fdccfcf5b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3635702434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3635702434
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.1277297930
Short name T728
Test name
Test status
Simulation time 7396190834 ps
CPU time 28.66 seconds
Started Aug 01 05:36:39 PM PDT 24
Finished Aug 01 05:37:08 PM PDT 24
Peak memory 203608 kb
Host smart-5e9727e2-1b90-46fd-ab27-1b6fc972b20a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277297930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.1277297930
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.4159542060
Short name T162
Test name
Test status
Simulation time 5645962946 ps
CPU time 26.83 seconds
Started Aug 01 05:36:31 PM PDT 24
Finished Aug 01 05:36:58 PM PDT 24
Peak memory 203380 kb
Host smart-c951a52e-29f4-428c-a40a-8c87dd9ae630
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4159542060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.4159542060
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.3624689606
Short name T712
Test name
Test status
Simulation time 56360983 ps
CPU time 2.56 seconds
Started Aug 01 05:36:32 PM PDT 24
Finished Aug 01 05:36:35 PM PDT 24
Peak memory 203372 kb
Host smart-13b7caa5-5f40-4c9f-90a5-087ec9e754ee
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624689606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.3624689606
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.2036132841
Short name T767
Test name
Test status
Simulation time 4584412822 ps
CPU time 134.46 seconds
Started Aug 01 05:36:33 PM PDT 24
Finished Aug 01 05:38:48 PM PDT 24
Peak memory 207188 kb
Host smart-ee148efc-0393-4e8f-9353-b853b38fab65
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2036132841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2036132841
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.1362996532
Short name T328
Test name
Test status
Simulation time 1858913964 ps
CPU time 164.01 seconds
Started Aug 01 05:36:33 PM PDT 24
Finished Aug 01 05:39:18 PM PDT 24
Peak memory 208936 kb
Host smart-822d9a27-8477-4b1c-bcf5-60386216ff95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1362996532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.1362996532
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.2023562629
Short name T286
Test name
Test status
Simulation time 1770730339 ps
CPU time 226.63 seconds
Started Aug 01 05:36:36 PM PDT 24
Finished Aug 01 05:40:22 PM PDT 24
Peak memory 208020 kb
Host smart-19d9cb16-40f6-4a58-bda8-e59e235b4a6e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2023562629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand
_reset.2023562629
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1579285550
Short name T294
Test name
Test status
Simulation time 2250489903 ps
CPU time 251.38 seconds
Started Aug 01 05:36:35 PM PDT 24
Finished Aug 01 05:40:46 PM PDT 24
Peak memory 220356 kb
Host smart-73a5db71-91bc-4cb2-9e46-baabd6cca7e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1579285550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res
et_error.1579285550
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.1727719688
Short name T228
Test name
Test status
Simulation time 597667682 ps
CPU time 8.63 seconds
Started Aug 01 05:36:39 PM PDT 24
Finished Aug 01 05:36:48 PM PDT 24
Peak memory 204828 kb
Host smart-29c5735f-ac01-4c88-acc9-8b04ad29aef4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1727719688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1727719688
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.2402056749
Short name T83
Test name
Test status
Simulation time 7088594637 ps
CPU time 53.93 seconds
Started Aug 01 05:36:43 PM PDT 24
Finished Aug 01 05:37:37 PM PDT 24
Peak memory 211724 kb
Host smart-7bf2818d-a991-48da-aa99-b0367785db5b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2402056749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2402056749
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.2517558898
Short name T448
Test name
Test status
Simulation time 91986033709 ps
CPU time 590.91 seconds
Started Aug 01 05:36:45 PM PDT 24
Finished Aug 01 05:46:36 PM PDT 24
Peak memory 211704 kb
Host smart-32637abc-eeeb-49b3-9cbb-ca77018991b5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2517558898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo
w_rsp.2517558898
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.1635893438
Short name T582
Test name
Test status
Simulation time 74529201 ps
CPU time 7.17 seconds
Started Aug 01 05:36:42 PM PDT 24
Finished Aug 01 05:36:49 PM PDT 24
Peak memory 203356 kb
Host smart-cf82ae0b-c8b8-4711-8903-3c85b7a525cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1635893438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.1635893438
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.2250411866
Short name T187
Test name
Test status
Simulation time 64873990 ps
CPU time 4.15 seconds
Started Aug 01 05:36:46 PM PDT 24
Finished Aug 01 05:36:50 PM PDT 24
Peak memory 203484 kb
Host smart-d3b63e79-7136-4022-8e31-764e70587359
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2250411866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2250411866
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.1384290738
Short name T385
Test name
Test status
Simulation time 2750710112 ps
CPU time 35.97 seconds
Started Aug 01 05:36:35 PM PDT 24
Finished Aug 01 05:37:11 PM PDT 24
Peak memory 211732 kb
Host smart-94ea2c5c-54d2-438d-818f-2dcb7b8c11be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1384290738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1384290738
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.3151942362
Short name T244
Test name
Test status
Simulation time 3660213169 ps
CPU time 11.5 seconds
Started Aug 01 05:36:46 PM PDT 24
Finished Aug 01 05:36:58 PM PDT 24
Peak memory 203552 kb
Host smart-c3a41601-6043-490d-b812-f991a1bcd9a3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151942362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3151942362
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.108101883
Short name T266
Test name
Test status
Simulation time 19607926760 ps
CPU time 135.88 seconds
Started Aug 01 05:36:45 PM PDT 24
Finished Aug 01 05:39:01 PM PDT 24
Peak memory 211664 kb
Host smart-ae92e827-bca1-46dc-9504-74622dfebdc0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=108101883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.108101883
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.1170905977
Short name T572
Test name
Test status
Simulation time 253312920 ps
CPU time 25.8 seconds
Started Aug 01 05:36:43 PM PDT 24
Finished Aug 01 05:37:09 PM PDT 24
Peak memory 211684 kb
Host smart-30fbb5b3-ea9e-4b46-b25f-238b296c5c0d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170905977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1170905977
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.3425484782
Short name T349
Test name
Test status
Simulation time 595153229 ps
CPU time 7.38 seconds
Started Aug 01 05:36:44 PM PDT 24
Finished Aug 01 05:36:51 PM PDT 24
Peak memory 203516 kb
Host smart-01dd0027-05e6-4a9b-88c8-fbf76421b362
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3425484782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3425484782
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.104317741
Short name T477
Test name
Test status
Simulation time 110692286 ps
CPU time 2.91 seconds
Started Aug 01 05:36:31 PM PDT 24
Finished Aug 01 05:36:34 PM PDT 24
Peak memory 203556 kb
Host smart-c465356c-6122-4575-8638-b69720777b26
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=104317741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.104317741
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.4118305010
Short name T74
Test name
Test status
Simulation time 12105076420 ps
CPU time 25.4 seconds
Started Aug 01 05:36:36 PM PDT 24
Finished Aug 01 05:37:01 PM PDT 24
Peak memory 203480 kb
Host smart-23894c00-e5ec-4ce5-a320-5c854db80323
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118305010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.4118305010
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3014914406
Short name T441
Test name
Test status
Simulation time 6280746093 ps
CPU time 36.37 seconds
Started Aug 01 05:36:29 PM PDT 24
Finished Aug 01 05:37:06 PM PDT 24
Peak memory 203540 kb
Host smart-83f4f0c3-090b-4ecf-a9e4-4ee6c70e7633
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3014914406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3014914406
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2872551812
Short name T339
Test name
Test status
Simulation time 23960994 ps
CPU time 2.12 seconds
Started Aug 01 05:36:33 PM PDT 24
Finished Aug 01 05:36:35 PM PDT 24
Peak memory 203376 kb
Host smart-67c37ade-693b-425b-b4ad-f070aede197b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872551812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2872551812
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.2937628034
Short name T786
Test name
Test status
Simulation time 1480599746 ps
CPU time 27.37 seconds
Started Aug 01 05:36:42 PM PDT 24
Finished Aug 01 05:37:10 PM PDT 24
Peak memory 204564 kb
Host smart-fb0692a1-759e-44a6-b7c5-0c3afb1ff066
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2937628034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2937628034
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.2277685953
Short name T642
Test name
Test status
Simulation time 487626102 ps
CPU time 20.75 seconds
Started Aug 01 05:36:42 PM PDT 24
Finished Aug 01 05:37:03 PM PDT 24
Peak memory 203848 kb
Host smart-3ac5f8fa-7b8f-43ec-bb5e-115cf995c99b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2277685953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.2277685953
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.545992982
Short name T717
Test name
Test status
Simulation time 455044066 ps
CPU time 140.77 seconds
Started Aug 01 05:36:42 PM PDT 24
Finished Aug 01 05:39:03 PM PDT 24
Peak memory 208544 kb
Host smart-e08360f9-59c6-408e-a952-d81a948c0e96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=545992982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_
reset.545992982
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1780270532
Short name T236
Test name
Test status
Simulation time 3666084520 ps
CPU time 194.29 seconds
Started Aug 01 05:36:40 PM PDT 24
Finished Aug 01 05:39:55 PM PDT 24
Peak memory 210788 kb
Host smart-c5d6fab9-3b23-4f9f-93ab-2e18e3ef90db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1780270532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res
et_error.1780270532
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.441749685
Short name T494
Test name
Test status
Simulation time 154208989 ps
CPU time 8.66 seconds
Started Aug 01 05:36:46 PM PDT 24
Finished Aug 01 05:36:55 PM PDT 24
Peak memory 211680 kb
Host smart-87f8fadd-2826-493c-947a-eb64c348297c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=441749685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.441749685
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.2377309960
Short name T201
Test name
Test status
Simulation time 52302298 ps
CPU time 10.34 seconds
Started Aug 01 05:36:45 PM PDT 24
Finished Aug 01 05:36:55 PM PDT 24
Peak memory 211632 kb
Host smart-1ec9f11b-8415-4983-879a-0255334b2db7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2377309960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.2377309960
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.4153187752
Short name T496
Test name
Test status
Simulation time 13364102852 ps
CPU time 62.8 seconds
Started Aug 01 05:36:42 PM PDT 24
Finished Aug 01 05:37:44 PM PDT 24
Peak memory 205112 kb
Host smart-9168d5b4-d499-45b2-ab3e-d8a416c09389
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4153187752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo
w_rsp.4153187752
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.3197777378
Short name T156
Test name
Test status
Simulation time 132247594 ps
CPU time 14.53 seconds
Started Aug 01 05:36:43 PM PDT 24
Finished Aug 01 05:36:57 PM PDT 24
Peak memory 203480 kb
Host smart-0a30878e-660c-4af0-923b-012bd818b6f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3197777378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3197777378
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.889915715
Short name T791
Test name
Test status
Simulation time 642850237 ps
CPU time 21.84 seconds
Started Aug 01 05:36:47 PM PDT 24
Finished Aug 01 05:37:09 PM PDT 24
Peak memory 203496 kb
Host smart-22a31570-e87e-40ce-88a4-4cc487cecb0a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=889915715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.889915715
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.3245179428
Short name T107
Test name
Test status
Simulation time 1157500409 ps
CPU time 38.24 seconds
Started Aug 01 05:36:44 PM PDT 24
Finished Aug 01 05:37:23 PM PDT 24
Peak memory 211684 kb
Host smart-9253365d-e979-47fa-876c-816352309a0a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3245179428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.3245179428
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.2259039408
Short name T293
Test name
Test status
Simulation time 194265802612 ps
CPU time 223.41 seconds
Started Aug 01 05:36:42 PM PDT 24
Finished Aug 01 05:40:26 PM PDT 24
Peak memory 204748 kb
Host smart-0580fd4c-a0bc-4525-b1d0-f9e68cd77db0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259039408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2259039408
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.4230090244
Short name T842
Test name
Test status
Simulation time 1584015218 ps
CPU time 11.15 seconds
Started Aug 01 05:36:48 PM PDT 24
Finished Aug 01 05:36:59 PM PDT 24
Peak memory 203472 kb
Host smart-14710b16-220a-4b70-9d52-cceeaead6dbd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4230090244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.4230090244
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.3653304259
Short name T343
Test name
Test status
Simulation time 209234674 ps
CPU time 24.57 seconds
Started Aug 01 05:36:43 PM PDT 24
Finished Aug 01 05:37:08 PM PDT 24
Peak memory 204656 kb
Host smart-1e5cb4bf-71ea-4320-a4c2-97f9b60585ac
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653304259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3653304259
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.3304860937
Short name T104
Test name
Test status
Simulation time 158904659 ps
CPU time 2.44 seconds
Started Aug 01 05:36:46 PM PDT 24
Finished Aug 01 05:36:48 PM PDT 24
Peak memory 203508 kb
Host smart-c435a1d4-6455-46e6-aa6d-a7b2e7c9e85f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3304860937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3304860937
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.2948632335
Short name T317
Test name
Test status
Simulation time 33503687 ps
CPU time 2.37 seconds
Started Aug 01 05:36:50 PM PDT 24
Finished Aug 01 05:36:53 PM PDT 24
Peak memory 203460 kb
Host smart-d0ae23de-3175-46b3-95c5-fa587359819d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2948632335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2948632335
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.380082638
Short name T330
Test name
Test status
Simulation time 20534195829 ps
CPU time 36.12 seconds
Started Aug 01 05:36:43 PM PDT 24
Finished Aug 01 05:37:20 PM PDT 24
Peak memory 203496 kb
Host smart-d864f500-89e4-4bf8-a906-c9a3ab5a1bf5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=380082638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.380082638
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3411257363
Short name T242
Test name
Test status
Simulation time 13172509526 ps
CPU time 36.17 seconds
Started Aug 01 05:36:42 PM PDT 24
Finished Aug 01 05:37:18 PM PDT 24
Peak memory 203420 kb
Host smart-c8f291d6-0ebf-45df-9417-cb666694fb19
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3411257363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3411257363
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3685288460
Short name T329
Test name
Test status
Simulation time 52137292 ps
CPU time 2.19 seconds
Started Aug 01 05:36:43 PM PDT 24
Finished Aug 01 05:36:46 PM PDT 24
Peak memory 203472 kb
Host smart-651ebee3-7e40-43ed-b12b-db26a0edb8c4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685288460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3685288460
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.440904663
Short name T619
Test name
Test status
Simulation time 305161234 ps
CPU time 14.31 seconds
Started Aug 01 05:36:51 PM PDT 24
Finished Aug 01 05:37:05 PM PDT 24
Peak memory 204508 kb
Host smart-e69a2c77-54c1-47dc-a470-968cd77f4ca2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=440904663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.440904663
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3799182508
Short name T616
Test name
Test status
Simulation time 5753545409 ps
CPU time 135.81 seconds
Started Aug 01 05:36:44 PM PDT 24
Finished Aug 01 05:39:00 PM PDT 24
Peak memory 205532 kb
Host smart-762d718e-1102-44d4-a755-40bccd699cca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3799182508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3799182508
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1368230857
Short name T35
Test name
Test status
Simulation time 524583610 ps
CPU time 293.86 seconds
Started Aug 01 05:36:45 PM PDT 24
Finished Aug 01 05:41:39 PM PDT 24
Peak memory 210028 kb
Host smart-fafb78a7-7388-4259-aa40-b79aafb92ede
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1368230857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand
_reset.1368230857
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3364031341
Short name T820
Test name
Test status
Simulation time 2148024705 ps
CPU time 118.67 seconds
Started Aug 01 05:36:49 PM PDT 24
Finished Aug 01 05:38:48 PM PDT 24
Peak memory 208612 kb
Host smart-9958f2bd-65bb-449b-a300-b03441ae3509
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3364031341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res
et_error.3364031341
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.1973666180
Short name T358
Test name
Test status
Simulation time 719410470 ps
CPU time 10.89 seconds
Started Aug 01 05:36:47 PM PDT 24
Finished Aug 01 05:36:58 PM PDT 24
Peak memory 205000 kb
Host smart-25526cc7-408d-4da9-a9a5-55ed9fec94f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1973666180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1973666180
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.561465452
Short name T634
Test name
Test status
Simulation time 647819204 ps
CPU time 17.03 seconds
Started Aug 01 05:36:50 PM PDT 24
Finished Aug 01 05:37:07 PM PDT 24
Peak memory 205620 kb
Host smart-4e712447-7d94-42bc-b61a-c09f64baa975
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=561465452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.561465452
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.1981907123
Short name T95
Test name
Test status
Simulation time 55374616365 ps
CPU time 411.86 seconds
Started Aug 01 05:36:44 PM PDT 24
Finished Aug 01 05:43:36 PM PDT 24
Peak memory 211724 kb
Host smart-7011ccd8-6aaf-4dd4-8e99-170d418bfc7a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1981907123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo
w_rsp.1981907123
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1577851335
Short name T10
Test name
Test status
Simulation time 506715347 ps
CPU time 11.83 seconds
Started Aug 01 05:36:44 PM PDT 24
Finished Aug 01 05:36:56 PM PDT 24
Peak memory 203504 kb
Host smart-53a40e4b-6fe5-4abb-be32-808c4ecb5929
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1577851335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1577851335
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.3923909401
Short name T577
Test name
Test status
Simulation time 840081895 ps
CPU time 20.67 seconds
Started Aug 01 05:36:45 PM PDT 24
Finished Aug 01 05:37:06 PM PDT 24
Peak memory 203320 kb
Host smart-1f81a932-8a6c-4d62-a459-a61e215ef1e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3923909401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3923909401
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.1713948809
Short name T501
Test name
Test status
Simulation time 1024452925 ps
CPU time 34.26 seconds
Started Aug 01 05:36:45 PM PDT 24
Finished Aug 01 05:37:19 PM PDT 24
Peak memory 211588 kb
Host smart-29dfe2dd-6c91-46ac-b2c8-4ac1582c3e6e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1713948809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1713948809
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.2553063079
Short name T779
Test name
Test status
Simulation time 26495607559 ps
CPU time 143.96 seconds
Started Aug 01 05:36:42 PM PDT 24
Finished Aug 01 05:39:06 PM PDT 24
Peak memory 211696 kb
Host smart-2db81e43-25dc-4c7b-9b44-67bf5f597dcb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2553063079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2553063079
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.792228311
Short name T369
Test name
Test status
Simulation time 61381418 ps
CPU time 7.42 seconds
Started Aug 01 05:36:43 PM PDT 24
Finished Aug 01 05:36:51 PM PDT 24
Peak memory 211640 kb
Host smart-95bd4d18-be2c-45ee-acd6-7d194a453dd1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792228311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.792228311
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.2891941102
Short name T439
Test name
Test status
Simulation time 60090142 ps
CPU time 4.12 seconds
Started Aug 01 05:36:42 PM PDT 24
Finished Aug 01 05:36:46 PM PDT 24
Peak memory 203772 kb
Host smart-6cc6d129-f85e-4fd6-b6c2-74783cae01d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2891941102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2891941102
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.3121832633
Short name T521
Test name
Test status
Simulation time 31211237 ps
CPU time 2.69 seconds
Started Aug 01 05:36:42 PM PDT 24
Finished Aug 01 05:36:45 PM PDT 24
Peak memory 203452 kb
Host smart-61b84d2e-d529-40e9-abe0-7aa83647214e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3121832633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3121832633
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.238617680
Short name T718
Test name
Test status
Simulation time 5982346083 ps
CPU time 33.3 seconds
Started Aug 01 05:36:46 PM PDT 24
Finished Aug 01 05:37:19 PM PDT 24
Peak memory 203544 kb
Host smart-cfd3e305-b50c-41cb-8cca-c74e49118121
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=238617680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.238617680
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.37383046
Short name T333
Test name
Test status
Simulation time 7695163525 ps
CPU time 27.75 seconds
Started Aug 01 05:36:46 PM PDT 24
Finished Aug 01 05:37:14 PM PDT 24
Peak memory 203440 kb
Host smart-f61f8292-247a-4134-8e19-4648935a9bd5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=37383046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.37383046
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1002639439
Short name T884
Test name
Test status
Simulation time 25915229 ps
CPU time 2.07 seconds
Started Aug 01 05:36:50 PM PDT 24
Finished Aug 01 05:36:52 PM PDT 24
Peak memory 203472 kb
Host smart-24235787-5c8f-4562-b4b4-0f37480ec797
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002639439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.1002639439
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.415678071
Short name T686
Test name
Test status
Simulation time 2797347740 ps
CPU time 96.43 seconds
Started Aug 01 05:36:48 PM PDT 24
Finished Aug 01 05:38:25 PM PDT 24
Peak memory 207224 kb
Host smart-9f336eb2-b93d-4edf-884b-2af349ed9592
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=415678071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.415678071
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.3512650878
Short name T475
Test name
Test status
Simulation time 3653665967 ps
CPU time 53.14 seconds
Started Aug 01 05:36:42 PM PDT 24
Finished Aug 01 05:37:35 PM PDT 24
Peak memory 211708 kb
Host smart-2b82586e-aff2-4c5c-b44c-2bc401d77f01
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3512650878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3512650878
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.359660676
Short name T202
Test name
Test status
Simulation time 2402316613 ps
CPU time 349.74 seconds
Started Aug 01 05:36:47 PM PDT 24
Finished Aug 01 05:42:36 PM PDT 24
Peak memory 219836 kb
Host smart-10377998-ccc9-4167-bcf6-ea2f8cfc8a2b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=359660676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_
reset.359660676
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.1536865184
Short name T729
Test name
Test status
Simulation time 8038672388 ps
CPU time 191.2 seconds
Started Aug 01 05:36:39 PM PDT 24
Finished Aug 01 05:39:50 PM PDT 24
Peak memory 210808 kb
Host smart-b619d1b1-f19f-4371-9032-d5877df3444e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1536865184 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res
et_error.1536865184
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.173751425
Short name T691
Test name
Test status
Simulation time 36370239 ps
CPU time 4.56 seconds
Started Aug 01 05:36:42 PM PDT 24
Finished Aug 01 05:36:47 PM PDT 24
Peak memory 204636 kb
Host smart-cc5bbde4-fd1f-4506-be9e-40a70857d89f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=173751425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.173751425
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.4026977858
Short name T551
Test name
Test status
Simulation time 2146214023 ps
CPU time 50.12 seconds
Started Aug 01 05:36:46 PM PDT 24
Finished Aug 01 05:37:37 PM PDT 24
Peak memory 211640 kb
Host smart-c89793d9-168a-4046-80f8-9d040097fe38
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4026977858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.4026977858
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.3913077588
Short name T108
Test name
Test status
Simulation time 24506512809 ps
CPU time 200.04 seconds
Started Aug 01 05:36:46 PM PDT 24
Finished Aug 01 05:40:06 PM PDT 24
Peak memory 206332 kb
Host smart-b5b8c7d5-e53a-4fe7-ae1c-21b1eb872884
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3913077588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo
w_rsp.3913077588
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.3871415768
Short name T371
Test name
Test status
Simulation time 678703397 ps
CPU time 25.73 seconds
Started Aug 01 05:36:47 PM PDT 24
Finished Aug 01 05:37:13 PM PDT 24
Peak memory 203516 kb
Host smart-001a822f-5894-4e43-a563-4a00a75325cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3871415768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.3871415768
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.1728434532
Short name T111
Test name
Test status
Simulation time 23996907 ps
CPU time 3.1 seconds
Started Aug 01 05:36:48 PM PDT 24
Finished Aug 01 05:36:51 PM PDT 24
Peak memory 203492 kb
Host smart-078f6e65-b668-4f3a-ba9f-4ac8136da3be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1728434532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1728434532
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.4228633370
Short name T534
Test name
Test status
Simulation time 345197511 ps
CPU time 10 seconds
Started Aug 01 05:36:42 PM PDT 24
Finished Aug 01 05:36:52 PM PDT 24
Peak memory 204600 kb
Host smart-5ce3d392-a508-4d2c-8d18-0cc318e33a19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4228633370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.4228633370
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.3132918685
Short name T898
Test name
Test status
Simulation time 35203770482 ps
CPU time 195.07 seconds
Started Aug 01 05:36:42 PM PDT 24
Finished Aug 01 05:39:58 PM PDT 24
Peak memory 211628 kb
Host smart-88e5ae72-83d9-461c-b29d-95062b35fa24
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132918685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3132918685
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2052497970
Short name T503
Test name
Test status
Simulation time 28972134678 ps
CPU time 118.95 seconds
Started Aug 01 05:36:42 PM PDT 24
Finished Aug 01 05:38:41 PM PDT 24
Peak memory 211732 kb
Host smart-1856713b-020a-4cbd-b291-2f1a88b7c911
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2052497970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2052497970
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.1544213057
Short name T735
Test name
Test status
Simulation time 168026770 ps
CPU time 20.55 seconds
Started Aug 01 05:36:46 PM PDT 24
Finished Aug 01 05:37:07 PM PDT 24
Peak memory 204836 kb
Host smart-4724f122-6a7b-45a6-b057-6503b1b462e3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544213057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1544213057
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.3671278990
Short name T189
Test name
Test status
Simulation time 3210405037 ps
CPU time 34.63 seconds
Started Aug 01 05:36:46 PM PDT 24
Finished Aug 01 05:37:21 PM PDT 24
Peak memory 204168 kb
Host smart-11a9e2ce-a0be-4dc3-9d29-6287dbd59381
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3671278990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3671278990
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.3024277544
Short name T808
Test name
Test status
Simulation time 145149187 ps
CPU time 3.38 seconds
Started Aug 01 05:36:44 PM PDT 24
Finished Aug 01 05:36:48 PM PDT 24
Peak memory 203488 kb
Host smart-b46f87da-06a8-4857-ade2-6c707927a3b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3024277544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3024277544
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.389767630
Short name T740
Test name
Test status
Simulation time 8943155231 ps
CPU time 26.61 seconds
Started Aug 01 05:36:46 PM PDT 24
Finished Aug 01 05:37:12 PM PDT 24
Peak memory 203468 kb
Host smart-81907e48-c90f-4e26-b367-7aa382783990
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=389767630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.389767630
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.1618160280
Short name T420
Test name
Test status
Simulation time 29322529156 ps
CPU time 56.47 seconds
Started Aug 01 05:36:40 PM PDT 24
Finished Aug 01 05:37:37 PM PDT 24
Peak memory 203512 kb
Host smart-0eddf504-a1a2-4bc4-a1a0-f669716fe41a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1618160280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1618160280
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.3458641954
Short name T602
Test name
Test status
Simulation time 37252177 ps
CPU time 2.14 seconds
Started Aug 01 05:36:47 PM PDT 24
Finished Aug 01 05:36:49 PM PDT 24
Peak memory 203428 kb
Host smart-3ce1a88c-1d30-4db9-9f2b-70cb923d5934
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458641954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.3458641954
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.4184724139
Short name T838
Test name
Test status
Simulation time 2786305282 ps
CPU time 122.15 seconds
Started Aug 01 05:36:51 PM PDT 24
Finished Aug 01 05:38:53 PM PDT 24
Peak memory 205900 kb
Host smart-3790c49d-8520-49ea-b189-fcaf744da9bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4184724139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.4184724139
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.2007972380
Short name T299
Test name
Test status
Simulation time 4428430277 ps
CPU time 129.11 seconds
Started Aug 01 05:36:51 PM PDT 24
Finished Aug 01 05:39:00 PM PDT 24
Peak memory 206984 kb
Host smart-489fd0bc-9375-4cc9-958e-c415cbab92c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2007972380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2007972380
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1513442391
Short name T743
Test name
Test status
Simulation time 3652092994 ps
CPU time 326.65 seconds
Started Aug 01 05:36:54 PM PDT 24
Finished Aug 01 05:42:20 PM PDT 24
Peak memory 208084 kb
Host smart-070166dc-c733-49bd-888f-457a66c04038
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1513442391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand
_reset.1513442391
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2420011952
Short name T419
Test name
Test status
Simulation time 20489426877 ps
CPU time 645.88 seconds
Started Aug 01 05:36:49 PM PDT 24
Finished Aug 01 05:47:35 PM PDT 24
Peak memory 228056 kb
Host smart-fb9ac7a5-adc8-494d-899c-da44a16814ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2420011952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res
et_error.2420011952
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.2913133650
Short name T75
Test name
Test status
Simulation time 1490167394 ps
CPU time 12.29 seconds
Started Aug 01 05:36:47 PM PDT 24
Finished Aug 01 05:37:00 PM PDT 24
Peak memory 211656 kb
Host smart-098dccef-3bfd-4c7d-a2bf-8c551a02c55d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2913133650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2913133650
Directory /workspace/9.xbar_unmapped_addr/latest
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