Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}
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Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 64 0 64 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1890 1 T7 1 T18 1 T20 6
all_values[1] 1820 1 T7 1 T18 3 T20 4
all_values[2] 1908 1 T24 2 T18 1 T20 12
all_values[3] 1892 1 T7 2 T18 4 T20 5
all_values[4] 1832 1 T7 2 T18 2 T20 4
all_values[5] 1804 1 T7 4 T18 2 T20 2
all_values[6] 1797 1 T7 4 T18 1 T20 5
all_values[7] 1801 1 T7 2 T24 1 T18 3
all_values[8] 1723 1 T7 2 T24 1 T18 2
all_values[9] 1800 1 T7 3 T18 1 T20 5
all_values[10] 1849 1 T7 1 T24 2 T18 3
all_values[11] 1923 1 T7 2 T24 1 T18 4
all_values[12] 1857 1 T18 1 T20 2 T31 2
all_values[13] 1886 1 T7 2 T24 1 T20 5
all_values[14] 1895 1 T7 3 T24 1 T18 4
all_values[15] 1795 1 T7 4 T24 1 T18 3
all_values[16] 1816 1 T7 2 T20 2 T31 1
all_values[17] 1883 1 T7 1 T18 2 T20 3
all_values[18] 1827 1 T7 2 T18 3 T20 2
all_values[19] 1886 1 T7 2 T24 1 T20 6
all_values[20] 1845 1 T18 2 T20 4 T42 1
all_values[21] 1754 1 T18 3 T20 4 T42 1
all_values[22] 1832 1 T7 2 T24 2 T20 8
all_values[23] 1852 1 T18 2 T20 7 T42 1
all_values[24] 1823 1 T7 2 T24 1 T20 2
all_values[25] 1783 1 T18 1 T20 4 T42 1
all_values[26] 1846 1 T7 1 T24 2 T18 3
all_values[27] 1819 1 T7 4 T18 4 T20 6
all_values[28] 1780 1 T18 1 T20 4 T42 1
all_values[29] 1859 1 T7 2 T18 4 T20 4
all_values[30] 1924 1 T7 2 T24 1 T18 3
all_values[31] 1915 1 T18 3 T20 9 T31 2
all_values[32] 1856 1 T7 3 T24 1 T18 2
all_values[33] 1868 1 T7 3 T18 3 T20 4
all_values[34] 1857 1 T18 1 T20 1 T42 3
all_values[35] 1810 1 T7 1 T18 4 T20 7
all_values[36] 1856 1 T7 1 T24 1 T18 1
all_values[37] 1809 1 T18 1 T20 4 T42 1
all_values[38] 1811 1 T7 3 T18 1 T20 6
all_values[39] 1800 1 T7 2 T18 1 T20 4
all_values[40] 1850 1 T7 2 T18 2 T20 6
all_values[41] 1845 1 T7 2 T24 1 T18 3
all_values[42] 1900 1 T7 1 T18 4 T20 7
all_values[43] 1880 1 T7 3 T24 2 T18 3
all_values[44] 1809 1 T7 2 T18 1 T20 4
all_values[45] 1883 1 T7 1 T24 1 T18 2
all_values[46] 1833 1 T7 2 T18 2 T20 4
all_values[47] 1901 1 T7 1 T24 1 T18 2
all_values[48] 1818 1 T20 1 T42 2 T31 4
all_values[49] 1776 1 T7 2 T18 3 T20 4
all_values[50] 1871 1 T7 5 T18 1 T20 3
all_values[51] 1777 1 T7 2 T24 1 T18 1
all_values[52] 1821 1 T7 1 T18 4 T20 1
all_values[53] 1849 1 T7 1 T24 1 T18 3
all_values[54] 1867 1 T7 2 T18 4 T20 1
all_values[55] 1832 1 T7 2 T18 1 T20 3
all_values[56] 1818 1 T24 1 T18 3 T20 7
all_values[57] 1812 1 T7 3 T24 1 T18 2
all_values[58] 1861 1 T7 1 T18 5 T20 7
all_values[59] 1811 1 T7 1 T18 1 T20 4
all_values[60] 1878 1 T18 2 T20 2 T42 2
all_values[61] 1854 1 T7 1 T18 4 T20 1
all_values[62] 1798 1 T7 2 T24 1 T18 3
all_values[63] 1841 1 T7 3 T20 2 T31 3

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