Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1913	1			T3	23		T4	5		T13	3
all_values[1]	1940	1			T3	22		T4	7		T13	1
all_values[2]	1881	1			T3	30		T4	2		T13	6
all_values[3]	1904	1			T3	16		T4	3		T13	1
all_values[4]	1909	1			T3	21		T4	5		T13	5
all_values[5]	1913	1			T3	13		T4	3		T13	2
all_values[6]	1909	1			T3	24		T4	2		T13	1
all_values[7]	1932	1			T3	19		T4	5		T13	5
all_values[8]	1824	1			T3	18		T4	2		T13	6
all_values[9]	1880	1			T3	21		T4	3		T15	20
all_values[10]	1880	1			T3	20		T4	5		T13	3
all_values[11]	1938	1			T3	16		T4	3		T13	2
all_values[12]	1867	1			T3	20		T4	2		T13	7
all_values[13]	1898	1			T3	24		T4	4		T39	2
all_values[14]	1986	1			T3	34		T4	3		T13	2
all_values[15]	1850	1			T3	20		T4	4		T13	6
all_values[16]	1997	1			T3	16		T4	2		T13	2
all_values[17]	1915	1			T3	20		T4	3		T13	3
all_values[18]	1861	1			T3	24		T4	4		T13	2
all_values[19]	1957	1			T3	26		T4	1		T13	3
all_values[20]	1950	1			T3	24		T4	7		T13	4
all_values[21]	1865	1			T3	22		T4	4		T13	3
all_values[22]	1929	1			T3	22		T4	3		T13	4
all_values[23]	1893	1			T3	24		T4	6		T13	4
all_values[24]	1875	1			T3	20		T4	9		T13	2
all_values[25]	1913	1			T3	21		T4	2		T13	2
all_values[26]	1894	1			T3	16		T4	2		T13	5
all_values[27]	1886	1			T3	19		T4	4		T13	5
all_values[28]	1899	1			T3	12		T4	1		T13	4
all_values[29]	2004	1			T3	19		T4	4		T13	2
all_values[30]	1905	1			T3	21		T4	1		T13	1
all_values[31]	1985	1			T3	23		T4	5		T39	1
all_values[32]	1959	1			T3	22		T4	7		T15	11
all_values[33]	1875	1			T3	22		T4	4		T13	4
all_values[34]	1871	1			T3	16		T4	3		T13	1
all_values[35]	1859	1			T3	24		T4	4		T13	2
all_values[36]	2001	1			T3	30		T4	7		T13	6
all_values[37]	1820	1			T3	12		T4	4		T13	4
all_values[38]	1923	1			T3	13		T4	4		T13	2
all_values[39]	1944	1			T3	16		T4	4		T13	2
all_values[40]	1847	1			T3	21		T4	4		T13	2
all_values[41]	1888	1			T3	20		T4	5		T13	3
all_values[42]	1944	1			T3	15		T4	3		T13	3
all_values[43]	1900	1			T3	17		T4	1		T13	3
all_values[44]	1970	1			T3	13		T4	6		T13	7
all_values[45]	1964	1			T3	15		T4	2		T13	1
all_values[46]	1925	1			T3	18		T4	3		T13	5
all_values[47]	1923	1			T3	15		T4	3		T13	2
all_values[48]	1918	1			T3	25		T4	2		T13	5
all_values[49]	2015	1			T3	13		T4	1		T13	4
all_values[50]	1929	1			T3	27		T4	4		T13	5
all_values[51]	1929	1			T3	18		T4	1		T13	1
all_values[52]	1966	1			T3	28		T4	3		T13	4
all_values[53]	1965	1			T3	22		T4	2		T13	1
all_values[54]	1915	1			T3	24		T4	4		T13	4
all_values[55]	1971	1			T3	13		T4	2		T13	3
all_values[56]	1926	1			T3	16		T4	5		T13	2
all_values[57]	1929	1			T3	21		T4	5		T13	3
all_values[58]	1929	1			T3	20		T4	3		T13	2
all_values[59]	1910	1			T3	14		T4	1		T13	2
all_values[60]	1872	1			T3	34		T4	3		T13	2
all_values[61]	1947	1			T3	18		T4	5		T13	4
all_values[62]	1961	1			T3	23		T4	5		T13	3
all_values[63]	1860	1			T3	24		T13	2		T15	16