Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1754	1			T8	14		T15	1		T17	8
all_values[1]	1753	1			T8	18		T15	1		T17	5
all_values[2]	1729	1			T8	16		T17	6		T19	31
all_values[3]	1737	1			T8	18		T15	1		T17	8
all_values[4]	1734	1			T8	18		T17	7		T19	26
all_values[5]	1781	1			T8	15		T14	1		T17	8
all_values[6]	1676	1			T8	15		T15	3		T17	10
all_values[7]	1772	1			T8	16		T17	4		T19	26
all_values[8]	1754	1			T8	17		T17	4		T19	30
all_values[9]	1697	1			T8	14		T17	8		T19	25
all_values[10]	1663	1			T8	15		T14	1		T15	2
all_values[11]	1695	1			T8	14		T17	8		T19	30
all_values[12]	1627	1			T8	10		T14	1		T15	2
all_values[13]	1768	1			T8	17		T15	2		T17	2
all_values[14]	1676	1			T8	19		T17	1		T19	26
all_values[15]	1645	1			T8	10		T17	5		T19	27
all_values[16]	1668	1			T8	13		T17	1		T19	29
all_values[17]	1738	1			T8	11		T15	3		T17	7
all_values[18]	1781	1			T8	14		T15	1		T17	11
all_values[19]	1726	1			T8	15		T15	2		T17	7
all_values[20]	1718	1			T8	17		T15	2		T17	5
all_values[21]	1746	1			T8	16		T17	2		T19	21
all_values[22]	1687	1			T8	17		T15	2		T17	5
all_values[23]	1705	1			T8	13		T15	3		T17	7
all_values[24]	1698	1			T8	22		T15	2		T17	10
all_values[25]	1666	1			T8	16		T17	4		T19	21
all_values[26]	1662	1			T8	18		T17	3		T19	21
all_values[27]	1637	1			T8	11		T15	2		T17	3
all_values[28]	1783	1			T8	15		T15	1		T17	4
all_values[29]	1687	1			T8	11		T15	2		T17	5
all_values[30]	1688	1			T8	14		T17	4		T19	24
all_values[31]	1724	1			T8	12		T15	1		T17	3
all_values[32]	1680	1			T8	17		T15	2		T17	2
all_values[33]	1674	1			T8	11		T15	2		T17	9
all_values[34]	1755	1			T8	17		T15	1		T19	19
all_values[35]	1691	1			T8	9		T15	3		T17	8
all_values[36]	1700	1			T8	18		T15	2		T17	2
all_values[37]	1682	1			T8	13		T15	1		T19	25
all_values[38]	1681	1			T8	14		T14	1		T17	4
all_values[39]	1663	1			T8	13		T15	1		T17	2
all_values[40]	1692	1			T8	15		T17	4		T19	16
all_values[41]	1676	1			T8	15		T15	4		T17	4
all_values[42]	1676	1			T8	16		T14	1		T15	4
all_values[43]	1676	1			T8	11		T15	2		T17	7
all_values[44]	1730	1			T8	14		T14	1		T15	1
all_values[45]	1732	1			T8	28		T14	1		T15	1
all_values[46]	1782	1			T8	18		T14	1		T15	1
all_values[47]	1658	1			T8	11		T14	1		T17	8
all_values[48]	1745	1			T8	17		T15	1		T17	2
all_values[49]	1732	1			T8	14		T15	1		T17	4
all_values[50]	1706	1			T8	17		T15	1		T17	3
all_values[51]	1687	1			T8	12		T15	1		T17	4
all_values[52]	1698	1			T8	18		T15	2		T17	1
all_values[53]	1712	1			T8	15		T15	2		T17	7
all_values[54]	1717	1			T8	19		T15	1		T17	3
all_values[55]	1760	1			T8	23		T15	2		T17	4
all_values[56]	1691	1			T8	12		T15	1		T17	3
all_values[57]	1723	1			T8	8		T17	6		T19	22
all_values[58]	1722	1			T8	14		T17	6		T19	21
all_values[59]	1744	1			T8	24		T15	1		T17	3
all_values[60]	1733	1			T8	20		T15	1		T17	5
all_values[61]	1682	1			T8	13		T14	1		T15	1
all_values[62]	1694	1			T8	18		T15	2		T19	22
all_values[63]	1679	1			T8	12		T14	1		T15	1