Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1656	1			T7	5		T9	1		T11	20
all_values[1]	1741	1			T2	1		T7	2		T9	2
all_values[2]	1754	1			T2	1		T7	2		T11	13
all_values[3]	1700	1			T2	1		T7	2		T11	19
all_values[4]	1694	1			T2	1		T7	3		T9	2
all_values[5]	1595	1			T7	5		T11	23		T12	20
all_values[6]	1623	1			T7	3		T9	1		T11	24
all_values[7]	1690	1			T2	2		T7	1		T11	12
all_values[8]	1664	1			T2	1		T7	1		T9	2
all_values[9]	1676	1			T7	8		T9	3		T11	17
all_values[10]	1613	1			T7	1		T11	23		T12	18
all_values[11]	1707	1			T7	4		T11	16		T12	19
all_values[12]	1702	1			T2	1		T7	6		T11	12
all_values[13]	1763	1			T7	4		T9	1		T11	12
all_values[14]	1634	1			T7	1		T11	18		T12	21
all_values[15]	1643	1			T2	1		T7	4		T9	2
all_values[16]	1615	1			T2	1		T7	1		T9	1
all_values[17]	1669	1			T7	4		T9	2		T11	16
all_values[18]	1725	1			T2	2		T7	5		T9	1
all_values[19]	1643	1			T7	4		T11	20		T12	13
all_values[20]	1665	1			T7	1		T9	2		T11	25
all_values[21]	1606	1			T7	3		T11	23		T12	18
all_values[22]	1714	1			T7	3		T9	1		T11	11
all_values[23]	1673	1			T2	1		T7	3		T9	2
all_values[24]	1685	1			T2	1		T7	2		T11	15
all_values[25]	1660	1			T7	2		T9	1		T11	20
all_values[26]	1587	1			T7	1		T11	20		T12	22
all_values[27]	1645	1			T7	5		T9	3		T11	18
all_values[28]	1713	1			T7	4		T9	1		T11	32
all_values[29]	1604	1			T2	1		T7	4		T9	2
all_values[30]	1661	1			T2	1		T7	2		T9	1
all_values[31]	1633	1			T2	2		T7	5		T9	2
all_values[32]	1691	1			T7	3		T9	1		T11	18
all_values[33]	1587	1			T9	1		T11	19		T12	10
all_values[34]	1632	1			T7	1		T11	20		T12	7
all_values[35]	1692	1			T2	2		T7	6		T9	2
all_values[36]	1654	1			T7	7		T11	14		T12	25
all_values[37]	1704	1			T2	2		T7	6		T11	12
all_values[38]	1724	1			T7	4		T11	19		T12	17
all_values[39]	1692	1			T7	5		T11	9		T12	15
all_values[40]	1693	1			T7	4		T9	1		T11	15
all_values[41]	1677	1			T2	1		T7	1		T9	1
all_values[42]	1680	1			T2	2		T7	2		T9	1
all_values[43]	1680	1			T2	1		T7	1		T11	19
all_values[44]	1660	1			T2	1		T7	2		T9	1
all_values[45]	1687	1			T2	2		T7	6		T11	24
all_values[46]	1661	1			T2	2		T7	1		T9	2
all_values[47]	1643	1			T7	2		T9	1		T11	16
all_values[48]	1651	1			T2	1		T7	3		T11	11
all_values[49]	1619	1			T2	2		T7	3		T11	21
all_values[50]	1680	1			T2	2		T7	3		T11	17
all_values[51]	1701	1			T7	2		T11	18		T12	14
all_values[52]	1670	1			T2	1		T7	3		T9	1
all_values[53]	1629	1			T2	1		T7	3		T11	17
all_values[54]	1631	1			T2	1		T7	4		T11	24
all_values[55]	1719	1			T7	3		T9	1		T11	25
all_values[56]	1659	1			T2	2		T7	1		T11	17
all_values[57]	1639	1			T7	5		T9	1		T11	16
all_values[58]	1635	1			T2	1		T7	3		T9	3
all_values[59]	1648	1			T2	1		T7	3		T9	1
all_values[60]	1661	1			T7	3		T9	1		T11	13
all_values[61]	1727	1			T2	1		T7	5		T9	1
all_values[62]	1607	1			T2	1		T11	18		T12	13
all_values[63]	1691	1			T2	3		T7	4		T9	2