Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1950	1			T7	40		T15	3		T16	6
all_values[1]	1884	1			T7	30		T15	5		T16	8
all_values[2]	1901	1			T7	39		T15	1		T16	9
all_values[3]	1994	1			T7	40		T15	2		T16	10
all_values[4]	1886	1			T7	38		T15	2		T16	7
all_values[5]	1915	1			T7	42		T15	1		T16	7
all_values[6]	1861	1			T7	32		T15	2		T16	6
all_values[7]	1846	1			T7	35		T15	2		T16	7
all_values[8]	1934	1			T7	31		T15	2		T16	7
all_values[9]	1968	1			T7	52		T15	5		T16	5
all_values[10]	1853	1			T7	29		T15	1		T16	5
all_values[11]	1907	1			T7	41		T15	2		T16	4
all_values[12]	1934	1			T7	41		T15	1		T16	6
all_values[13]	1961	1			T7	36		T15	4		T16	5
all_values[14]	1878	1			T7	38		T15	1		T16	7
all_values[15]	1973	1			T7	35		T16	3		T20	1
all_values[16]	2014	1			T7	30		T15	1		T16	7
all_values[17]	1986	1			T7	28		T15	2		T16	7
all_values[18]	1894	1			T7	31		T15	4		T16	4
all_values[19]	1954	1			T7	28		T15	4		T16	3
all_values[20]	1902	1			T7	45		T15	1		T16	4
all_values[21]	1936	1			T7	36		T16	5		T20	2
all_values[22]	2007	1			T7	32		T15	2		T16	6
all_values[23]	1890	1			T7	39		T15	2		T16	4
all_values[24]	1926	1			T7	26		T15	2		T16	2
all_values[25]	1860	1			T7	40		T15	6		T16	7
all_values[26]	1914	1			T7	45		T15	1		T16	7
all_values[27]	1984	1			T7	28		T15	3		T16	6
all_values[28]	2000	1			T7	48		T15	4		T16	3
all_values[29]	1856	1			T7	26		T15	5		T16	9
all_values[30]	1900	1			T7	47		T15	1		T16	4
all_values[31]	1942	1			T7	36		T15	5		T16	10
all_values[32]	1964	1			T7	50		T15	1		T16	3
all_values[33]	1952	1			T7	31		T15	3		T16	4
all_values[34]	1967	1			T7	31		T15	3		T16	4
all_values[35]	1974	1			T7	32		T15	6		T16	8
all_values[36]	1905	1			T7	30		T15	2		T16	3
all_values[37]	1897	1			T7	44		T15	1		T16	5
all_values[38]	1918	1			T7	43		T15	4		T16	3
all_values[39]	1871	1			T7	39		T16	8		T20	2
all_values[40]	1947	1			T7	40		T15	5		T16	8
all_values[41]	1969	1			T7	26		T15	3		T16	6
all_values[42]	1931	1			T7	42		T15	3		T16	5
all_values[43]	1926	1			T7	37		T15	2		T16	5
all_values[44]	1947	1			T7	42		T15	3		T16	3
all_values[45]	1966	1			T7	45		T15	7		T16	8
all_values[46]	1857	1			T7	41		T15	5		T16	10
all_values[47]	1913	1			T7	34		T15	6		T16	11
all_values[48]	1965	1			T7	36		T15	2		T16	11
all_values[49]	1943	1			T7	47		T15	2		T16	3
all_values[50]	1968	1			T7	35		T15	2		T20	1
all_values[51]	1960	1			T7	39		T15	2		T16	12
all_values[52]	1956	1			T7	44		T15	1		T16	8
all_values[53]	1905	1			T7	34		T15	3		T16	5
all_values[54]	1979	1			T7	52		T16	10		T20	2
all_values[55]	1936	1			T7	38		T15	4		T16	6
all_values[56]	1939	1			T7	44		T15	1		T16	7
all_values[57]	1876	1			T7	39		T15	5		T16	9
all_values[58]	1929	1			T7	35		T15	4		T16	5
all_values[59]	1891	1			T7	39		T15	2		T16	7
all_values[60]	1962	1			T7	27		T15	3		T16	4
all_values[61]	1864	1			T7	36		T15	2		T16	5
all_values[62]	1932	1			T7	34		T15	3		T16	2
all_values[63]	1972	1			T7	43		T15	1		T16	10