Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1610	1			T41	5		T15	22		T46	3
all_values[1]	1703	1			T41	1		T15	18		T46	1
all_values[2]	1641	1			T41	1		T15	20		T46	5
all_values[3]	1670	1			T41	3		T15	17		T46	1
all_values[4]	1692	1			T41	2		T15	20		T46	2
all_values[5]	1759	1			T41	2		T15	23		T46	5
all_values[6]	1649	1			T15	21		T46	5		T16	12
all_values[7]	1688	1			T41	1		T15	15		T46	6
all_values[8]	1635	1			T41	3		T15	17		T46	1
all_values[9]	1673	1			T41	2		T15	15		T46	4
all_values[10]	1680	1			T41	2		T15	20		T46	3
all_values[11]	1697	1			T41	1		T15	19		T46	2
all_values[12]	1649	1			T15	27		T46	1		T16	12
all_values[13]	1692	1			T41	1		T15	19		T46	4
all_values[14]	1727	1			T15	23		T46	3		T16	9
all_values[15]	1757	1			T41	2		T15	22		T46	5
all_values[16]	1719	1			T41	1		T15	21		T46	4
all_values[17]	1599	1			T41	1		T15	17		T46	2
all_values[18]	1719	1			T41	2		T15	32		T46	6
all_values[19]	1735	1			T15	20		T46	3		T16	16
all_values[20]	1649	1			T41	2		T15	28		T46	2
all_values[21]	1618	1			T41	4		T15	18		T46	3
all_values[22]	1756	1			T15	34		T46	3		T16	16
all_values[23]	1671	1			T41	1		T15	25		T46	1
all_values[24]	1661	1			T15	18		T46	7		T16	16
all_values[25]	1693	1			T41	3		T15	22		T46	1
all_values[26]	1667	1			T41	1		T15	20		T46	5
all_values[27]	1821	1			T41	1		T15	21		T46	1
all_values[28]	1676	1			T41	1		T15	19		T46	5
all_values[29]	1689	1			T41	1		T15	31		T46	2
all_values[30]	1674	1			T15	27		T46	1		T16	15
all_values[31]	1649	1			T15	25		T46	8		T16	13
all_values[32]	1688	1			T15	20		T46	2		T16	9
all_values[33]	1699	1			T41	2		T15	22		T46	3
all_values[34]	1753	1			T41	1		T15	22		T46	6
all_values[35]	1657	1			T41	2		T15	22		T46	1
all_values[36]	1698	1			T41	1		T15	12		T46	2
all_values[37]	1678	1			T41	3		T15	20		T46	4
all_values[38]	1689	1			T41	3		T15	23		T46	3
all_values[39]	1709	1			T41	3		T15	23		T46	1
all_values[40]	1624	1			T15	21		T46	3		T16	23
all_values[41]	1723	1			T15	26		T46	3		T16	16
all_values[42]	1709	1			T41	1		T15	25		T46	4
all_values[43]	1732	1			T41	2		T15	23		T46	5
all_values[44]	1718	1			T41	2		T15	17		T46	1
all_values[45]	1698	1			T41	2		T15	27		T46	1
all_values[46]	1660	1			T41	1		T15	18		T46	3
all_values[47]	1679	1			T15	27		T46	3		T16	14
all_values[48]	1711	1			T41	3		T15	22		T46	4
all_values[49]	1690	1			T41	1		T15	22		T46	3
all_values[50]	1661	1			T41	1		T15	18		T46	3
all_values[51]	1610	1			T15	23		T16	15		T18	3
all_values[52]	1664	1			T41	2		T15	23		T46	3
all_values[53]	1680	1			T41	4		T15	18		T46	3
all_values[54]	1689	1			T41	4		T15	20		T46	4
all_values[55]	1799	1			T15	23		T46	1		T16	14
all_values[56]	1636	1			T41	2		T15	24		T46	3
all_values[57]	1767	1			T15	20		T46	2		T16	24
all_values[58]	1751	1			T41	3		T15	25		T46	4
all_values[59]	1767	1			T15	20		T46	5		T16	9
all_values[60]	1695	1			T41	1		T15	19		T46	2
all_values[61]	1710	1			T41	2		T15	24		T46	4
all_values[62]	1682	1			T41	2		T15	17		T16	15
all_values[63]	1653	1			T15	22		T46	5		T16	22