Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1828	1			T1	1		T3	1		T16	5
all_values[1]	1827	1			T1	1		T3	4		T16	9
all_values[2]	1802	1			T16	4		T72	1		T35	10
all_values[3]	1859	1			T1	1		T3	3		T16	4
all_values[4]	1801	1			T16	6		T72	1		T35	7
all_values[5]	1813	1			T3	4		T16	3		T35	4
all_values[6]	1773	1			T1	1		T3	2		T16	4
all_values[7]	1723	1			T1	1		T3	4		T16	3
all_values[8]	1834	1			T3	4		T16	3		T35	2
all_values[9]	1789	1			T3	6		T16	3		T72	2
all_values[10]	1812	1			T3	1		T16	2		T35	3
all_values[11]	1731	1			T1	1		T3	2		T16	4
all_values[12]	1774	1			T1	2		T3	2		T16	7
all_values[13]	1837	1			T3	2		T16	7		T35	2
all_values[14]	1716	1			T3	3		T16	5		T35	5
all_values[15]	1818	1			T1	2		T3	4		T16	4
all_values[16]	1814	1			T3	4		T16	8		T35	3
all_values[17]	1859	1			T3	1		T16	4		T72	1
all_values[18]	1777	1			T3	1		T16	10		T35	5
all_values[19]	1790	1			T3	3		T16	5		T35	2
all_values[20]	1781	1			T1	1		T3	4		T16	3
all_values[21]	1813	1			T1	1		T3	1		T16	6
all_values[22]	1788	1			T1	3		T3	4		T16	4
all_values[23]	1720	1			T1	1		T3	3		T16	5
all_values[24]	1824	1			T1	1		T3	3		T16	9
all_values[25]	1818	1			T3	1		T16	5		T35	8
all_values[26]	1827	1			T3	1		T16	8		T72	1
all_values[27]	1871	1			T3	6		T16	2		T35	3
all_values[28]	1752	1			T1	2		T3	4		T16	4
all_values[29]	1790	1			T1	2		T3	1		T16	6
all_values[30]	1750	1			T3	1		T16	5		T35	3
all_values[31]	1734	1			T3	3		T16	3		T35	6
all_values[32]	1856	1			T3	3		T16	4		T35	5
all_values[33]	1869	1			T1	2		T3	6		T16	6
all_values[34]	1783	1			T3	4		T16	6		T72	1
all_values[35]	1762	1			T1	1		T3	2		T16	4
all_values[36]	1731	1			T3	5		T16	4		T35	5
all_values[37]	1766	1			T3	1		T16	5		T35	9
all_values[38]	1774	1			T1	1		T3	1		T16	7
all_values[39]	1746	1			T1	1		T3	4		T16	6
all_values[40]	1766	1			T1	1		T3	2		T16	4
all_values[41]	1752	1			T3	2		T16	8		T35	3
all_values[42]	1778	1			T1	2		T3	4		T16	3
all_values[43]	1801	1			T3	2		T16	4		T35	8
all_values[44]	1786	1			T1	1		T3	2		T16	3
all_values[45]	1836	1			T16	5		T35	5		T20	1
all_values[46]	1752	1			T1	2		T3	3		T16	7
all_values[47]	1724	1			T3	2		T16	5		T35	6
all_values[48]	1869	1			T1	1		T3	1		T16	3
all_values[49]	1743	1			T1	1		T3	4		T16	10
all_values[50]	1826	1			T1	1		T3	3		T16	2
all_values[51]	1802	1			T1	2		T3	1		T16	10
all_values[52]	1816	1			T1	3		T3	3		T16	4
all_values[53]	1833	1			T3	3		T16	1		T35	6
all_values[54]	1800	1			T3	6		T16	5		T35	7
all_values[55]	1790	1			T3	3		T16	8		T72	1
all_values[56]	1820	1			T1	1		T3	7		T16	3
all_values[57]	1830	1			T1	2		T3	2		T16	3
all_values[58]	1806	1			T1	2		T3	2		T16	2
all_values[59]	1764	1			T1	1		T3	6		T16	4
all_values[60]	1847	1			T1	1		T3	2		T16	6
all_values[61]	1805	1			T3	3		T16	6		T72	1
all_values[62]	1773	1			T3	5		T16	7		T35	1
all_values[63]	1831	1			T1	2		T3	4		T16	8