Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 502 1 T9 3 T10 3 T12 2
all_values[1] 535 1 T9 4 T10 4 T12 1
all_values[2] 536 1 T9 7 T10 1 T12 1
all_values[3] 518 1 T9 7 T10 2 T12 1
all_values[4] 473 1 T9 3 T12 2 T14 1
all_values[5] 491 1 T9 7 T10 3 T12 1
all_values[6] 514 1 T9 3 T10 3 T12 4
all_values[7] 480 1 T9 8 T10 1 T12 2
all_values[8] 496 1 T9 3 T10 4 T12 2
all_values[9] 486 1 T9 6 T10 3 T12 1
all_values[10] 518 1 T9 3 T12 2 T16 1
all_values[11] 536 1 T9 5 T10 3 T12 2
all_values[12] 502 1 T9 7 T10 1 T12 2
all_values[13] 538 1 T9 4 T10 2 T12 1
all_values[14] 487 1 T9 8 T10 3 T12 1
all_values[15] 525 1 T9 3 T10 4 T12 5
all_values[16] 498 1 T9 8 T10 1 T12 3
all_values[17] 535 1 T9 4 T10 3 T12 7
all_values[18] 508 1 T9 4 T10 1 T12 3
all_values[19] 456 1 T9 6 T10 2 T12 1
all_values[20] 519 1 T9 10 T10 1 T12 1
all_values[21] 490 1 T9 5 T10 1 T12 1
all_values[22] 465 1 T9 4 T10 2 T12 4
all_values[23] 474 1 T9 2 T10 2 T12 3

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