Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1862	1			T3	1		T7	15		T8	2
all_values[1]	1818	1			T7	12		T9	4		T11	12
all_values[2]	1883	1			T3	2		T7	16		T8	1
all_values[3]	1908	1			T3	1		T7	10		T8	1
all_values[4]	1793	1			T3	2		T7	25		T8	2
all_values[5]	1911	1			T3	1		T7	16		T8	3
all_values[6]	1840	1			T3	3		T7	13		T8	3
all_values[7]	1854	1			T7	11		T8	3		T9	2
all_values[8]	1925	1			T3	1		T7	20		T8	2
all_values[9]	1901	1			T3	1		T7	7		T8	2
all_values[10]	1893	1			T3	1		T7	17		T8	1
all_values[11]	1920	1			T3	2		T7	11		T8	3
all_values[12]	1892	1			T3	2		T7	16		T9	2
all_values[13]	1936	1			T7	22		T8	3		T9	9
all_values[14]	1903	1			T7	17		T8	2		T9	6
all_values[15]	1861	1			T3	1		T7	14		T8	3
all_values[16]	1829	1			T7	13		T8	3		T9	3
all_values[17]	1848	1			T3	2		T7	14		T8	1
all_values[18]	1907	1			T7	14		T8	5		T9	5
all_values[19]	1877	1			T3	3		T7	16		T9	2
all_values[20]	1869	1			T3	1		T7	9		T8	1
all_values[21]	1844	1			T3	2		T7	17		T8	2
all_values[22]	1863	1			T3	3		T7	10		T8	1
all_values[23]	1876	1			T3	2		T7	13		T8	1
all_values[24]	1837	1			T3	4		T7	11		T8	4
all_values[25]	1858	1			T3	2		T7	7		T8	2
all_values[26]	1872	1			T7	11		T8	2		T9	2
all_values[27]	1860	1			T7	20		T9	2		T11	5
all_values[28]	1848	1			T7	9		T8	1		T9	4
all_values[29]	1920	1			T3	3		T7	11		T8	1
all_values[30]	1924	1			T3	2		T7	12		T8	4
all_values[31]	1919	1			T3	3		T7	14		T8	2
all_values[32]	1882	1			T3	1		T7	13		T8	1
all_values[33]	1906	1			T7	13		T8	2		T9	8
all_values[34]	1884	1			T7	20		T8	3		T9	4
all_values[35]	1847	1			T3	1		T7	9		T8	2
all_values[36]	1909	1			T3	1		T7	14		T8	1
all_values[37]	1878	1			T3	3		T7	11		T8	2
all_values[38]	1844	1			T3	2		T7	12		T8	2
all_values[39]	1870	1			T3	3		T7	10		T8	4
all_values[40]	1925	1			T3	1		T7	6		T8	3
all_values[41]	1915	1			T3	4		T7	13		T8	3
all_values[42]	1834	1			T3	2		T7	17		T8	4
all_values[43]	1927	1			T3	1		T7	14		T9	4
all_values[44]	1862	1			T3	1		T7	11		T8	2
all_values[45]	1843	1			T3	1		T7	12		T8	4
all_values[46]	1849	1			T3	2		T7	15		T8	3
all_values[47]	1872	1			T3	3		T7	17		T8	3
all_values[48]	1839	1			T3	2		T7	15		T8	1
all_values[49]	1904	1			T3	2		T7	10		T8	2
all_values[50]	1810	1			T7	12		T8	3		T9	4
all_values[51]	1825	1			T3	2		T7	14		T9	4
all_values[52]	1922	1			T7	7		T8	5		T9	5
all_values[53]	1931	1			T3	2		T7	10		T8	3
all_values[54]	1955	1			T3	2		T7	13		T8	2
all_values[55]	1901	1			T3	1		T7	14		T8	4
all_values[56]	1844	1			T3	3		T7	15		T9	2
all_values[57]	1911	1			T3	2		T7	13		T9	4
all_values[58]	1936	1			T7	14		T8	6		T9	2
all_values[59]	1873	1			T3	2		T7	11		T8	2
all_values[60]	1818	1			T3	1		T7	16		T8	1
all_values[61]	1837	1			T3	2		T7	9		T8	2
all_values[62]	1905	1			T3	2		T7	16		T8	4
all_values[63]	1865	1			T3	3		T7	12		T8	3