Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1847	1			T1	6		T2	23		T3	1
all_values[1]	1741	1			T1	8		T2	20		T3	4
all_values[2]	1834	1			T1	7		T2	20		T3	6
all_values[3]	1697	1			T1	6		T2	28		T3	5
all_values[4]	1778	1			T1	10		T2	24		T3	7
all_values[5]	1829	1			T1	9		T2	17		T3	4
all_values[6]	1787	1			T1	9		T2	23		T3	3
all_values[7]	1834	1			T1	7		T2	27		T3	2
all_values[8]	1780	1			T1	5		T2	17		T3	2
all_values[9]	1776	1			T1	2		T2	25		T3	5
all_values[10]	1789	1			T1	5		T2	20		T3	6
all_values[11]	1788	1			T1	10		T2	23		T3	4
all_values[12]	1782	1			T1	8		T2	26		T3	1
all_values[13]	1774	1			T1	1		T2	21		T3	9
all_values[14]	1826	1			T1	11		T2	28		T3	4
all_values[15]	1869	1			T1	9		T2	33		T3	5
all_values[16]	1844	1			T1	7		T2	24		T3	2
all_values[17]	1825	1			T1	12		T2	24		T3	4
all_values[18]	1773	1			T1	11		T2	33		T3	4
all_values[19]	1841	1			T1	6		T2	19		T3	2
all_values[20]	1827	1			T1	6		T2	30		T7	2
all_values[21]	1834	1			T1	9		T2	18		T3	5
all_values[22]	1821	1			T1	5		T2	24		T3	5
all_values[23]	1780	1			T1	8		T2	21		T3	3
all_values[24]	1770	1			T1	6		T2	22		T3	6
all_values[25]	1830	1			T1	9		T2	19		T3	3
all_values[26]	1798	1			T1	12		T2	22		T3	3
all_values[27]	1807	1			T1	10		T2	18		T3	3
all_values[28]	1778	1			T1	5		T2	28		T3	2
all_values[29]	1843	1			T1	6		T2	21		T3	3
all_values[30]	1800	1			T1	4		T2	25		T3	4
all_values[31]	1715	1			T1	6		T2	31		T3	6
all_values[32]	1790	1			T1	9		T2	15		T3	6
all_values[33]	1833	1			T1	9		T2	25		T3	4
all_values[34]	1799	1			T1	7		T2	24		T3	7
all_values[35]	1807	1			T1	5		T2	27		T3	1
all_values[36]	1790	1			T1	9		T2	22		T3	3
all_values[37]	1760	1			T1	7		T2	20		T3	4
all_values[38]	1734	1			T1	6		T2	20		T3	6
all_values[39]	1839	1			T1	6		T2	20		T3	3
all_values[40]	1860	1			T1	11		T2	33		T3	3
all_values[41]	1782	1			T1	7		T2	18		T3	5
all_values[42]	1858	1			T1	9		T2	18		T3	2
all_values[43]	1811	1			T1	7		T2	22		T7	1
all_values[44]	1775	1			T1	8		T2	25		T3	2
all_values[45]	1835	1			T1	11		T2	20		T3	2
all_values[46]	1770	1			T1	8		T2	26		T3	6
all_values[47]	1778	1			T1	12		T2	24		T3	4
all_values[48]	1868	1			T1	9		T2	20		T3	3
all_values[49]	1877	1			T1	8		T2	20		T3	4
all_values[50]	1787	1			T1	12		T2	30		T3	5
all_values[51]	1783	1			T1	8		T2	19		T3	1
all_values[52]	1753	1			T1	6		T2	18		T3	3
all_values[53]	1822	1			T1	4		T2	28		T3	3
all_values[54]	1797	1			T1	4		T2	19		T3	4
all_values[55]	1802	1			T1	9		T2	32		T3	4
all_values[56]	1785	1			T1	9		T2	19		T3	3
all_values[57]	1795	1			T1	6		T2	17		T3	6
all_values[58]	1888	1			T1	12		T2	25		T3	5
all_values[59]	1734	1			T1	5		T2	27		T3	3
all_values[60]	1780	1			T1	6		T2	27		T3	4
all_values[61]	1791	1			T1	9		T2	30		T3	2
all_values[62]	1805	1			T1	6		T2	24		T3	4
all_values[63]	1806	1			T1	16		T2	19		T3	10