Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1618	1			T2	5		T3	3		T10	4
all_values[1]	1724	1			T10	3		T19	3		T22	3
all_values[2]	1739	1			T2	1		T10	2		T19	3
all_values[3]	1731	1			T2	5		T3	2		T10	7
all_values[4]	1620	1			T2	2		T3	1		T10	2
all_values[5]	1717	1			T2	1		T3	3		T10	6
all_values[6]	1621	1			T2	2		T3	3		T10	4
all_values[7]	1690	1			T2	3		T3	3		T10	4
all_values[8]	1773	1			T2	4		T3	2		T10	6
all_values[9]	1667	1			T2	1		T3	3		T10	6
all_values[10]	1620	1			T2	4		T3	2		T10	5
all_values[11]	1706	1			T2	1		T3	4		T10	3
all_values[12]	1591	1			T3	3		T10	5		T19	1
all_values[13]	1669	1			T2	3		T3	4		T10	3
all_values[14]	1670	1			T2	2		T3	2		T10	7
all_values[15]	1625	1			T2	2		T3	1		T10	4
all_values[16]	1661	1			T2	4		T3	1		T10	5
all_values[17]	1639	1			T2	3		T10	7		T19	3
all_values[18]	1652	1			T3	3		T10	4		T19	3
all_values[19]	1716	1			T2	1		T3	4		T10	3
all_values[20]	1745	1			T2	3		T3	4		T10	3
all_values[21]	1666	1			T2	2		T3	1		T10	5
all_values[22]	1748	1			T2	1		T3	3		T10	8
all_values[23]	1678	1			T2	2		T3	1		T10	4
all_values[24]	1656	1			T3	2		T10	6		T19	5
all_values[25]	1670	1			T3	2		T10	4		T15	1
all_values[26]	1698	1			T3	5		T10	3		T19	2
all_values[27]	1690	1			T2	2		T3	1		T10	4
all_values[28]	1745	1			T2	2		T3	3		T10	1
all_values[29]	1760	1			T2	2		T3	3		T10	5
all_values[30]	1710	1			T2	1		T3	2		T10	6
all_values[31]	1627	1			T2	4		T3	2		T10	2
all_values[32]	1703	1			T2	2		T3	1		T10	6
all_values[33]	1688	1			T2	4		T3	1		T10	3
all_values[34]	1729	1			T2	4		T3	2		T10	6
all_values[35]	1718	1			T2	3		T3	3		T10	5
all_values[36]	1674	1			T2	1		T3	5		T10	2
all_values[37]	1712	1			T3	3		T10	1		T19	3
all_values[38]	1592	1			T2	4		T10	4		T19	3
all_values[39]	1626	1			T10	8		T19	5		T35	2
all_values[40]	1713	1			T2	2		T3	3		T10	5
all_values[41]	1646	1			T2	2		T3	2		T10	2
all_values[42]	1676	1			T2	1		T3	1		T10	3
all_values[43]	1677	1			T2	1		T3	1		T10	6
all_values[44]	1672	1			T3	6		T10	5		T15	1
all_values[45]	1626	1			T2	1		T3	3		T10	5
all_values[46]	1733	1			T2	4		T3	3		T10	2
all_values[47]	1703	1			T3	6		T10	5		T15	2
all_values[48]	1699	1			T2	4		T3	1		T10	7
all_values[49]	1738	1			T2	5		T3	3		T10	7
all_values[50]	1647	1			T2	1		T3	5		T10	4
all_values[51]	1672	1			T2	2		T3	6		T10	4
all_values[52]	1597	1			T2	3		T3	2		T10	5
all_values[53]	1691	1			T2	1		T3	4		T10	7
all_values[54]	1613	1			T2	1		T3	1		T10	2
all_values[55]	1715	1			T2	3		T3	2		T10	6
all_values[56]	1686	1			T3	3		T10	4		T19	4
all_values[57]	1703	1			T2	1		T3	1		T10	1
all_values[58]	1631	1			T2	1		T3	3		T10	5
all_values[59]	1700	1			T2	4		T3	4		T10	3
all_values[60]	1674	1			T2	1		T3	5		T10	3
all_values[61]	1610	1			T2	1		T3	3		T10	4
all_values[62]	1658	1			T2	2		T3	3		T10	3
all_values[63]	1653	1			T2	2		T3	4		T10	3