Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1681	1			T1	3		T2	6		T7	19
all_values[1]	1733	1			T1	3		T2	9		T7	30
all_values[2]	1805	1			T1	3		T2	6		T7	31
all_values[3]	1728	1			T1	1		T2	9		T7	30
all_values[4]	1763	1			T1	2		T2	8		T7	33
all_values[5]	1691	1			T1	2		T2	4		T7	37
all_values[6]	1788	1			T1	2		T2	9		T7	28
all_values[7]	1727	1			T1	5		T2	7		T7	31
all_values[8]	1818	1			T1	2		T2	8		T7	31
all_values[9]	1844	1			T1	3		T2	4		T7	32
all_values[10]	1780	1			T1	2		T2	8		T7	35
all_values[11]	1792	1			T1	1		T2	13		T7	37
all_values[12]	1711	1			T1	2		T2	5		T7	23
all_values[13]	1725	1			T1	2		T2	3		T7	37
all_values[14]	1728	1			T1	5		T2	3		T7	24
all_values[15]	1708	1			T1	2		T2	6		T7	23
all_values[16]	1740	1			T1	1		T2	6		T7	35
all_values[17]	1797	1			T1	3		T2	7		T7	36
all_values[18]	1716	1			T1	1		T2	6		T7	30
all_values[19]	1749	1			T1	1		T2	6		T7	28
all_values[20]	1710	1			T1	4		T2	8		T7	28
all_values[21]	1744	1			T1	1		T2	5		T7	25
all_values[22]	1761	1			T1	1		T2	5		T7	37
all_values[23]	1781	1			T1	1		T2	13		T7	34
all_values[24]	1775	1			T1	3		T2	6		T7	26
all_values[25]	1696	1			T1	3		T2	9		T7	28
all_values[26]	1711	1			T1	2		T2	9		T7	38
all_values[27]	1725	1			T1	3		T2	5		T7	25
all_values[28]	1757	1			T1	1		T2	1		T7	23
all_values[29]	1711	1			T1	3		T2	4		T7	31
all_values[30]	1691	1			T2	6		T7	29		T10	6
all_values[31]	1654	1			T1	1		T2	4		T7	30
all_values[32]	1785	1			T1	2		T2	8		T7	36
all_values[33]	1750	1			T1	4		T2	9		T7	23
all_values[34]	1722	1			T1	3		T2	8		T7	27
all_values[35]	1725	1			T1	2		T2	6		T7	32
all_values[36]	1768	1			T1	2		T2	7		T7	31
all_values[37]	1719	1			T1	1		T2	6		T7	25
all_values[38]	1773	1			T2	2		T7	32		T10	10
all_values[39]	1692	1			T2	6		T7	34		T10	9
all_values[40]	1754	1			T1	5		T2	2		T7	36
all_values[41]	1721	1			T1	5		T2	1		T7	29
all_values[42]	1801	1			T1	2		T2	4		T7	24
all_values[43]	1747	1			T1	1		T2	8		T7	33
all_values[44]	1688	1			T1	1		T2	2		T7	27
all_values[45]	1786	1			T2	4		T7	37		T10	9
all_values[46]	1730	1			T1	4		T2	3		T7	34
all_values[47]	1703	1			T2	3		T7	24		T10	11
all_values[48]	1762	1			T1	2		T2	12		T7	34
all_values[49]	1789	1			T1	1		T2	5		T7	25
all_values[50]	1744	1			T1	4		T2	8		T7	32
all_values[51]	1715	1			T1	4		T2	5		T7	38
all_values[52]	1769	1			T1	1		T2	7		T7	29
all_values[53]	1766	1			T1	4		T2	6		T7	28
all_values[54]	1754	1			T1	2		T2	6		T7	28
all_values[55]	1713	1			T1	6		T2	6		T7	35
all_values[56]	1681	1			T1	1		T2	4		T7	32
all_values[57]	1656	1			T1	2		T2	7		T7	23
all_values[58]	1751	1			T1	3		T2	2		T7	30
all_values[59]	1763	1			T1	3		T2	8		T7	30
all_values[60]	1711	1			T1	3		T2	7		T7	39
all_values[61]	1769	1			T1	1		T2	4		T7	28
all_values[62]	1785	1			T1	1		T2	7		T7	29
all_values[63]	1832	1			T1	2		T2	10		T7	37