Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1708	1			T8	36		T10	3		T14	6
all_values[1]	1648	1			T8	35		T10	4		T14	13
all_values[2]	1736	1			T8	49		T10	1		T14	4
all_values[3]	1654	1			T8	36		T10	1		T14	6
all_values[4]	1663	1			T8	26		T10	2		T14	10
all_values[5]	1708	1			T8	27		T10	1		T14	5
all_values[6]	1624	1			T8	25		T10	4		T14	10
all_values[7]	1701	1			T8	40		T10	3		T14	8
all_values[8]	1657	1			T8	43		T10	2		T14	12
all_values[9]	1726	1			T8	44		T10	6		T14	13
all_values[10]	1618	1			T8	21		T10	2		T14	7
all_values[11]	1709	1			T8	35		T10	2		T14	6
all_values[12]	1709	1			T8	29		T10	5		T14	17
all_values[13]	1742	1			T8	35		T14	10		T15	27
all_values[14]	1741	1			T8	34		T10	5		T14	6
all_values[15]	1696	1			T8	29		T10	1		T14	8
all_values[16]	1752	1			T8	42		T10	4		T14	10
all_values[17]	1740	1			T8	35		T10	2		T14	9
all_values[18]	1675	1			T8	31		T10	1		T14	11
all_values[19]	1650	1			T8	35		T10	2		T14	5
all_values[20]	1611	1			T8	34		T10	2		T14	9
all_values[21]	1656	1			T8	33		T14	9		T15	21
all_values[22]	1632	1			T8	39		T10	1		T14	10
all_values[23]	1745	1			T8	38		T10	2		T14	11
all_values[24]	1695	1			T8	37		T10	4		T14	11
all_values[25]	1725	1			T8	40		T10	5		T14	11
all_values[26]	1692	1			T8	39		T10	3		T14	5
all_values[27]	1734	1			T8	27		T10	5		T14	6
all_values[28]	1641	1			T8	31		T10	3		T14	8
all_values[29]	1707	1			T8	39		T10	2		T14	13
all_values[30]	1719	1			T8	28		T10	7		T14	11
all_values[31]	1740	1			T8	39		T10	2		T14	12
all_values[32]	1639	1			T8	31		T10	5		T14	9
all_values[33]	1708	1			T8	29		T10	7		T14	6
all_values[34]	1658	1			T8	30		T10	1		T14	12
all_values[35]	1670	1			T8	32		T14	7		T15	21
all_values[36]	1680	1			T8	34		T10	3		T14	14
all_values[37]	1764	1			T8	40		T10	2		T14	5
all_values[38]	1646	1			T8	28		T10	5		T14	14
all_values[39]	1657	1			T8	42		T10	6		T14	13
all_values[40]	1704	1			T8	23		T10	2		T14	10
all_values[41]	1720	1			T8	50		T10	2		T14	11
all_values[42]	1611	1			T8	36		T10	3		T14	6
all_values[43]	1659	1			T8	30		T10	5		T14	16
all_values[44]	1738	1			T8	31		T10	3		T14	8
all_values[45]	1633	1			T8	30		T10	4		T14	7
all_values[46]	1730	1			T8	44		T10	6		T14	16
all_values[47]	1631	1			T8	30		T10	2		T14	7
all_values[48]	1683	1			T8	29		T10	9		T14	8
all_values[49]	1716	1			T8	40		T10	2		T14	9
all_values[50]	1683	1			T8	33		T10	3		T14	8
all_values[51]	1726	1			T8	34		T10	4		T14	12
all_values[52]	1710	1			T8	37		T10	4		T14	8
all_values[53]	1605	1			T8	29		T10	4		T14	5
all_values[54]	1679	1			T8	27		T10	3		T14	16
all_values[55]	1741	1			T8	41		T10	4		T14	9
all_values[56]	1731	1			T8	35		T10	2		T14	14
all_values[57]	1713	1			T8	40		T10	6		T14	16
all_values[58]	1751	1			T8	21		T10	2		T14	5
all_values[59]	1693	1			T8	31		T10	7		T14	5
all_values[60]	1674	1			T8	32		T10	2		T14	8
all_values[61]	1715	1			T8	44		T10	5		T14	11
all_values[62]	1693	1			T8	33		T10	3		T14	5
all_values[63]	1706	1			T8	51		T10	3		T14	8