Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1955	1			T1	1		T3	4		T7	11
all_values[1]	1910	1			T1	3		T3	3		T7	12
all_values[2]	1925	1			T1	5		T3	6		T7	11
all_values[3]	1963	1			T1	2		T3	4		T7	6
all_values[4]	1939	1			T1	6		T3	6		T7	16
all_values[5]	2019	1			T1	2		T3	4		T7	17
all_values[6]	1941	1			T1	2		T3	6		T7	10
all_values[7]	1912	1			T1	4		T3	6		T7	10
all_values[8]	1936	1			T1	3		T3	3		T7	13
all_values[9]	2059	1			T1	5		T3	3		T7	13
all_values[10]	1980	1			T1	3		T3	7		T7	13
all_values[11]	1975	1			T1	4		T3	6		T7	17
all_values[12]	2011	1			T1	3		T3	4		T7	14
all_values[13]	1948	1			T1	3		T3	4		T7	17
all_values[14]	1930	1			T1	2		T3	5		T7	18
all_values[15]	2046	1			T1	2		T3	2		T7	11
all_values[16]	2000	1			T1	2		T3	2		T7	8
all_values[17]	1960	1			T1	3		T3	4		T7	16
all_values[18]	1960	1			T1	4		T3	3		T7	14
all_values[19]	1985	1			T1	7		T3	4		T7	14
all_values[20]	1942	1			T1	7		T3	6		T7	23
all_values[21]	1935	1			T1	4		T3	4		T7	14
all_values[22]	2009	1			T1	3		T3	2		T7	13
all_values[23]	2007	1			T1	3		T3	4		T7	9
all_values[24]	1983	1			T1	2		T3	4		T7	17
all_values[25]	1912	1			T1	2		T3	4		T7	13
all_values[26]	1972	1			T1	1		T3	4		T7	19
all_values[27]	1964	1			T1	4		T3	2		T7	20
all_values[28]	2031	1			T1	1		T3	13		T7	11
all_values[29]	1991	1			T1	1		T3	3		T7	9
all_values[30]	1984	1			T1	3		T3	5		T7	6
all_values[31]	1933	1			T3	3		T7	11		T4	2
all_values[32]	2018	1			T1	2		T3	4		T7	10
all_values[33]	1962	1			T1	5		T3	4		T7	11
all_values[34]	1903	1			T1	1		T3	2		T7	20
all_values[35]	1878	1			T1	3		T3	3		T7	14
all_values[36]	1984	1			T3	6		T7	6		T4	4
all_values[37]	2034	1			T1	1		T3	2		T7	14
all_values[38]	1986	1			T1	8		T3	3		T7	14
all_values[39]	1935	1			T1	5		T3	10		T7	16
all_values[40]	1925	1			T1	5		T3	2		T7	11
all_values[41]	1945	1			T1	3		T3	3		T7	9
all_values[42]	1921	1			T1	3		T3	4		T7	7
all_values[43]	1977	1			T1	1		T3	7		T7	14
all_values[44]	1926	1			T1	7		T3	1		T7	14
all_values[45]	1926	1			T1	3		T3	2		T7	8
all_values[46]	2010	1			T1	1		T3	3		T7	14
all_values[47]	1972	1			T1	3		T3	5		T7	13
all_values[48]	1968	1			T1	5		T3	4		T7	15
all_values[49]	2003	1			T1	1		T3	5		T7	14
all_values[50]	2036	1			T3	2		T7	10		T4	3
all_values[51]	2004	1			T1	3		T3	4		T7	8
all_values[52]	1957	1			T1	3		T3	4		T7	9
all_values[53]	1896	1			T1	4		T3	6		T7	11
all_values[54]	1993	1			T1	2		T3	6		T7	9
all_values[55]	1990	1			T1	5		T3	6		T7	13
all_values[56]	1909	1			T1	1		T3	7		T7	15
all_values[57]	1892	1			T1	3		T3	4		T7	16
all_values[58]	1965	1			T3	3		T7	9		T4	1
all_values[59]	2001	1			T1	2		T3	5		T7	18
all_values[60]	1867	1			T1	1		T3	7		T7	12
all_values[61]	1963	1			T1	1		T3	2		T7	7
all_values[62]	1888	1			T1	1		T3	3		T7	15
all_values[63]	1984	1			T1	1		T3	3		T7	14