Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1612	1			T8	1		T10	3		T11	28
all_values[1]	1638	1			T7	1		T8	1		T10	1
all_values[2]	1630	1			T10	2		T11	20		T14	8
all_values[3]	1606	1			T8	1		T10	2		T11	30
all_values[4]	1575	1			T10	2		T11	22		T14	3
all_values[5]	1612	1			T10	4		T11	26		T14	4
all_values[6]	1559	1			T8	1		T10	2		T11	24
all_values[7]	1592	1			T8	2		T11	24		T14	10
all_values[8]	1603	1			T10	3		T11	27		T14	6
all_values[9]	1610	1			T10	2		T11	17		T14	10
all_values[10]	1635	1			T8	2		T11	27		T14	5
all_values[11]	1597	1			T10	5		T11	32		T14	9
all_values[12]	1615	1			T8	2		T10	2		T11	21
all_values[13]	1612	1			T10	2		T11	20		T14	6
all_values[14]	1655	1			T10	2		T11	31		T14	7
all_values[15]	1615	1			T7	1		T10	3		T11	22
all_values[16]	1670	1			T7	1		T8	2		T11	28
all_values[17]	1620	1			T10	1		T11	25		T14	3
all_values[18]	1601	1			T8	1		T10	4		T11	26
all_values[19]	1570	1			T8	2		T11	14		T14	4
all_values[20]	1668	1			T8	1		T10	5		T11	29
all_values[21]	1573	1			T8	2		T10	4		T11	30
all_values[22]	1657	1			T10	4		T11	25		T14	12
all_values[23]	1595	1			T8	2		T10	3		T11	31
all_values[24]	1571	1			T8	2		T10	4		T11	23
all_values[25]	1672	1			T8	1		T10	5		T11	17
all_values[26]	1644	1			T7	1		T10	3		T11	31
all_values[27]	1594	1			T8	1		T10	1		T11	22
all_values[28]	1578	1			T10	1		T11	24		T14	6
all_values[29]	1539	1			T8	1		T10	1		T11	35
all_values[30]	1602	1			T7	1		T8	2		T10	3
all_values[31]	1687	1			T8	2		T10	3		T11	31
all_values[32]	1577	1			T8	4		T10	4		T11	20
all_values[33]	1662	1			T10	1		T11	26		T14	4
all_values[34]	1647	1			T10	4		T11	24		T14	4
all_values[35]	1597	1			T8	3		T10	3		T11	26
all_values[36]	1596	1			T8	2		T10	4		T11	23
all_values[37]	1673	1			T11	28		T14	6		T18	19
all_values[38]	1676	1			T8	2		T11	27		T14	9
all_values[39]	1624	1			T8	1		T10	3		T11	27
all_values[40]	1608	1			T8	2		T10	4		T11	33
all_values[41]	1622	1			T11	35		T14	4		T18	17
all_values[42]	1623	1			T10	4		T11	22		T14	9
all_values[43]	1568	1			T10	2		T11	36		T14	7
all_values[44]	1644	1			T7	1		T8	2		T10	5
all_values[45]	1643	1			T10	1		T11	30		T14	5
all_values[46]	1609	1			T7	1		T8	4		T11	20
all_values[47]	1663	1			T7	3		T8	2		T10	2
all_values[48]	1612	1			T7	1		T8	1		T10	2
all_values[49]	1560	1			T8	1		T10	1		T11	25
all_values[50]	1646	1			T10	3		T11	23		T14	8
all_values[51]	1559	1			T7	1		T8	1		T10	1
all_values[52]	1660	1			T10	3		T11	18		T14	13
all_values[53]	1603	1			T8	1		T10	4		T11	19
all_values[54]	1660	1			T8	1		T10	2		T11	29
all_values[55]	1652	1			T8	1		T10	2		T11	22
all_values[56]	1587	1			T8	2		T10	1		T11	26
all_values[57]	1680	1			T8	2		T10	6		T11	28
all_values[58]	1682	1			T10	1		T11	30		T14	4
all_values[59]	1540	1			T8	2		T10	5		T11	23
all_values[60]	1630	1			T8	1		T10	1		T11	29
all_values[61]	1654	1			T10	6		T11	30		T14	8
all_values[62]	1588	1			T7	1		T10	1		T11	19
all_values[63]	1589	1			T8	2		T10	2		T11	28