Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 573 1 T7 1 T8 1 T15 7
all_values[1] 526 1 T7 1 T15 7 T18 7
all_values[2] 561 1 T15 3 T18 7 T20 2
all_values[3] 527 1 T7 1 T15 7 T18 4
all_values[4] 522 1 T15 4 T16 1 T18 1
all_values[5] 553 1 T8 1 T12 1 T15 6
all_values[6] 528 1 T15 3 T18 6 T19 3
all_values[7] 525 1 T8 1 T12 1 T15 5
all_values[8] 525 1 T8 1 T15 7 T18 9
all_values[9] 567 1 T8 2 T15 4 T18 6
all_values[10] 511 1 T15 5 T18 7 T19 2
all_values[11] 509 1 T12 1 T15 5 T18 6
all_values[12] 547 1 T12 2 T15 7 T18 6
all_values[13] 532 1 T8 2 T12 1 T15 6
all_values[14] 512 1 T15 6 T18 8 T19 4
all_values[15] 581 1 T12 1 T15 5 T18 5
all_values[16] 545 1 T8 1 T15 4 T18 7
all_values[17] 523 1 T8 2 T15 4 T18 3
all_values[18] 584 1 T8 2 T15 6 T18 5
all_values[19] 563 1 T15 6 T18 12 T39 2
all_values[20] 546 1 T7 1 T8 1 T15 5
all_values[21] 581 1 T8 1 T12 1 T15 2
all_values[22] 523 1 T7 2 T12 1 T15 6
all_values[23] 509 1 T8 1 T15 7 T18 1

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