Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1865	1			T12	2		T15	13		T16	3
all_values[1]	1849	1			T12	2		T15	12		T16	6
all_values[2]	1886	1			T12	3		T15	12		T16	6
all_values[3]	1852	1			T12	5		T15	6		T16	5
all_values[4]	1819	1			T12	6		T15	13		T16	6
all_values[5]	1880	1			T15	13		T16	3		T18	16
all_values[6]	1834	1			T12	2		T15	9		T16	4
all_values[7]	1867	1			T12	3		T15	10		T16	7
all_values[8]	1840	1			T12	1		T15	13		T16	3
all_values[9]	1898	1			T12	3		T15	12		T16	4
all_values[10]	1793	1			T12	3		T15	6		T16	5
all_values[11]	1868	1			T12	1		T15	15		T16	2
all_values[12]	1847	1			T12	1		T15	14		T16	7
all_values[13]	1890	1			T15	10		T16	2		T18	30
all_values[14]	1867	1			T12	3		T15	18		T16	3
all_values[15]	1915	1			T12	6		T15	11		T16	7
all_values[16]	1877	1			T12	5		T15	14		T16	2
all_values[17]	1819	1			T12	2		T15	16		T16	6
all_values[18]	1904	1			T12	4		T15	13		T16	4
all_values[19]	1864	1			T12	2		T15	6		T16	5
all_values[20]	1908	1			T12	2		T15	13		T16	6
all_values[21]	1905	1			T12	2		T15	17		T16	4
all_values[22]	1898	1			T12	1		T15	15		T16	3
all_values[23]	1830	1			T12	4		T15	12		T16	6
all_values[24]	1838	1			T12	1		T15	13		T16	5
all_values[25]	1845	1			T15	13		T16	4		T18	22
all_values[26]	1865	1			T12	2		T15	13		T16	1
all_values[27]	1886	1			T12	2		T15	7		T16	3
all_values[28]	1870	1			T12	5		T15	7		T16	5
all_values[29]	1870	1			T12	4		T15	7		T16	6
all_values[30]	1833	1			T12	2		T15	10		T16	5
all_values[31]	1893	1			T12	4		T15	13		T16	4
all_values[32]	1775	1			T12	5		T15	15		T16	6
all_values[33]	1815	1			T12	1		T15	6		T16	2
all_values[34]	1904	1			T12	2		T15	12		T18	26
all_values[35]	1867	1			T12	3		T15	12		T16	7
all_values[36]	1881	1			T12	3		T15	13		T16	5
all_values[37]	1810	1			T12	1		T15	13		T16	1
all_values[38]	1910	1			T12	2		T15	11		T16	5
all_values[39]	1881	1			T12	2		T15	10		T16	3
all_values[40]	1956	1			T15	13		T16	5		T18	22
all_values[41]	1913	1			T12	4		T15	7		T16	6
all_values[42]	1883	1			T12	2		T15	15		T16	2
all_values[43]	1833	1			T12	1		T15	14		T16	8
all_values[44]	1916	1			T12	4		T15	25		T16	2
all_values[45]	1871	1			T12	3		T15	11		T16	2
all_values[46]	1880	1			T12	3		T15	6		T16	5
all_values[47]	1814	1			T12	7		T15	10		T16	2
all_values[48]	1905	1			T12	1		T15	16		T16	5
all_values[49]	1850	1			T12	2		T15	9		T16	3
all_values[50]	1923	1			T12	4		T15	13		T16	5
all_values[51]	1821	1			T12	1		T15	5		T16	6
all_values[52]	1818	1			T12	2		T15	12		T16	4
all_values[53]	1843	1			T12	1		T15	10		T16	5
all_values[54]	1893	1			T12	1		T15	10		T16	2
all_values[55]	1867	1			T12	1		T15	7		T16	5
all_values[56]	1868	1			T12	3		T15	9		T16	10
all_values[57]	1886	1			T12	1		T15	6		T16	3
all_values[58]	1878	1			T12	3		T15	15		T16	5
all_values[59]	1834	1			T12	1		T15	12		T16	9
all_values[60]	1863	1			T12	3		T15	9		T16	4
all_values[61]	1849	1			T12	6		T15	9		T16	5
all_values[62]	1881	1			T12	1		T15	10		T16	4
all_values[63]	1807	1			T12	3		T15	7		T16	7