Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1831	1			T1	5		T3	27		T11	2
all_values[1]	1865	1			T1	6		T3	21		T11	4
all_values[2]	1803	1			T1	7		T3	15		T11	1
all_values[3]	1812	1			T1	11		T3	13		T14	32
all_values[4]	1766	1			T1	10		T3	10		T11	1
all_values[5]	1854	1			T1	6		T3	24		T11	3
all_values[6]	1803	1			T1	11		T3	23		T11	2
all_values[7]	1833	1			T1	7		T3	27		T14	26
all_values[8]	1833	1			T1	13		T3	12		T11	3
all_values[9]	1839	1			T1	7		T3	15		T14	31
all_values[10]	1831	1			T1	12		T3	14		T11	1
all_values[11]	1856	1			T1	4		T3	18		T11	3
all_values[12]	1870	1			T1	6		T3	20		T11	2
all_values[13]	1834	1			T1	4		T3	27		T11	6
all_values[14]	1860	1			T1	6		T3	20		T11	1
all_values[15]	1881	1			T1	12		T3	16		T11	2
all_values[16]	1882	1			T1	8		T3	26		T11	3
all_values[17]	1819	1			T1	4		T3	20		T11	1
all_values[18]	1856	1			T1	4		T3	20		T11	2
all_values[19]	1799	1			T1	4		T3	24		T11	1
all_values[20]	1781	1			T1	10		T3	18		T11	3
all_values[21]	1915	1			T1	9		T3	19		T14	30
all_values[22]	1839	1			T1	9		T3	25		T11	2
all_values[23]	1779	1			T1	9		T3	12		T11	1
all_values[24]	1867	1			T1	4		T3	22		T11	3
all_values[25]	1775	1			T1	3		T3	16		T11	1
all_values[26]	1937	1			T1	12		T3	20		T11	3
all_values[27]	1903	1			T1	7		T3	21		T11	5
all_values[28]	1767	1			T1	9		T3	21		T11	2
all_values[29]	1891	1			T1	9		T3	14		T11	3
all_values[30]	1876	1			T1	11		T3	11		T14	35
all_values[31]	1923	1			T1	8		T3	21		T11	3
all_values[32]	1839	1			T1	6		T3	14		T11	4
all_values[33]	1850	1			T1	2		T3	13		T11	5
all_values[34]	1847	1			T1	7		T3	24		T14	31
all_values[35]	1872	1			T1	5		T3	20		T11	2
all_values[36]	1816	1			T1	11		T3	12		T11	2
all_values[37]	1863	1			T1	5		T3	20		T14	27
all_values[38]	1878	1			T1	6		T3	15		T11	2
all_values[39]	1846	1			T1	7		T3	20		T11	3
all_values[40]	1854	1			T1	3		T3	17		T11	1
all_values[41]	1857	1			T1	11		T3	21		T11	4
all_values[42]	1823	1			T1	7		T3	21		T11	3
all_values[43]	1786	1			T1	6		T3	14		T11	5
all_values[44]	1856	1			T1	7		T3	20		T11	4
all_values[45]	1899	1			T1	8		T3	11		T11	4
all_values[46]	1858	1			T1	10		T3	20		T11	1
all_values[47]	1817	1			T1	2		T3	14		T11	3
all_values[48]	1855	1			T1	7		T3	14		T11	1
all_values[49]	1848	1			T1	11		T3	28		T11	1
all_values[50]	1868	1			T1	11		T3	20		T11	3
all_values[51]	1802	1			T1	10		T3	16		T11	1
all_values[52]	1799	1			T1	7		T3	20		T11	3
all_values[53]	1810	1			T1	7		T3	25		T11	3
all_values[54]	1802	1			T1	10		T3	23		T11	1
all_values[55]	1791	1			T1	4		T3	15		T11	2
all_values[56]	1830	1			T1	10		T3	16		T11	4
all_values[57]	1828	1			T1	11		T3	19		T11	1
all_values[58]	1885	1			T1	12		T3	19		T11	1
all_values[59]	1814	1			T1	6		T3	21		T11	4
all_values[60]	1753	1			T1	6		T3	16		T11	2
all_values[61]	1802	1			T1	3		T3	17		T11	5
all_values[62]	1788	1			T1	10		T3	16		T11	3
all_values[63]	1771	1			T1	7		T3	17		T11	2