Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1785	1			T14	43		T15	3		T17	4
all_values[1]	1838	1			T14	42		T15	5		T17	7
all_values[2]	1842	1			T14	39		T15	6		T17	1
all_values[3]	1787	1			T14	34		T15	2		T17	7
all_values[4]	1789	1			T14	34		T15	6		T17	8
all_values[5]	1764	1			T3	1		T14	37		T15	2
all_values[6]	1772	1			T14	33		T15	2		T17	4
all_values[7]	1751	1			T14	34		T15	3		T17	6
all_values[8]	1765	1			T3	1		T14	33		T15	4
all_values[9]	1777	1			T14	42		T15	1		T17	9
all_values[10]	1761	1			T14	44		T15	3		T17	4
all_values[11]	1770	1			T14	47		T15	6		T17	7
all_values[12]	1886	1			T14	36		T15	3		T17	6
all_values[13]	1769	1			T14	41		T15	1		T17	2
all_values[14]	1796	1			T14	40		T15	3		T17	12
all_values[15]	1798	1			T3	1		T14	32		T15	2
all_values[16]	1834	1			T14	42		T15	5		T17	8
all_values[17]	1846	1			T14	40		T15	6		T17	6
all_values[18]	1801	1			T3	1		T14	44		T15	3
all_values[19]	1819	1			T14	41		T15	3		T17	5
all_values[20]	1733	1			T14	34		T15	3		T17	6
all_values[21]	1836	1			T14	48		T15	4		T17	5
all_values[22]	1782	1			T14	36		T15	4		T17	6
all_values[23]	1832	1			T3	1		T14	27		T15	3
all_values[24]	1768	1			T14	28		T15	2		T17	7
all_values[25]	1756	1			T3	1		T14	38		T15	1
all_values[26]	1806	1			T14	22		T15	2		T17	7
all_values[27]	1708	1			T14	27		T15	2		T17	4
all_values[28]	1770	1			T14	28		T15	5		T17	6
all_values[29]	1807	1			T14	33		T15	3		T17	7
all_values[30]	1771	1			T14	35		T15	2		T17	3
all_values[31]	1897	1			T3	1		T14	40		T15	2
all_values[32]	1791	1			T14	39		T17	1		T18	20
all_values[33]	1785	1			T14	38		T15	4		T17	5
all_values[34]	1838	1			T14	42		T15	4		T17	4
all_values[35]	1773	1			T14	40		T15	1		T17	6
all_values[36]	1834	1			T14	44		T15	4		T17	5
all_values[37]	1777	1			T14	31		T15	3		T17	2
all_values[38]	1671	1			T14	28		T15	3		T17	7
all_values[39]	1803	1			T14	44		T15	3		T17	6
all_values[40]	1824	1			T14	39		T15	7		T17	4
all_values[41]	1733	1			T14	31		T15	1		T17	2
all_values[42]	1696	1			T3	2		T14	41		T15	3
all_values[43]	1789	1			T14	36		T15	4		T17	7
all_values[44]	1836	1			T14	26		T15	1		T17	5
all_values[45]	1800	1			T14	37		T15	2		T17	2
all_values[46]	1769	1			T14	42		T15	1		T17	8
all_values[47]	1772	1			T14	37		T15	4		T17	8
all_values[48]	1712	1			T14	37		T15	1		T17	3
all_values[49]	1769	1			T14	44		T15	5		T17	3
all_values[50]	1805	1			T14	44		T15	2		T17	7
all_values[51]	1817	1			T14	31		T15	2		T17	6
all_values[52]	1822	1			T14	31		T15	2		T17	3
all_values[53]	1791	1			T14	37		T15	2		T17	7
all_values[54]	1735	1			T14	28		T15	4		T17	4
all_values[55]	1813	1			T14	35		T15	6		T17	4
all_values[56]	1794	1			T14	43		T15	4		T17	1
all_values[57]	1832	1			T14	40		T15	3		T17	8
all_values[58]	1728	1			T14	34		T15	2		T17	4
all_values[59]	1780	1			T3	1		T14	39		T15	3
all_values[60]	1705	1			T14	41		T15	6		T17	5
all_values[61]	1770	1			T3	1		T14	34		T15	4
all_values[62]	1725	1			T14	34		T15	3		T17	1
all_values[63]	1802	1			T14	35		T15	2		T17	3