Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 513 1 T7 1 T47 1 T21 3
all_values[1] 525 1 T21 1 T299 1 T40 1
all_values[2] 491 1 T7 1 T47 1 T21 2
all_values[3] 538 1 T47 2 T252 2 T77 1
all_values[4] 490 1 T73 1 T47 2 T5 1
all_values[5] 547 1 T47 5 T299 1 T39 1
all_values[6] 522 1 T47 1 T299 1 T39 1
all_values[7] 510 1 T47 1 T299 3 T241 1
all_values[8] 500 1 T21 1 T241 1 T105 1
all_values[9] 528 1 T48 1 T47 1 T21 1
all_values[10] 490 1 T39 1 T252 1 T32 1
all_values[11] 554 1 T299 1 T40 2 T175 1
all_values[12] 511 1 T21 1 T299 1 T252 1
all_values[13] 472 1 T21 1 T299 2 T252 1
all_values[14] 474 1 T39 1 T82 2 T282 1
all_values[15] 479 1 T21 2 T299 1 T241 1
all_values[16] 475 1 T47 2 T21 1 T40 1
all_values[17] 549 1 T47 1 T21 1 T241 1
all_values[18] 491 1 T47 3 T21 2 T299 1
all_values[19] 511 1 T299 1 T40 1 T77 1
all_values[20] 513 1 T47 2 T299 1 T252 3
all_values[21] 516 1 T21 1 T241 1 T175 1
all_values[22] 532 1 T47 2 T299 1 T40 2
all_values[23] 508 1 T21 1 T299 1 T40 1

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