Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1945	1			T9	2		T15	5		T50	2
all_values[1]	1891	1			T9	2		T15	4		T75	1
all_values[2]	1877	1			T9	2		T15	3		T20	1
all_values[3]	1982	1			T9	2		T15	5		T50	2
all_values[4]	1858	1			T9	2		T15	4		T50	1
all_values[5]	1935	1			T9	2		T15	4		T50	1
all_values[6]	1894	1			T9	1		T15	2		T50	2
all_values[7]	1827	1			T9	2		T15	1		T50	2
all_values[8]	1859	1			T15	3		T20	3		T47	1
all_values[9]	1919	1			T9	3		T15	3		T50	1
all_values[10]	1885	1			T9	4		T15	3		T47	3
all_values[11]	1866	1			T15	5		T50	3		T20	1
all_values[12]	1872	1			T9	2		T15	5		T50	1
all_values[13]	1924	1			T9	3		T15	1		T20	1
all_values[14]	1855	1			T9	2		T15	2		T50	2
all_values[15]	1955	1			T15	3		T50	1		T75	1
all_values[16]	1905	1			T15	2		T50	4		T20	1
all_values[17]	1915	1			T9	1		T15	3		T50	1
all_values[18]	1899	1			T9	4		T15	2		T20	1
all_values[19]	1911	1			T9	2		T50	1		T47	2
all_values[20]	1921	1			T20	1		T47	3		T38	5
all_values[21]	1902	1			T15	2		T20	1		T47	3
all_values[22]	1944	1			T9	1		T15	3		T50	2
all_values[23]	1863	1			T9	3		T15	5		T50	1
all_values[24]	1873	1			T9	2		T15	2		T50	1
all_values[25]	1854	1			T9	1		T15	1		T47	2
all_values[26]	1932	1			T15	1		T50	2		T47	1
all_values[27]	1898	1			T15	4		T50	2		T20	1
all_values[28]	1871	1			T9	1		T15	1		T47	3
all_values[29]	1891	1			T9	2		T15	1		T50	1
all_values[30]	1909	1			T9	1		T15	1		T47	1
all_values[31]	1943	1			T15	1		T50	1		T20	1
all_values[32]	1844	1			T9	1		T15	2		T20	3
all_values[33]	1885	1			T9	2		T15	1		T50	1
all_values[34]	1897	1			T15	2		T20	1		T47	1
all_values[35]	1888	1			T15	2		T50	1		T20	1
all_values[36]	1951	1			T9	2		T15	1		T47	2
all_values[37]	1963	1			T9	3		T15	1		T47	3
all_values[38]	1818	1			T9	2		T15	4		T20	2
all_values[39]	1935	1			T9	5		T15	5		T50	1
all_values[40]	1895	1			T9	1		T15	2		T20	1
all_values[41]	1923	1			T9	2		T15	2		T50	1
all_values[42]	1802	1			T9	3		T15	1		T20	1
all_values[43]	1854	1			T9	5		T15	3		T20	4
all_values[44]	1873	1			T9	2		T15	1		T47	4
all_values[45]	1910	1			T9	2		T15	2		T50	1
all_values[46]	1853	1			T9	1		T20	2		T47	6
all_values[47]	1848	1			T9	1		T15	1		T47	5
all_values[48]	1845	1			T9	3		T15	2		T20	1
all_values[49]	1950	1			T9	1		T15	3		T20	1
all_values[50]	1977	1			T9	1		T15	1		T20	2
all_values[51]	1917	1			T15	3		T20	2		T47	2
all_values[52]	1835	1			T9	1		T47	1		T75	1
all_values[53]	1963	1			T9	3		T15	2		T20	1
all_values[54]	1886	1			T9	2		T15	1		T20	2
all_values[55]	1973	1			T9	1		T15	4		T50	1
all_values[56]	1911	1			T9	2		T15	2		T47	1
all_values[57]	1876	1			T9	2		T15	5		T20	2
all_values[58]	1852	1			T9	1		T15	3		T50	3
all_values[59]	1872	1			T9	2		T15	2		T50	1
all_values[60]	1883	1			T9	2		T15	1		T50	1
all_values[61]	1802	1			T9	1		T15	1		T50	1
all_values[62]	1884	1			T15	2		T50	2		T47	1
all_values[63]	1937	1			T9	3		T20	1		T47	2