Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1952	1			T16	1		T24	1		T47	4
all_values[1]	1837	1			T12	5		T16	2		T57	1
all_values[2]	1876	1			T16	1		T47	7		T38	2
all_values[3]	1878	1			T24	3		T47	1		T38	1
all_values[4]	1897	1			T12	1		T57	1		T24	2
all_values[5]	1914	1			T12	1		T16	2		T24	2
all_values[6]	1904	1			T12	1		T16	2		T24	2
all_values[7]	1900	1			T12	2		T16	2		T57	2
all_values[8]	1848	1			T12	1		T16	2		T24	3
all_values[9]	2000	1			T16	1		T57	1		T24	2
all_values[10]	1856	1			T12	1		T16	1		T24	5
all_values[11]	1837	1			T12	2		T24	3		T47	7
all_values[12]	1911	1			T12	2		T16	2		T24	1
all_values[13]	1895	1			T12	1		T16	1		T57	1
all_values[14]	1859	1			T16	1		T57	1		T24	5
all_values[15]	1900	1			T12	2		T16	2		T47	7
all_values[16]	1968	1			T12	1		T24	5		T47	3
all_values[17]	1908	1			T12	3		T57	1		T24	3
all_values[18]	1885	1			T12	5		T16	1		T57	1
all_values[19]	1960	1			T12	1		T16	2		T57	1
all_values[20]	1840	1			T12	1		T16	1		T57	1
all_values[21]	1844	1			T24	1		T47	3		T84	3
all_values[22]	1861	1			T12	1		T24	3		T84	4
all_values[23]	1925	1			T12	1		T57	3		T24	1
all_values[24]	1868	1			T12	1		T24	2		T47	6
all_values[25]	1894	1			T12	2		T57	4		T24	2
all_values[26]	1868	1			T12	1		T57	2		T24	4
all_values[27]	1872	1			T12	2		T57	1		T24	2
all_values[28]	1916	1			T12	3		T24	2		T47	4
all_values[29]	1871	1			T57	1		T24	2		T47	2
all_values[30]	1907	1			T12	1		T16	2		T24	2
all_values[31]	1901	1			T12	2		T57	2		T24	1
all_values[32]	1895	1			T12	1		T16	2		T47	3
all_values[33]	1966	1			T57	1		T24	1		T47	8
all_values[34]	1857	1			T12	1		T16	2		T57	1
all_values[35]	1894	1			T12	2		T16	2		T57	2
all_values[36]	1854	1			T12	3		T16	1		T57	1
all_values[37]	1880	1			T12	1		T57	1		T24	3
all_values[38]	1818	1			T12	1		T57	2		T24	3
all_values[39]	1954	1			T24	2		T47	5		T38	4
all_values[40]	1937	1			T16	1		T24	3		T84	5
all_values[41]	1931	1			T16	1		T57	2		T24	4
all_values[42]	1958	1			T12	2		T16	1		T57	2
all_values[43]	1848	1			T12	1		T57	1		T24	3
all_values[44]	1893	1			T47	4		T38	1		T84	2
all_values[45]	1827	1			T12	1		T24	3		T47	4
all_values[46]	1904	1			T12	3		T16	2		T57	3
all_values[47]	1895	1			T16	1		T57	2		T24	1
all_values[48]	1925	1			T12	1		T24	1		T47	4
all_values[49]	1931	1			T24	1		T47	6		T84	7
all_values[50]	1940	1			T12	3		T16	2		T57	1
all_values[51]	1941	1			T12	1		T16	2		T57	1
all_values[52]	1864	1			T57	1		T24	2		T47	5
all_values[53]	1882	1			T12	6		T24	2		T47	3
all_values[54]	1982	1			T16	1		T57	2		T24	1
all_values[55]	1897	1			T12	1		T57	2		T24	5
all_values[56]	1882	1			T16	1		T57	4		T24	2
all_values[57]	1978	1			T12	1		T16	1		T57	1
all_values[58]	1870	1			T24	1		T47	1		T84	10
all_values[59]	1822	1			T16	2		T24	3		T47	4
all_values[60]	1936	1			T16	1		T57	3		T24	2
all_values[61]	1840	1			T12	2		T16	1		T24	2
all_values[62]	1896	1			T12	1		T16	1		T24	2
all_values[63]	1861	1			T16	2		T24	2		T47	6