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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.03 99.26 88.97 98.80 95.88 99.26 100.00


Total test records in report: 900
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T768 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.2992459049 Aug 23 03:15:25 AM UTC 24 Aug 23 03:16:06 AM UTC 24 9968380460 ps
T769 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.3945206988 Aug 23 03:15:42 AM UTC 24 Aug 23 03:16:07 AM UTC 24 1957483655 ps
T770 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.3658800022 Aug 23 03:16:01 AM UTC 24 Aug 23 03:16:11 AM UTC 24 113832804 ps
T771 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.4091301188 Aug 23 03:15:52 AM UTC 24 Aug 23 03:16:11 AM UTC 24 136793555 ps
T772 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.4221637739 Aug 23 03:14:52 AM UTC 24 Aug 23 03:16:18 AM UTC 24 29441633925 ps
T773 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1715003763 Aug 23 03:15:58 AM UTC 24 Aug 23 03:16:19 AM UTC 24 3495190514 ps
T774 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.72185210 Aug 23 03:13:01 AM UTC 24 Aug 23 03:16:19 AM UTC 24 927169302 ps
T775 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random.2879944498 Aug 23 03:16:00 AM UTC 24 Aug 23 03:16:22 AM UTC 24 1087132158 ps
T776 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.992669208 Aug 23 03:16:12 AM UTC 24 Aug 23 03:16:23 AM UTC 24 225793639 ps
T777 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.2880675713 Aug 23 03:15:52 AM UTC 24 Aug 23 03:16:25 AM UTC 24 1575616754 ps
T778 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.819827319 Aug 23 03:16:08 AM UTC 24 Aug 23 03:16:29 AM UTC 24 138494679 ps
T779 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.3407109947 Aug 23 03:15:56 AM UTC 24 Aug 23 03:16:31 AM UTC 24 7405885088 ps
T780 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.950521181 Aug 23 03:16:21 AM UTC 24 Aug 23 03:16:32 AM UTC 24 629746258 ps
T781 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.1776478537 Aug 23 03:16:32 AM UTC 24 Aug 23 03:16:36 AM UTC 24 165282488 ps
T782 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.3682777927 Aug 23 03:16:20 AM UTC 24 Aug 23 03:16:36 AM UTC 24 864761543 ps
T783 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3653063855 Aug 23 03:16:33 AM UTC 24 Aug 23 03:16:36 AM UTC 24 57735679 ps
T784 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1736257018 Aug 23 03:14:52 AM UTC 24 Aug 23 03:16:37 AM UTC 24 16429119581 ps
T785 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.3582946335 Aug 23 03:16:20 AM UTC 24 Aug 23 03:16:40 AM UTC 24 322564846 ps
T786 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.1318020819 Aug 23 03:12:19 AM UTC 24 Aug 23 03:16:41 AM UTC 24 1471308531 ps
T787 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.172549258 Aug 23 03:16:38 AM UTC 24 Aug 23 03:16:45 AM UTC 24 38472870 ps
T788 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.757991508 Aug 23 03:16:38 AM UTC 24 Aug 23 03:16:55 AM UTC 24 204274620 ps
T789 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.427550983 Aug 23 03:15:09 AM UTC 24 Aug 23 03:16:56 AM UTC 24 4327036332 ps
T790 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.128408365 Aug 23 03:12:58 AM UTC 24 Aug 23 03:17:06 AM UTC 24 1191505699 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.3024113854 Aug 23 03:16:23 AM UTC 24 Aug 23 03:17:07 AM UTC 24 4272132762 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3037433878 Aug 23 03:09:47 AM UTC 24 Aug 23 03:17:09 AM UTC 24 3172315112 ps
T791 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.4077377844 Aug 23 03:16:38 AM UTC 24 Aug 23 03:17:11 AM UTC 24 7819337684 ps
T792 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.2288402994 Aug 23 03:14:26 AM UTC 24 Aug 23 03:17:11 AM UTC 24 7993469555 ps
T793 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1613945171 Aug 23 03:16:36 AM UTC 24 Aug 23 03:17:13 AM UTC 24 7059434023 ps
T794 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.2392516068 Aug 23 03:16:57 AM UTC 24 Aug 23 03:17:13 AM UTC 24 1432932104 ps
T795 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.2044560839 Aug 23 03:17:08 AM UTC 24 Aug 23 03:17:15 AM UTC 24 62469179 ps
T796 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.3527977322 Aug 23 03:16:06 AM UTC 24 Aug 23 03:17:17 AM UTC 24 12364629663 ps
T797 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1547385131 Aug 23 03:16:25 AM UTC 24 Aug 23 03:17:17 AM UTC 24 3726471630 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.4066993230 Aug 23 03:17:16 AM UTC 24 Aug 23 03:17:20 AM UTC 24 150890460 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.3329372026 Aug 23 03:17:09 AM UTC 24 Aug 23 03:17:21 AM UTC 24 1657873357 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.379726821 Aug 23 03:16:46 AM UTC 24 Aug 23 03:17:21 AM UTC 24 1139283180 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2188317966 Aug 23 03:17:18 AM UTC 24 Aug 23 03:17:21 AM UTC 24 31075869 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.2444229660 Aug 23 03:17:23 AM UTC 24 Aug 23 03:17:30 AM UTC 24 76967858 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.1126812786 Aug 23 03:17:08 AM UTC 24 Aug 23 03:17:33 AM UTC 24 951067911 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.4234341019 Aug 23 03:15:12 AM UTC 24 Aug 23 03:17:42 AM UTC 24 349497714 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2732379348 Aug 23 03:17:18 AM UTC 24 Aug 23 03:17:45 AM UTC 24 10198289784 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.1461228498 Aug 23 03:17:23 AM UTC 24 Aug 23 03:17:52 AM UTC 24 1143767615 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3731241585 Aug 23 03:16:26 AM UTC 24 Aug 23 03:17:52 AM UTC 24 3251688891 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1143062902 Aug 23 03:17:21 AM UTC 24 Aug 23 03:17:53 AM UTC 24 3873465502 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.609236667 Aug 23 03:17:46 AM UTC 24 Aug 23 03:17:54 AM UTC 24 119130039 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3247502677 Aug 23 03:17:53 AM UTC 24 Aug 23 03:18:01 AM UTC 24 106837447 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.4110323737 Aug 23 03:17:54 AM UTC 24 Aug 23 03:18:03 AM UTC 24 315034750 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.1303873832 Aug 23 03:17:53 AM UTC 24 Aug 23 03:18:07 AM UTC 24 249505489 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.4009269193 Aug 23 03:17:34 AM UTC 24 Aug 23 03:18:09 AM UTC 24 3306117523 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.479863324 Aug 23 03:18:11 AM UTC 24 Aug 23 03:18:14 AM UTC 24 79819681 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.634406456 Aug 23 03:18:10 AM UTC 24 Aug 23 03:18:15 AM UTC 24 321793673 ps
T815 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2358787110 Aug 23 03:17:43 AM UTC 24 Aug 23 03:18:28 AM UTC 24 9046666398 ps
T816 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2847818169 Aug 23 03:18:04 AM UTC 24 Aug 23 03:18:29 AM UTC 24 245685080 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.90625827 Aug 23 03:17:31 AM UTC 24 Aug 23 03:18:29 AM UTC 24 13577700253 ps
T818 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.557100775 Aug 23 03:15:26 AM UTC 24 Aug 23 03:18:32 AM UTC 24 26284576493 ps
T819 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.973461734 Aug 23 03:16:42 AM UTC 24 Aug 23 03:18:33 AM UTC 24 21135756989 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.3843601127 Aug 23 03:18:29 AM UTC 24 Aug 23 03:18:33 AM UTC 24 30290784 ps
T821 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.4282149677 Aug 23 03:18:31 AM UTC 24 Aug 23 03:18:33 AM UTC 24 17346579 ps
T822 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.4062073185 Aug 23 03:18:35 AM UTC 24 Aug 23 03:18:41 AM UTC 24 97574839 ps
T823 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1477591465 Aug 23 03:18:16 AM UTC 24 Aug 23 03:18:43 AM UTC 24 9364303631 ps
T824 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.2858697105 Aug 23 03:18:41 AM UTC 24 Aug 23 03:18:45 AM UTC 24 27072405 ps
T825 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2878586057 Aug 23 03:18:16 AM UTC 24 Aug 23 03:18:49 AM UTC 24 16157584918 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3179617978 Aug 23 03:14:55 AM UTC 24 Aug 23 03:18:50 AM UTC 24 51455578463 ps
T826 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.3264102762 Aug 23 03:18:44 AM UTC 24 Aug 23 03:18:52 AM UTC 24 235317069 ps
T827 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3174425859 Aug 23 03:18:46 AM UTC 24 Aug 23 03:19:01 AM UTC 24 1588536906 ps
T828 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.772969732 Aug 23 03:17:13 AM UTC 24 Aug 23 03:19:02 AM UTC 24 992767948 ps
T829 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.4037972763 Aug 23 03:14:28 AM UTC 24 Aug 23 03:19:03 AM UTC 24 2011580931 ps
T830 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.2197044865 Aug 23 03:19:03 AM UTC 24 Aug 23 03:19:06 AM UTC 24 29747424 ps
T831 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.246018019 Aug 23 03:15:11 AM UTC 24 Aug 23 03:19:08 AM UTC 24 500207973 ps
T832 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1428027738 Aug 23 03:19:05 AM UTC 24 Aug 23 03:19:08 AM UTC 24 33598642 ps
T833 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2582278517 Aug 23 03:08:53 AM UTC 24 Aug 23 03:19:10 AM UTC 24 212157057468 ps
T834 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.1287696035 Aug 23 03:17:15 AM UTC 24 Aug 23 03:19:13 AM UTC 24 1386216373 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.4083212491 Aug 23 03:17:13 AM UTC 24 Aug 23 03:19:16 AM UTC 24 5489836135 ps
T835 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.2396526666 Aug 23 03:19:11 AM UTC 24 Aug 23 03:19:17 AM UTC 24 48657125 ps
T836 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.395289486 Aug 23 03:18:33 AM UTC 24 Aug 23 03:19:20 AM UTC 24 4488041192 ps
T837 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.3034281323 Aug 23 03:19:09 AM UTC 24 Aug 23 03:19:22 AM UTC 24 633063424 ps
T838 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3208175993 Aug 23 03:18:53 AM UTC 24 Aug 23 03:19:29 AM UTC 24 5978401327 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3158700269 Aug 23 03:16:07 AM UTC 24 Aug 23 03:19:29 AM UTC 24 40740481059 ps
T839 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.1307288844 Aug 23 03:19:15 AM UTC 24 Aug 23 03:19:32 AM UTC 24 6308869663 ps
T840 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.4222601764 Aug 23 03:19:18 AM UTC 24 Aug 23 03:19:34 AM UTC 24 3324525868 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.414562575 Aug 23 03:19:09 AM UTC 24 Aug 23 03:19:35 AM UTC 24 4332261215 ps
T841 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1656193452 Aug 23 03:12:45 AM UTC 24 Aug 23 03:19:36 AM UTC 24 56807849145 ps
T842 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.3883378401 Aug 23 03:19:31 AM UTC 24 Aug 23 03:19:36 AM UTC 24 143013800 ps
T843 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.3286662276 Aug 23 03:19:23 AM UTC 24 Aug 23 03:19:40 AM UTC 24 733737829 ps
T844 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.2608641881 Aug 23 03:19:41 AM UTC 24 Aug 23 03:19:45 AM UTC 24 118997558 ps
T845 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.712720555 Aug 23 03:19:07 AM UTC 24 Aug 23 03:19:45 AM UTC 24 17585594858 ps
T846 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.530813749 Aug 23 03:19:33 AM UTC 24 Aug 23 03:19:46 AM UTC 24 526351206 ps
T847 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2142252220 Aug 23 03:19:36 AM UTC 24 Aug 23 03:19:48 AM UTC 24 79809269 ps
T848 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1571969835 Aug 23 03:19:31 AM UTC 24 Aug 23 03:19:48 AM UTC 24 240064767 ps
T849 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2318059125 Aug 23 03:19:46 AM UTC 24 Aug 23 03:19:49 AM UTC 24 50992756 ps
T850 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.810086493 Aug 23 03:19:49 AM UTC 24 Aug 23 03:19:55 AM UTC 24 80012981 ps
T851 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.3777428814 Aug 23 03:19:49 AM UTC 24 Aug 23 03:20:00 AM UTC 24 462042539 ps
T852 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.239242726 Aug 23 03:10:51 AM UTC 24 Aug 23 03:20:01 AM UTC 24 110148972857 ps
T853 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.862017157 Aug 23 03:19:34 AM UTC 24 Aug 23 03:20:07 AM UTC 24 418439189 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2761159266 Aug 23 03:19:46 AM UTC 24 Aug 23 03:20:15 AM UTC 24 6903785773 ps
T854 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.3863627542 Aug 23 03:20:08 AM UTC 24 Aug 23 03:20:20 AM UTC 24 196264723 ps
T855 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2496298898 Aug 23 03:19:48 AM UTC 24 Aug 23 03:20:22 AM UTC 24 25390584083 ps
T856 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2392535204 Aug 23 03:17:14 AM UTC 24 Aug 23 03:20:23 AM UTC 24 16093029523 ps
T857 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3527551485 Aug 23 03:13:10 AM UTC 24 Aug 23 03:20:29 AM UTC 24 135711040555 ps
T858 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.351260577 Aug 23 03:20:23 AM UTC 24 Aug 23 03:20:33 AM UTC 24 97639892 ps
T859 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.3938854841 Aug 23 03:20:21 AM UTC 24 Aug 23 03:20:35 AM UTC 24 1140824138 ps
T860 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.385508514 Aug 23 03:19:37 AM UTC 24 Aug 23 03:20:38 AM UTC 24 433661361 ps
T861 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1415800511 Aug 23 03:15:30 AM UTC 24 Aug 23 03:20:43 AM UTC 24 52873113124 ps
T862 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.1569335788 Aug 23 03:20:39 AM UTC 24 Aug 23 03:20:43 AM UTC 24 179315580 ps
T863 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2331531736 Aug 23 03:20:44 AM UTC 24 Aug 23 03:20:47 AM UTC 24 116347493 ps
T864 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.2139832723 Aug 23 03:20:17 AM UTC 24 Aug 23 03:20:47 AM UTC 24 1122864040 ps
T865 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.213170943 Aug 23 03:17:55 AM UTC 24 Aug 23 03:20:47 AM UTC 24 8018592111 ps
T866 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.2738387228 Aug 23 03:20:00 AM UTC 24 Aug 23 03:20:48 AM UTC 24 4055163027 ps
T867 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.2212782748 Aug 23 03:16:42 AM UTC 24 Aug 23 03:20:48 AM UTC 24 119812958532 ps
T868 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.2571293899 Aug 23 03:17:23 AM UTC 24 Aug 23 03:20:49 AM UTC 24 61842104488 ps
T869 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.783594861 Aug 23 03:18:03 AM UTC 24 Aug 23 03:20:53 AM UTC 24 410718715 ps
T870 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.2609853767 Aug 23 03:18:09 AM UTC 24 Aug 23 03:20:58 AM UTC 24 5492565958 ps
T871 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.2959262230 Aug 23 03:20:49 AM UTC 24 Aug 23 03:20:58 AM UTC 24 291571227 ps
T872 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2323519990 Aug 23 03:20:49 AM UTC 24 Aug 23 03:21:03 AM UTC 24 470126336 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1016065303 Aug 23 03:18:35 AM UTC 24 Aug 23 03:21:04 AM UTC 24 29232668302 ps
T873 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.2091621831 Aug 23 03:21:00 AM UTC 24 Aug 23 03:21:05 AM UTC 24 293048961 ps
T874 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.3301132460 Aug 23 03:21:00 AM UTC 24 Aug 23 03:21:09 AM UTC 24 1766703328 ps
T875 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.2765297875 Aug 23 03:18:50 AM UTC 24 Aug 23 03:21:10 AM UTC 24 13713958634 ps
T876 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3090285119 Aug 23 03:16:30 AM UTC 24 Aug 23 03:21:10 AM UTC 24 2485178737 ps
T877 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3585316325 Aug 23 03:20:44 AM UTC 24 Aug 23 03:21:11 AM UTC 24 6154248181 ps
T878 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.176399696 Aug 23 03:20:49 AM UTC 24 Aug 23 03:21:11 AM UTC 24 4225607968 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.3045832934 Aug 23 03:20:49 AM UTC 24 Aug 23 03:21:12 AM UTC 24 4078989695 ps
T879 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.2907480043 Aug 23 03:21:04 AM UTC 24 Aug 23 03:21:14 AM UTC 24 270449047 ps
T880 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.4287897772 Aug 23 03:18:31 AM UTC 24 Aug 23 03:21:16 AM UTC 24 40756239118 ps
T881 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.99135752 Aug 23 03:21:06 AM UTC 24 Aug 23 03:21:19 AM UTC 24 167393478 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2419515349 Aug 23 03:18:33 AM UTC 24 Aug 23 03:21:31 AM UTC 24 41926544474 ps
T882 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.4163593463 Aug 23 03:21:06 AM UTC 24 Aug 23 03:21:35 AM UTC 24 1152147710 ps
T883 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.578346791 Aug 23 03:20:25 AM UTC 24 Aug 23 03:21:39 AM UTC 24 1007463380 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3389018089 Aug 23 03:14:28 AM UTC 24 Aug 23 03:21:39 AM UTC 24 14876209238 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2151537826 Aug 23 03:15:50 AM UTC 24 Aug 23 03:21:44 AM UTC 24 2658508680 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.2844865990 Aug 23 03:20:51 AM UTC 24 Aug 23 03:21:51 AM UTC 24 1535730152 ps
T884 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2208428192 Aug 23 03:19:37 AM UTC 24 Aug 23 03:21:52 AM UTC 24 5944265814 ps
T885 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3531201636 Aug 23 03:19:17 AM UTC 24 Aug 23 03:22:01 AM UTC 24 25951684972 ps
T886 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.4226354180 Aug 23 03:20:36 AM UTC 24 Aug 23 03:22:06 AM UTC 24 569044527 ps
T887 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2659753230 Aug 23 03:19:02 AM UTC 24 Aug 23 03:22:22 AM UTC 24 624990768 ps
T888 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.1078889098 Aug 23 03:19:51 AM UTC 24 Aug 23 03:22:24 AM UTC 24 43587192965 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1210548184 Aug 23 03:10:12 AM UTC 24 Aug 23 03:22:28 AM UTC 24 341383070393 ps
T889 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.1036190672 Aug 23 03:21:13 AM UTC 24 Aug 23 03:22:34 AM UTC 24 1394530087 ps
T890 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3722211439 Aug 23 03:19:56 AM UTC 24 Aug 23 03:23:06 AM UTC 24 30545992745 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.3633659305 Aug 23 03:18:52 AM UTC 24 Aug 23 03:23:12 AM UTC 24 8687281920 ps
T891 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.587769434 Aug 23 03:20:51 AM UTC 24 Aug 23 03:23:23 AM UTC 24 28775379508 ps
T892 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2517454346 Aug 23 03:20:54 AM UTC 24 Aug 23 03:23:27 AM UTC 24 17559416819 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.2432408177 Aug 23 03:14:18 AM UTC 24 Aug 23 03:23:28 AM UTC 24 181255021974 ps
T893 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.548650846 Aug 23 03:20:34 AM UTC 24 Aug 23 03:23:49 AM UTC 24 9873680657 ps
T894 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.4267187251 Aug 23 03:20:30 AM UTC 24 Aug 23 03:24:03 AM UTC 24 940008449 ps
T895 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3423907246 Aug 23 03:16:56 AM UTC 24 Aug 23 03:24:22 AM UTC 24 193067746971 ps
T896 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.4218111326 Aug 23 03:21:10 AM UTC 24 Aug 23 03:25:19 AM UTC 24 10373250183 ps
T897 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.308527239 Aug 23 03:20:03 AM UTC 24 Aug 23 03:25:20 AM UTC 24 38942199201 ps
T898 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.3018760248 Aug 23 03:21:13 AM UTC 24 Aug 23 03:25:55 AM UTC 24 2423300842 ps
T899 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1511034936 Aug 23 03:19:21 AM UTC 24 Aug 23 03:26:35 AM UTC 24 65205443751 ps
T900 /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.2016624318 Aug 23 03:16:12 AM UTC 24 Aug 23 03:27:16 AM UTC 24 217465021952 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random.2086157390
Short name T8
Test name
Test status
Simulation time 2949331800 ps
CPU time 30.36 seconds
Started Aug 23 02:38:55 AM UTC 24
Finished Aug 23 02:39:27 AM UTC 24
Peak memory 219012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086157390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.2086157390
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/0.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.1185859877
Short name T254
Test name
Test status
Simulation time 77275928747 ps
CPU time 560.83 seconds
Started Aug 23 02:46:16 AM UTC 24
Finished Aug 23 02:55:43 AM UTC 24
Peak memory 222936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185859877 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.1185859877
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/5.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.297929495
Short name T84
Test name
Test status
Simulation time 6480090615 ps
CPU time 179.29 seconds
Started Aug 23 02:41:10 AM UTC 24
Finished Aug 23 02:44:12 AM UTC 24
Peak memory 223104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297929495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.297929495
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/1.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.458519314
Short name T38
Test name
Test status
Simulation time 1522023227 ps
CPU time 49.85 seconds
Started Aug 23 02:43:09 AM UTC 24
Finished Aug 23 02:44:00 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458519314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.458519314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/2.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.1415909754
Short name T262
Test name
Test status
Simulation time 3667503855 ps
CPU time 121.96 seconds
Started Aug 23 02:52:56 AM UTC 24
Finished Aug 23 02:55:00 AM UTC 24
Peak memory 221000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415909754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.1415909754
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/11.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.4248751497
Short name T136
Test name
Test status
Simulation time 404673991383 ps
CPU time 850.7 seconds
Started Aug 23 02:49:15 AM UTC 24
Finished Aug 23 03:03:35 AM UTC 24
Peak memory 222616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248751497 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.4248751497
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/8.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.2781400539
Short name T5
Test name
Test status
Simulation time 1245186932 ps
CPU time 39.47 seconds
Started Aug 23 02:47:12 AM UTC 24
Finished Aug 23 02:47:53 AM UTC 24
Peak memory 219204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781400539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2781400539
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/6.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.76900056
Short name T16
Test name
Test status
Simulation time 287753865 ps
CPU time 30.88 seconds
Started Aug 23 02:39:53 AM UTC 24
Finished Aug 23 02:40:25 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76900056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.76900056
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/0.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.2281550125
Short name T90
Test name
Test status
Simulation time 16906004168 ps
CPU time 193.48 seconds
Started Aug 23 02:45:27 AM UTC 24
Finished Aug 23 02:48:43 AM UTC 24
Peak memory 223044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281550125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2281550125
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/4.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.2214539707
Short name T7
Test name
Test status
Simulation time 4637620109 ps
CPU time 26.65 seconds
Started Aug 23 02:38:54 AM UTC 24
Finished Aug 23 02:39:22 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214539707 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2214539707
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/0.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3264357896
Short name T104
Test name
Test status
Simulation time 17695348555 ps
CPU time 324.74 seconds
Started Aug 23 02:39:56 AM UTC 24
Finished Aug 23 02:45:25 AM UTC 24
Peak memory 223348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264357896 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.3264357896
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/0.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.4099124316
Short name T97
Test name
Test status
Simulation time 18596675001 ps
CPU time 738.43 seconds
Started Aug 23 02:39:37 AM UTC 24
Finished Aug 23 02:52:04 AM UTC 24
Peak memory 224728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099124316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.4099124316
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/0.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.3124307152
Short name T51
Test name
Test status
Simulation time 1418056863 ps
CPU time 290.73 seconds
Started Aug 23 02:47:38 AM UTC 24
Finished Aug 23 02:52:33 AM UTC 24
Peak memory 223240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124307152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.3124307152
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/6.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.2501234617
Short name T1
Test name
Test status
Simulation time 476176679 ps
CPU time 2.8 seconds
Started Aug 23 02:38:54 AM UTC 24
Finished Aug 23 02:38:58 AM UTC 24
Peak memory 217048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501234617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2501234617
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/0.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.1626263667
Short name T31
Test name
Test status
Simulation time 849526944 ps
CPU time 180.5 seconds
Started Aug 23 02:50:38 AM UTC 24
Finished Aug 23 02:53:41 AM UTC 24
Peak memory 223244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626263667 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.1626263667
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/9.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3659471953
Short name T48
Test name
Test status
Simulation time 748473679 ps
CPU time 164.77 seconds
Started Aug 23 02:59:31 AM UTC 24
Finished Aug 23 03:02:19 AM UTC 24
Peak memory 222968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659471953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.3659471953
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/19.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2646195870
Short name T37
Test name
Test status
Simulation time 25812143837 ps
CPU time 273.63 seconds
Started Aug 23 02:39:13 AM UTC 24
Finished Aug 23 02:43:51 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646195870 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.2646195870
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/0.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.2522418767
Short name T40
Test name
Test status
Simulation time 4128701564 ps
CPU time 243.3 seconds
Started Aug 23 03:06:07 AM UTC 24
Finished Aug 23 03:10:14 AM UTC 24
Peak memory 223372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522418767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.2522418767
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/27.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.94054090
Short name T43
Test name
Test status
Simulation time 12010545510 ps
CPU time 218.12 seconds
Started Aug 23 03:11:42 AM UTC 24
Finished Aug 23 03:15:24 AM UTC 24
Peak memory 220072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94054090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.94054090
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/36.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.1160366422
Short name T46
Test name
Test status
Simulation time 116679495 ps
CPU time 15.86 seconds
Started Aug 23 02:47:21 AM UTC 24
Finished Aug 23 02:47:38 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160366422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1160366422
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/6.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.4194086783
Short name T13
Test name
Test status
Simulation time 758147048 ps
CPU time 37.68 seconds
Started Aug 23 02:39:13 AM UTC 24
Finished Aug 23 02:39:52 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194086783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.4194086783
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/0.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.419146932
Short name T14
Test name
Test status
Simulation time 1627664893 ps
CPU time 18.39 seconds
Started Aug 23 02:39:34 AM UTC 24
Finished Aug 23 02:39:55 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419146932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.419146932
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/0.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.958128175
Short name T11
Test name
Test status
Simulation time 376745653 ps
CPU time 5.63 seconds
Started Aug 23 02:39:27 AM UTC 24
Finished Aug 23 02:39:34 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958128175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.958128175
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/0.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.3829611948
Short name T26
Test name
Test status
Simulation time 29841339041 ps
CPU time 57.51 seconds
Started Aug 23 02:38:59 AM UTC 24
Finished Aug 23 02:39:58 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829611948 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3829611948
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/0.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1912423775
Short name T167
Test name
Test status
Simulation time 64059167106 ps
CPU time 229.15 seconds
Started Aug 23 02:38:59 AM UTC 24
Finished Aug 23 02:42:51 AM UTC 24
Peak memory 217032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912423775 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1912423775
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/0.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.1090413726
Short name T3
Test name
Test status
Simulation time 765483095 ps
CPU time 14.62 seconds
Started Aug 23 02:38:57 AM UTC 24
Finished Aug 23 02:39:12 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090413726 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.1090413726
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/0.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.2673624589
Short name T12
Test name
Test status
Simulation time 846152215 ps
CPU time 10.88 seconds
Started Aug 23 02:39:23 AM UTC 24
Finished Aug 23 02:39:35 AM UTC 24
Peak memory 217148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673624589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2673624589
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/0.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.50683589
Short name T9
Test name
Test status
Simulation time 7674001285 ps
CPU time 31.76 seconds
Started Aug 23 02:38:54 AM UTC 24
Finished Aug 23 02:39:27 AM UTC 24
Peak memory 217008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50683589 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.50683589
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/0.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.1628355911
Short name T2
Test name
Test status
Simulation time 67713137 ps
CPU time 3 seconds
Started Aug 23 02:38:54 AM UTC 24
Finished Aug 23 02:38:58 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628355911 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1628355911
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/0.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.3973295179
Short name T15
Test name
Test status
Simulation time 305687450 ps
CPU time 36.67 seconds
Started Aug 23 02:39:34 AM UTC 24
Finished Aug 23 02:40:13 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973295179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3973295179
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/0.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.2890595513
Short name T10
Test name
Test status
Simulation time 179578416 ps
CPU time 3.63 seconds
Started Aug 23 02:39:28 AM UTC 24
Finished Aug 23 02:39:34 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890595513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2890595513
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/0.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.3685449361
Short name T19
Test name
Test status
Simulation time 2755538202 ps
CPU time 32.29 seconds
Started Aug 23 02:40:42 AM UTC 24
Finished Aug 23 02:41:16 AM UTC 24
Peak memory 218944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685449361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.3685449361
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/1.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.918323972
Short name T229
Test name
Test status
Simulation time 78805902113 ps
CPU time 283.48 seconds
Started Aug 23 02:40:49 AM UTC 24
Finished Aug 23 02:45:37 AM UTC 24
Peak memory 218952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918323972 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.918323972
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/1.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.440617661
Short name T28
Test name
Test status
Simulation time 758144572 ps
CPU time 22.29 seconds
Started Aug 23 02:41:09 AM UTC 24
Finished Aug 23 02:41:32 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440617661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.440617661
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/1.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.2254613711
Short name T20
Test name
Test status
Simulation time 275142412 ps
CPU time 24.46 seconds
Started Aug 23 02:40:51 AM UTC 24
Finished Aug 23 02:41:16 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254613711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2254613711
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/1.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random.2279039726
Short name T18
Test name
Test status
Simulation time 1809753849 ps
CPU time 23.96 seconds
Started Aug 23 02:40:25 AM UTC 24
Finished Aug 23 02:40:51 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279039726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.2279039726
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/1.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.1424731102
Short name T226
Test name
Test status
Simulation time 44888938234 ps
CPU time 115.35 seconds
Started Aug 23 02:40:36 AM UTC 24
Finished Aug 23 02:42:33 AM UTC 24
Peak memory 216892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424731102 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.1424731102
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/1.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.788337756
Short name T22
Test name
Test status
Simulation time 14958123724 ps
CPU time 90.56 seconds
Started Aug 23 02:40:38 AM UTC 24
Finished Aug 23 02:42:11 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788337756 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.788337756
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/1.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.3017547387
Short name T17
Test name
Test status
Simulation time 402994159 ps
CPU time 22.83 seconds
Started Aug 23 02:40:26 AM UTC 24
Finished Aug 23 02:40:50 AM UTC 24
Peak memory 217152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017547387 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.3017547387
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/1.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.2624951632
Short name T57
Test name
Test status
Simulation time 1591756226 ps
CPU time 17 seconds
Started Aug 23 02:40:51 AM UTC 24
Finished Aug 23 02:41:09 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624951632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2624951632
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/1.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.3789248861
Short name T54
Test name
Test status
Simulation time 23122797 ps
CPU time 2.87 seconds
Started Aug 23 02:39:59 AM UTC 24
Finished Aug 23 02:40:03 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789248861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3789248861
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/1.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3559675752
Short name T56
Test name
Test status
Simulation time 4883157238 ps
CPU time 30.69 seconds
Started Aug 23 02:40:09 AM UTC 24
Finished Aug 23 02:40:41 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559675752 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3559675752
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/1.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.2455695279
Short name T79
Test name
Test status
Simulation time 3925272797 ps
CPU time 34.72 seconds
Started Aug 23 02:40:14 AM UTC 24
Finished Aug 23 02:40:50 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455695279 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2455695279
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/1.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.4093572896
Short name T55
Test name
Test status
Simulation time 51958749 ps
CPU time 3.16 seconds
Started Aug 23 02:40:04 AM UTC 24
Finished Aug 23 02:40:08 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093572896 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.4093572896
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/1.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.3766028209
Short name T21
Test name
Test status
Simulation time 194588997 ps
CPU time 6.2 seconds
Started Aug 23 02:41:17 AM UTC 24
Finished Aug 23 02:41:25 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766028209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.3766028209
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/1.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.1942368689
Short name T50
Test name
Test status
Simulation time 8624855684 ps
CPU time 188.57 seconds
Started Aug 23 02:41:17 AM UTC 24
Finished Aug 23 02:44:29 AM UTC 24
Peak memory 222976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942368689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.1942368689
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/1.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.2261550882
Short name T259
Test name
Test status
Simulation time 3574033090 ps
CPU time 387.69 seconds
Started Aug 23 02:41:26 AM UTC 24
Finished Aug 23 02:47:59 AM UTC 24
Peak memory 233656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261550882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.2261550882
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/1.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.2602440121
Short name T27
Test name
Test status
Simulation time 576645369 ps
CPU time 14.91 seconds
Started Aug 23 02:40:52 AM UTC 24
Finished Aug 23 02:41:08 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602440121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2602440121
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/1.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.53436128
Short name T96
Test name
Test status
Simulation time 120304814 ps
CPU time 8.17 seconds
Started Aug 23 02:51:08 AM UTC 24
Finished Aug 23 02:51:17 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53436128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.53436128
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/10.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.293667723
Short name T413
Test name
Test status
Simulation time 68765277832 ps
CPU time 538.08 seconds
Started Aug 23 02:51:18 AM UTC 24
Finished Aug 23 03:00:23 AM UTC 24
Peak memory 220564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293667723 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.293667723
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/10.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3785048770
Short name T299
Test name
Test status
Simulation time 498723929 ps
CPU time 16.41 seconds
Started Aug 23 02:51:31 AM UTC 24
Finished Aug 23 02:51:49 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785048770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3785048770
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/10.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.4251060612
Short name T300
Test name
Test status
Simulation time 1396874460 ps
CPU time 30.05 seconds
Started Aug 23 02:51:27 AM UTC 24
Finished Aug 23 02:51:59 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251060612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.4251060612
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/10.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random.2515731263
Short name T170
Test name
Test status
Simulation time 365685355 ps
CPU time 16.43 seconds
Started Aug 23 02:50:49 AM UTC 24
Finished Aug 23 02:51:07 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515731263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.2515731263
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/10.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.3127013478
Short name T310
Test name
Test status
Simulation time 87533687160 ps
CPU time 141.35 seconds
Started Aug 23 02:51:01 AM UTC 24
Finished Aug 23 02:53:24 AM UTC 24
Peak memory 219264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127013478 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3127013478
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/10.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.1354189785
Short name T322
Test name
Test status
Simulation time 31220884558 ps
CPU time 163.2 seconds
Started Aug 23 02:51:07 AM UTC 24
Finished Aug 23 02:53:53 AM UTC 24
Peak memory 218888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354189785 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1354189785
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/10.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.1315884424
Short name T295
Test name
Test status
Simulation time 120812606 ps
CPU time 5.13 seconds
Started Aug 23 02:51:00 AM UTC 24
Finished Aug 23 02:51:06 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315884424 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.1315884424
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/10.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.1566191003
Short name T297
Test name
Test status
Simulation time 600068016 ps
CPU time 17.73 seconds
Started Aug 23 02:51:21 AM UTC 24
Finished Aug 23 02:51:40 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566191003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1566191003
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/10.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.1521154265
Short name T223
Test name
Test status
Simulation time 170877892 ps
CPU time 4.3 seconds
Started Aug 23 02:50:38 AM UTC 24
Finished Aug 23 02:50:43 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521154265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1521154265
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/10.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.2325733388
Short name T296
Test name
Test status
Simulation time 4675456300 ps
CPU time 43.3 seconds
Started Aug 23 02:50:45 AM UTC 24
Finished Aug 23 02:51:30 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325733388 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2325733388
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/10.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.1335844044
Short name T171
Test name
Test status
Simulation time 34635452134 ps
CPU time 56.34 seconds
Started Aug 23 02:50:49 AM UTC 24
Finished Aug 23 02:51:47 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335844044 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.1335844044
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/10.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3645212941
Short name T293
Test name
Test status
Simulation time 46402104 ps
CPU time 3.22 seconds
Started Aug 23 02:50:44 AM UTC 24
Finished Aug 23 02:50:48 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645212941 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3645212941
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/10.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.249260485
Short name T109
Test name
Test status
Simulation time 1065228283 ps
CPU time 26.56 seconds
Started Aug 23 02:51:41 AM UTC 24
Finished Aug 23 02:52:09 AM UTC 24
Peak memory 218808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249260485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.249260485
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/10.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.729589670
Short name T255
Test name
Test status
Simulation time 9005502516 ps
CPU time 207.77 seconds
Started Aug 23 02:51:48 AM UTC 24
Finished Aug 23 02:55:20 AM UTC 24
Peak memory 220996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729589670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.729589670
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/10.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.2237707679
Short name T265
Test name
Test status
Simulation time 227843632 ps
CPU time 73.17 seconds
Started Aug 23 02:51:47 AM UTC 24
Finished Aug 23 02:53:02 AM UTC 24
Peak memory 218816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237707679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.2237707679
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/10.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2549938649
Short name T264
Test name
Test status
Simulation time 206102980 ps
CPU time 61.17 seconds
Started Aug 23 02:51:49 AM UTC 24
Finished Aug 23 02:52:52 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549938649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.2549938649
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/10.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.3519658318
Short name T298
Test name
Test status
Simulation time 109012494 ps
CPU time 14.93 seconds
Started Aug 23 02:51:30 AM UTC 24
Finished Aug 23 02:51:46 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519658318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3519658318
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/10.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.1384253301
Short name T175
Test name
Test status
Simulation time 311294458 ps
CPU time 30.18 seconds
Started Aug 23 02:52:27 AM UTC 24
Finished Aug 23 02:52:59 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384253301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.1384253301
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/11.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1182759928
Short name T231
Test name
Test status
Simulation time 9436574760 ps
CPU time 57.85 seconds
Started Aug 23 02:52:29 AM UTC 24
Finished Aug 23 02:53:29 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182759928 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.1182759928
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/11.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2000507677
Short name T304
Test name
Test status
Simulation time 236836693 ps
CPU time 15.25 seconds
Started Aug 23 02:52:42 AM UTC 24
Finished Aug 23 02:52:59 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000507677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2000507677
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/11.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.2776511773
Short name T303
Test name
Test status
Simulation time 262900789 ps
CPU time 20.03 seconds
Started Aug 23 02:52:34 AM UTC 24
Finished Aug 23 02:52:55 AM UTC 24
Peak memory 217152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776511773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2776511773
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/11.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random.2731619244
Short name T135
Test name
Test status
Simulation time 350707477 ps
CPU time 23.62 seconds
Started Aug 23 02:52:08 AM UTC 24
Finished Aug 23 02:52:32 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731619244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.2731619244
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/11.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.964551454
Short name T221
Test name
Test status
Simulation time 25459231965 ps
CPU time 107.97 seconds
Started Aug 23 02:52:10 AM UTC 24
Finished Aug 23 02:54:00 AM UTC 24
Peak memory 217224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964551454 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.964551454
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/11.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.2269229174
Short name T133
Test name
Test status
Simulation time 1880227924 ps
CPU time 11.38 seconds
Started Aug 23 02:52:14 AM UTC 24
Finished Aug 23 02:52:26 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269229174 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2269229174
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/11.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.3377825686
Short name T134
Test name
Test status
Simulation time 106502239 ps
CPU time 18.18 seconds
Started Aug 23 02:52:09 AM UTC 24
Finished Aug 23 02:52:28 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377825686 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.3377825686
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/11.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.3791996217
Short name T305
Test name
Test status
Simulation time 1151914962 ps
CPU time 27.31 seconds
Started Aug 23 02:52:34 AM UTC 24
Finished Aug 23 02:53:03 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791996217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3791996217
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/11.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.1040616065
Short name T301
Test name
Test status
Simulation time 42823250 ps
CPU time 2.73 seconds
Started Aug 23 02:52:00 AM UTC 24
Finished Aug 23 02:52:03 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040616065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1040616065
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/11.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.1295469384
Short name T309
Test name
Test status
Simulation time 21096439374 ps
CPU time 63.19 seconds
Started Aug 23 02:52:05 AM UTC 24
Finished Aug 23 02:53:10 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295469384 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.1295469384
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/11.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.2339941517
Short name T306
Test name
Test status
Simulation time 15302465764 ps
CPU time 58.08 seconds
Started Aug 23 02:52:06 AM UTC 24
Finished Aug 23 02:53:06 AM UTC 24
Peak memory 216872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339941517 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.2339941517
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/11.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.1284530510
Short name T132
Test name
Test status
Simulation time 28225937 ps
CPU time 2.9 seconds
Started Aug 23 02:52:04 AM UTC 24
Finished Aug 23 02:52:08 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284530510 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.1284530510
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/11.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.800555899
Short name T329
Test name
Test status
Simulation time 1592453686 ps
CPU time 78.02 seconds
Started Aug 23 02:52:54 AM UTC 24
Finished Aug 23 02:54:14 AM UTC 24
Peak memory 218816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800555899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.800555899
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/11.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2520250764
Short name T327
Test name
Test status
Simulation time 2096239118 ps
CPU time 68.72 seconds
Started Aug 23 02:53:00 AM UTC 24
Finished Aug 23 02:54:11 AM UTC 24
Peak memory 218820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520250764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2520250764
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/11.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.3948663472
Short name T32
Test name
Test status
Simulation time 3348343999 ps
CPU time 179.81 seconds
Started Aug 23 02:53:00 AM UTC 24
Finished Aug 23 02:56:03 AM UTC 24
Peak memory 223340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948663472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.3948663472
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/11.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.1762217060
Short name T228
Test name
Test status
Simulation time 651178866 ps
CPU time 20.07 seconds
Started Aug 23 02:52:40 AM UTC 24
Finished Aug 23 02:53:01 AM UTC 24
Peak memory 219200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762217060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1762217060
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/11.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.1560445672
Short name T111
Test name
Test status
Simulation time 1709267952 ps
CPU time 26.94 seconds
Started Aug 23 02:53:11 AM UTC 24
Finished Aug 23 02:53:39 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560445672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1560445672
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/12.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.3331796109
Short name T561
Test name
Test status
Simulation time 118249103607 ps
CPU time 869.27 seconds
Started Aug 23 02:53:25 AM UTC 24
Finished Aug 23 03:08:03 AM UTC 24
Peak memory 222936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331796109 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.3331796109
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/12.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.1415499160
Short name T323
Test name
Test status
Simulation time 443990444 ps
CPU time 18.52 seconds
Started Aug 23 02:53:38 AM UTC 24
Finished Aug 23 02:53:58 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415499160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.1415499160
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/12.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.1624364086
Short name T316
Test name
Test status
Simulation time 137821587 ps
CPU time 7.85 seconds
Started Aug 23 02:53:32 AM UTC 24
Finished Aug 23 02:53:41 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624364086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1624364086
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/12.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random.3124903774
Short name T317
Test name
Test status
Simulation time 436300700 ps
CPU time 32.2 seconds
Started Aug 23 02:53:07 AM UTC 24
Finished Aug 23 02:53:41 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124903774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3124903774
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/12.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.1539529181
Short name T354
Test name
Test status
Simulation time 39076440286 ps
CPU time 216.8 seconds
Started Aug 23 02:53:09 AM UTC 24
Finished Aug 23 02:56:48 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539529181 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1539529181
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/12.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3081732326
Short name T311
Test name
Test status
Simulation time 1945312707 ps
CPU time 17.84 seconds
Started Aug 23 02:53:11 AM UTC 24
Finished Aug 23 02:53:30 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081732326 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3081732326
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/12.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.2693794392
Short name T312
Test name
Test status
Simulation time 281935206 ps
CPU time 21.84 seconds
Started Aug 23 02:53:08 AM UTC 24
Finished Aug 23 02:53:32 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693794392 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.2693794392
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/12.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.1988685636
Short name T326
Test name
Test status
Simulation time 1106304690 ps
CPU time 38.09 seconds
Started Aug 23 02:53:30 AM UTC 24
Finished Aug 23 02:54:10 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988685636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1988685636
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/12.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.2562573655
Short name T308
Test name
Test status
Simulation time 157177657 ps
CPU time 4.17 seconds
Started Aug 23 02:53:03 AM UTC 24
Finished Aug 23 02:53:08 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562573655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2562573655
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/12.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.1173737442
Short name T313
Test name
Test status
Simulation time 19240820462 ps
CPU time 31.83 seconds
Started Aug 23 02:53:04 AM UTC 24
Finished Aug 23 02:53:37 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173737442 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1173737442
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/12.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.3450282878
Short name T319
Test name
Test status
Simulation time 2727568854 ps
CPU time 39.62 seconds
Started Aug 23 02:53:04 AM UTC 24
Finished Aug 23 02:53:45 AM UTC 24
Peak memory 216872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450282878 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3450282878
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/12.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.1199954277
Short name T307
Test name
Test status
Simulation time 38103993 ps
CPU time 3.24 seconds
Started Aug 23 02:53:03 AM UTC 24
Finished Aug 23 02:53:07 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199954277 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.1199954277
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/12.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.254050930
Short name T113
Test name
Test status
Simulation time 3794578982 ps
CPU time 97.15 seconds
Started Aug 23 02:53:40 AM UTC 24
Finished Aug 23 02:55:19 AM UTC 24
Peak memory 218944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254050930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.254050930
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/12.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.1285007099
Short name T347
Test name
Test status
Simulation time 6822771034 ps
CPU time 128.64 seconds
Started Aug 23 02:53:42 AM UTC 24
Finished Aug 23 02:55:53 AM UTC 24
Peak memory 220996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285007099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1285007099
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/12.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2307354241
Short name T178
Test name
Test status
Simulation time 1151451273 ps
CPU time 264.21 seconds
Started Aug 23 02:53:42 AM UTC 24
Finished Aug 23 02:58:10 AM UTC 24
Peak memory 223344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307354241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.2307354241
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/12.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.1120841793
Short name T241
Test name
Test status
Simulation time 612942400 ps
CPU time 149.52 seconds
Started Aug 23 02:53:42 AM UTC 24
Finished Aug 23 02:56:14 AM UTC 24
Peak memory 223224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120841793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.1120841793
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/12.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.2709343570
Short name T318
Test name
Test status
Simulation time 88574880 ps
CPU time 8.73 seconds
Started Aug 23 02:53:33 AM UTC 24
Finished Aug 23 02:53:43 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709343570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2709343570
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/12.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.353408310
Short name T331
Test name
Test status
Simulation time 808261722 ps
CPU time 22.38 seconds
Started Aug 23 02:53:56 AM UTC 24
Finished Aug 23 02:54:19 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353408310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.353408310
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/13.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.2285009540
Short name T411
Test name
Test status
Simulation time 118946253520 ps
CPU time 369.97 seconds
Started Aug 23 02:53:59 AM UTC 24
Finished Aug 23 03:00:13 AM UTC 24
Peak memory 219204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285009540 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.2285009540
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/13.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.4148443999
Short name T334
Test name
Test status
Simulation time 619986457 ps
CPU time 14.14 seconds
Started Aug 23 02:54:11 AM UTC 24
Finished Aug 23 02:54:27 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148443999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.4148443999
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/13.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.3562359688
Short name T325
Test name
Test status
Simulation time 18985414 ps
CPU time 3.01 seconds
Started Aug 23 02:54:06 AM UTC 24
Finished Aug 23 02:54:10 AM UTC 24
Peak memory 217020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562359688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3562359688
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/13.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random.1803087068
Short name T112
Test name
Test status
Simulation time 2841810139 ps
CPU time 30.71 seconds
Started Aug 23 02:53:46 AM UTC 24
Finished Aug 23 02:54:18 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803087068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.1803087068
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/13.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.1854406230
Short name T363
Test name
Test status
Simulation time 79443921997 ps
CPU time 232.13 seconds
Started Aug 23 02:53:49 AM UTC 24
Finished Aug 23 02:57:45 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854406230 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.1854406230
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/13.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2973953083
Short name T222
Test name
Test status
Simulation time 39929834749 ps
CPU time 211.13 seconds
Started Aug 23 02:53:53 AM UTC 24
Finished Aug 23 02:57:28 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973953083 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2973953083
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/13.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.1336666729
Short name T324
Test name
Test status
Simulation time 347599542 ps
CPU time 15.52 seconds
Started Aug 23 02:53:48 AM UTC 24
Finished Aug 23 02:54:05 AM UTC 24
Peak memory 217152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336666729 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1336666729
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/13.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.2378743160
Short name T328
Test name
Test status
Simulation time 1045159609 ps
CPU time 10.83 seconds
Started Aug 23 02:54:01 AM UTC 24
Finished Aug 23 02:54:13 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378743160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2378743160
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/13.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.4146250300
Short name T320
Test name
Test status
Simulation time 267893290 ps
CPU time 4.49 seconds
Started Aug 23 02:53:42 AM UTC 24
Finished Aug 23 02:53:47 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146250300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.4146250300
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/13.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.1818740918
Short name T330
Test name
Test status
Simulation time 5939900607 ps
CPU time 32.5 seconds
Started Aug 23 02:53:43 AM UTC 24
Finished Aug 23 02:54:17 AM UTC 24
Peak memory 217140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818740918 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.1818740918
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/13.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2117549766
Short name T64
Test name
Test status
Simulation time 5739865856 ps
CPU time 37.27 seconds
Started Aug 23 02:53:45 AM UTC 24
Finished Aug 23 02:54:23 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117549766 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2117549766
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/13.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.4066630963
Short name T321
Test name
Test status
Simulation time 126175163 ps
CPU time 3.66 seconds
Started Aug 23 02:53:43 AM UTC 24
Finished Aug 23 02:53:48 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066630963 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.4066630963
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/13.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.4150059148
Short name T119
Test name
Test status
Simulation time 3493901426 ps
CPU time 102.08 seconds
Started Aug 23 02:54:11 AM UTC 24
Finished Aug 23 02:55:56 AM UTC 24
Peak memory 220996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150059148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.4150059148
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/13.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.351229072
Short name T337
Test name
Test status
Simulation time 1637588119 ps
CPU time 31.64 seconds
Started Aug 23 02:54:14 AM UTC 24
Finished Aug 23 02:54:47 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351229072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.351229072
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/13.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1868626480
Short name T382
Test name
Test status
Simulation time 4133125847 ps
CPU time 271.69 seconds
Started Aug 23 02:54:12 AM UTC 24
Finished Aug 23 02:58:47 AM UTC 24
Peak memory 223044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868626480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.1868626480
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/13.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.3278303481
Short name T346
Test name
Test status
Simulation time 8121825194 ps
CPU time 74.35 seconds
Started Aug 23 02:54:15 AM UTC 24
Finished Aug 23 02:55:31 AM UTC 24
Peak memory 220996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278303481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.3278303481
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/13.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.655211811
Short name T214
Test name
Test status
Simulation time 702706983 ps
CPU time 21.75 seconds
Started Aug 23 02:54:07 AM UTC 24
Finished Aug 23 02:54:30 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655211811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.655211811
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/13.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.2903419306
Short name T258
Test name
Test status
Simulation time 2135740604 ps
CPU time 44.65 seconds
Started Aug 23 02:54:44 AM UTC 24
Finished Aug 23 02:55:30 AM UTC 24
Peak memory 219140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903419306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.2903419306
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/14.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.2860435664
Short name T121
Test name
Test status
Simulation time 71456815546 ps
CPU time 201.74 seconds
Started Aug 23 02:54:45 AM UTC 24
Finished Aug 23 02:58:10 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860435664 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.2860435664
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/14.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3350706391
Short name T342
Test name
Test status
Simulation time 110287935 ps
CPU time 17.82 seconds
Started Aug 23 02:55:02 AM UTC 24
Finished Aug 23 02:55:21 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350706391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.3350706391
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/14.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.664387819
Short name T340
Test name
Test status
Simulation time 1085603523 ps
CPU time 21.48 seconds
Started Aug 23 02:54:50 AM UTC 24
Finished Aug 23 02:55:13 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664387819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.664387819
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/14.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random.3571272037
Short name T338
Test name
Test status
Simulation time 435084286 ps
CPU time 22.65 seconds
Started Aug 23 02:54:25 AM UTC 24
Finished Aug 23 02:54:49 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571272037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.3571272037
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/14.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.4290767161
Short name T378
Test name
Test status
Simulation time 42847217186 ps
CPU time 248.31 seconds
Started Aug 23 02:54:27 AM UTC 24
Finished Aug 23 02:58:39 AM UTC 24
Peak memory 219204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290767161 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.4290767161
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/14.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2143855940
Short name T172
Test name
Test status
Simulation time 11541368204 ps
CPU time 74.97 seconds
Started Aug 23 02:54:32 AM UTC 24
Finished Aug 23 02:55:49 AM UTC 24
Peak memory 217224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143855940 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2143855940
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/14.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.1927281900
Short name T336
Test name
Test status
Simulation time 372133083 ps
CPU time 17.69 seconds
Started Aug 23 02:54:25 AM UTC 24
Finished Aug 23 02:54:44 AM UTC 24
Peak memory 217152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927281900 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.1927281900
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/14.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.933154690
Short name T343
Test name
Test status
Simulation time 1160614984 ps
CPU time 33.54 seconds
Started Aug 23 02:54:48 AM UTC 24
Finished Aug 23 02:55:23 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933154690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.933154690
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/14.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.4075559351
Short name T333
Test name
Test status
Simulation time 155527044 ps
CPU time 4.63 seconds
Started Aug 23 02:54:18 AM UTC 24
Finished Aug 23 02:54:24 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075559351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.4075559351
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/14.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3211036713
Short name T339
Test name
Test status
Simulation time 8757749532 ps
CPU time 35.14 seconds
Started Aug 23 02:54:21 AM UTC 24
Finished Aug 23 02:54:57 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211036713 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3211036713
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/14.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.673831548
Short name T335
Test name
Test status
Simulation time 2715697477 ps
CPU time 18.02 seconds
Started Aug 23 02:54:24 AM UTC 24
Finished Aug 23 02:54:43 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673831548 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.673831548
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/14.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.3991672665
Short name T332
Test name
Test status
Simulation time 74797268 ps
CPU time 2.91 seconds
Started Aug 23 02:54:19 AM UTC 24
Finished Aug 23 02:54:23 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991672665 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.3991672665
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/14.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.3649730955
Short name T189
Test name
Test status
Simulation time 5455243316 ps
CPU time 115.92 seconds
Started Aug 23 02:55:14 AM UTC 24
Finished Aug 23 02:57:12 AM UTC 24
Peak memory 220996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649730955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3649730955
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/14.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.569909906
Short name T358
Test name
Test status
Simulation time 15397529374 ps
CPU time 126.28 seconds
Started Aug 23 02:55:20 AM UTC 24
Finished Aug 23 02:57:29 AM UTC 24
Peak memory 218952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569909906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.569909906
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/14.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.346077048
Short name T190
Test name
Test status
Simulation time 4435980775 ps
CPU time 404.53 seconds
Started Aug 23 02:55:20 AM UTC 24
Finished Aug 23 03:02:10 AM UTC 24
Peak memory 224960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346077048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.346077048
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/14.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.3320252914
Short name T459
Test name
Test status
Simulation time 10815042140 ps
CPU time 473.62 seconds
Started Aug 23 02:55:22 AM UTC 24
Finished Aug 23 03:03:21 AM UTC 24
Peak memory 237324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320252914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.3320252914
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/14.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.371701211
Short name T341
Test name
Test status
Simulation time 187634773 ps
CPU time 20.79 seconds
Started Aug 23 02:54:58 AM UTC 24
Finished Aug 23 02:55:20 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371701211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.371701211
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/14.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.201996870
Short name T65
Test name
Test status
Simulation time 472895845 ps
CPU time 26.37 seconds
Started Aug 23 02:55:49 AM UTC 24
Finished Aug 23 02:56:17 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201996870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.201996870
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/15.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.2337316679
Short name T73
Test name
Test status
Simulation time 132418452930 ps
CPU time 541.66 seconds
Started Aug 23 02:55:54 AM UTC 24
Finished Aug 23 03:05:02 AM UTC 24
Peak memory 222548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337316679 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.2337316679
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/15.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.3338694461
Short name T240
Test name
Test status
Simulation time 46990613 ps
CPU time 7.29 seconds
Started Aug 23 02:56:03 AM UTC 24
Finished Aug 23 02:56:11 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338694461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.3338694461
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/15.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.3201520070
Short name T237
Test name
Test status
Simulation time 138959968 ps
CPU time 3.35 seconds
Started Aug 23 02:55:57 AM UTC 24
Finished Aug 23 02:56:02 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201520070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3201520070
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/15.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random.2819545189
Short name T224
Test name
Test status
Simulation time 2009236016 ps
CPU time 36.68 seconds
Started Aug 23 02:55:32 AM UTC 24
Finished Aug 23 02:56:10 AM UTC 24
Peak memory 218876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819545189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2819545189
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/15.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.4144851821
Short name T66
Test name
Test status
Simulation time 21838699217 ps
CPU time 97.45 seconds
Started Aug 23 02:55:33 AM UTC 24
Finished Aug 23 02:57:13 AM UTC 24
Peak memory 217152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144851821 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.4144851821
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/15.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.2550910604
Short name T151
Test name
Test status
Simulation time 5375309254 ps
CPU time 69.77 seconds
Started Aug 23 02:55:44 AM UTC 24
Finished Aug 23 02:56:56 AM UTC 24
Peak memory 217160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550910604 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.2550910604
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/15.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.3706351650
Short name T348
Test name
Test status
Simulation time 203142900 ps
CPU time 22.67 seconds
Started Aug 23 02:55:32 AM UTC 24
Finished Aug 23 02:55:56 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706351650 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3706351650
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/15.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.438852819
Short name T351
Test name
Test status
Simulation time 1499071947 ps
CPU time 35.54 seconds
Started Aug 23 02:55:57 AM UTC 24
Finished Aug 23 02:56:34 AM UTC 24
Peak memory 216956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438852819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.438852819
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/15.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.2930646430
Short name T344
Test name
Test status
Simulation time 27735276 ps
CPU time 2.95 seconds
Started Aug 23 02:55:22 AM UTC 24
Finished Aug 23 02:55:26 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930646430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.2930646430
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/15.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2605862540
Short name T236
Test name
Test status
Simulation time 4376247295 ps
CPU time 30.05 seconds
Started Aug 23 02:55:27 AM UTC 24
Finished Aug 23 02:55:58 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605862540 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2605862540
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/15.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.872676214
Short name T238
Test name
Test status
Simulation time 3075038791 ps
CPU time 32.8 seconds
Started Aug 23 02:55:28 AM UTC 24
Finished Aug 23 02:56:02 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872676214 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.872676214
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/15.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.2344905943
Short name T345
Test name
Test status
Simulation time 34705982 ps
CPU time 2.18 seconds
Started Aug 23 02:55:24 AM UTC 24
Finished Aug 23 02:55:27 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344905943 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.2344905943
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/15.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.1634896440
Short name T368
Test name
Test status
Simulation time 973148559 ps
CPU time 130.5 seconds
Started Aug 23 02:56:03 AM UTC 24
Finished Aug 23 02:58:16 AM UTC 24
Peak memory 219080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634896440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1634896440
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/15.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.2082121974
Short name T374
Test name
Test status
Simulation time 3463815440 ps
CPU time 139.63 seconds
Started Aug 23 02:56:06 AM UTC 24
Finished Aug 23 02:58:28 AM UTC 24
Peak memory 219208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082121974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2082121974
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/15.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.424843835
Short name T405
Test name
Test status
Simulation time 4042798709 ps
CPU time 209.19 seconds
Started Aug 23 02:56:04 AM UTC 24
Finished Aug 23 02:59:37 AM UTC 24
Peak memory 220992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424843835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.424843835
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/15.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2537700223
Short name T364
Test name
Test status
Simulation time 2921280098 ps
CPU time 102.75 seconds
Started Aug 23 02:56:11 AM UTC 24
Finished Aug 23 02:57:56 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537700223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.2537700223
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/15.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.1140517701
Short name T239
Test name
Test status
Simulation time 34209175 ps
CPU time 4.34 seconds
Started Aug 23 02:56:00 AM UTC 24
Finished Aug 23 02:56:05 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140517701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1140517701
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/15.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.179198818
Short name T357
Test name
Test status
Simulation time 889700106 ps
CPU time 44.28 seconds
Started Aug 23 02:56:42 AM UTC 24
Finished Aug 23 02:57:28 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179198818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.179198818
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/16.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.4187881396
Short name T256
Test name
Test status
Simulation time 22342662667 ps
CPU time 148.25 seconds
Started Aug 23 02:56:50 AM UTC 24
Finished Aug 23 02:59:20 AM UTC 24
Peak memory 219016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187881396 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.4187881396
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/16.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.3333337278
Short name T356
Test name
Test status
Simulation time 121032456 ps
CPU time 4.54 seconds
Started Aug 23 02:57:14 AM UTC 24
Finished Aug 23 02:57:19 AM UTC 24
Peak memory 217152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333337278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.3333337278
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/16.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.2986602319
Short name T361
Test name
Test status
Simulation time 2195614196 ps
CPU time 32.04 seconds
Started Aug 23 02:57:05 AM UTC 24
Finished Aug 23 02:57:38 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986602319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2986602319
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/16.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random.1532998448
Short name T350
Test name
Test status
Simulation time 278357861 ps
CPU time 11.17 seconds
Started Aug 23 02:56:21 AM UTC 24
Finished Aug 23 02:56:34 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532998448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1532998448
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/16.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.1433875720
Short name T402
Test name
Test status
Simulation time 25801637717 ps
CPU time 172.59 seconds
Started Aug 23 02:56:35 AM UTC 24
Finished Aug 23 02:59:30 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433875720 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1433875720
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/16.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.116948021
Short name T388
Test name
Test status
Simulation time 69119388251 ps
CPU time 131.08 seconds
Started Aug 23 02:56:41 AM UTC 24
Finished Aug 23 02:58:55 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116948021 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.116948021
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/16.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.1455787876
Short name T353
Test name
Test status
Simulation time 50228338 ps
CPU time 5.07 seconds
Started Aug 23 02:56:35 AM UTC 24
Finished Aug 23 02:56:41 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455787876 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.1455787876
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/16.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.1675212153
Short name T232
Test name
Test status
Simulation time 3278892101 ps
CPU time 40.32 seconds
Started Aug 23 02:56:57 AM UTC 24
Finished Aug 23 02:57:39 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675212153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1675212153
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/16.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.1860946460
Short name T242
Test name
Test status
Simulation time 109130201 ps
CPU time 3.62 seconds
Started Aug 23 02:56:12 AM UTC 24
Finished Aug 23 02:56:17 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860946460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1860946460
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/16.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.629828141
Short name T355
Test name
Test status
Simulation time 8003844745 ps
CPU time 45.36 seconds
Started Aug 23 02:56:18 AM UTC 24
Finished Aug 23 02:57:04 AM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629828141 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.629828141
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/16.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2465053237
Short name T352
Test name
Test status
Simulation time 2599311545 ps
CPU time 21.89 seconds
Started Aug 23 02:56:18 AM UTC 24
Finished Aug 23 02:56:41 AM UTC 24
Peak memory 217132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465053237 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2465053237
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/16.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2527911367
Short name T349
Test name
Test status
Simulation time 70426497 ps
CPU time 3.09 seconds
Started Aug 23 02:56:15 AM UTC 24
Finished Aug 23 02:56:20 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527911367 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2527911367
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/16.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.3241518383
Short name T179
Test name
Test status
Simulation time 1590486996 ps
CPU time 68.45 seconds
Started Aug 23 02:57:20 AM UTC 24
Finished Aug 23 02:58:30 AM UTC 24
Peak memory 221064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241518383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3241518383
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/16.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.2208155577
Short name T390
Test name
Test status
Simulation time 1661638103 ps
CPU time 85.18 seconds
Started Aug 23 02:57:29 AM UTC 24
Finished Aug 23 02:58:56 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208155577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2208155577
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/16.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3433292032
Short name T359
Test name
Test status
Simulation time 8259956 ps
CPU time 5.38 seconds
Started Aug 23 02:57:29 AM UTC 24
Finished Aug 23 02:57:36 AM UTC 24
Peak memory 217072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433292032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.3433292032
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/16.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.137422680
Short name T423
Test name
Test status
Simulation time 7520275863 ps
CPU time 188.86 seconds
Started Aug 23 02:57:30 AM UTC 24
Finished Aug 23 03:00:42 AM UTC 24
Peak memory 223352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137422680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.137422680
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/16.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.4017943458
Short name T247
Test name
Test status
Simulation time 483938404 ps
CPU time 15.06 seconds
Started Aug 23 02:57:14 AM UTC 24
Finished Aug 23 02:57:30 AM UTC 24
Peak memory 217152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017943458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.4017943458
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/16.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.2727033408
Short name T372
Test name
Test status
Simulation time 265558049 ps
CPU time 23.68 seconds
Started Aug 23 02:57:57 AM UTC 24
Finished Aug 23 02:58:22 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727033408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2727033408
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/17.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.4162490224
Short name T553
Test name
Test status
Simulation time 71570854090 ps
CPU time 574.18 seconds
Started Aug 23 02:58:02 AM UTC 24
Finished Aug 23 03:07:42 AM UTC 24
Peak memory 220500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162490224 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.4162490224
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/17.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.4213004473
Short name T369
Test name
Test status
Simulation time 270941361 ps
CPU time 5.49 seconds
Started Aug 23 02:58:11 AM UTC 24
Finished Aug 23 02:58:18 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213004473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.4213004473
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/17.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.1732095208
Short name T375
Test name
Test status
Simulation time 1412492162 ps
CPU time 20.1 seconds
Started Aug 23 02:58:08 AM UTC 24
Finished Aug 23 02:58:30 AM UTC 24
Peak memory 216964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732095208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1732095208
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/17.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random.12498952
Short name T365
Test name
Test status
Simulation time 869822895 ps
CPU time 19.72 seconds
Started Aug 23 02:57:40 AM UTC 24
Finished Aug 23 02:58:01 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12498952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.12498952
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/17.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.3610458772
Short name T489
Test name
Test status
Simulation time 351800484808 ps
CPU time 405.6 seconds
Started Aug 23 02:57:44 AM UTC 24
Finished Aug 23 03:04:35 AM UTC 24
Peak memory 218832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610458772 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3610458772
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/17.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2834542343
Short name T67
Test name
Test status
Simulation time 11215756576 ps
CPU time 41.58 seconds
Started Aug 23 02:57:46 AM UTC 24
Finished Aug 23 02:58:29 AM UTC 24
Peak memory 217164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834542343 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2834542343
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/17.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.1467572486
Short name T215
Test name
Test status
Simulation time 310563681 ps
CPU time 24.09 seconds
Started Aug 23 02:57:42 AM UTC 24
Finished Aug 23 02:58:07 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467572486 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.1467572486
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/17.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.2111917846
Short name T376
Test name
Test status
Simulation time 6998606648 ps
CPU time 27.64 seconds
Started Aug 23 02:58:03 AM UTC 24
Finished Aug 23 02:58:32 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111917846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2111917846
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/17.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.4096421554
Short name T360
Test name
Test status
Simulation time 309112088 ps
CPU time 5.28 seconds
Started Aug 23 02:57:32 AM UTC 24
Finished Aug 23 02:57:38 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096421554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.4096421554
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/17.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.171217884
Short name T367
Test name
Test status
Simulation time 5080470958 ps
CPU time 33.84 seconds
Started Aug 23 02:57:40 AM UTC 24
Finished Aug 23 02:58:15 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171217884 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.171217884
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/17.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.101486860
Short name T366
Test name
Test status
Simulation time 3046419182 ps
CPU time 28.94 seconds
Started Aug 23 02:57:40 AM UTC 24
Finished Aug 23 02:58:10 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101486860 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.101486860
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/17.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3540488311
Short name T362
Test name
Test status
Simulation time 56012513 ps
CPU time 2.92 seconds
Started Aug 23 02:57:37 AM UTC 24
Finished Aug 23 02:57:41 AM UTC 24
Peak memory 217064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540488311 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3540488311
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/17.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.1808611381
Short name T216
Test name
Test status
Simulation time 949302004 ps
CPU time 60.2 seconds
Started Aug 23 02:58:11 AM UTC 24
Finished Aug 23 02:59:13 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808611381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1808611381
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/17.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.2860696850
Short name T380
Test name
Test status
Simulation time 423010958 ps
CPU time 26.74 seconds
Started Aug 23 02:58:17 AM UTC 24
Finished Aug 23 02:58:45 AM UTC 24
Peak memory 217096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860696850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2860696850
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/17.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.2769692911
Short name T467
Test name
Test status
Simulation time 1064117036 ps
CPU time 309.66 seconds
Started Aug 23 02:58:16 AM UTC 24
Finished Aug 23 03:03:30 AM UTC 24
Peak memory 222980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769692911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.2769692911
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/17.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.139060790
Short name T44
Test name
Test status
Simulation time 6210009853 ps
CPU time 129.27 seconds
Started Aug 23 02:58:18 AM UTC 24
Finished Aug 23 03:00:30 AM UTC 24
Peak memory 223048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139060790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.139060790
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/17.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.1816429308
Short name T370
Test name
Test status
Simulation time 308806838 ps
CPU time 5.96 seconds
Started Aug 23 02:58:11 AM UTC 24
Finished Aug 23 02:58:18 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816429308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1816429308
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/17.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.3701778618
Short name T383
Test name
Test status
Simulation time 2314614325 ps
CPU time 15.37 seconds
Started Aug 23 02:58:32 AM UTC 24
Finished Aug 23 02:58:48 AM UTC 24
Peak memory 219204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701778618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3701778618
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/18.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.81171087
Short name T477
Test name
Test status
Simulation time 63956611535 ps
CPU time 320.18 seconds
Started Aug 23 02:58:34 AM UTC 24
Finished Aug 23 03:03:58 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81171087 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.81171087
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/18.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.2893341907
Short name T384
Test name
Test status
Simulation time 44142870 ps
CPU time 1.85 seconds
Started Aug 23 02:58:46 AM UTC 24
Finished Aug 23 02:58:49 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893341907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.2893341907
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/18.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.2990649199
Short name T385
Test name
Test status
Simulation time 1728740968 ps
CPU time 8.55 seconds
Started Aug 23 02:58:40 AM UTC 24
Finished Aug 23 02:58:50 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990649199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2990649199
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/18.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random.874540888
Short name T379
Test name
Test status
Simulation time 392935157 ps
CPU time 15.93 seconds
Started Aug 23 02:58:27 AM UTC 24
Finished Aug 23 02:58:44 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874540888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.874540888
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/18.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.2178809200
Short name T425
Test name
Test status
Simulation time 43846065438 ps
CPU time 149.68 seconds
Started Aug 23 02:58:29 AM UTC 24
Finished Aug 23 03:01:01 AM UTC 24
Peak memory 218940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178809200 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2178809200
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/18.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3426467799
Short name T439
Test name
Test status
Simulation time 37170086577 ps
CPU time 188.55 seconds
Started Aug 23 02:58:30 AM UTC 24
Finished Aug 23 03:01:42 AM UTC 24
Peak memory 216908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426467799 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3426467799
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/18.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.1429091827
Short name T377
Test name
Test status
Simulation time 63290860 ps
CPU time 5.91 seconds
Started Aug 23 02:58:29 AM UTC 24
Finished Aug 23 02:58:36 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429091827 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.1429091827
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/18.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.417677327
Short name T381
Test name
Test status
Simulation time 466099753 ps
CPU time 8.04 seconds
Started Aug 23 02:58:37 AM UTC 24
Finished Aug 23 02:58:46 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417677327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.417677327
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/18.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.3430153746
Short name T371
Test name
Test status
Simulation time 41557159 ps
CPU time 1.87 seconds
Started Aug 23 02:58:18 AM UTC 24
Finished Aug 23 02:58:21 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430153746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3430153746
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/18.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.3141646069
Short name T386
Test name
Test status
Simulation time 5138221951 ps
CPU time 28.05 seconds
Started Aug 23 02:58:23 AM UTC 24
Finished Aug 23 02:58:52 AM UTC 24
Peak memory 217204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141646069 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3141646069
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/18.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.3401598597
Short name T389
Test name
Test status
Simulation time 6362310474 ps
CPU time 28.53 seconds
Started Aug 23 02:58:26 AM UTC 24
Finished Aug 23 02:58:56 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401598597 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3401598597
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/18.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3035785156
Short name T373
Test name
Test status
Simulation time 33615679 ps
CPU time 2.25 seconds
Started Aug 23 02:58:23 AM UTC 24
Finished Aug 23 02:58:26 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035785156 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3035785156
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/18.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.2693625824
Short name T122
Test name
Test status
Simulation time 4543123402 ps
CPU time 98.77 seconds
Started Aug 23 02:58:46 AM UTC 24
Finished Aug 23 03:00:27 AM UTC 24
Peak memory 220928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693625824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2693625824
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/18.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1269241852
Short name T419
Test name
Test status
Simulation time 2994278457 ps
CPU time 107.74 seconds
Started Aug 23 02:58:49 AM UTC 24
Finished Aug 23 03:00:38 AM UTC 24
Peak memory 220996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269241852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1269241852
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/18.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.1092255841
Short name T499
Test name
Test status
Simulation time 12489730204 ps
CPU time 363.74 seconds
Started Aug 23 02:58:49 AM UTC 24
Finished Aug 23 03:04:57 AM UTC 24
Peak memory 221000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092255841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.1092255841
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/18.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2106063858
Short name T473
Test name
Test status
Simulation time 7252592346 ps
CPU time 298.67 seconds
Started Aug 23 02:58:50 AM UTC 24
Finished Aug 23 03:03:52 AM UTC 24
Peak memory 233916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106063858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.2106063858
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/18.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.1016710277
Short name T392
Test name
Test status
Simulation time 99557842 ps
CPU time 11.81 seconds
Started Aug 23 02:58:45 AM UTC 24
Finished Aug 23 02:58:58 AM UTC 24
Peak memory 218812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016710277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1016710277
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/18.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.2591540866
Short name T407
Test name
Test status
Simulation time 1148193879 ps
CPU time 31.11 seconds
Started Aug 23 02:59:12 AM UTC 24
Finished Aug 23 02:59:44 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591540866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.2591540866
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/19.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2084989664
Short name T125
Test name
Test status
Simulation time 218922062711 ps
CPU time 416.88 seconds
Started Aug 23 02:59:14 AM UTC 24
Finished Aug 23 03:06:16 AM UTC 24
Peak memory 220500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084989664 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.2084989664
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/19.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.3944721659
Short name T400
Test name
Test status
Simulation time 49114967 ps
CPU time 6.19 seconds
Started Aug 23 02:59:23 AM UTC 24
Finished Aug 23 02:59:30 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944721659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3944721659
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/19.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.2495701044
Short name T398
Test name
Test status
Simulation time 64415987 ps
CPU time 1.94 seconds
Started Aug 23 02:59:19 AM UTC 24
Finished Aug 23 02:59:22 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495701044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2495701044
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/19.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random.1715382389
Short name T397
Test name
Test status
Simulation time 1209946829 ps
CPU time 24.5 seconds
Started Aug 23 02:58:56 AM UTC 24
Finished Aug 23 02:59:22 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715382389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.1715382389
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/19.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.503615439
Short name T417
Test name
Test status
Simulation time 19852215377 ps
CPU time 97.28 seconds
Started Aug 23 02:58:58 AM UTC 24
Finished Aug 23 03:00:37 AM UTC 24
Peak memory 216904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503615439 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.503615439
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/19.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.2595922878
Short name T393
Test name
Test status
Simulation time 2424336245 ps
CPU time 11.57 seconds
Started Aug 23 02:58:59 AM UTC 24
Finished Aug 23 02:59:11 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595922878 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2595922878
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/19.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.1389234862
Short name T394
Test name
Test status
Simulation time 316759150 ps
CPU time 16.16 seconds
Started Aug 23 02:58:58 AM UTC 24
Finished Aug 23 02:59:15 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389234862 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1389234862
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/19.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.282693805
Short name T396
Test name
Test status
Simulation time 151332367 ps
CPU time 4.31 seconds
Started Aug 23 02:59:16 AM UTC 24
Finished Aug 23 02:59:22 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282693805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.282693805
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/19.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.4062494026
Short name T387
Test name
Test status
Simulation time 52229016 ps
CPU time 1.76 seconds
Started Aug 23 02:58:51 AM UTC 24
Finished Aug 23 02:58:54 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062494026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.4062494026
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/19.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.2382324659
Short name T401
Test name
Test status
Simulation time 23083437528 ps
CPU time 34.74 seconds
Started Aug 23 02:58:54 AM UTC 24
Finished Aug 23 02:59:30 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382324659 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2382324659
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/19.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1223765475
Short name T395
Test name
Test status
Simulation time 2589508260 ps
CPU time 21.1 seconds
Started Aug 23 02:58:56 AM UTC 24
Finished Aug 23 02:59:19 AM UTC 24
Peak memory 216872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223765475 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1223765475
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/19.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.2970777076
Short name T391
Test name
Test status
Simulation time 42769116 ps
CPU time 2.47 seconds
Started Aug 23 02:58:53 AM UTC 24
Finished Aug 23 02:58:57 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970777076 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.2970777076
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/19.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.2905560450
Short name T412
Test name
Test status
Simulation time 2263205486 ps
CPU time 57.22 seconds
Started Aug 23 02:59:23 AM UTC 24
Finished Aug 23 03:00:21 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905560450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2905560450
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/19.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.4148295614
Short name T420
Test name
Test status
Simulation time 4624059656 ps
CPU time 73.1 seconds
Started Aug 23 02:59:25 AM UTC 24
Finished Aug 23 03:00:40 AM UTC 24
Peak memory 219208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148295614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.4148295614
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/19.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.3775799439
Short name T523
Test name
Test status
Simulation time 2532872658 ps
CPU time 418.22 seconds
Started Aug 23 02:59:23 AM UTC 24
Finished Aug 23 03:06:26 AM UTC 24
Peak memory 233968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775799439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.3775799439
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/19.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.1584958004
Short name T399
Test name
Test status
Simulation time 17190640 ps
CPU time 1.61 seconds
Started Aug 23 02:59:21 AM UTC 24
Finished Aug 23 02:59:24 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584958004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.1584958004
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/19.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.662209325
Short name T266
Test name
Test status
Simulation time 65687824 ps
CPU time 8.87 seconds
Started Aug 23 02:42:19 AM UTC 24
Finished Aug 23 02:42:29 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662209325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.662209325
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/2.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3434504233
Short name T100
Test name
Test status
Simulation time 48305012391 ps
CPU time 166.11 seconds
Started Aug 23 02:42:22 AM UTC 24
Finished Aug 23 02:45:11 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434504233 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.3434504233
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/2.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.2764102341
Short name T186
Test name
Test status
Simulation time 2780748488 ps
CPU time 22.42 seconds
Started Aug 23 02:42:52 AM UTC 24
Finished Aug 23 02:43:16 AM UTC 24
Peak memory 216972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764102341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.2764102341
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/2.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.3645235681
Short name T25
Test name
Test status
Simulation time 3131116640 ps
CPU time 31.84 seconds
Started Aug 23 02:42:34 AM UTC 24
Finished Aug 23 02:43:07 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645235681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3645235681
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/2.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random.1779883387
Short name T29
Test name
Test status
Simulation time 2079957300 ps
CPU time 13.93 seconds
Started Aug 23 02:41:48 AM UTC 24
Finished Aug 23 02:42:03 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779883387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.1779883387
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/2.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.3984751915
Short name T107
Test name
Test status
Simulation time 51585328873 ps
CPU time 208.88 seconds
Started Aug 23 02:42:11 AM UTC 24
Finished Aug 23 02:45:44 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984751915 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3984751915
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/2.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.1485726444
Short name T184
Test name
Test status
Simulation time 2806544504 ps
CPU time 38.96 seconds
Started Aug 23 02:42:19 AM UTC 24
Finished Aug 23 02:43:00 AM UTC 24
Peak memory 216904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485726444 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1485726444
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/2.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.307402327
Short name T23
Test name
Test status
Simulation time 126070161 ps
CPU time 13.45 seconds
Started Aug 23 02:42:04 AM UTC 24
Finished Aug 23 02:42:19 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307402327 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.307402327
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/2.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.1587398463
Short name T24
Test name
Test status
Simulation time 349845377 ps
CPU time 18.55 seconds
Started Aug 23 02:42:30 AM UTC 24
Finished Aug 23 02:42:50 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587398463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1587398463
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/2.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.879203209
Short name T80
Test name
Test status
Simulation time 29596979 ps
CPU time 2.86 seconds
Started Aug 23 02:41:33 AM UTC 24
Finished Aug 23 02:41:38 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879203209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.879203209
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/2.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3251959509
Short name T82
Test name
Test status
Simulation time 6823851376 ps
CPU time 34.05 seconds
Started Aug 23 02:41:43 AM UTC 24
Finished Aug 23 02:42:18 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251959509 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3251959509
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/2.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.2467545733
Short name T183
Test name
Test status
Simulation time 19306082587 ps
CPU time 69.09 seconds
Started Aug 23 02:41:43 AM UTC 24
Finished Aug 23 02:42:54 AM UTC 24
Peak memory 217140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467545733 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2467545733
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/2.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.4039664540
Short name T81
Test name
Test status
Simulation time 50884844 ps
CPU time 2.81 seconds
Started Aug 23 02:41:38 AM UTC 24
Finished Aug 23 02:41:42 AM UTC 24
Peak memory 217068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039664540 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.4039664540
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/2.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.81204412
Short name T86
Test name
Test status
Simulation time 5116058604 ps
CPU time 171.38 seconds
Started Aug 23 02:42:54 AM UTC 24
Finished Aug 23 02:45:49 AM UTC 24
Peak memory 223032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81204412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-si
m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.81204412
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/2.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1636492817
Short name T34
Test name
Test status
Simulation time 334684841 ps
CPU time 133.71 seconds
Started Aug 23 02:43:00 AM UTC 24
Finished Aug 23 02:45:18 AM UTC 24
Peak memory 220936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636492817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.1636492817
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/2.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.110818075
Short name T47
Test name
Test status
Simulation time 96863201 ps
CPU time 24.74 seconds
Started Aug 23 02:43:10 AM UTC 24
Finished Aug 23 02:43:36 AM UTC 24
Peak memory 218888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110818075 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.110818075
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/2.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.3943458454
Short name T185
Test name
Test status
Simulation time 213182635 ps
CPU time 17.58 seconds
Started Aug 23 02:42:50 AM UTC 24
Finished Aug 23 02:43:09 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943458454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3943458454
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/2.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.888630358
Short name T409
Test name
Test status
Simulation time 72081432 ps
CPU time 4.21 seconds
Started Aug 23 02:59:56 AM UTC 24
Finished Aug 23 03:00:01 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888630358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.888630358
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/20.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.565770951
Short name T485
Test name
Test status
Simulation time 84411480313 ps
CPU time 252.34 seconds
Started Aug 23 03:00:07 AM UTC 24
Finished Aug 23 03:04:23 AM UTC 24
Peak memory 219208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565770951 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.565770951
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/20.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.2620268459
Short name T415
Test name
Test status
Simulation time 235972343 ps
CPU time 6.6 seconds
Started Aug 23 03:00:24 AM UTC 24
Finished Aug 23 03:00:31 AM UTC 24
Peak memory 217028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620268459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.2620268459
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/20.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.3911939573
Short name T416
Test name
Test status
Simulation time 823812996 ps
CPU time 16.49 seconds
Started Aug 23 03:00:14 AM UTC 24
Finished Aug 23 03:00:32 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911939573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3911939573
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/20.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random.2507374452
Short name T406
Test name
Test status
Simulation time 82932352 ps
CPU time 2.46 seconds
Started Aug 23 02:59:38 AM UTC 24
Finished Aug 23 02:59:41 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507374452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.2507374452
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/20.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.2539779503
Short name T160
Test name
Test status
Simulation time 65104379342 ps
CPU time 203.45 seconds
Started Aug 23 02:59:45 AM UTC 24
Finished Aug 23 03:03:12 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539779503 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2539779503
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/20.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.706921897
Short name T434
Test name
Test status
Simulation time 12234968661 ps
CPU time 93.56 seconds
Started Aug 23 02:59:52 AM UTC 24
Finished Aug 23 03:01:27 AM UTC 24
Peak memory 216904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706921897 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.706921897
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/20.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.681096276
Short name T408
Test name
Test status
Simulation time 261185030 ps
CPU time 8.52 seconds
Started Aug 23 02:59:42 AM UTC 24
Finished Aug 23 02:59:51 AM UTC 24
Peak memory 217148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681096276 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.681096276
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/20.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.2842596425
Short name T414
Test name
Test status
Simulation time 1322727161 ps
CPU time 19.78 seconds
Started Aug 23 03:00:07 AM UTC 24
Finished Aug 23 03:00:29 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842596425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2842596425
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/20.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.2900942273
Short name T404
Test name
Test status
Simulation time 299990929 ps
CPU time 3.23 seconds
Started Aug 23 02:59:31 AM UTC 24
Finished Aug 23 02:59:35 AM UTC 24
Peak memory 217132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900942273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2900942273
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/20.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.741448713
Short name T410
Test name
Test status
Simulation time 9316720737 ps
CPU time 28.36 seconds
Started Aug 23 02:59:35 AM UTC 24
Finished Aug 23 03:00:05 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741448713 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.741448713
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/20.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.979268206
Short name T145
Test name
Test status
Simulation time 2119580209 ps
CPU time 17.69 seconds
Started Aug 23 02:59:36 AM UTC 24
Finished Aug 23 02:59:55 AM UTC 24
Peak memory 217068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979268206 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.979268206
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/20.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.611300229
Short name T403
Test name
Test status
Simulation time 23455213 ps
CPU time 1.79 seconds
Started Aug 23 02:59:31 AM UTC 24
Finished Aug 23 02:59:34 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611300229 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.611300229
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/20.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.2935236391
Short name T448
Test name
Test status
Simulation time 1631498405 ps
CPU time 115.92 seconds
Started Aug 23 03:00:28 AM UTC 24
Finished Aug 23 03:02:26 AM UTC 24
Peak memory 220864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935236391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2935236391
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/20.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.2425809694
Short name T481
Test name
Test status
Simulation time 17911359471 ps
CPU time 207.89 seconds
Started Aug 23 03:00:31 AM UTC 24
Finished Aug 23 03:04:02 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425809694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2425809694
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/20.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1295889933
Short name T452
Test name
Test status
Simulation time 455420632 ps
CPU time 128.6 seconds
Started Aug 23 03:00:30 AM UTC 24
Finished Aug 23 03:02:41 AM UTC 24
Peak memory 221192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295889933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.1295889933
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/20.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.2465959551
Short name T426
Test name
Test status
Simulation time 3345598370 ps
CPU time 158.51 seconds
Started Aug 23 03:00:32 AM UTC 24
Finished Aug 23 03:03:13 AM UTC 24
Peak memory 223420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465959551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.2465959551
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/20.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.3723655548
Short name T422
Test name
Test status
Simulation time 211622235 ps
CPU time 17.66 seconds
Started Aug 23 03:00:23 AM UTC 24
Finished Aug 23 03:00:41 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723655548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3723655548
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/20.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.221449127
Short name T428
Test name
Test status
Simulation time 400535161 ps
CPU time 9.22 seconds
Started Aug 23 03:00:56 AM UTC 24
Finished Aug 23 03:01:06 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221449127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.221449127
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/21.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2740112843
Short name T457
Test name
Test status
Simulation time 36458540420 ps
CPU time 127.43 seconds
Started Aug 23 03:01:02 AM UTC 24
Finished Aug 23 03:03:11 AM UTC 24
Peak memory 218952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740112843 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.2740112843
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/21.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.4192111782
Short name T432
Test name
Test status
Simulation time 189079649 ps
CPU time 3.61 seconds
Started Aug 23 03:01:09 AM UTC 24
Finished Aug 23 03:01:14 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192111782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.4192111782
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/21.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.4228525343
Short name T435
Test name
Test status
Simulation time 939836978 ps
CPU time 24.86 seconds
Started Aug 23 03:01:07 AM UTC 24
Finished Aug 23 03:01:33 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228525343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.4228525343
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/21.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random.2640724624
Short name T427
Test name
Test status
Simulation time 224662198 ps
CPU time 22.06 seconds
Started Aug 23 03:00:40 AM UTC 24
Finished Aug 23 03:01:03 AM UTC 24
Peak memory 217152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640724624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.2640724624
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/21.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.1955334238
Short name T462
Test name
Test status
Simulation time 35798272388 ps
CPU time 158.74 seconds
Started Aug 23 03:00:42 AM UTC 24
Finished Aug 23 03:03:23 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955334238 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1955334238
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/21.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.2564706984
Short name T180
Test name
Test status
Simulation time 17150936627 ps
CPU time 57.24 seconds
Started Aug 23 03:00:44 AM UTC 24
Finished Aug 23 03:01:42 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564706984 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.2564706984
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/21.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.4266328990
Short name T424
Test name
Test status
Simulation time 101446109 ps
CPU time 11.31 seconds
Started Aug 23 03:00:42 AM UTC 24
Finished Aug 23 03:00:55 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266328990 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.4266328990
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/21.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.2906556694
Short name T430
Test name
Test status
Simulation time 149146454 ps
CPU time 3.14 seconds
Started Aug 23 03:01:04 AM UTC 24
Finished Aug 23 03:01:08 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906556694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2906556694
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/21.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.638132971
Short name T418
Test name
Test status
Simulation time 163623573 ps
CPU time 2.78 seconds
Started Aug 23 03:00:34 AM UTC 24
Finished Aug 23 03:00:37 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638132971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.638132971
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/21.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.173013958
Short name T431
Test name
Test status
Simulation time 7985448214 ps
CPU time 34.13 seconds
Started Aug 23 03:00:38 AM UTC 24
Finished Aug 23 03:01:13 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173013958 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.173013958
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/21.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.1206105998
Short name T429
Test name
Test status
Simulation time 4124947843 ps
CPU time 27.19 seconds
Started Aug 23 03:00:39 AM UTC 24
Finished Aug 23 03:01:08 AM UTC 24
Peak memory 216872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206105998 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.1206105998
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/21.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3879486489
Short name T421
Test name
Test status
Simulation time 28415457 ps
CPU time 2.14 seconds
Started Aug 23 03:00:38 AM UTC 24
Finished Aug 23 03:00:41 AM UTC 24
Peak memory 217004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879486489 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3879486489
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/21.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.3706090189
Short name T437
Test name
Test status
Simulation time 900128980 ps
CPU time 23.8 seconds
Started Aug 23 03:01:15 AM UTC 24
Finished Aug 23 03:01:40 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706090189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3706090189
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/21.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.2765671822
Short name T445
Test name
Test status
Simulation time 1402035339 ps
CPU time 62.28 seconds
Started Aug 23 03:01:19 AM UTC 24
Finished Aug 23 03:02:23 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765671822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2765671822
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/21.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3267198030
Short name T49
Test name
Test status
Simulation time 3040968899 ps
CPU time 366.68 seconds
Started Aug 23 03:01:15 AM UTC 24
Finished Aug 23 03:07:26 AM UTC 24
Peak memory 224668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267198030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.3267198030
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/21.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.2519689847
Short name T442
Test name
Test status
Simulation time 413416725 ps
CPU time 42.04 seconds
Started Aug 23 03:01:29 AM UTC 24
Finished Aug 23 03:02:13 AM UTC 24
Peak memory 219144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519689847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.2519689847
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/21.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.3164220462
Short name T433
Test name
Test status
Simulation time 1515540005 ps
CPU time 8.98 seconds
Started Aug 23 03:01:08 AM UTC 24
Finished Aug 23 03:01:18 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164220462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3164220462
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/21.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.590751156
Short name T69
Test name
Test status
Simulation time 934494501 ps
CPU time 31.1 seconds
Started Aug 23 03:02:10 AM UTC 24
Finished Aug 23 03:02:43 AM UTC 24
Peak memory 218816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590751156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.590751156
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/22.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2802483554
Short name T586
Test name
Test status
Simulation time 77553704188 ps
CPU time 391.74 seconds
Started Aug 23 03:02:13 AM UTC 24
Finished Aug 23 03:08:49 AM UTC 24
Peak memory 222548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802483554 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.2802483554
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/22.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.1816210675
Short name T449
Test name
Test status
Simulation time 234128583 ps
CPU time 6.58 seconds
Started Aug 23 03:02:23 AM UTC 24
Finished Aug 23 03:02:31 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816210675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.1816210675
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/22.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.3335158456
Short name T447
Test name
Test status
Simulation time 131207514 ps
CPU time 6.55 seconds
Started Aug 23 03:02:18 AM UTC 24
Finished Aug 23 03:02:25 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335158456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3335158456
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/22.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random.3990059862
Short name T444
Test name
Test status
Simulation time 1177692443 ps
CPU time 33.13 seconds
Started Aug 23 03:01:42 AM UTC 24
Finished Aug 23 03:02:17 AM UTC 24
Peak memory 218812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990059862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.3990059862
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/22.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.2307561700
Short name T217
Test name
Test status
Simulation time 41628003998 ps
CPU time 227.48 seconds
Started Aug 23 03:01:59 AM UTC 24
Finished Aug 23 03:05:49 AM UTC 24
Peak memory 217216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307561700 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2307561700
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/22.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.2688281016
Short name T454
Test name
Test status
Simulation time 10815913499 ps
CPU time 40.79 seconds
Started Aug 23 03:02:09 AM UTC 24
Finished Aug 23 03:02:51 AM UTC 24
Peak memory 216908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688281016 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2688281016
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/22.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.3781366936
Short name T440
Test name
Test status
Simulation time 137889832 ps
CPU time 12.98 seconds
Started Aug 23 03:01:44 AM UTC 24
Finished Aug 23 03:01:58 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781366936 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.3781366936
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/22.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.2018007554
Short name T446
Test name
Test status
Simulation time 159469125 ps
CPU time 7.26 seconds
Started Aug 23 03:02:15 AM UTC 24
Finished Aug 23 03:02:23 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018007554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2018007554
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/22.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.2688475866
Short name T436
Test name
Test status
Simulation time 38856418 ps
CPU time 1.79 seconds
Started Aug 23 03:01:34 AM UTC 24
Finished Aug 23 03:01:37 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688475866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2688475866
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/22.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.906323051
Short name T441
Test name
Test status
Simulation time 7656594703 ps
CPU time 26.56 seconds
Started Aug 23 03:01:40 AM UTC 24
Finished Aug 23 03:02:08 AM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906323051 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.906323051
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/22.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.2743394359
Short name T443
Test name
Test status
Simulation time 7951361066 ps
CPU time 29.56 seconds
Started Aug 23 03:01:42 AM UTC 24
Finished Aug 23 03:02:13 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743394359 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2743394359
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/22.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3041371473
Short name T438
Test name
Test status
Simulation time 45078956 ps
CPU time 1.95 seconds
Started Aug 23 03:01:38 AM UTC 24
Finished Aug 23 03:01:41 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041371473 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3041371473
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/22.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.13051608
Short name T484
Test name
Test status
Simulation time 13528391659 ps
CPU time 113.37 seconds
Started Aug 23 03:02:24 AM UTC 24
Finished Aug 23 03:04:20 AM UTC 24
Peak memory 221248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13051608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-si
m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.13051608
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/22.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.2716183601
Short name T464
Test name
Test status
Simulation time 5377552201 ps
CPU time 57.2 seconds
Started Aug 23 03:02:27 AM UTC 24
Finished Aug 23 03:03:25 AM UTC 24
Peak memory 219208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716183601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2716183601
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/22.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.380123762
Short name T202
Test name
Test status
Simulation time 2280602923 ps
CPU time 94.77 seconds
Started Aug 23 03:02:26 AM UTC 24
Finished Aug 23 03:04:03 AM UTC 24
Peak memory 220924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380123762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.380123762
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/22.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3334409650
Short name T529
Test name
Test status
Simulation time 6121884475 ps
CPU time 254.93 seconds
Started Aug 23 03:02:32 AM UTC 24
Finished Aug 23 03:06:50 AM UTC 24
Peak memory 233592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334409650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.3334409650
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/22.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.3794111487
Short name T450
Test name
Test status
Simulation time 1020409378 ps
CPU time 13.49 seconds
Started Aug 23 03:02:20 AM UTC 24
Finished Aug 23 03:02:35 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794111487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3794111487
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/22.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.3561002730
Short name T456
Test name
Test status
Simulation time 73739559 ps
CPU time 7.43 seconds
Started Aug 23 03:02:52 AM UTC 24
Finished Aug 23 03:03:00 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561002730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.3561002730
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/23.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.3533507482
Short name T225
Test name
Test status
Simulation time 7886298191 ps
CPU time 27.29 seconds
Started Aug 23 03:03:01 AM UTC 24
Finished Aug 23 03:03:30 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533507482 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.3533507482
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/23.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.677182826
Short name T458
Test name
Test status
Simulation time 41621357 ps
CPU time 3.86 seconds
Started Aug 23 03:03:15 AM UTC 24
Finished Aug 23 03:03:20 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677182826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.677182826
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/23.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.1054788175
Short name T460
Test name
Test status
Simulation time 397183372 ps
CPU time 7.95 seconds
Started Aug 23 03:03:12 AM UTC 24
Finished Aug 23 03:03:22 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054788175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1054788175
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/23.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random.1772323939
Short name T455
Test name
Test status
Simulation time 113041234 ps
CPU time 8.9 seconds
Started Aug 23 03:02:41 AM UTC 24
Finished Aug 23 03:02:51 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772323939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1772323939
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/23.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.463803377
Short name T487
Test name
Test status
Simulation time 26754124385 ps
CPU time 100.72 seconds
Started Aug 23 03:02:49 AM UTC 24
Finished Aug 23 03:04:31 AM UTC 24
Peak memory 216960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463803377 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.463803377
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/23.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.557045068
Short name T463
Test name
Test status
Simulation time 4308166272 ps
CPU time 30.65 seconds
Started Aug 23 03:02:52 AM UTC 24
Finished Aug 23 03:03:24 AM UTC 24
Peak memory 217164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557045068 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.557045068
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/23.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.3603296481
Short name T453
Test name
Test status
Simulation time 142157806 ps
CPU time 3.04 seconds
Started Aug 23 03:02:44 AM UTC 24
Finished Aug 23 03:02:48 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603296481 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.3603296481
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/23.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.1424284881
Short name T235
Test name
Test status
Simulation time 1758969505 ps
CPU time 15.92 seconds
Started Aug 23 03:03:09 AM UTC 24
Finished Aug 23 03:03:26 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424284881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1424284881
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/23.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.3405537140
Short name T68
Test name
Test status
Simulation time 332494301 ps
CPU time 2.86 seconds
Started Aug 23 03:02:36 AM UTC 24
Finished Aug 23 03:02:40 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405537140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3405537140
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/23.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.4282108948
Short name T70
Test name
Test status
Simulation time 5216583886 ps
CPU time 27.13 seconds
Started Aug 23 03:02:40 AM UTC 24
Finished Aug 23 03:03:09 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282108948 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.4282108948
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/23.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.3828132115
Short name T71
Test name
Test status
Simulation time 12462995463 ps
CPU time 31.3 seconds
Started Aug 23 03:02:41 AM UTC 24
Finished Aug 23 03:03:14 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828132115 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3828132115
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/23.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3620603314
Short name T451
Test name
Test status
Simulation time 38109887 ps
CPU time 2.09 seconds
Started Aug 23 03:02:37 AM UTC 24
Finished Aug 23 03:02:40 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620603314 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3620603314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/23.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.87479824
Short name T515
Test name
Test status
Simulation time 40815519100 ps
CPU time 157.42 seconds
Started Aug 23 03:03:15 AM UTC 24
Finished Aug 23 03:05:55 AM UTC 24
Peak memory 220984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87479824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-si
m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.87479824
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/23.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1243979464
Short name T468
Test name
Test status
Simulation time 281896523 ps
CPU time 16.96 seconds
Started Aug 23 03:03:22 AM UTC 24
Finished Aug 23 03:03:41 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243979464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1243979464
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/23.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3292573638
Short name T501
Test name
Test status
Simulation time 372829688 ps
CPU time 99.99 seconds
Started Aug 23 03:03:21 AM UTC 24
Finished Aug 23 03:05:03 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292573638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.3292573638
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/23.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3846067602
Short name T587
Test name
Test status
Simulation time 8318342611 ps
CPU time 323.37 seconds
Started Aug 23 03:03:22 AM UTC 24
Finished Aug 23 03:08:50 AM UTC 24
Peak memory 233972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846067602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.3846067602
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/23.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.2411055111
Short name T461
Test name
Test status
Simulation time 227158869 ps
CPU time 8.22 seconds
Started Aug 23 03:03:12 AM UTC 24
Finished Aug 23 03:03:22 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411055111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2411055111
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/23.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.3451746678
Short name T474
Test name
Test status
Simulation time 269512452 ps
CPU time 23.8 seconds
Started Aug 23 03:03:30 AM UTC 24
Finished Aug 23 03:03:56 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451746678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.3451746678
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/24.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.237812362
Short name T139
Test name
Test status
Simulation time 86909070314 ps
CPU time 636.1 seconds
Started Aug 23 03:03:36 AM UTC 24
Finished Aug 23 03:14:19 AM UTC 24
Peak memory 222612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237812362 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.237812362
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/24.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.3262540535
Short name T475
Test name
Test status
Simulation time 145221282 ps
CPU time 3.24 seconds
Started Aug 23 03:03:52 AM UTC 24
Finished Aug 23 03:03:56 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262540535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.3262540535
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/24.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.1725025503
Short name T483
Test name
Test status
Simulation time 1683491703 ps
CPU time 28.92 seconds
Started Aug 23 03:03:49 AM UTC 24
Finished Aug 23 03:04:19 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725025503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1725025503
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/24.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random.525791513
Short name T471
Test name
Test status
Simulation time 1982565356 ps
CPU time 23.16 seconds
Started Aug 23 03:03:27 AM UTC 24
Finished Aug 23 03:03:51 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525791513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.525791513
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/24.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.3528965712
Short name T526
Test name
Test status
Simulation time 34439306298 ps
CPU time 183.74 seconds
Started Aug 23 03:03:28 AM UTC 24
Finished Aug 23 03:06:34 AM UTC 24
Peak memory 216892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528965712 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3528965712
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/24.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.599101406
Short name T72
Test name
Test status
Simulation time 5292590374 ps
CPU time 21.29 seconds
Started Aug 23 03:03:30 AM UTC 24
Finished Aug 23 03:03:53 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599101406 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.599101406
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/24.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.2358464040
Short name T469
Test name
Test status
Simulation time 370561965 ps
CPU time 19.9 seconds
Started Aug 23 03:03:27 AM UTC 24
Finished Aug 23 03:03:48 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358464040 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.2358464040
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/24.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.518311859
Short name T470
Test name
Test status
Simulation time 799822813 ps
CPU time 8.45 seconds
Started Aug 23 03:03:42 AM UTC 24
Finished Aug 23 03:03:51 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518311859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.518311859
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/24.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.1827712960
Short name T465
Test name
Test status
Simulation time 550298276 ps
CPU time 2.69 seconds
Started Aug 23 03:03:22 AM UTC 24
Finished Aug 23 03:03:26 AM UTC 24
Peak memory 217068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827712960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1827712960
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/24.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.2790795214
Short name T476
Test name
Test status
Simulation time 5544664283 ps
CPU time 30.39 seconds
Started Aug 23 03:03:25 AM UTC 24
Finished Aug 23 03:03:56 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790795214 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2790795214
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/24.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.1396925898
Short name T472
Test name
Test status
Simulation time 9576641540 ps
CPU time 24.74 seconds
Started Aug 23 03:03:26 AM UTC 24
Finished Aug 23 03:03:52 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396925898 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1396925898
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/24.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.2707199231
Short name T466
Test name
Test status
Simulation time 26972535 ps
CPU time 1.83 seconds
Started Aug 23 03:03:25 AM UTC 24
Finished Aug 23 03:03:28 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707199231 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.2707199231
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/24.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.4197399356
Short name T123
Test name
Test status
Simulation time 1180412221 ps
CPU time 18.23 seconds
Started Aug 23 03:03:54 AM UTC 24
Finished Aug 23 03:04:13 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197399356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.4197399356
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/24.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.1267660316
Short name T33
Test name
Test status
Simulation time 3246418324 ps
CPU time 107.38 seconds
Started Aug 23 03:03:54 AM UTC 24
Finished Aug 23 03:05:43 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267660316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1267660316
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/24.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.3349870859
Short name T544
Test name
Test status
Simulation time 572742834 ps
CPU time 216.98 seconds
Started Aug 23 03:03:54 AM UTC 24
Finished Aug 23 03:07:34 AM UTC 24
Peak memory 221128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349870859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.3349870859
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/24.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.1608842027
Short name T497
Test name
Test status
Simulation time 225678963 ps
CPU time 49.16 seconds
Started Aug 23 03:03:57 AM UTC 24
Finished Aug 23 03:04:48 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608842027 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.1608842027
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/24.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.448886515
Short name T480
Test name
Test status
Simulation time 78000725 ps
CPU time 8.65 seconds
Started Aug 23 03:03:52 AM UTC 24
Finished Aug 23 03:04:02 AM UTC 24
Peak memory 219136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448886515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.448886515
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/24.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.904668383
Short name T124
Test name
Test status
Simulation time 6603089178 ps
CPU time 55.81 seconds
Started Aug 23 03:04:10 AM UTC 24
Finished Aug 23 03:05:08 AM UTC 24
Peak memory 219208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904668383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.904668383
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/25.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.1360628567
Short name T638
Test name
Test status
Simulation time 53087243151 ps
CPU time 394.01 seconds
Started Aug 23 03:04:14 AM UTC 24
Finished Aug 23 03:10:52 AM UTC 24
Peak memory 222612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360628567 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.1360628567
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/25.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3943667651
Short name T498
Test name
Test status
Simulation time 1347196020 ps
CPU time 23.33 seconds
Started Aug 23 03:04:24 AM UTC 24
Finished Aug 23 03:04:49 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943667651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3943667651
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/25.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.125871720
Short name T491
Test name
Test status
Simulation time 164414653 ps
CPU time 14.87 seconds
Started Aug 23 03:04:20 AM UTC 24
Finished Aug 23 03:04:36 AM UTC 24
Peak memory 216388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125871720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.125871720
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/25.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random.2560500661
Short name T482
Test name
Test status
Simulation time 2474355785 ps
CPU time 14.3 seconds
Started Aug 23 03:04:03 AM UTC 24
Finished Aug 23 03:04:18 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560500661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.2560500661
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/25.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.2549653012
Short name T527
Test name
Test status
Simulation time 56863326519 ps
CPU time 159.8 seconds
Started Aug 23 03:04:03 AM UTC 24
Finished Aug 23 03:06:45 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549653012 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2549653012
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/25.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.199821745
Short name T488
Test name
Test status
Simulation time 4094584468 ps
CPU time 29.06 seconds
Started Aug 23 03:04:04 AM UTC 24
Finished Aug 23 03:04:34 AM UTC 24
Peak memory 216908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199821745 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.199821745
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/25.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.2789188185
Short name T203
Test name
Test status
Simulation time 109967992 ps
CPU time 5.62 seconds
Started Aug 23 03:04:03 AM UTC 24
Finished Aug 23 03:04:10 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789188185 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2789188185
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/25.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.173874262
Short name T490
Test name
Test status
Simulation time 4319620944 ps
CPU time 13.85 seconds
Started Aug 23 03:04:20 AM UTC 24
Finished Aug 23 03:04:35 AM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173874262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.173874262
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/25.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.1590498037
Short name T479
Test name
Test status
Simulation time 152053735 ps
CPU time 3.48 seconds
Started Aug 23 03:03:57 AM UTC 24
Finished Aug 23 03:04:02 AM UTC 24
Peak memory 217068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590498037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1590498037
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/25.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.505913942
Short name T492
Test name
Test status
Simulation time 21704407447 ps
CPU time 35.79 seconds
Started Aug 23 03:03:59 AM UTC 24
Finished Aug 23 03:04:36 AM UTC 24
Peak memory 217204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505913942 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.505913942
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/25.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.1867671300
Short name T486
Test name
Test status
Simulation time 4143733808 ps
CPU time 23.41 seconds
Started Aug 23 03:04:01 AM UTC 24
Finished Aug 23 03:04:26 AM UTC 24
Peak memory 216872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867671300 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1867671300
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/25.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2362933089
Short name T478
Test name
Test status
Simulation time 41810691 ps
CPU time 2.07 seconds
Started Aug 23 03:03:57 AM UTC 24
Finished Aug 23 03:04:00 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362933089 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2362933089
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/25.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.2764189525
Short name T546
Test name
Test status
Simulation time 3871554591 ps
CPU time 184.61 seconds
Started Aug 23 03:04:27 AM UTC 24
Finished Aug 23 03:07:35 AM UTC 24
Peak memory 223304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764189525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2764189525
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/25.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.3073754673
Short name T545
Test name
Test status
Simulation time 6839628977 ps
CPU time 176.33 seconds
Started Aug 23 03:04:36 AM UTC 24
Finished Aug 23 03:07:35 AM UTC 24
Peak memory 218944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073754673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3073754673
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/25.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1972952738
Short name T539
Test name
Test status
Simulation time 820851545 ps
CPU time 155.59 seconds
Started Aug 23 03:04:32 AM UTC 24
Finished Aug 23 03:07:11 AM UTC 24
Peak memory 220868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972952738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.1972952738
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/25.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.525334465
Short name T531
Test name
Test status
Simulation time 457304700 ps
CPU time 133.45 seconds
Started Aug 23 03:04:36 AM UTC 24
Finished Aug 23 03:06:51 AM UTC 24
Peak memory 222920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525334465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.525334465
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/25.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.2548297589
Short name T495
Test name
Test status
Simulation time 1355097511 ps
CPU time 21.38 seconds
Started Aug 23 03:04:21 AM UTC 24
Finished Aug 23 03:04:43 AM UTC 24
Peak memory 219136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548297589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.2548297589
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/25.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.1222650025
Short name T510
Test name
Test status
Simulation time 1536916551 ps
CPU time 42.27 seconds
Started Aug 23 03:04:50 AM UTC 24
Finished Aug 23 03:05:34 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222650025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.1222650025
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/26.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.2681004178
Short name T528
Test name
Test status
Simulation time 17207845732 ps
CPU time 116.15 seconds
Started Aug 23 03:04:50 AM UTC 24
Finished Aug 23 03:06:48 AM UTC 24
Peak memory 218952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681004178 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.2681004178
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/26.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3850316079
Short name T509
Test name
Test status
Simulation time 3685776218 ps
CPU time 21.29 seconds
Started Aug 23 03:05:04 AM UTC 24
Finished Aug 23 03:05:27 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850316079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3850316079
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/26.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.3692786480
Short name T508
Test name
Test status
Simulation time 477377386 ps
CPU time 17.04 seconds
Started Aug 23 03:05:01 AM UTC 24
Finished Aug 23 03:05:19 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692786480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3692786480
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/26.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random.3275351186
Short name T500
Test name
Test status
Simulation time 178828899 ps
CPU time 17.76 seconds
Started Aug 23 03:04:40 AM UTC 24
Finished Aug 23 03:04:59 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275351186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3275351186
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/26.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.3515064989
Short name T127
Test name
Test status
Simulation time 98417322438 ps
CPU time 182.96 seconds
Started Aug 23 03:04:48 AM UTC 24
Finished Aug 23 03:07:53 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515064989 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3515064989
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/26.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.778336114
Short name T541
Test name
Test status
Simulation time 48964688271 ps
CPU time 150 seconds
Started Aug 23 03:04:49 AM UTC 24
Finished Aug 23 03:07:21 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778336114 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.778336114
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/26.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.2333832621
Short name T496
Test name
Test status
Simulation time 19043319 ps
CPU time 1.69 seconds
Started Aug 23 03:04:45 AM UTC 24
Finished Aug 23 03:04:47 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333832621 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.2333832621
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/26.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.2468029832
Short name T502
Test name
Test status
Simulation time 189885995 ps
CPU time 3.88 seconds
Started Aug 23 03:04:59 AM UTC 24
Finished Aug 23 03:05:04 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468029832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2468029832
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/26.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.1908624905
Short name T493
Test name
Test status
Simulation time 26604375 ps
CPU time 1.96 seconds
Started Aug 23 03:04:36 AM UTC 24
Finished Aug 23 03:04:39 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908624905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1908624905
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/26.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2148759040
Short name T505
Test name
Test status
Simulation time 7245790303 ps
CPU time 32.51 seconds
Started Aug 23 03:04:37 AM UTC 24
Finished Aug 23 03:05:11 AM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148759040 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2148759040
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/26.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.1171724292
Short name T503
Test name
Test status
Simulation time 3534040134 ps
CPU time 24.92 seconds
Started Aug 23 03:04:39 AM UTC 24
Finished Aug 23 03:05:05 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171724292 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1171724292
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/26.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.339820629
Short name T494
Test name
Test status
Simulation time 40323792 ps
CPU time 1.86 seconds
Started Aug 23 03:04:37 AM UTC 24
Finished Aug 23 03:04:40 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339820629 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.339820629
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/26.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.1369458470
Short name T524
Test name
Test status
Simulation time 3089294497 ps
CPU time 78.98 seconds
Started Aug 23 03:05:05 AM UTC 24
Finished Aug 23 03:06:26 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369458470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1369458470
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/26.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.809747818
Short name T518
Test name
Test status
Simulation time 659300691 ps
CPU time 56.65 seconds
Started Aug 23 03:05:09 AM UTC 24
Finished Aug 23 03:06:07 AM UTC 24
Peak memory 219208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809747818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.809747818
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/26.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.3624105263
Short name T517
Test name
Test status
Simulation time 308344129 ps
CPU time 53.21 seconds
Started Aug 23 03:05:06 AM UTC 24
Finished Aug 23 03:06:01 AM UTC 24
Peak memory 219144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624105263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.3624105263
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/26.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.3648627973
Short name T560
Test name
Test status
Simulation time 7375820883 ps
CPU time 171.93 seconds
Started Aug 23 03:05:09 AM UTC 24
Finished Aug 23 03:08:03 AM UTC 24
Peak memory 223416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648627973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.3648627973
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/26.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.3314421055
Short name T504
Test name
Test status
Simulation time 126881208 ps
CPU time 3.33 seconds
Started Aug 23 03:05:03 AM UTC 24
Finished Aug 23 03:05:07 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314421055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3314421055
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/26.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.1022253469
Short name T209
Test name
Test status
Simulation time 4482720128 ps
CPU time 33.78 seconds
Started Aug 23 03:05:46 AM UTC 24
Finished Aug 23 03:06:21 AM UTC 24
Peak memory 218944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022253469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1022253469
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/27.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.3020622516
Short name T210
Test name
Test status
Simulation time 11658901563 ps
CPU time 49.41 seconds
Started Aug 23 03:05:47 AM UTC 24
Finished Aug 23 03:06:38 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020622516 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.3020622516
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/27.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.508074562
Short name T522
Test name
Test status
Simulation time 810430342 ps
CPU time 20.9 seconds
Started Aug 23 03:06:01 AM UTC 24
Finished Aug 23 03:06:23 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508074562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.508074562
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/27.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.3674452795
Short name T519
Test name
Test status
Simulation time 2855497450 ps
CPU time 20.18 seconds
Started Aug 23 03:05:51 AM UTC 24
Finished Aug 23 03:06:12 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674452795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3674452795
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/27.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random.3905627567
Short name T511
Test name
Test status
Simulation time 46852784 ps
CPU time 5.6 seconds
Started Aug 23 03:05:27 AM UTC 24
Finished Aug 23 03:05:34 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905627567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.3905627567
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/27.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.1451648961
Short name T604
Test name
Test status
Simulation time 96504436118 ps
CPU time 231.67 seconds
Started Aug 23 03:05:35 AM UTC 24
Finished Aug 23 03:09:29 AM UTC 24
Peak memory 218968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451648961 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1451648961
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/27.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3055754506
Short name T126
Test name
Test status
Simulation time 9138172025 ps
CPU time 43.15 seconds
Started Aug 23 03:05:44 AM UTC 24
Finished Aug 23 03:06:29 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055754506 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3055754506
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/27.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.413958264
Short name T512
Test name
Test status
Simulation time 397698124 ps
CPU time 9.17 seconds
Started Aug 23 03:05:35 AM UTC 24
Finished Aug 23 03:05:45 AM UTC 24
Peak memory 216488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413958264 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.413958264
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/27.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.510476121
Short name T516
Test name
Test status
Simulation time 631526690 ps
CPU time 9.54 seconds
Started Aug 23 03:05:49 AM UTC 24
Finished Aug 23 03:06:00 AM UTC 24
Peak memory 217024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510476121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.510476121
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/27.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.3505151272
Short name T506
Test name
Test status
Simulation time 59138705 ps
CPU time 2.04 seconds
Started Aug 23 03:05:12 AM UTC 24
Finished Aug 23 03:05:15 AM UTC 24
Peak memory 217068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505151272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3505151272
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/27.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1158312518
Short name T513
Test name
Test status
Simulation time 6884029222 ps
CPU time 25.16 seconds
Started Aug 23 03:05:20 AM UTC 24
Finished Aug 23 03:05:47 AM UTC 24
Peak memory 216660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158312518 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1158312518
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/27.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3269023676
Short name T514
Test name
Test status
Simulation time 11076932487 ps
CPU time 28.22 seconds
Started Aug 23 03:05:20 AM UTC 24
Finished Aug 23 03:05:50 AM UTC 24
Peak memory 216872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269023676 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3269023676
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/27.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.4111250397
Short name T507
Test name
Test status
Simulation time 31305039 ps
CPU time 1.74 seconds
Started Aug 23 03:05:16 AM UTC 24
Finished Aug 23 03:05:19 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111250397 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.4111250397
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/27.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.3949388801
Short name T572
Test name
Test status
Simulation time 6197367938 ps
CPU time 144.16 seconds
Started Aug 23 03:06:02 AM UTC 24
Finished Aug 23 03:08:29 AM UTC 24
Peak memory 220928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949388801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3949388801
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/27.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2230870108
Short name T542
Test name
Test status
Simulation time 936932553 ps
CPU time 78.95 seconds
Started Aug 23 03:06:08 AM UTC 24
Finished Aug 23 03:07:29 AM UTC 24
Peak memory 219144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230870108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2230870108
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/27.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.2603304610
Short name T628
Test name
Test status
Simulation time 6327457217 ps
CPU time 250.84 seconds
Started Aug 23 03:06:13 AM UTC 24
Finished Aug 23 03:10:27 AM UTC 24
Peak memory 223416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603304610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.2603304610
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/27.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.3899877507
Short name T74
Test name
Test status
Simulation time 420220660 ps
CPU time 9.64 seconds
Started Aug 23 03:05:56 AM UTC 24
Finished Aug 23 03:06:06 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899877507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3899877507
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/27.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.1214110269
Short name T534
Test name
Test status
Simulation time 1199205922 ps
CPU time 23.71 seconds
Started Aug 23 03:06:34 AM UTC 24
Finished Aug 23 03:07:00 AM UTC 24
Peak memory 219140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214110269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1214110269
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/28.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.1675852876
Short name T138
Test name
Test status
Simulation time 78691216741 ps
CPU time 324.82 seconds
Started Aug 23 03:06:36 AM UTC 24
Finished Aug 23 03:12:05 AM UTC 24
Peak memory 220500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675852876 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.1675852876
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/28.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.1835911467
Short name T536
Test name
Test status
Simulation time 708475226 ps
CPU time 10.59 seconds
Started Aug 23 03:06:49 AM UTC 24
Finished Aug 23 03:07:01 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835911467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.1835911467
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/28.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.3991927285
Short name T532
Test name
Test status
Simulation time 176997875 ps
CPU time 11.06 seconds
Started Aug 23 03:06:45 AM UTC 24
Finished Aug 23 03:06:57 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991927285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3991927285
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/28.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random.3697097275
Short name T525
Test name
Test status
Simulation time 340794893 ps
CPU time 6.97 seconds
Started Aug 23 03:06:25 AM UTC 24
Finished Aug 23 03:06:33 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697097275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.3697097275
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/28.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.2097479813
Short name T161
Test name
Test status
Simulation time 67627168697 ps
CPU time 160.35 seconds
Started Aug 23 03:06:27 AM UTC 24
Finished Aug 23 03:09:10 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097479813 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2097479813
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/28.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.642982465
Short name T548
Test name
Test status
Simulation time 9879815747 ps
CPU time 67.03 seconds
Started Aug 23 03:06:29 AM UTC 24
Finished Aug 23 03:07:38 AM UTC 24
Peak memory 217160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642982465 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.642982465
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/28.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.2117793181
Short name T530
Test name
Test status
Simulation time 173731604 ps
CPU time 22.47 seconds
Started Aug 23 03:06:27 AM UTC 24
Finished Aug 23 03:06:51 AM UTC 24
Peak memory 216960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117793181 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2117793181
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/28.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.1001091448
Short name T233
Test name
Test status
Simulation time 888421329 ps
CPU time 14.1 seconds
Started Aug 23 03:06:39 AM UTC 24
Finished Aug 23 03:06:55 AM UTC 24
Peak memory 217024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001091448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1001091448
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/28.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.20442443
Short name T520
Test name
Test status
Simulation time 283211509 ps
CPU time 3.32 seconds
Started Aug 23 03:06:17 AM UTC 24
Finished Aug 23 03:06:21 AM UTC 24
Peak memory 216752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20442443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs
/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.20442443
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/28.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.564504503
Short name T245
Test name
Test status
Simulation time 14117446830 ps
CPU time 37 seconds
Started Aug 23 03:06:22 AM UTC 24
Finished Aug 23 03:07:00 AM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564504503 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.564504503
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/28.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.2458559193
Short name T75
Test name
Test status
Simulation time 3204697264 ps
CPU time 17.92 seconds
Started Aug 23 03:06:24 AM UTC 24
Finished Aug 23 03:06:43 AM UTC 24
Peak memory 216872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458559193 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2458559193
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/28.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1761720056
Short name T521
Test name
Test status
Simulation time 126785870 ps
CPU time 1.9 seconds
Started Aug 23 03:06:22 AM UTC 24
Finished Aug 23 03:06:25 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761720056 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1761720056
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/28.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.1930967593
Short name T129
Test name
Test status
Simulation time 6132987267 ps
CPU time 158.23 seconds
Started Aug 23 03:06:51 AM UTC 24
Finished Aug 23 03:09:32 AM UTC 24
Peak memory 223040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930967593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1930967593
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/28.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3082215607
Short name T549
Test name
Test status
Simulation time 631887249 ps
CPU time 45.61 seconds
Started Aug 23 03:06:53 AM UTC 24
Finished Aug 23 03:07:40 AM UTC 24
Peak memory 218820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082215607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3082215607
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/28.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.4232810183
Short name T580
Test name
Test status
Simulation time 369294664 ps
CPU time 108.62 seconds
Started Aug 23 03:06:51 AM UTC 24
Finished Aug 23 03:08:42 AM UTC 24
Peak memory 220868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232810183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.4232810183
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/28.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.2266787148
Short name T569
Test name
Test status
Simulation time 4595134667 ps
CPU time 81.38 seconds
Started Aug 23 03:06:56 AM UTC 24
Finished Aug 23 03:08:19 AM UTC 24
Peak memory 221260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266787148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.2266787148
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/28.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.1180632247
Short name T533
Test name
Test status
Simulation time 113178210 ps
CPU time 10.58 seconds
Started Aug 23 03:06:46 AM UTC 24
Finished Aug 23 03:06:58 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180632247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1180632247
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/28.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.797907173
Short name T218
Test name
Test status
Simulation time 783456340 ps
CPU time 40.87 seconds
Started Aug 23 03:07:11 AM UTC 24
Finished Aug 23 03:07:53 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797907173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.797907173
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/29.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.884085502
Short name T137
Test name
Test status
Simulation time 2782545212 ps
CPU time 22.97 seconds
Started Aug 23 03:07:14 AM UTC 24
Finished Aug 23 03:07:38 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884085502 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.884085502
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/29.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.2855540223
Short name T554
Test name
Test status
Simulation time 1179494145 ps
CPU time 15.26 seconds
Started Aug 23 03:07:30 AM UTC 24
Finished Aug 23 03:07:47 AM UTC 24
Peak memory 216364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855540223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.2855540223
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/29.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.3551413893
Short name T547
Test name
Test status
Simulation time 1093656630 ps
CPU time 8.55 seconds
Started Aug 23 03:07:27 AM UTC 24
Finished Aug 23 03:07:37 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551413893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3551413893
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/29.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random.2453064163
Short name T540
Test name
Test status
Simulation time 453825555 ps
CPU time 10.92 seconds
Started Aug 23 03:07:01 AM UTC 24
Finished Aug 23 03:07:14 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453064163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2453064163
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/29.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.196182081
Short name T621
Test name
Test status
Simulation time 44967653052 ps
CPU time 186.69 seconds
Started Aug 23 03:07:03 AM UTC 24
Finished Aug 23 03:10:12 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196182081 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.196182081
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/29.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.4197662755
Short name T77
Test name
Test status
Simulation time 5749324230 ps
CPU time 43.53 seconds
Started Aug 23 03:07:08 AM UTC 24
Finished Aug 23 03:07:53 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197662755 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.4197662755
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/29.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.3800385292
Short name T538
Test name
Test status
Simulation time 33883585 ps
CPU time 3.91 seconds
Started Aug 23 03:07:02 AM UTC 24
Finished Aug 23 03:07:06 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800385292 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.3800385292
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/29.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.970481687
Short name T551
Test name
Test status
Simulation time 982404501 ps
CPU time 16.85 seconds
Started Aug 23 03:07:22 AM UTC 24
Finished Aug 23 03:07:40 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970481687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.970481687
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/29.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.1062828612
Short name T535
Test name
Test status
Simulation time 37714520 ps
CPU time 1.74 seconds
Started Aug 23 03:06:58 AM UTC 24
Finished Aug 23 03:07:01 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062828612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.1062828612
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/29.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.1660598327
Short name T76
Test name
Test status
Simulation time 10878321047 ps
CPU time 28.43 seconds
Started Aug 23 03:07:00 AM UTC 24
Finished Aug 23 03:07:30 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660598327 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1660598327
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/29.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.89318789
Short name T543
Test name
Test status
Simulation time 3730022168 ps
CPU time 26.81 seconds
Started Aug 23 03:07:01 AM UTC 24
Finished Aug 23 03:07:30 AM UTC 24
Peak memory 216868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89318789 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.89318789
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/29.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.310420649
Short name T537
Test name
Test status
Simulation time 152378932 ps
CPU time 2.31 seconds
Started Aug 23 03:06:59 AM UTC 24
Finished Aug 23 03:07:02 AM UTC 24
Peak memory 217068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310420649 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.310420649
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/29.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.1786143148
Short name T573
Test name
Test status
Simulation time 3011106595 ps
CPU time 56.57 seconds
Started Aug 23 03:07:31 AM UTC 24
Finished Aug 23 03:08:29 AM UTC 24
Peak memory 218944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786143148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1786143148
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/29.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1732886472
Short name T591
Test name
Test status
Simulation time 2200537580 ps
CPU time 85.35 seconds
Started Aug 23 03:07:36 AM UTC 24
Finished Aug 23 03:09:03 AM UTC 24
Peak memory 220996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732886472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1732886472
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/29.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.1606685111
Short name T589
Test name
Test status
Simulation time 183782370 ps
CPU time 78.98 seconds
Started Aug 23 03:07:35 AM UTC 24
Finished Aug 23 03:08:55 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606685111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.1606685111
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/29.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.2373677282
Short name T592
Test name
Test status
Simulation time 950789529 ps
CPU time 90.08 seconds
Started Aug 23 03:07:36 AM UTC 24
Finished Aug 23 03:09:08 AM UTC 24
Peak memory 222988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373677282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.2373677282
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/29.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.4081379719
Short name T555
Test name
Test status
Simulation time 147195603 ps
CPU time 17.29 seconds
Started Aug 23 03:07:30 AM UTC 24
Finished Aug 23 03:07:49 AM UTC 24
Peak memory 216340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081379719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.4081379719
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/29.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.2682450726
Short name T85
Test name
Test status
Simulation time 3295178582 ps
CPU time 47.45 seconds
Started Aug 23 02:44:01 AM UTC 24
Finished Aug 23 02:44:50 AM UTC 24
Peak memory 218944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682450726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2682450726
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/3.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.3524025842
Short name T207
Test name
Test status
Simulation time 11236325875 ps
CPU time 114.7 seconds
Started Aug 23 02:44:02 AM UTC 24
Finished Aug 23 02:45:59 AM UTC 24
Peak memory 216620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524025842 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.3524025842
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/3.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.220768444
Short name T156
Test name
Test status
Simulation time 50871426 ps
CPU time 9.11 seconds
Started Aug 23 02:44:14 AM UTC 24
Finished Aug 23 02:44:24 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220768444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.220768444
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/3.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.4034301049
Short name T155
Test name
Test status
Simulation time 115145178 ps
CPU time 13.22 seconds
Started Aug 23 02:44:07 AM UTC 24
Finished Aug 23 02:44:22 AM UTC 24
Peak memory 217148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034301049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.4034301049
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/3.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random.649603561
Short name T166
Test name
Test status
Simulation time 588803628 ps
CPU time 24.37 seconds
Started Aug 23 02:43:35 AM UTC 24
Finished Aug 23 02:44:01 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649603561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.649603561
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/3.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.546284281
Short name T98
Test name
Test status
Simulation time 12506083711 ps
CPU time 60.89 seconds
Started Aug 23 02:43:52 AM UTC 24
Finished Aug 23 02:44:54 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546284281 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.546284281
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/3.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.3180242447
Short name T198
Test name
Test status
Simulation time 24180871153 ps
CPU time 200.55 seconds
Started Aug 23 02:44:00 AM UTC 24
Finished Aug 23 02:47:23 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180242447 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3180242447
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/3.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.2966012120
Short name T244
Test name
Test status
Simulation time 245373145 ps
CPU time 21.57 seconds
Started Aug 23 02:43:37 AM UTC 24
Finished Aug 23 02:43:59 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966012120 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2966012120
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/3.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.1705684725
Short name T154
Test name
Test status
Simulation time 157717778 ps
CPU time 13.08 seconds
Started Aug 23 02:44:07 AM UTC 24
Finished Aug 23 02:44:21 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705684725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1705684725
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/3.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.4240351083
Short name T187
Test name
Test status
Simulation time 39625059 ps
CPU time 2.67 seconds
Started Aug 23 02:43:17 AM UTC 24
Finished Aug 23 02:43:21 AM UTC 24
Peak memory 217072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240351083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.4240351083
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/3.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3630536891
Short name T182
Test name
Test status
Simulation time 5093733082 ps
CPU time 43.01 seconds
Started Aug 23 02:43:22 AM UTC 24
Finished Aug 23 02:44:07 AM UTC 24
Peak memory 217136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630536891 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3630536891
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/3.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1229697136
Short name T181
Test name
Test status
Simulation time 21100318385 ps
CPU time 42.89 seconds
Started Aug 23 02:43:22 AM UTC 24
Finished Aug 23 02:44:06 AM UTC 24
Peak memory 217140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229697136 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1229697136
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/3.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.644647450
Short name T188
Test name
Test status
Simulation time 50201583 ps
CPU time 3.13 seconds
Started Aug 23 02:43:17 AM UTC 24
Finished Aug 23 02:43:22 AM UTC 24
Peak memory 217064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644647450 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.644647450
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/3.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.3019215425
Short name T159
Test name
Test status
Simulation time 399341836 ps
CPU time 26.42 seconds
Started Aug 23 02:44:21 AM UTC 24
Finished Aug 23 02:44:48 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019215425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3019215425
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/3.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3173915471
Short name T103
Test name
Test status
Simulation time 4729346714 ps
CPU time 55.53 seconds
Started Aug 23 02:44:22 AM UTC 24
Finished Aug 23 02:45:19 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173915471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3173915471
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/3.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.2074967805
Short name T201
Test name
Test status
Simulation time 5338445135 ps
CPU time 247.25 seconds
Started Aug 23 02:44:22 AM UTC 24
Finished Aug 23 02:48:33 AM UTC 24
Peak memory 220992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074967805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.2074967805
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/3.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.2032372231
Short name T102
Test name
Test status
Simulation time 216659759 ps
CPU time 49.95 seconds
Started Aug 23 02:44:25 AM UTC 24
Finished Aug 23 02:45:17 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032372231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.2032372231
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/3.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.2269289211
Short name T153
Test name
Test status
Simulation time 34523531 ps
CPU time 6.92 seconds
Started Aug 23 02:44:13 AM UTC 24
Finished Aug 23 02:44:20 AM UTC 24
Peak memory 217104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269289211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2269289211
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/3.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.1481096094
Short name T559
Test name
Test status
Simulation time 629306583 ps
CPU time 14.47 seconds
Started Aug 23 03:07:47 AM UTC 24
Finished Aug 23 03:08:03 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481096094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1481096094
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/30.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.779471933
Short name T568
Test name
Test status
Simulation time 2957402968 ps
CPU time 25.54 seconds
Started Aug 23 03:07:49 AM UTC 24
Finished Aug 23 03:08:16 AM UTC 24
Peak memory 217220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779471933 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.779471933
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/30.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.1168216850
Short name T562
Test name
Test status
Simulation time 51507136 ps
CPU time 1.83 seconds
Started Aug 23 03:08:01 AM UTC 24
Finished Aug 23 03:08:04 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168216850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.1168216850
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/30.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.665525516
Short name T571
Test name
Test status
Simulation time 961822797 ps
CPU time 26.31 seconds
Started Aug 23 03:07:54 AM UTC 24
Finished Aug 23 03:08:21 AM UTC 24
Peak memory 216600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665525516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.665525516
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/30.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random.2173169842
Short name T558
Test name
Test status
Simulation time 961059260 ps
CPU time 20.86 seconds
Started Aug 23 03:07:41 AM UTC 24
Finished Aug 23 03:08:03 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173169842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.2173169842
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/30.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.4099578448
Short name T577
Test name
Test status
Simulation time 26510402435 ps
CPU time 52.04 seconds
Started Aug 23 03:07:42 AM UTC 24
Finished Aug 23 03:08:35 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099578448 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.4099578448
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/30.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.4187991446
Short name T607
Test name
Test status
Simulation time 14570940698 ps
CPU time 117.72 seconds
Started Aug 23 03:07:43 AM UTC 24
Finished Aug 23 03:09:43 AM UTC 24
Peak memory 217160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187991446 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.4187991446
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/30.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.407611593
Short name T556
Test name
Test status
Simulation time 187024933 ps
CPU time 17.12 seconds
Started Aug 23 03:07:42 AM UTC 24
Finished Aug 23 03:08:00 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407611593 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.407611593
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/30.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.769980442
Short name T567
Test name
Test status
Simulation time 1506853458 ps
CPU time 20.58 seconds
Started Aug 23 03:07:54 AM UTC 24
Finished Aug 23 03:08:16 AM UTC 24
Peak memory 216648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769980442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.769980442
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/30.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.559724344
Short name T550
Test name
Test status
Simulation time 30061185 ps
CPU time 2.06 seconds
Started Aug 23 03:07:37 AM UTC 24
Finished Aug 23 03:07:40 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559724344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.559724344
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/30.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1131237254
Short name T565
Test name
Test status
Simulation time 7620748367 ps
CPU time 27.79 seconds
Started Aug 23 03:07:39 AM UTC 24
Finished Aug 23 03:08:08 AM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131237254 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1131237254
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/30.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.3183784078
Short name T557
Test name
Test status
Simulation time 2625937315 ps
CPU time 20.73 seconds
Started Aug 23 03:07:41 AM UTC 24
Finished Aug 23 03:08:03 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183784078 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3183784078
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/30.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.850267190
Short name T552
Test name
Test status
Simulation time 32188247 ps
CPU time 2.08 seconds
Started Aug 23 03:07:38 AM UTC 24
Finished Aug 23 03:07:41 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850267190 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.850267190
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/30.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.574787840
Short name T618
Test name
Test status
Simulation time 4865421428 ps
CPU time 117.62 seconds
Started Aug 23 03:08:03 AM UTC 24
Finished Aug 23 03:10:03 AM UTC 24
Peak memory 221000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574787840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.574787840
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/30.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.1717905035
Short name T575
Test name
Test status
Simulation time 561248772 ps
CPU time 26.88 seconds
Started Aug 23 03:08:03 AM UTC 24
Finished Aug 23 03:08:32 AM UTC 24
Peak memory 217096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717905035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1717905035
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/30.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.1666639550
Short name T675
Test name
Test status
Simulation time 5547074238 ps
CPU time 251.1 seconds
Started Aug 23 03:08:03 AM UTC 24
Finished Aug 23 03:12:18 AM UTC 24
Peak memory 223364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666639550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.1666639550
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/30.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.3139983009
Short name T636
Test name
Test status
Simulation time 3926196779 ps
CPU time 156.07 seconds
Started Aug 23 03:08:05 AM UTC 24
Finished Aug 23 03:10:44 AM UTC 24
Peak memory 223312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139983009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.3139983009
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/30.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.3200425984
Short name T566
Test name
Test status
Simulation time 308696217 ps
CPU time 17.83 seconds
Started Aug 23 03:07:55 AM UTC 24
Finished Aug 23 03:08:14 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200425984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.3200425984
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/30.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.3424473011
Short name T128
Test name
Test status
Simulation time 2902835164 ps
CPU time 46.76 seconds
Started Aug 23 03:08:20 AM UTC 24
Finished Aug 23 03:09:08 AM UTC 24
Peak memory 218944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424473011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3424473011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/31.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.789122986
Short name T162
Test name
Test status
Simulation time 26385920438 ps
CPU time 106.28 seconds
Started Aug 23 03:08:22 AM UTC 24
Finished Aug 23 03:10:11 AM UTC 24
Peak memory 218952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789122986 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.789122986
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/31.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.2694498253
Short name T582
Test name
Test status
Simulation time 629145080 ps
CPU time 12.04 seconds
Started Aug 23 03:08:32 AM UTC 24
Finished Aug 23 03:08:45 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694498253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2694498253
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/31.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.439713596
Short name T585
Test name
Test status
Simulation time 226714919 ps
CPU time 17.17 seconds
Started Aug 23 03:08:30 AM UTC 24
Finished Aug 23 03:08:48 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439713596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.439713596
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/31.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random.1323439752
Short name T574
Test name
Test status
Simulation time 214754018 ps
CPU time 20.4 seconds
Started Aug 23 03:08:10 AM UTC 24
Finished Aug 23 03:08:31 AM UTC 24
Peak memory 218812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323439752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.1323439752
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/31.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.3412232366
Short name T660
Test name
Test status
Simulation time 41028390343 ps
CPU time 201.17 seconds
Started Aug 23 03:08:16 AM UTC 24
Finished Aug 23 03:11:41 AM UTC 24
Peak memory 219264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412232366 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3412232366
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/31.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.3023705255
Short name T668
Test name
Test status
Simulation time 80396128251 ps
CPU time 220.91 seconds
Started Aug 23 03:08:18 AM UTC 24
Finished Aug 23 03:12:02 AM UTC 24
Peak memory 217224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023705255 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3023705255
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/31.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.2002804963
Short name T570
Test name
Test status
Simulation time 51722252 ps
CPU time 4.34 seconds
Started Aug 23 03:08:15 AM UTC 24
Finished Aug 23 03:08:21 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002804963 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.2002804963
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/31.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.904543503
Short name T576
Test name
Test status
Simulation time 210090699 ps
CPU time 11.27 seconds
Started Aug 23 03:08:22 AM UTC 24
Finished Aug 23 03:08:35 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904543503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.904543503
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/31.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.3576849307
Short name T564
Test name
Test status
Simulation time 65366194 ps
CPU time 2.06 seconds
Started Aug 23 03:08:05 AM UTC 24
Finished Aug 23 03:08:08 AM UTC 24
Peak memory 217068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576849307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3576849307
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/31.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.3462876884
Short name T578
Test name
Test status
Simulation time 6531602294 ps
CPU time 29.41 seconds
Started Aug 23 03:08:08 AM UTC 24
Finished Aug 23 03:08:39 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462876884 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3462876884
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/31.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.4075061861
Short name T579
Test name
Test status
Simulation time 7872450918 ps
CPU time 30.56 seconds
Started Aug 23 03:08:10 AM UTC 24
Finished Aug 23 03:08:42 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075061861 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.4075061861
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/31.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.4228944364
Short name T563
Test name
Test status
Simulation time 81311715 ps
CPU time 1.65 seconds
Started Aug 23 03:08:05 AM UTC 24
Finished Aug 23 03:08:08 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228944364 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.4228944364
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/31.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.926000401
Short name T593
Test name
Test status
Simulation time 1044299098 ps
CPU time 34.18 seconds
Started Aug 23 03:08:33 AM UTC 24
Finished Aug 23 03:09:09 AM UTC 24
Peak memory 218816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926000401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.926000401
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/31.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.2057502222
Short name T623
Test name
Test status
Simulation time 5365231373 ps
CPU time 99.39 seconds
Started Aug 23 03:08:37 AM UTC 24
Finished Aug 23 03:10:18 AM UTC 24
Peak memory 221000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057502222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2057502222
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/31.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3968371644
Short name T682
Test name
Test status
Simulation time 759162982 ps
CPU time 232.04 seconds
Started Aug 23 03:08:35 AM UTC 24
Finished Aug 23 03:12:31 AM UTC 24
Peak memory 220872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968371644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.3968371644
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/31.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.2580922147
Short name T666
Test name
Test status
Simulation time 4275681892 ps
CPU time 194.03 seconds
Started Aug 23 03:08:40 AM UTC 24
Finished Aug 23 03:11:57 AM UTC 24
Peak memory 223612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580922147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.2580922147
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/31.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.3102828885
Short name T581
Test name
Test status
Simulation time 375911360 ps
CPU time 12.83 seconds
Started Aug 23 03:08:31 AM UTC 24
Finished Aug 23 03:08:45 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102828885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3102828885
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/31.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.751503300
Short name T601
Test name
Test status
Simulation time 314160527 ps
CPU time 31.63 seconds
Started Aug 23 03:08:51 AM UTC 24
Finished Aug 23 03:09:24 AM UTC 24
Peak memory 218820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751503300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.751503300
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/32.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2582278517
Short name T833
Test name
Test status
Simulation time 212157057468 ps
CPU time 610.01 seconds
Started Aug 23 03:08:53 AM UTC 24
Finished Aug 23 03:19:10 AM UTC 24
Peak memory 220568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582278517 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.2582278517
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/32.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2749969801
Short name T602
Test name
Test status
Simulation time 563678824 ps
CPU time 14.93 seconds
Started Aug 23 03:09:09 AM UTC 24
Finished Aug 23 03:09:25 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749969801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2749969801
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/32.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.4100966895
Short name T594
Test name
Test status
Simulation time 239265818 ps
CPU time 11.79 seconds
Started Aug 23 03:08:58 AM UTC 24
Finished Aug 23 03:09:11 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100966895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.4100966895
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/32.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random.39480884
Short name T588
Test name
Test status
Simulation time 51566767 ps
CPU time 4.16 seconds
Started Aug 23 03:08:47 AM UTC 24
Finished Aug 23 03:08:52 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39480884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.39480884
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/32.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.2851868538
Short name T616
Test name
Test status
Simulation time 18455954391 ps
CPU time 70.53 seconds
Started Aug 23 03:08:49 AM UTC 24
Finished Aug 23 03:10:01 AM UTC 24
Peak memory 217152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851868538 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2851868538
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/32.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1611950271
Short name T165
Test name
Test status
Simulation time 104793898152 ps
CPU time 276.48 seconds
Started Aug 23 03:08:51 AM UTC 24
Finished Aug 23 03:13:31 AM UTC 24
Peak memory 218520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611950271 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1611950271
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/32.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.1146182578
Short name T590
Test name
Test status
Simulation time 446110025 ps
CPU time 8.96 seconds
Started Aug 23 03:08:47 AM UTC 24
Finished Aug 23 03:08:57 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146182578 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1146182578
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/32.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.3203668607
Short name T595
Test name
Test status
Simulation time 1271246665 ps
CPU time 17.87 seconds
Started Aug 23 03:08:57 AM UTC 24
Finished Aug 23 03:09:16 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203668607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3203668607
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/32.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.716237051
Short name T583
Test name
Test status
Simulation time 32199570 ps
CPU time 1.93 seconds
Started Aug 23 03:08:43 AM UTC 24
Finished Aug 23 03:08:46 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716237051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.716237051
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/32.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.2136959914
Short name T598
Test name
Test status
Simulation time 12666000194 ps
CPU time 32.78 seconds
Started Aug 23 03:08:46 AM UTC 24
Finished Aug 23 03:09:20 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136959914 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2136959914
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/32.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.1423421646
Short name T596
Test name
Test status
Simulation time 6530438879 ps
CPU time 29.93 seconds
Started Aug 23 03:08:47 AM UTC 24
Finished Aug 23 03:09:18 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423421646 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1423421646
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/32.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2220238320
Short name T584
Test name
Test status
Simulation time 37457880 ps
CPU time 2.24 seconds
Started Aug 23 03:08:43 AM UTC 24
Finished Aug 23 03:08:47 AM UTC 24
Peak memory 216940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220238320 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2220238320
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/32.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.279791890
Short name T620
Test name
Test status
Simulation time 680257960 ps
CPU time 60.96 seconds
Started Aug 23 03:09:09 AM UTC 24
Finished Aug 23 03:10:11 AM UTC 24
Peak memory 218816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279791890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.279791890
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/32.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.3283264849
Short name T619
Test name
Test status
Simulation time 4481492957 ps
CPU time 52.55 seconds
Started Aug 23 03:09:12 AM UTC 24
Finished Aug 23 03:10:06 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283264849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3283264849
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/32.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3001750240
Short name T651
Test name
Test status
Simulation time 477282838 ps
CPU time 132.49 seconds
Started Aug 23 03:09:10 AM UTC 24
Finished Aug 23 03:11:25 AM UTC 24
Peak memory 221188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001750240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.3001750240
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/32.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.4135932171
Short name T650
Test name
Test status
Simulation time 1780182600 ps
CPU time 128.77 seconds
Started Aug 23 03:09:12 AM UTC 24
Finished Aug 23 03:11:23 AM UTC 24
Peak memory 222984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135932171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.4135932171
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/32.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.2832475586
Short name T597
Test name
Test status
Simulation time 938537552 ps
CPU time 14.19 seconds
Started Aug 23 03:09:04 AM UTC 24
Finished Aug 23 03:09:20 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832475586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2832475586
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/32.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.222101747
Short name T611
Test name
Test status
Simulation time 1295819976 ps
CPU time 19.12 seconds
Started Aug 23 03:09:29 AM UTC 24
Finished Aug 23 03:09:49 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222101747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.222101747
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/33.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.331310387
Short name T732
Test name
Test status
Simulation time 38176164404 ps
CPU time 306.91 seconds
Started Aug 23 03:09:30 AM UTC 24
Finished Aug 23 03:14:41 AM UTC 24
Peak memory 219332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331310387 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.331310387
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/33.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.2189797967
Short name T617
Test name
Test status
Simulation time 2322503478 ps
CPU time 17.14 seconds
Started Aug 23 03:09:44 AM UTC 24
Finished Aug 23 03:10:03 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189797967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2189797967
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/33.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.27495898
Short name T608
Test name
Test status
Simulation time 72605534 ps
CPU time 5.2 seconds
Started Aug 23 03:09:38 AM UTC 24
Finished Aug 23 03:09:45 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27495898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.27495898
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/33.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random.1413149965
Short name T610
Test name
Test status
Simulation time 1286400654 ps
CPU time 25.77 seconds
Started Aug 23 03:09:22 AM UTC 24
Finished Aug 23 03:09:49 AM UTC 24
Peak memory 216960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413149965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.1413149965
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/33.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.1009174448
Short name T635
Test name
Test status
Simulation time 27222444571 ps
CPU time 73 seconds
Started Aug 23 03:09:25 AM UTC 24
Finished Aug 23 03:10:41 AM UTC 24
Peak memory 216892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009174448 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.1009174448
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/33.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.1650590921
Short name T605
Test name
Test status
Simulation time 1381605653 ps
CPU time 10.89 seconds
Started Aug 23 03:09:25 AM UTC 24
Finished Aug 23 03:09:37 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650590921 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.1650590921
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/33.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.1680568804
Short name T603
Test name
Test status
Simulation time 35433833 ps
CPU time 4.03 seconds
Started Aug 23 03:09:23 AM UTC 24
Finished Aug 23 03:09:28 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680568804 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1680568804
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/33.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.361197892
Short name T606
Test name
Test status
Simulation time 417792848 ps
CPU time 7.05 seconds
Started Aug 23 03:09:33 AM UTC 24
Finished Aug 23 03:09:41 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361197892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.361197892
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/33.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.786312173
Short name T599
Test name
Test status
Simulation time 636861560 ps
CPU time 2.72 seconds
Started Aug 23 03:09:17 AM UTC 24
Finished Aug 23 03:09:21 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786312173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.786312173
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/33.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.1053377019
Short name T609
Test name
Test status
Simulation time 7746912411 ps
CPU time 24.55 seconds
Started Aug 23 03:09:20 AM UTC 24
Finished Aug 23 03:09:46 AM UTC 24
Peak memory 217140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053377019 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1053377019
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/33.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.3027256106
Short name T613
Test name
Test status
Simulation time 9565974430 ps
CPU time 32.25 seconds
Started Aug 23 03:09:20 AM UTC 24
Finished Aug 23 03:09:54 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027256106 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3027256106
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/33.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.1474303940
Short name T600
Test name
Test status
Simulation time 38770465 ps
CPU time 1.65 seconds
Started Aug 23 03:09:19 AM UTC 24
Finished Aug 23 03:09:22 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474303940 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.1474303940
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/33.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.948951058
Short name T630
Test name
Test status
Simulation time 2189645871 ps
CPU time 43.19 seconds
Started Aug 23 03:09:45 AM UTC 24
Finished Aug 23 03:10:30 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948951058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.948951058
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/33.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.870570450
Short name T643
Test name
Test status
Simulation time 1108193707 ps
CPU time 68.56 seconds
Started Aug 23 03:09:50 AM UTC 24
Finished Aug 23 03:11:01 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870570450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.870570450
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/33.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3037433878
Short name T220
Test name
Test status
Simulation time 3172315112 ps
CPU time 435.79 seconds
Started Aug 23 03:09:47 AM UTC 24
Finished Aug 23 03:17:09 AM UTC 24
Peak memory 224856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037433878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.3037433878
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/33.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2271840740
Short name T637
Test name
Test status
Simulation time 244345631 ps
CPU time 58.52 seconds
Started Aug 23 03:09:50 AM UTC 24
Finished Aug 23 03:10:50 AM UTC 24
Peak memory 220936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271840740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.2271840740
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/33.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.462975969
Short name T612
Test name
Test status
Simulation time 153098047 ps
CPU time 5.03 seconds
Started Aug 23 03:09:43 AM UTC 24
Finished Aug 23 03:09:49 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462975969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.462975969
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/33.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.542004736
Short name T641
Test name
Test status
Simulation time 1542608965 ps
CPU time 46.42 seconds
Started Aug 23 03:10:11 AM UTC 24
Finished Aug 23 03:10:59 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542004736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.542004736
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/34.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1210548184
Short name T213
Test name
Test status
Simulation time 341383070393 ps
CPU time 728.06 seconds
Started Aug 23 03:10:12 AM UTC 24
Finished Aug 23 03:22:28 AM UTC 24
Peak memory 222872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210548184 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.1210548184
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/34.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1886160301
Short name T627
Test name
Test status
Simulation time 156205664 ps
CPU time 5.1 seconds
Started Aug 23 03:10:19 AM UTC 24
Finished Aug 23 03:10:26 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886160301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.1886160301
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/34.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.1089338116
Short name T633
Test name
Test status
Simulation time 4640751381 ps
CPU time 21.15 seconds
Started Aug 23 03:10:14 AM UTC 24
Finished Aug 23 03:10:36 AM UTC 24
Peak memory 216736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089338116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1089338116
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/34.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random.2840583335
Short name T622
Test name
Test status
Simulation time 115853991 ps
CPU time 10.35 seconds
Started Aug 23 03:10:01 AM UTC 24
Finished Aug 23 03:10:13 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840583335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.2840583335
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/34.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.72630337
Short name T676
Test name
Test status
Simulation time 97554044760 ps
CPU time 131.25 seconds
Started Aug 23 03:10:05 AM UTC 24
Finished Aug 23 03:12:18 AM UTC 24
Peak memory 217160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72630337 -assert nopostproc +UVM_TESTNAME=xbar_base_
test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.72630337
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/34.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1249177781
Short name T656
Test name
Test status
Simulation time 20510028478 ps
CPU time 89.34 seconds
Started Aug 23 03:10:07 AM UTC 24
Finished Aug 23 03:11:38 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249177781 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1249177781
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/34.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.1714633787
Short name T624
Test name
Test status
Simulation time 197002465 ps
CPU time 15.21 seconds
Started Aug 23 03:10:03 AM UTC 24
Finished Aug 23 03:10:20 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714633787 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.1714633787
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/34.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.2879693936
Short name T626
Test name
Test status
Simulation time 141533179 ps
CPU time 10.01 seconds
Started Aug 23 03:10:14 AM UTC 24
Finished Aug 23 03:10:25 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879693936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2879693936
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/34.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.3249307909
Short name T614
Test name
Test status
Simulation time 179333616 ps
CPU time 3.32 seconds
Started Aug 23 03:09:50 AM UTC 24
Finished Aug 23 03:09:55 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249307909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3249307909
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/34.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.362595972
Short name T634
Test name
Test status
Simulation time 27990432145 ps
CPU time 42.22 seconds
Started Aug 23 03:09:56 AM UTC 24
Finished Aug 23 03:10:40 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362595972 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.362595972
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/34.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.3331227510
Short name T629
Test name
Test status
Simulation time 6631913036 ps
CPU time 28.58 seconds
Started Aug 23 03:10:00 AM UTC 24
Finished Aug 23 03:10:30 AM UTC 24
Peak memory 217132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331227510 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3331227510
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/34.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.837631591
Short name T615
Test name
Test status
Simulation time 24439350 ps
CPU time 1.75 seconds
Started Aug 23 03:09:56 AM UTC 24
Finished Aug 23 03:09:59 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837631591 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.837631591
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/34.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.4127233194
Short name T684
Test name
Test status
Simulation time 4716175499 ps
CPU time 133.47 seconds
Started Aug 23 03:10:21 AM UTC 24
Finished Aug 23 03:12:36 AM UTC 24
Peak memory 220928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127233194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.4127233194
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/34.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3932062227
Short name T677
Test name
Test status
Simulation time 4866473973 ps
CPU time 111.36 seconds
Started Aug 23 03:10:26 AM UTC 24
Finished Aug 23 03:12:20 AM UTC 24
Peak memory 218656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932062227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3932062227
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/34.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3087513887
Short name T204
Test name
Test status
Simulation time 174874423 ps
CPU time 72.26 seconds
Started Aug 23 03:10:26 AM UTC 24
Finished Aug 23 03:11:41 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087513887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.3087513887
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/34.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1188601826
Short name T683
Test name
Test status
Simulation time 590793681 ps
CPU time 122.9 seconds
Started Aug 23 03:10:26 AM UTC 24
Finished Aug 23 03:12:32 AM UTC 24
Peak memory 222756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188601826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.1188601826
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/34.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.222373947
Short name T625
Test name
Test status
Simulation time 117466259 ps
CPU time 8.47 seconds
Started Aug 23 03:10:15 AM UTC 24
Finished Aug 23 03:10:25 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222373947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.222373947
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/34.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.2768673321
Short name T163
Test name
Test status
Simulation time 645241384 ps
CPU time 25.25 seconds
Started Aug 23 03:10:45 AM UTC 24
Finished Aug 23 03:11:11 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768673321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.2768673321
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/35.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.239242726
Short name T852
Test name
Test status
Simulation time 110148972857 ps
CPU time 544.57 seconds
Started Aug 23 03:10:51 AM UTC 24
Finished Aug 23 03:20:01 AM UTC 24
Peak memory 220500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239242726 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.239242726
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/35.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1431784670
Short name T646
Test name
Test status
Simulation time 454130735 ps
CPU time 7.68 seconds
Started Aug 23 03:11:01 AM UTC 24
Finished Aug 23 03:11:09 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431784670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1431784670
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/35.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.3047067030
Short name T652
Test name
Test status
Simulation time 1211682963 ps
CPU time 26.23 seconds
Started Aug 23 03:10:58 AM UTC 24
Finished Aug 23 03:11:25 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047067030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3047067030
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/35.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random.891057221
Short name T640
Test name
Test status
Simulation time 763390124 ps
CPU time 22.08 seconds
Started Aug 23 03:10:35 AM UTC 24
Finished Aug 23 03:10:58 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891057221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.891057221
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/35.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.732890686
Short name T715
Test name
Test status
Simulation time 66671477321 ps
CPU time 186.63 seconds
Started Aug 23 03:10:40 AM UTC 24
Finished Aug 23 03:13:49 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732890686 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.732890686
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/35.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3614324676
Short name T689
Test name
Test status
Simulation time 16514258013 ps
CPU time 127.11 seconds
Started Aug 23 03:10:42 AM UTC 24
Finished Aug 23 03:12:51 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614324676 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3614324676
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/35.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.1486160082
Short name T642
Test name
Test status
Simulation time 309871626 ps
CPU time 21.1 seconds
Started Aug 23 03:10:37 AM UTC 24
Finished Aug 23 03:10:59 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486160082 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1486160082
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/35.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.712923311
Short name T639
Test name
Test status
Simulation time 225015337 ps
CPU time 3.32 seconds
Started Aug 23 03:10:53 AM UTC 24
Finished Aug 23 03:10:57 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712923311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.712923311
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/35.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.3318566760
Short name T631
Test name
Test status
Simulation time 165963782 ps
CPU time 3.07 seconds
Started Aug 23 03:10:28 AM UTC 24
Finished Aug 23 03:10:32 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318566760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3318566760
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/35.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.2040746436
Short name T78
Test name
Test status
Simulation time 6036628951 ps
CPU time 29.02 seconds
Started Aug 23 03:10:31 AM UTC 24
Finished Aug 23 03:11:02 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040746436 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2040746436
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/35.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.2716697512
Short name T644
Test name
Test status
Simulation time 4028579636 ps
CPU time 28.54 seconds
Started Aug 23 03:10:33 AM UTC 24
Finished Aug 23 03:11:03 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716697512 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2716697512
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/35.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.563019978
Short name T632
Test name
Test status
Simulation time 113230867 ps
CPU time 1.92 seconds
Started Aug 23 03:10:31 AM UTC 24
Finished Aug 23 03:10:34 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563019978 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.563019978
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/35.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.2740750944
Short name T649
Test name
Test status
Simulation time 177962106 ps
CPU time 13.23 seconds
Started Aug 23 03:11:01 AM UTC 24
Finished Aug 23 03:11:15 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740750944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2740750944
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/35.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2497126087
Short name T687
Test name
Test status
Simulation time 9999655698 ps
CPU time 99.55 seconds
Started Aug 23 03:11:03 AM UTC 24
Finished Aug 23 03:12:45 AM UTC 24
Peak memory 218952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497126087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2497126087
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/35.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.2946723205
Short name T698
Test name
Test status
Simulation time 145896316 ps
CPU time 121.6 seconds
Started Aug 23 03:11:02 AM UTC 24
Finished Aug 23 03:13:06 AM UTC 24
Peak memory 221192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946723205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.2946723205
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/35.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3842789836
Short name T739
Test name
Test status
Simulation time 3991667676 ps
CPU time 231.74 seconds
Started Aug 23 03:11:03 AM UTC 24
Finished Aug 23 03:14:58 AM UTC 24
Peak memory 223348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842789836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.3842789836
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/35.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.2048183602
Short name T645
Test name
Test status
Simulation time 252359948 ps
CPU time 8.11 seconds
Started Aug 23 03:10:59 AM UTC 24
Finished Aug 23 03:11:08 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048183602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2048183602
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/35.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.3631010082
Short name T657
Test name
Test status
Simulation time 186695776 ps
CPU time 10.1 seconds
Started Aug 23 03:11:27 AM UTC 24
Finished Aug 23 03:11:38 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631010082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.3631010082
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/36.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3206472888
Short name T140
Test name
Test status
Simulation time 108415025332 ps
CPU time 257.98 seconds
Started Aug 23 03:11:29 AM UTC 24
Finished Aug 23 03:15:50 AM UTC 24
Peak memory 218952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206472888 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.3206472888
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/36.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.4264512072
Short name T665
Test name
Test status
Simulation time 537247982 ps
CPU time 8.54 seconds
Started Aug 23 03:11:39 AM UTC 24
Finished Aug 23 03:11:49 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264512072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.4264512072
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/36.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.3560322450
Short name T667
Test name
Test status
Simulation time 961978170 ps
CPU time 18.93 seconds
Started Aug 23 03:11:37 AM UTC 24
Finished Aug 23 03:11:58 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560322450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.3560322450
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/36.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random.3233979156
Short name T249
Test name
Test status
Simulation time 916743473 ps
CPU time 25.81 seconds
Started Aug 23 03:11:14 AM UTC 24
Finished Aug 23 03:11:41 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233979156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.3233979156
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/36.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.2848336396
Short name T721
Test name
Test status
Simulation time 41370193730 ps
CPU time 171.05 seconds
Started Aug 23 03:11:23 AM UTC 24
Finished Aug 23 03:14:17 AM UTC 24
Peak memory 217152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848336396 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2848336396
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/36.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.1906162344
Short name T655
Test name
Test status
Simulation time 2508459046 ps
CPU time 8.95 seconds
Started Aug 23 03:11:27 AM UTC 24
Finished Aug 23 03:11:37 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906162344 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1906162344
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/36.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.3598877199
Short name T653
Test name
Test status
Simulation time 283854444 ps
CPU time 10.93 seconds
Started Aug 23 03:11:16 AM UTC 24
Finished Aug 23 03:11:28 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598877199 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.3598877199
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/36.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.673396220
Short name T658
Test name
Test status
Simulation time 50475925 ps
CPU time 3.55 seconds
Started Aug 23 03:11:34 AM UTC 24
Finished Aug 23 03:11:39 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673396220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.673396220
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/36.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.3048259791
Short name T647
Test name
Test status
Simulation time 25788951 ps
CPU time 1.94 seconds
Started Aug 23 03:11:10 AM UTC 24
Finished Aug 23 03:11:13 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048259791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3048259791
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/36.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2940011376
Short name T661
Test name
Test status
Simulation time 5727335149 ps
CPU time 27.53 seconds
Started Aug 23 03:11:12 AM UTC 24
Finished Aug 23 03:11:41 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940011376 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2940011376
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/36.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.2513103665
Short name T654
Test name
Test status
Simulation time 2833868997 ps
CPU time 19 seconds
Started Aug 23 03:11:14 AM UTC 24
Finished Aug 23 03:11:34 AM UTC 24
Peak memory 217132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513103665 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2513103665
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/36.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1202903520
Short name T648
Test name
Test status
Simulation time 155369998 ps
CPU time 2.04 seconds
Started Aug 23 03:11:10 AM UTC 24
Finished Aug 23 03:11:13 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202903520 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1202903520
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/36.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.1424693087
Short name T703
Test name
Test status
Simulation time 1241070161 ps
CPU time 85.25 seconds
Started Aug 23 03:11:40 AM UTC 24
Finished Aug 23 03:13:08 AM UTC 24
Peak memory 221192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424693087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1424693087
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/36.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.4179312039
Short name T735
Test name
Test status
Simulation time 1041206245 ps
CPU time 188.31 seconds
Started Aug 23 03:11:42 AM UTC 24
Finished Aug 23 03:14:54 AM UTC 24
Peak memory 220372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179312039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.4179312039
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/36.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.1144957051
Short name T709
Test name
Test status
Simulation time 502457957 ps
CPU time 113.53 seconds
Started Aug 23 03:11:42 AM UTC 24
Finished Aug 23 03:13:38 AM UTC 24
Peak memory 222428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144957051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.1144957051
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/36.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.161335364
Short name T662
Test name
Test status
Simulation time 82460710 ps
CPU time 1.72 seconds
Started Aug 23 03:11:39 AM UTC 24
Finished Aug 23 03:11:42 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161335364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.161335364
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/36.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.949219030
Short name T671
Test name
Test status
Simulation time 25145634 ps
CPU time 3.55 seconds
Started Aug 23 03:12:05 AM UTC 24
Finished Aug 23 03:12:10 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949219030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.949219030
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/37.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.2380293304
Short name T701
Test name
Test status
Simulation time 12734616592 ps
CPU time 58.74 seconds
Started Aug 23 03:12:06 AM UTC 24
Finished Aug 23 03:13:07 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380293304 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.2380293304
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/37.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2314290154
Short name T685
Test name
Test status
Simulation time 838600313 ps
CPU time 22.23 seconds
Started Aug 23 03:12:14 AM UTC 24
Finished Aug 23 03:12:38 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314290154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2314290154
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/37.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.2405988600
Short name T678
Test name
Test status
Simulation time 167702728 ps
CPU time 11.65 seconds
Started Aug 23 03:12:11 AM UTC 24
Finished Aug 23 03:12:24 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405988600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2405988600
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/37.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random.3295900182
Short name T669
Test name
Test status
Simulation time 394248263 ps
CPU time 12.77 seconds
Started Aug 23 03:11:50 AM UTC 24
Finished Aug 23 03:12:04 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295900182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.3295900182
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/37.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.2856663
Short name T767
Test name
Test status
Simulation time 122591156719 ps
CPU time 243.06 seconds
Started Aug 23 03:11:59 AM UTC 24
Finished Aug 23 03:16:05 AM UTC 24
Peak memory 217220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856663 -assert nopostproc +UVM_TESTNAME=xbar_base_t
est +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2856663
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/37.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1924172852
Short name T744
Test name
Test status
Simulation time 22057068891 ps
CPU time 184.96 seconds
Started Aug 23 03:12:03 AM UTC 24
Finished Aug 23 03:15:11 AM UTC 24
Peak memory 219212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924172852 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1924172852
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/37.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.2602634018
Short name T670
Test name
Test status
Simulation time 164584762 ps
CPU time 10.41 seconds
Started Aug 23 03:11:57 AM UTC 24
Finished Aug 23 03:12:09 AM UTC 24
Peak memory 217020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602634018 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2602634018
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/37.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.1017138070
Short name T673
Test name
Test status
Simulation time 113547100 ps
CPU time 2.8 seconds
Started Aug 23 03:12:10 AM UTC 24
Finished Aug 23 03:12:14 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017138070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.1017138070
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/37.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.2348045704
Short name T663
Test name
Test status
Simulation time 29287323 ps
CPU time 1.89 seconds
Started Aug 23 03:11:42 AM UTC 24
Finished Aug 23 03:11:45 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348045704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2348045704
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/37.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3506037094
Short name T674
Test name
Test status
Simulation time 6111148474 ps
CPU time 28.16 seconds
Started Aug 23 03:11:47 AM UTC 24
Finished Aug 23 03:12:16 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506037094 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3506037094
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/37.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.1600010451
Short name T672
Test name
Test status
Simulation time 5654898528 ps
CPU time 25.4 seconds
Started Aug 23 03:11:47 AM UTC 24
Finished Aug 23 03:12:13 AM UTC 24
Peak memory 216872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600010451 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1600010451
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/37.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.1991551444
Short name T664
Test name
Test status
Simulation time 67664297 ps
CPU time 2.05 seconds
Started Aug 23 03:11:42 AM UTC 24
Finished Aug 23 03:11:46 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991551444 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.1991551444
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/37.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.2379804338
Short name T704
Test name
Test status
Simulation time 2325452130 ps
CPU time 50.17 seconds
Started Aug 23 03:12:17 AM UTC 24
Finished Aug 23 03:13:08 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379804338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2379804338
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/37.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1885824626
Short name T738
Test name
Test status
Simulation time 8473982399 ps
CPU time 156.27 seconds
Started Aug 23 03:12:19 AM UTC 24
Finished Aug 23 03:14:58 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885824626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1885824626
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/37.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.1318020819
Short name T786
Test name
Test status
Simulation time 1471308531 ps
CPU time 258.05 seconds
Started Aug 23 03:12:19 AM UTC 24
Finished Aug 23 03:16:41 AM UTC 24
Peak memory 223044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318020819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.1318020819
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/37.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.2620050469
Short name T691
Test name
Test status
Simulation time 169853529 ps
CPU time 33.47 seconds
Started Aug 23 03:12:21 AM UTC 24
Finished Aug 23 03:12:55 AM UTC 24
Peak memory 219144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620050469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.2620050469
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/37.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.2157523254
Short name T679
Test name
Test status
Simulation time 93179532 ps
CPU time 10.41 seconds
Started Aug 23 03:12:14 AM UTC 24
Finished Aug 23 03:12:26 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157523254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2157523254
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/37.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.3802475303
Short name T693
Test name
Test status
Simulation time 1081673756 ps
CPU time 16.66 seconds
Started Aug 23 03:12:39 AM UTC 24
Finished Aug 23 03:12:57 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802475303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.3802475303
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/38.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1656193452
Short name T841
Test name
Test status
Simulation time 56807849145 ps
CPU time 405.76 seconds
Started Aug 23 03:12:45 AM UTC 24
Finished Aug 23 03:19:36 AM UTC 24
Peak memory 222548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656193452 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.1656193452
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/38.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.2182355282
Short name T697
Test name
Test status
Simulation time 159375198 ps
CPU time 4.95 seconds
Started Aug 23 03:12:57 AM UTC 24
Finished Aug 23 03:13:03 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182355282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.2182355282
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/38.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.2921323794
Short name T705
Test name
Test status
Simulation time 894417365 ps
CPU time 15.48 seconds
Started Aug 23 03:12:52 AM UTC 24
Finished Aug 23 03:13:09 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921323794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2921323794
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/38.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random.1076225221
Short name T688
Test name
Test status
Simulation time 588220138 ps
CPU time 15.33 seconds
Started Aug 23 03:12:32 AM UTC 24
Finished Aug 23 03:12:49 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076225221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.1076225221
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/38.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.616296723
Short name T690
Test name
Test status
Simulation time 3397526079 ps
CPU time 12.42 seconds
Started Aug 23 03:12:38 AM UTC 24
Finished Aug 23 03:12:51 AM UTC 24
Peak memory 217152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616296723 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.616296723
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/38.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.1863363139
Short name T754
Test name
Test status
Simulation time 24462259451 ps
CPU time 170.15 seconds
Started Aug 23 03:12:39 AM UTC 24
Finished Aug 23 03:15:32 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863363139 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1863363139
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/38.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.1794838501
Short name T686
Test name
Test status
Simulation time 47049454 ps
CPU time 5 seconds
Started Aug 23 03:12:32 AM UTC 24
Finished Aug 23 03:12:38 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794838501 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1794838501
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/38.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.1506530783
Short name T696
Test name
Test status
Simulation time 1038838571 ps
CPU time 11.12 seconds
Started Aug 23 03:12:50 AM UTC 24
Finished Aug 23 03:13:02 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506530783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1506530783
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/38.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.2233944375
Short name T680
Test name
Test status
Simulation time 36082869 ps
CPU time 1.73 seconds
Started Aug 23 03:12:25 AM UTC 24
Finished Aug 23 03:12:28 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233944375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2233944375
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/38.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.1806360502
Short name T692
Test name
Test status
Simulation time 6201527746 ps
CPU time 26.53 seconds
Started Aug 23 03:12:28 AM UTC 24
Finished Aug 23 03:12:56 AM UTC 24
Peak memory 217204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806360502 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.1806360502
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/38.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1963004486
Short name T694
Test name
Test status
Simulation time 9149698278 ps
CPU time 27.46 seconds
Started Aug 23 03:12:31 AM UTC 24
Finished Aug 23 03:12:59 AM UTC 24
Peak memory 217132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963004486 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1963004486
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/38.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.3135293278
Short name T681
Test name
Test status
Simulation time 27706120 ps
CPU time 1.91 seconds
Started Aug 23 03:12:27 AM UTC 24
Finished Aug 23 03:12:30 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135293278 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.3135293278
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/38.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.2774452733
Short name T700
Test name
Test status
Simulation time 387816313 ps
CPU time 8.76 seconds
Started Aug 23 03:12:57 AM UTC 24
Finished Aug 23 03:13:07 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774452733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2774452733
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/38.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2740418299
Short name T766
Test name
Test status
Simulation time 13573000595 ps
CPU time 177.5 seconds
Started Aug 23 03:13:00 AM UTC 24
Finished Aug 23 03:16:00 AM UTC 24
Peak memory 223048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740418299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2740418299
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/38.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.128408365
Short name T790
Test name
Test status
Simulation time 1191505699 ps
CPU time 245.06 seconds
Started Aug 23 03:12:58 AM UTC 24
Finished Aug 23 03:17:06 AM UTC 24
Peak memory 222912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128408365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.128408365
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/38.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.72185210
Short name T774
Test name
Test status
Simulation time 927169302 ps
CPU time 195.01 seconds
Started Aug 23 03:13:01 AM UTC 24
Finished Aug 23 03:16:19 AM UTC 24
Peak memory 223352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72185210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.72185210
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/38.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.3940130980
Short name T695
Test name
Test status
Simulation time 54452926 ps
CPU time 6.97 seconds
Started Aug 23 03:12:52 AM UTC 24
Finished Aug 23 03:13:00 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940130980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3940130980
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/38.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.1061975727
Short name T720
Test name
Test status
Simulation time 6267957366 ps
CPU time 57.57 seconds
Started Aug 23 03:13:10 AM UTC 24
Finished Aug 23 03:14:09 AM UTC 24
Peak memory 219204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061975727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.1061975727
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/39.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3527551485
Short name T857
Test name
Test status
Simulation time 135711040555 ps
CPU time 434.14 seconds
Started Aug 23 03:13:10 AM UTC 24
Finished Aug 23 03:20:29 AM UTC 24
Peak memory 222612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527551485 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.3527551485
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/39.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.740011994
Short name T713
Test name
Test status
Simulation time 130726524 ps
CPU time 5.56 seconds
Started Aug 23 03:13:37 AM UTC 24
Finished Aug 23 03:13:44 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740011994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.740011994
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/39.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.1150024568
Short name T711
Test name
Test status
Simulation time 247211904 ps
CPU time 7.11 seconds
Started Aug 23 03:13:33 AM UTC 24
Finished Aug 23 03:13:41 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150024568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1150024568
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/39.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random.1554281996
Short name T710
Test name
Test status
Simulation time 1007534112 ps
CPU time 29.36 seconds
Started Aug 23 03:13:08 AM UTC 24
Finished Aug 23 03:13:39 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554281996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1554281996
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/39.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.2322669492
Short name T741
Test name
Test status
Simulation time 36746405636 ps
CPU time 117.39 seconds
Started Aug 23 03:13:08 AM UTC 24
Finished Aug 23 03:15:08 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322669492 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2322669492
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/39.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.3421054392
Short name T719
Test name
Test status
Simulation time 26331188945 ps
CPU time 56.97 seconds
Started Aug 23 03:13:10 AM UTC 24
Finished Aug 23 03:14:08 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421054392 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3421054392
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/39.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.2664497446
Short name T706
Test name
Test status
Simulation time 507551305 ps
CPU time 18.73 seconds
Started Aug 23 03:13:08 AM UTC 24
Finished Aug 23 03:13:28 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664497446 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.2664497446
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/39.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.3428292663
Short name T712
Test name
Test status
Simulation time 744900772 ps
CPU time 11.05 seconds
Started Aug 23 03:13:29 AM UTC 24
Finished Aug 23 03:13:42 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428292663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3428292663
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/39.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.11990827
Short name T699
Test name
Test status
Simulation time 201242366 ps
CPU time 2.71 seconds
Started Aug 23 03:13:03 AM UTC 24
Finished Aug 23 03:13:06 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11990827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs
/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.11990827
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/39.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.642903441
Short name T708
Test name
Test status
Simulation time 7459918757 ps
CPU time 28.46 seconds
Started Aug 23 03:13:06 AM UTC 24
Finished Aug 23 03:13:36 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642903441 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.642903441
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/39.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.2380887046
Short name T707
Test name
Test status
Simulation time 8744338960 ps
CPU time 21.71 seconds
Started Aug 23 03:13:08 AM UTC 24
Finished Aug 23 03:13:31 AM UTC 24
Peak memory 216872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380887046 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2380887046
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/39.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2672687178
Short name T702
Test name
Test status
Simulation time 51198817 ps
CPU time 2.19 seconds
Started Aug 23 03:13:04 AM UTC 24
Finished Aug 23 03:13:07 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672687178 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2672687178
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/39.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.3049530810
Short name T734
Test name
Test status
Simulation time 4591278799 ps
CPU time 70.09 seconds
Started Aug 23 03:13:39 AM UTC 24
Finished Aug 23 03:14:51 AM UTC 24
Peak memory 220928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049530810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3049530810
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/39.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.158327025
Short name T742
Test name
Test status
Simulation time 9913527813 ps
CPU time 83.78 seconds
Started Aug 23 03:13:43 AM UTC 24
Finished Aug 23 03:15:09 AM UTC 24
Peak memory 221000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158327025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.158327025
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/39.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.3327252828
Short name T716
Test name
Test status
Simulation time 86518106 ps
CPU time 12.03 seconds
Started Aug 23 03:13:39 AM UTC 24
Finished Aug 23 03:13:53 AM UTC 24
Peak memory 218816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327252828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.3327252828
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/39.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2191324897
Short name T723
Test name
Test status
Simulation time 25366892 ps
CPU time 39.45 seconds
Started Aug 23 03:13:43 AM UTC 24
Finished Aug 23 03:14:24 AM UTC 24
Peak memory 219208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191324897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.2191324897
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/39.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.2676505681
Short name T205
Test name
Test status
Simulation time 168033596 ps
CPU time 17.11 seconds
Started Aug 23 03:13:33 AM UTC 24
Finished Aug 23 03:13:52 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676505681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2676505681
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/39.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.4259834683
Short name T87
Test name
Test status
Simulation time 5832788012 ps
CPU time 62.77 seconds
Started Aug 23 02:45:11 AM UTC 24
Finished Aug 23 02:46:16 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259834683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.4259834683
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/4.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3963454906
Short name T89
Test name
Test status
Simulation time 26958125604 ps
CPU time 155.87 seconds
Started Aug 23 02:45:16 AM UTC 24
Finished Aug 23 02:47:54 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963454906 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.3963454906
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/4.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3837511628
Short name T267
Test name
Test status
Simulation time 137740307 ps
CPU time 11.93 seconds
Started Aug 23 02:45:27 AM UTC 24
Finished Aug 23 02:45:40 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837511628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3837511628
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/4.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.3904272750
Short name T269
Test name
Test status
Simulation time 2222984300 ps
CPU time 36.07 seconds
Started Aug 23 02:45:19 AM UTC 24
Finished Aug 23 02:45:56 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904272750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3904272750
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/4.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random.2944623412
Short name T99
Test name
Test status
Simulation time 106866389 ps
CPU time 18.39 seconds
Started Aug 23 02:44:51 AM UTC 24
Finished Aug 23 02:45:11 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944623412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.2944623412
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/4.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.101789205
Short name T274
Test name
Test status
Simulation time 34694405381 ps
CPU time 150.88 seconds
Started Aug 23 02:45:10 AM UTC 24
Finished Aug 23 02:47:44 AM UTC 24
Peak memory 216864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101789205 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.101789205
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/4.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.2372047989
Short name T191
Test name
Test status
Simulation time 8565481445 ps
CPU time 90.09 seconds
Started Aug 23 02:45:11 AM UTC 24
Finished Aug 23 02:46:43 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372047989 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2372047989
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/4.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.4215666966
Short name T101
Test name
Test status
Simulation time 344646578 ps
CPU time 18.11 seconds
Started Aug 23 02:44:55 AM UTC 24
Finished Aug 23 02:45:14 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215666966 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.4215666966
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/4.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.1177827178
Short name T168
Test name
Test status
Simulation time 871849333 ps
CPU time 23.6 seconds
Started Aug 23 02:45:18 AM UTC 24
Finished Aug 23 02:45:43 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177827178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1177827178
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/4.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.930542231
Short name T157
Test name
Test status
Simulation time 119624066 ps
CPU time 4.4 seconds
Started Aug 23 02:44:30 AM UTC 24
Finished Aug 23 02:44:36 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930542231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.930542231
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/4.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2677373737
Short name T105
Test name
Test status
Simulation time 16732447706 ps
CPU time 43.56 seconds
Started Aug 23 02:44:41 AM UTC 24
Finished Aug 23 02:45:26 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677373737 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2677373737
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/4.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2839235872
Short name T106
Test name
Test status
Simulation time 7330622279 ps
CPU time 36.08 seconds
Started Aug 23 02:44:50 AM UTC 24
Finished Aug 23 02:45:27 AM UTC 24
Peak memory 217132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839235872 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2839235872
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/4.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2669271262
Short name T158
Test name
Test status
Simulation time 81328508 ps
CPU time 2.2 seconds
Started Aug 23 02:44:37 AM UTC 24
Finished Aug 23 02:44:40 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669271262 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2669271262
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/4.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.858523194
Short name T260
Test name
Test status
Simulation time 720209583 ps
CPU time 60.36 seconds
Started Aug 23 02:45:38 AM UTC 24
Finished Aug 23 02:46:40 AM UTC 24
Peak memory 218816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858523194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.858523194
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/4.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.671578697
Short name T92
Test name
Test status
Simulation time 8733248895 ps
CPU time 240.21 seconds
Started Aug 23 02:45:28 AM UTC 24
Finished Aug 23 02:49:32 AM UTC 24
Peak memory 223048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671578697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.671578697
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/4.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.1280650438
Short name T42
Test name
Test status
Simulation time 5388740110 ps
CPU time 114.45 seconds
Started Aug 23 02:45:41 AM UTC 24
Finished Aug 23 02:47:38 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280650438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.1280650438
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/4.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.4002791511
Short name T268
Test name
Test status
Simulation time 511234617 ps
CPU time 25.11 seconds
Started Aug 23 02:45:20 AM UTC 24
Finished Aug 23 02:45:46 AM UTC 24
Peak memory 218820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002791511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.4002791511
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/4.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.597100391
Short name T724
Test name
Test status
Simulation time 2545007891 ps
CPU time 13.71 seconds
Started Aug 23 03:14:10 AM UTC 24
Finished Aug 23 03:14:25 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597100391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.597100391
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/40.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.2432408177
Short name T211
Test name
Test status
Simulation time 181255021974 ps
CPU time 544.85 seconds
Started Aug 23 03:14:18 AM UTC 24
Finished Aug 23 03:23:28 AM UTC 24
Peak memory 220760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432408177 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.2432408177
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/40.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.2402266057
Short name T727
Test name
Test status
Simulation time 16712667 ps
CPU time 1.39 seconds
Started Aug 23 03:14:25 AM UTC 24
Finished Aug 23 03:14:27 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402266057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.2402266057
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/40.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.218797983
Short name T731
Test name
Test status
Simulation time 239187821 ps
CPU time 15.89 seconds
Started Aug 23 03:14:20 AM UTC 24
Finished Aug 23 03:14:37 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218797983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.218797983
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/40.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random.4019210801
Short name T206
Test name
Test status
Simulation time 737883407 ps
CPU time 23.92 seconds
Started Aug 23 03:13:53 AM UTC 24
Finished Aug 23 03:14:19 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019210801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.4019210801
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/40.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.2423815417
Short name T743
Test name
Test status
Simulation time 35321413124 ps
CPU time 68.18 seconds
Started Aug 23 03:14:00 AM UTC 24
Finished Aug 23 03:15:10 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423815417 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2423815417
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/40.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.991486586
Short name T722
Test name
Test status
Simulation time 1428391989 ps
CPU time 11.6 seconds
Started Aug 23 03:14:09 AM UTC 24
Finished Aug 23 03:14:22 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991486586 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.991486586
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/40.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.3799431855
Short name T718
Test name
Test status
Simulation time 61472692 ps
CPU time 4.61 seconds
Started Aug 23 03:13:54 AM UTC 24
Finished Aug 23 03:13:59 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799431855 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.3799431855
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/40.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.419168947
Short name T659
Test name
Test status
Simulation time 257266545 ps
CPU time 5.83 seconds
Started Aug 23 03:14:20 AM UTC 24
Finished Aug 23 03:14:27 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419168947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.419168947
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/40.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.1454223966
Short name T714
Test name
Test status
Simulation time 59775563 ps
CPU time 2.24 seconds
Started Aug 23 03:13:45 AM UTC 24
Finished Aug 23 03:13:48 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454223966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1454223966
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/40.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.1119905122
Short name T726
Test name
Test status
Simulation time 13874709164 ps
CPU time 34.62 seconds
Started Aug 23 03:13:51 AM UTC 24
Finished Aug 23 03:14:27 AM UTC 24
Peak memory 216948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119905122 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1119905122
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/40.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.2496670092
Short name T725
Test name
Test status
Simulation time 8879653390 ps
CPU time 33.11 seconds
Started Aug 23 03:13:52 AM UTC 24
Finished Aug 23 03:14:26 AM UTC 24
Peak memory 217132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496670092 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2496670092
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/40.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1613997293
Short name T717
Test name
Test status
Simulation time 51515696 ps
CPU time 2.21 seconds
Started Aug 23 03:13:49 AM UTC 24
Finished Aug 23 03:13:53 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613997293 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1613997293
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/40.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.2288402994
Short name T792
Test name
Test status
Simulation time 7993469555 ps
CPU time 162.44 seconds
Started Aug 23 03:14:26 AM UTC 24
Finished Aug 23 03:17:11 AM UTC 24
Peak memory 223108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288402994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2288402994
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/40.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.1843397571
Short name T751
Test name
Test status
Simulation time 550545554 ps
CPU time 55.94 seconds
Started Aug 23 03:14:28 AM UTC 24
Finished Aug 23 03:15:26 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843397571 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1843397571
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/40.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.4037972763
Short name T829
Test name
Test status
Simulation time 2011580931 ps
CPU time 271.7 seconds
Started Aug 23 03:14:28 AM UTC 24
Finished Aug 23 03:19:03 AM UTC 24
Peak memory 222920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037972763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.4037972763
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/40.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3389018089
Short name T41
Test name
Test status
Simulation time 14876209238 ps
CPU time 425.99 seconds
Started Aug 23 03:14:28 AM UTC 24
Finished Aug 23 03:21:39 AM UTC 24
Peak memory 235208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389018089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.3389018089
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/40.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.3742707059
Short name T729
Test name
Test status
Simulation time 104604162 ps
CPU time 8.73 seconds
Started Aug 23 03:14:22 AM UTC 24
Finished Aug 23 03:14:32 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742707059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3742707059
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/40.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.761506985
Short name T753
Test name
Test status
Simulation time 1023661905 ps
CPU time 32.5 seconds
Started Aug 23 03:14:55 AM UTC 24
Finished Aug 23 03:15:29 AM UTC 24
Peak memory 218820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761506985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.761506985
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/41.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3179617978
Short name T142
Test name
Test status
Simulation time 51455578463 ps
CPU time 231.62 seconds
Started Aug 23 03:14:55 AM UTC 24
Finished Aug 23 03:18:50 AM UTC 24
Peak memory 219208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179617978 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.3179617978
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/41.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.3246834524
Short name T750
Test name
Test status
Simulation time 1337213760 ps
CPU time 11.49 seconds
Started Aug 23 03:15:09 AM UTC 24
Finished Aug 23 03:15:22 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246834524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.3246834524
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/41.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.2825930130
Short name T752
Test name
Test status
Simulation time 2003797810 ps
CPU time 26.52 seconds
Started Aug 23 03:14:59 AM UTC 24
Finished Aug 23 03:15:27 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825930130 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2825930130
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/41.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random.678532950
Short name T736
Test name
Test status
Simulation time 153399900 ps
CPU time 14.25 seconds
Started Aug 23 03:14:39 AM UTC 24
Finished Aug 23 03:14:54 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678532950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.678532950
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/41.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.4221637739
Short name T772
Test name
Test status
Simulation time 29441633925 ps
CPU time 83.74 seconds
Started Aug 23 03:14:52 AM UTC 24
Finished Aug 23 03:16:18 AM UTC 24
Peak memory 216892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221637739 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.4221637739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/41.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1736257018
Short name T784
Test name
Test status
Simulation time 16429119581 ps
CPU time 102.29 seconds
Started Aug 23 03:14:52 AM UTC 24
Finished Aug 23 03:16:37 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736257018 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1736257018
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/41.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.2747656410
Short name T733
Test name
Test status
Simulation time 100708957 ps
CPU time 8.16 seconds
Started Aug 23 03:14:42 AM UTC 24
Finished Aug 23 03:14:51 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747656410 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.2747656410
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/41.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.1214275455
Short name T745
Test name
Test status
Simulation time 933835356 ps
CPU time 12.13 seconds
Started Aug 23 03:14:58 AM UTC 24
Finished Aug 23 03:15:11 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214275455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1214275455
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/41.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.893487419
Short name T728
Test name
Test status
Simulation time 143286658 ps
CPU time 2.22 seconds
Started Aug 23 03:14:28 AM UTC 24
Finished Aug 23 03:14:32 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893487419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.893487419
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/41.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.4060573844
Short name T740
Test name
Test status
Simulation time 7435725006 ps
CPU time 32.07 seconds
Started Aug 23 03:14:34 AM UTC 24
Finished Aug 23 03:15:07 AM UTC 24
Peak memory 217140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060573844 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.4060573844
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/41.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.4131268747
Short name T737
Test name
Test status
Simulation time 6532635813 ps
CPU time 19.14 seconds
Started Aug 23 03:14:36 AM UTC 24
Finished Aug 23 03:14:57 AM UTC 24
Peak memory 217132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131268747 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.4131268747
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/41.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.3175216568
Short name T730
Test name
Test status
Simulation time 22754940 ps
CPU time 1.91 seconds
Started Aug 23 03:14:33 AM UTC 24
Finished Aug 23 03:14:36 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175216568 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.3175216568
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/41.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.427550983
Short name T789
Test name
Test status
Simulation time 4327036332 ps
CPU time 103.94 seconds
Started Aug 23 03:15:09 AM UTC 24
Finished Aug 23 03:16:56 AM UTC 24
Peak memory 218944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427550983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.427550983
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/41.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3401845540
Short name T746
Test name
Test status
Simulation time 6660374 ps
CPU time 0.74 seconds
Started Aug 23 03:15:11 AM UTC 24
Finished Aug 23 03:15:13 AM UTC 24
Peak memory 204360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401845540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3401845540
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/41.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.246018019
Short name T831
Test name
Test status
Simulation time 500207973 ps
CPU time 233.22 seconds
Started Aug 23 03:15:11 AM UTC 24
Finished Aug 23 03:19:08 AM UTC 24
Peak memory 222916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246018019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.246018019
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/41.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.4234341019
Short name T803
Test name
Test status
Simulation time 349497714 ps
CPU time 146.66 seconds
Started Aug 23 03:15:12 AM UTC 24
Finished Aug 23 03:17:42 AM UTC 24
Peak memory 222916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234341019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.4234341019
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/41.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.1624492725
Short name T749
Test name
Test status
Simulation time 746701776 ps
CPU time 21.22 seconds
Started Aug 23 03:14:59 AM UTC 24
Finished Aug 23 03:15:22 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624492725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1624492725
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/41.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.3605061075
Short name T763
Test name
Test status
Simulation time 2636938103 ps
CPU time 26.46 seconds
Started Aug 23 03:15:28 AM UTC 24
Finished Aug 23 03:15:56 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605061075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3605061075
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/42.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1415800511
Short name T861
Test name
Test status
Simulation time 52873113124 ps
CPU time 308.82 seconds
Started Aug 23 03:15:30 AM UTC 24
Finished Aug 23 03:20:43 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415800511 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.1415800511
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/42.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.1637591786
Short name T762
Test name
Test status
Simulation time 118916109 ps
CPU time 8.51 seconds
Started Aug 23 03:15:45 AM UTC 24
Finished Aug 23 03:15:55 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637591786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.1637591786
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/42.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.3945206988
Short name T769
Test name
Test status
Simulation time 1957483655 ps
CPU time 23.98 seconds
Started Aug 23 03:15:42 AM UTC 24
Finished Aug 23 03:16:07 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945206988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3945206988
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/42.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random.1159769668
Short name T758
Test name
Test status
Simulation time 200955989 ps
CPU time 23.39 seconds
Started Aug 23 03:15:23 AM UTC 24
Finished Aug 23 03:15:48 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159769668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.1159769668
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/42.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.2992459049
Short name T768
Test name
Test status
Simulation time 9968380460 ps
CPU time 39.54 seconds
Started Aug 23 03:15:25 AM UTC 24
Finished Aug 23 03:16:06 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992459049 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2992459049
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/42.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.557100775
Short name T818
Test name
Test status
Simulation time 26284576493 ps
CPU time 183.14 seconds
Started Aug 23 03:15:26 AM UTC 24
Finished Aug 23 03:18:32 AM UTC 24
Peak memory 218952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557100775 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.557100775
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/42.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.3018558713
Short name T755
Test name
Test status
Simulation time 124998364 ps
CPU time 16.78 seconds
Started Aug 23 03:15:23 AM UTC 24
Finished Aug 23 03:15:41 AM UTC 24
Peak memory 217148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018558713 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.3018558713
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/42.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.3091392696
Short name T757
Test name
Test status
Simulation time 490194914 ps
CPU time 10.41 seconds
Started Aug 23 03:15:32 AM UTC 24
Finished Aug 23 03:15:44 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091392696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3091392696
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/42.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.347198198
Short name T747
Test name
Test status
Simulation time 201114680 ps
CPU time 2.7 seconds
Started Aug 23 03:15:12 AM UTC 24
Finished Aug 23 03:15:16 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347198198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.347198198
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/42.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1847465121
Short name T759
Test name
Test status
Simulation time 8148440283 ps
CPU time 30.03 seconds
Started Aug 23 03:15:17 AM UTC 24
Finished Aug 23 03:15:48 AM UTC 24
Peak memory 217140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847465121 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1847465121
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/42.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.2238095314
Short name T756
Test name
Test status
Simulation time 3550496723 ps
CPU time 23.25 seconds
Started Aug 23 03:15:18 AM UTC 24
Finished Aug 23 03:15:43 AM UTC 24
Peak memory 217132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238095314 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.2238095314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/42.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.993960410
Short name T748
Test name
Test status
Simulation time 26857875 ps
CPU time 1.99 seconds
Started Aug 23 03:15:14 AM UTC 24
Finished Aug 23 03:15:17 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993960410 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.993960410
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/42.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.1744333970
Short name T760
Test name
Test status
Simulation time 6914855 ps
CPU time 0.68 seconds
Started Aug 23 03:15:49 AM UTC 24
Finished Aug 23 03:15:50 AM UTC 24
Peak memory 204296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744333970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1744333970
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/42.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.2880675713
Short name T777
Test name
Test status
Simulation time 1575616754 ps
CPU time 32.27 seconds
Started Aug 23 03:15:52 AM UTC 24
Finished Aug 23 03:16:25 AM UTC 24
Peak memory 218820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880675713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2880675713
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/42.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2151537826
Short name T45
Test name
Test status
Simulation time 2658508680 ps
CPU time 349.41 seconds
Started Aug 23 03:15:50 AM UTC 24
Finished Aug 23 03:21:44 AM UTC 24
Peak memory 233592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151537826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.2151537826
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/42.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.4091301188
Short name T771
Test name
Test status
Simulation time 136793555 ps
CPU time 18.4 seconds
Started Aug 23 03:15:52 AM UTC 24
Finished Aug 23 03:16:11 AM UTC 24
Peak memory 218956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091301188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.4091301188
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/42.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.3492478348
Short name T761
Test name
Test status
Simulation time 290622787 ps
CPU time 7.16 seconds
Started Aug 23 03:15:44 AM UTC 24
Finished Aug 23 03:15:52 AM UTC 24
Peak memory 216960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492478348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3492478348
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/42.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.819827319
Short name T778
Test name
Test status
Simulation time 138494679 ps
CPU time 19.38 seconds
Started Aug 23 03:16:08 AM UTC 24
Finished Aug 23 03:16:29 AM UTC 24
Peak memory 218888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819827319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.819827319
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/43.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.2016624318
Short name T900
Test name
Test status
Simulation time 217465021952 ps
CPU time 656.58 seconds
Started Aug 23 03:16:12 AM UTC 24
Finished Aug 23 03:27:16 AM UTC 24
Peak memory 222872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016624318 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.2016624318
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/43.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.950521181
Short name T780
Test name
Test status
Simulation time 629746258 ps
CPU time 10.01 seconds
Started Aug 23 03:16:21 AM UTC 24
Finished Aug 23 03:16:32 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950521181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.950521181
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/43.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.3682777927
Short name T782
Test name
Test status
Simulation time 864761543 ps
CPU time 15.16 seconds
Started Aug 23 03:16:20 AM UTC 24
Finished Aug 23 03:16:36 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682777927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3682777927
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/43.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random.2879944498
Short name T775
Test name
Test status
Simulation time 1087132158 ps
CPU time 21.13 seconds
Started Aug 23 03:16:00 AM UTC 24
Finished Aug 23 03:16:22 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879944498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.2879944498
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/43.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.3527977322
Short name T796
Test name
Test status
Simulation time 12364629663 ps
CPU time 69.31 seconds
Started Aug 23 03:16:06 AM UTC 24
Finished Aug 23 03:17:17 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527977322 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3527977322
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/43.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3158700269
Short name T177
Test name
Test status
Simulation time 40740481059 ps
CPU time 199.07 seconds
Started Aug 23 03:16:07 AM UTC 24
Finished Aug 23 03:19:29 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158700269 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3158700269
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/43.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.3658800022
Short name T770
Test name
Test status
Simulation time 113832804 ps
CPU time 8.28 seconds
Started Aug 23 03:16:01 AM UTC 24
Finished Aug 23 03:16:11 AM UTC 24
Peak memory 217020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658800022 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.3658800022
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/43.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.992669208
Short name T776
Test name
Test status
Simulation time 225793639 ps
CPU time 10.17 seconds
Started Aug 23 03:16:12 AM UTC 24
Finished Aug 23 03:16:23 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992669208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.992669208
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/43.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.1615377018
Short name T764
Test name
Test status
Simulation time 38115725 ps
CPU time 1.94 seconds
Started Aug 23 03:15:53 AM UTC 24
Finished Aug 23 03:15:56 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615377018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1615377018
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/43.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.3407109947
Short name T779
Test name
Test status
Simulation time 7405885088 ps
CPU time 33.07 seconds
Started Aug 23 03:15:56 AM UTC 24
Finished Aug 23 03:16:31 AM UTC 24
Peak memory 217140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407109947 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3407109947
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/43.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1715003763
Short name T773
Test name
Test status
Simulation time 3495190514 ps
CPU time 19.83 seconds
Started Aug 23 03:15:58 AM UTC 24
Finished Aug 23 03:16:19 AM UTC 24
Peak memory 216872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715003763 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1715003763
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/43.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.781569208
Short name T765
Test name
Test status
Simulation time 30960336 ps
CPU time 1.91 seconds
Started Aug 23 03:15:56 AM UTC 24
Finished Aug 23 03:15:59 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781569208 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.781569208
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/43.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.3024113854
Short name T219
Test name
Test status
Simulation time 4272132762 ps
CPU time 41.99 seconds
Started Aug 23 03:16:23 AM UTC 24
Finished Aug 23 03:17:07 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024113854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3024113854
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/43.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3731241585
Short name T806
Test name
Test status
Simulation time 3251688891 ps
CPU time 83.96 seconds
Started Aug 23 03:16:26 AM UTC 24
Finished Aug 23 03:17:52 AM UTC 24
Peak memory 219272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731241585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.3731241585
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/43.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1547385131
Short name T797
Test name
Test status
Simulation time 3726471630 ps
CPU time 50.87 seconds
Started Aug 23 03:16:25 AM UTC 24
Finished Aug 23 03:17:17 AM UTC 24
Peak memory 219272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547385131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.1547385131
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/43.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3090285119
Short name T876
Test name
Test status
Simulation time 2485178737 ps
CPU time 275.65 seconds
Started Aug 23 03:16:30 AM UTC 24
Finished Aug 23 03:21:10 AM UTC 24
Peak memory 233980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090285119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.3090285119
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/43.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.3582946335
Short name T785
Test name
Test status
Simulation time 322564846 ps
CPU time 19.64 seconds
Started Aug 23 03:16:20 AM UTC 24
Finished Aug 23 03:16:40 AM UTC 24
Peak memory 218876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582946335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3582946335
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/43.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.379726821
Short name T799
Test name
Test status
Simulation time 1139283180 ps
CPU time 33.38 seconds
Started Aug 23 03:16:46 AM UTC 24
Finished Aug 23 03:17:21 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379726821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.379726821
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/44.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3423907246
Short name T895
Test name
Test status
Simulation time 193067746971 ps
CPU time 440.69 seconds
Started Aug 23 03:16:56 AM UTC 24
Finished Aug 23 03:24:22 AM UTC 24
Peak memory 220568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423907246 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.3423907246
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/44.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.3329372026
Short name T798
Test name
Test status
Simulation time 1657873357 ps
CPU time 10.27 seconds
Started Aug 23 03:17:09 AM UTC 24
Finished Aug 23 03:17:21 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329372026 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.3329372026
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/44.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.2044560839
Short name T795
Test name
Test status
Simulation time 62469179 ps
CPU time 6.37 seconds
Started Aug 23 03:17:08 AM UTC 24
Finished Aug 23 03:17:15 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044560839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2044560839
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/44.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.172549258
Short name T787
Test name
Test status
Simulation time 38472870 ps
CPU time 5.68 seconds
Started Aug 23 03:16:38 AM UTC 24
Finished Aug 23 03:16:45 AM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172549258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.172549258
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/44.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.973461734
Short name T819
Test name
Test status
Simulation time 21135756989 ps
CPU time 108.81 seconds
Started Aug 23 03:16:42 AM UTC 24
Finished Aug 23 03:18:33 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973461734 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.973461734
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/44.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.2212782748
Short name T867
Test name
Test status
Simulation time 119812958532 ps
CPU time 242.74 seconds
Started Aug 23 03:16:42 AM UTC 24
Finished Aug 23 03:20:48 AM UTC 24
Peak memory 216904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212782748 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2212782748
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/44.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.757991508
Short name T788
Test name
Test status
Simulation time 204274620 ps
CPU time 15.72 seconds
Started Aug 23 03:16:38 AM UTC 24
Finished Aug 23 03:16:55 AM UTC 24
Peak memory 217140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757991508 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.757991508
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/44.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.2392516068
Short name T794
Test name
Test status
Simulation time 1432932104 ps
CPU time 13.97 seconds
Started Aug 23 03:16:57 AM UTC 24
Finished Aug 23 03:17:13 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392516068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2392516068
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/44.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.1776478537
Short name T781
Test name
Test status
Simulation time 165282488 ps
CPU time 2.74 seconds
Started Aug 23 03:16:32 AM UTC 24
Finished Aug 23 03:16:36 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776478537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1776478537
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/44.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1613945171
Short name T793
Test name
Test status
Simulation time 7059434023 ps
CPU time 34.94 seconds
Started Aug 23 03:16:36 AM UTC 24
Finished Aug 23 03:17:13 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613945171 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1613945171
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/44.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.4077377844
Short name T791
Test name
Test status
Simulation time 7819337684 ps
CPU time 31.47 seconds
Started Aug 23 03:16:38 AM UTC 24
Finished Aug 23 03:17:11 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077377844 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.4077377844
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/44.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3653063855
Short name T783
Test name
Test status
Simulation time 57735679 ps
CPU time 2.04 seconds
Started Aug 23 03:16:33 AM UTC 24
Finished Aug 23 03:16:36 AM UTC 24
Peak memory 217064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653063855 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.3653063855
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/44.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.772969732
Short name T828
Test name
Test status
Simulation time 992767948 ps
CPU time 106.81 seconds
Started Aug 23 03:17:13 AM UTC 24
Finished Aug 23 03:19:02 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772969732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.772969732
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/44.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2392535204
Short name T856
Test name
Test status
Simulation time 16093029523 ps
CPU time 185.84 seconds
Started Aug 23 03:17:14 AM UTC 24
Finished Aug 23 03:20:23 AM UTC 24
Peak memory 219004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392535204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2392535204
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/44.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.4083212491
Short name T143
Test name
Test status
Simulation time 5489836135 ps
CPU time 120.71 seconds
Started Aug 23 03:17:13 AM UTC 24
Finished Aug 23 03:19:16 AM UTC 24
Peak memory 223304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083212491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.4083212491
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/44.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.1287696035
Short name T834
Test name
Test status
Simulation time 1386216373 ps
CPU time 116.37 seconds
Started Aug 23 03:17:15 AM UTC 24
Finished Aug 23 03:19:13 AM UTC 24
Peak memory 222920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287696035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.1287696035
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/44.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.1126812786
Short name T802
Test name
Test status
Simulation time 951067911 ps
CPU time 23.85 seconds
Started Aug 23 03:17:08 AM UTC 24
Finished Aug 23 03:17:33 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126812786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1126812786
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/44.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.4009269193
Short name T812
Test name
Test status
Simulation time 3306117523 ps
CPU time 33.58 seconds
Started Aug 23 03:17:34 AM UTC 24
Finished Aug 23 03:18:09 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009269193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.4009269193
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/45.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2358787110
Short name T815
Test name
Test status
Simulation time 9046666398 ps
CPU time 43.66 seconds
Started Aug 23 03:17:43 AM UTC 24
Finished Aug 23 03:18:28 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358787110 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.2358787110
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/45.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.4110323737
Short name T810
Test name
Test status
Simulation time 315034750 ps
CPU time 7.74 seconds
Started Aug 23 03:17:54 AM UTC 24
Finished Aug 23 03:18:03 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110323737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.4110323737
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/45.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3247502677
Short name T809
Test name
Test status
Simulation time 106837447 ps
CPU time 7.25 seconds
Started Aug 23 03:17:53 AM UTC 24
Finished Aug 23 03:18:01 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247502677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3247502677
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/45.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.1461228498
Short name T805
Test name
Test status
Simulation time 1143767615 ps
CPU time 27.99 seconds
Started Aug 23 03:17:23 AM UTC 24
Finished Aug 23 03:17:52 AM UTC 24
Peak memory 218876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461228498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.1461228498
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/45.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.2571293899
Short name T868
Test name
Test status
Simulation time 61842104488 ps
CPU time 204.05 seconds
Started Aug 23 03:17:23 AM UTC 24
Finished Aug 23 03:20:49 AM UTC 24
Peak memory 218940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571293899 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2571293899
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/45.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.90625827
Short name T817
Test name
Test status
Simulation time 13577700253 ps
CPU time 56.77 seconds
Started Aug 23 03:17:31 AM UTC 24
Finished Aug 23 03:18:29 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90625827 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.90625827
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/45.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.2444229660
Short name T801
Test name
Test status
Simulation time 76967858 ps
CPU time 5.77 seconds
Started Aug 23 03:17:23 AM UTC 24
Finished Aug 23 03:17:30 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444229660 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2444229660
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/45.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.609236667
Short name T808
Test name
Test status
Simulation time 119130039 ps
CPU time 7.1 seconds
Started Aug 23 03:17:46 AM UTC 24
Finished Aug 23 03:17:54 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609236667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.609236667
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/45.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.4066993230
Short name T246
Test name
Test status
Simulation time 150890460 ps
CPU time 3.21 seconds
Started Aug 23 03:17:16 AM UTC 24
Finished Aug 23 03:17:20 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066993230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.4066993230
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/45.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2732379348
Short name T804
Test name
Test status
Simulation time 10198289784 ps
CPU time 25.37 seconds
Started Aug 23 03:17:18 AM UTC 24
Finished Aug 23 03:17:45 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732379348 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2732379348
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/45.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1143062902
Short name T807
Test name
Test status
Simulation time 3873465502 ps
CPU time 30.58 seconds
Started Aug 23 03:17:21 AM UTC 24
Finished Aug 23 03:17:53 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143062902 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1143062902
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/45.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2188317966
Short name T800
Test name
Test status
Simulation time 31075869 ps
CPU time 1.99 seconds
Started Aug 23 03:17:18 AM UTC 24
Finished Aug 23 03:17:21 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188317966 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.2188317966
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/45.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.213170943
Short name T865
Test name
Test status
Simulation time 8018592111 ps
CPU time 169.34 seconds
Started Aug 23 03:17:55 AM UTC 24
Finished Aug 23 03:20:47 AM UTC 24
Peak memory 223364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213170943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.213170943
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/45.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2847818169
Short name T816
Test name
Test status
Simulation time 245685080 ps
CPU time 23.34 seconds
Started Aug 23 03:18:04 AM UTC 24
Finished Aug 23 03:18:29 AM UTC 24
Peak memory 217096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847818169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2847818169
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/45.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.783594861
Short name T869
Test name
Test status
Simulation time 410718715 ps
CPU time 167.2 seconds
Started Aug 23 03:18:03 AM UTC 24
Finished Aug 23 03:20:53 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783594861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.783594861
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/45.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.2609853767
Short name T870
Test name
Test status
Simulation time 5492565958 ps
CPU time 166.68 seconds
Started Aug 23 03:18:09 AM UTC 24
Finished Aug 23 03:20:58 AM UTC 24
Peak memory 223308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609853767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.2609853767
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/45.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.1303873832
Short name T811
Test name
Test status
Simulation time 249505489 ps
CPU time 13.09 seconds
Started Aug 23 03:17:53 AM UTC 24
Finished Aug 23 03:18:07 AM UTC 24
Peak memory 218812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303873832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1303873832
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/45.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.395289486
Short name T836
Test name
Test status
Simulation time 4488041192 ps
CPU time 45.2 seconds
Started Aug 23 03:18:33 AM UTC 24
Finished Aug 23 03:19:20 AM UTC 24
Peak memory 218952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395289486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.395289486
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/46.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1016065303
Short name T164
Test name
Test status
Simulation time 29232668302 ps
CPU time 147.14 seconds
Started Aug 23 03:18:35 AM UTC 24
Finished Aug 23 03:21:04 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016065303 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.1016065303
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/46.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3174425859
Short name T827
Test name
Test status
Simulation time 1588536906 ps
CPU time 13.84 seconds
Started Aug 23 03:18:46 AM UTC 24
Finished Aug 23 03:19:01 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174425859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.3174425859
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/46.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.2858697105
Short name T824
Test name
Test status
Simulation time 27072405 ps
CPU time 2.36 seconds
Started Aug 23 03:18:41 AM UTC 24
Finished Aug 23 03:18:45 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858697105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2858697105
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/46.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.3843601127
Short name T820
Test name
Test status
Simulation time 30290784 ps
CPU time 2.83 seconds
Started Aug 23 03:18:29 AM UTC 24
Finished Aug 23 03:18:33 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843601127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.3843601127
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/46.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.4287897772
Short name T880
Test name
Test status
Simulation time 40756239118 ps
CPU time 162.47 seconds
Started Aug 23 03:18:31 AM UTC 24
Finished Aug 23 03:21:16 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287897772 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.4287897772
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/46.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2419515349
Short name T141
Test name
Test status
Simulation time 41926544474 ps
CPU time 174.71 seconds
Started Aug 23 03:18:33 AM UTC 24
Finished Aug 23 03:21:31 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419515349 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2419515349
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/46.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.4282149677
Short name T821
Test name
Test status
Simulation time 17346579 ps
CPU time 1.65 seconds
Started Aug 23 03:18:31 AM UTC 24
Finished Aug 23 03:18:33 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282149677 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.4282149677
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/46.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.4062073185
Short name T822
Test name
Test status
Simulation time 97574839 ps
CPU time 4.52 seconds
Started Aug 23 03:18:35 AM UTC 24
Finished Aug 23 03:18:41 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062073185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.4062073185
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/46.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.634406456
Short name T814
Test name
Test status
Simulation time 321793673 ps
CPU time 3.75 seconds
Started Aug 23 03:18:10 AM UTC 24
Finished Aug 23 03:18:15 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634406456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.634406456
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/46.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1477591465
Short name T823
Test name
Test status
Simulation time 9364303631 ps
CPU time 25.73 seconds
Started Aug 23 03:18:16 AM UTC 24
Finished Aug 23 03:18:43 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477591465 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1477591465
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/46.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2878586057
Short name T825
Test name
Test status
Simulation time 16157584918 ps
CPU time 32.13 seconds
Started Aug 23 03:18:16 AM UTC 24
Finished Aug 23 03:18:49 AM UTC 24
Peak memory 216872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878586057 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2878586057
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/46.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.479863324
Short name T813
Test name
Test status
Simulation time 79819681 ps
CPU time 2.38 seconds
Started Aug 23 03:18:11 AM UTC 24
Finished Aug 23 03:18:14 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479863324 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.479863324
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/46.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.2765297875
Short name T875
Test name
Test status
Simulation time 13713958634 ps
CPU time 137.26 seconds
Started Aug 23 03:18:50 AM UTC 24
Finished Aug 23 03:21:10 AM UTC 24
Peak memory 222976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765297875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2765297875
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/46.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3208175993
Short name T838
Test name
Test status
Simulation time 5978401327 ps
CPU time 34.65 seconds
Started Aug 23 03:18:53 AM UTC 24
Finished Aug 23 03:19:29 AM UTC 24
Peak memory 216968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208175993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.3208175993
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/46.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.3633659305
Short name T52
Test name
Test status
Simulation time 8687281920 ps
CPU time 257.33 seconds
Started Aug 23 03:18:52 AM UTC 24
Finished Aug 23 03:23:12 AM UTC 24
Peak memory 221000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633659305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.3633659305
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/46.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2659753230
Short name T887
Test name
Test status
Simulation time 624990768 ps
CPU time 196.97 seconds
Started Aug 23 03:19:02 AM UTC 24
Finished Aug 23 03:22:22 AM UTC 24
Peak memory 223352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659753230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.2659753230
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/46.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.3264102762
Short name T826
Test name
Test status
Simulation time 235317069 ps
CPU time 6.16 seconds
Started Aug 23 03:18:44 AM UTC 24
Finished Aug 23 03:18:52 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264102762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.3264102762
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/46.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.4222601764
Short name T840
Test name
Test status
Simulation time 3324525868 ps
CPU time 14.25 seconds
Started Aug 23 03:19:18 AM UTC 24
Finished Aug 23 03:19:34 AM UTC 24
Peak memory 219204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222601764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.4222601764
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/47.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1511034936
Short name T899
Test name
Test status
Simulation time 65205443751 ps
CPU time 428.89 seconds
Started Aug 23 03:19:21 AM UTC 24
Finished Aug 23 03:26:35 AM UTC 24
Peak memory 222612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511034936 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.1511034936
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/47.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.530813749
Short name T846
Test name
Test status
Simulation time 526351206 ps
CPU time 11.98 seconds
Started Aug 23 03:19:33 AM UTC 24
Finished Aug 23 03:19:46 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530813749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.530813749
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/47.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1571969835
Short name T848
Test name
Test status
Simulation time 240064767 ps
CPU time 16.44 seconds
Started Aug 23 03:19:31 AM UTC 24
Finished Aug 23 03:19:48 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571969835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1571969835
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/47.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.3034281323
Short name T837
Test name
Test status
Simulation time 633063424 ps
CPU time 11.89 seconds
Started Aug 23 03:19:09 AM UTC 24
Finished Aug 23 03:19:22 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034281323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.3034281323
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/47.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.1307288844
Short name T839
Test name
Test status
Simulation time 6308869663 ps
CPU time 15.93 seconds
Started Aug 23 03:19:15 AM UTC 24
Finished Aug 23 03:19:32 AM UTC 24
Peak memory 216888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307288844 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1307288844
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/47.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3531201636
Short name T885
Test name
Test status
Simulation time 25951684972 ps
CPU time 161.87 seconds
Started Aug 23 03:19:17 AM UTC 24
Finished Aug 23 03:22:01 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531201636 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3531201636
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/47.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.2396526666
Short name T835
Test name
Test status
Simulation time 48657125 ps
CPU time 5.1 seconds
Started Aug 23 03:19:11 AM UTC 24
Finished Aug 23 03:19:17 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396526666 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.2396526666
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/47.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.3286662276
Short name T843
Test name
Test status
Simulation time 733737829 ps
CPU time 15.56 seconds
Started Aug 23 03:19:23 AM UTC 24
Finished Aug 23 03:19:40 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286662276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3286662276
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/47.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.2197044865
Short name T830
Test name
Test status
Simulation time 29747424 ps
CPU time 1.74 seconds
Started Aug 23 03:19:03 AM UTC 24
Finished Aug 23 03:19:06 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197044865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2197044865
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/47.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.712720555
Short name T845
Test name
Test status
Simulation time 17585594858 ps
CPU time 36.19 seconds
Started Aug 23 03:19:07 AM UTC 24
Finished Aug 23 03:19:45 AM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712720555 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.712720555
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/47.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.414562575
Short name T146
Test name
Test status
Simulation time 4332261215 ps
CPU time 24.69 seconds
Started Aug 23 03:19:09 AM UTC 24
Finished Aug 23 03:19:35 AM UTC 24
Peak memory 217140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414562575 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.414562575
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/47.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1428027738
Short name T832
Test name
Test status
Simulation time 33598642 ps
CPU time 2.1 seconds
Started Aug 23 03:19:05 AM UTC 24
Finished Aug 23 03:19:08 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428027738 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1428027738
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/47.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.862017157
Short name T853
Test name
Test status
Simulation time 418439189 ps
CPU time 31.63 seconds
Started Aug 23 03:19:34 AM UTC 24
Finished Aug 23 03:20:07 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862017157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.862017157
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/47.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2208428192
Short name T884
Test name
Test status
Simulation time 5944265814 ps
CPU time 131.88 seconds
Started Aug 23 03:19:37 AM UTC 24
Finished Aug 23 03:21:52 AM UTC 24
Peak memory 218952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208428192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2208428192
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/47.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2142252220
Short name T847
Test name
Test status
Simulation time 79809269 ps
CPU time 10.77 seconds
Started Aug 23 03:19:36 AM UTC 24
Finished Aug 23 03:19:48 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142252220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.2142252220
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/47.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.385508514
Short name T860
Test name
Test status
Simulation time 433661361 ps
CPU time 58.91 seconds
Started Aug 23 03:19:37 AM UTC 24
Finished Aug 23 03:20:38 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385508514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.385508514
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/47.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.3883378401
Short name T842
Test name
Test status
Simulation time 143013800 ps
CPU time 4.6 seconds
Started Aug 23 03:19:31 AM UTC 24
Finished Aug 23 03:19:36 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883378401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3883378401
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/47.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.2738387228
Short name T866
Test name
Test status
Simulation time 4055163027 ps
CPU time 45.88 seconds
Started Aug 23 03:20:00 AM UTC 24
Finished Aug 23 03:20:48 AM UTC 24
Peak memory 218944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738387228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2738387228
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/48.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.308527239
Short name T897
Test name
Test status
Simulation time 38942199201 ps
CPU time 313.43 seconds
Started Aug 23 03:20:03 AM UTC 24
Finished Aug 23 03:25:20 AM UTC 24
Peak memory 220568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308527239 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.308527239
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/48.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.351260577
Short name T858
Test name
Test status
Simulation time 97639892 ps
CPU time 8.79 seconds
Started Aug 23 03:20:23 AM UTC 24
Finished Aug 23 03:20:33 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351260577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.351260577
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/48.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.2139832723
Short name T864
Test name
Test status
Simulation time 1122864040 ps
CPU time 28.77 seconds
Started Aug 23 03:20:17 AM UTC 24
Finished Aug 23 03:20:47 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139832723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2139832723
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/48.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.3777428814
Short name T851
Test name
Test status
Simulation time 462042539 ps
CPU time 9.29 seconds
Started Aug 23 03:19:49 AM UTC 24
Finished Aug 23 03:20:00 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777428814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.3777428814
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/48.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.1078889098
Short name T888
Test name
Test status
Simulation time 43587192965 ps
CPU time 151.39 seconds
Started Aug 23 03:19:51 AM UTC 24
Finished Aug 23 03:22:24 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078889098 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1078889098
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/48.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3722211439
Short name T890
Test name
Test status
Simulation time 30545992745 ps
CPU time 187.02 seconds
Started Aug 23 03:19:56 AM UTC 24
Finished Aug 23 03:23:06 AM UTC 24
Peak memory 216904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722211439 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3722211439
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/48.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.810086493
Short name T850
Test name
Test status
Simulation time 80012981 ps
CPU time 5.1 seconds
Started Aug 23 03:19:49 AM UTC 24
Finished Aug 23 03:19:55 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810086493 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.810086493
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/48.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.3863627542
Short name T854
Test name
Test status
Simulation time 196264723 ps
CPU time 10.27 seconds
Started Aug 23 03:20:08 AM UTC 24
Finished Aug 23 03:20:20 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863627542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3863627542
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/48.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.2608641881
Short name T844
Test name
Test status
Simulation time 118997558 ps
CPU time 2.85 seconds
Started Aug 23 03:19:41 AM UTC 24
Finished Aug 23 03:19:45 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608641881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2608641881
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/48.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2761159266
Short name T147
Test name
Test status
Simulation time 6903785773 ps
CPU time 27.57 seconds
Started Aug 23 03:19:46 AM UTC 24
Finished Aug 23 03:20:15 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761159266 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2761159266
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/48.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2496298898
Short name T855
Test name
Test status
Simulation time 25390584083 ps
CPU time 33.4 seconds
Started Aug 23 03:19:48 AM UTC 24
Finished Aug 23 03:20:22 AM UTC 24
Peak memory 216872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496298898 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.2496298898
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/48.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2318059125
Short name T849
Test name
Test status
Simulation time 50992756 ps
CPU time 1.81 seconds
Started Aug 23 03:19:46 AM UTC 24
Finished Aug 23 03:19:49 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318059125 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2318059125
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/48.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.578346791
Short name T883
Test name
Test status
Simulation time 1007463380 ps
CPU time 72.25 seconds
Started Aug 23 03:20:25 AM UTC 24
Finished Aug 23 03:21:39 AM UTC 24
Peak memory 220928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578346791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.578346791
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/48.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.548650846
Short name T893
Test name
Test status
Simulation time 9873680657 ps
CPU time 191.92 seconds
Started Aug 23 03:20:34 AM UTC 24
Finished Aug 23 03:23:49 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548650846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.548650846
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/48.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.4267187251
Short name T894
Test name
Test status
Simulation time 940008449 ps
CPU time 210.18 seconds
Started Aug 23 03:20:30 AM UTC 24
Finished Aug 23 03:24:03 AM UTC 24
Peak memory 220936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267187251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.4267187251
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/48.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.4226354180
Short name T886
Test name
Test status
Simulation time 569044527 ps
CPU time 87.63 seconds
Started Aug 23 03:20:36 AM UTC 24
Finished Aug 23 03:22:06 AM UTC 24
Peak memory 222988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226354180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.4226354180
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/48.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.3938854841
Short name T859
Test name
Test status
Simulation time 1140824138 ps
CPU time 12.75 seconds
Started Aug 23 03:20:21 AM UTC 24
Finished Aug 23 03:20:35 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938854841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3938854841
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/48.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.2844865990
Short name T144
Test name
Test status
Simulation time 1535730152 ps
CPU time 58.13 seconds
Started Aug 23 03:20:51 AM UTC 24
Finished Aug 23 03:21:51 AM UTC 24
Peak memory 219140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844865990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2844865990
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/49.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2517454346
Short name T892
Test name
Test status
Simulation time 17559416819 ps
CPU time 150.38 seconds
Started Aug 23 03:20:54 AM UTC 24
Finished Aug 23 03:23:27 AM UTC 24
Peak memory 219268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517454346 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.2517454346
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/49.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.99135752
Short name T881
Test name
Test status
Simulation time 167393478 ps
CPU time 11.8 seconds
Started Aug 23 03:21:06 AM UTC 24
Finished Aug 23 03:21:19 AM UTC 24
Peak memory 217008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99135752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.99135752
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/49.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.3301132460
Short name T874
Test name
Test status
Simulation time 1766703328 ps
CPU time 8.62 seconds
Started Aug 23 03:21:00 AM UTC 24
Finished Aug 23 03:21:09 AM UTC 24
Peak memory 217020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301132460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3301132460
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/49.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2323519990
Short name T872
Test name
Test status
Simulation time 470126336 ps
CPU time 13.52 seconds
Started Aug 23 03:20:49 AM UTC 24
Finished Aug 23 03:21:03 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323519990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.2323519990
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/49.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.3045832934
Short name T148
Test name
Test status
Simulation time 4078989695 ps
CPU time 22.22 seconds
Started Aug 23 03:20:49 AM UTC 24
Finished Aug 23 03:21:12 AM UTC 24
Peak memory 216892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045832934 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3045832934
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/49.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.587769434
Short name T891
Test name
Test status
Simulation time 28775379508 ps
CPU time 149.36 seconds
Started Aug 23 03:20:51 AM UTC 24
Finished Aug 23 03:23:23 AM UTC 24
Peak memory 218956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587769434 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.587769434
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/49.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.2959262230
Short name T871
Test name
Test status
Simulation time 291571227 ps
CPU time 8.29 seconds
Started Aug 23 03:20:49 AM UTC 24
Finished Aug 23 03:20:58 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959262230 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.2959262230
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/49.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.2091621831
Short name T873
Test name
Test status
Simulation time 293048961 ps
CPU time 4.11 seconds
Started Aug 23 03:21:00 AM UTC 24
Finished Aug 23 03:21:05 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091621831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2091621831
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/49.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.1569335788
Short name T862
Test name
Test status
Simulation time 179315580 ps
CPU time 2.85 seconds
Started Aug 23 03:20:39 AM UTC 24
Finished Aug 23 03:20:43 AM UTC 24
Peak memory 217132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569335788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1569335788
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/49.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3585316325
Short name T877
Test name
Test status
Simulation time 6154248181 ps
CPU time 25.96 seconds
Started Aug 23 03:20:44 AM UTC 24
Finished Aug 23 03:21:11 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585316325 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3585316325
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/49.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.176399696
Short name T878
Test name
Test status
Simulation time 4225607968 ps
CPU time 20.93 seconds
Started Aug 23 03:20:49 AM UTC 24
Finished Aug 23 03:21:11 AM UTC 24
Peak memory 217132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176399696 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.176399696
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/49.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2331531736
Short name T863
Test name
Test status
Simulation time 116347493 ps
CPU time 1.84 seconds
Started Aug 23 03:20:44 AM UTC 24
Finished Aug 23 03:20:47 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331531736 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.2331531736
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/49.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.4163593463
Short name T882
Test name
Test status
Simulation time 1152147710 ps
CPU time 27.96 seconds
Started Aug 23 03:21:06 AM UTC 24
Finished Aug 23 03:21:35 AM UTC 24
Peak memory 219144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163593463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.4163593463
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/49.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.1036190672
Short name T889
Test name
Test status
Simulation time 1394530087 ps
CPU time 79.32 seconds
Started Aug 23 03:21:13 AM UTC 24
Finished Aug 23 03:22:34 AM UTC 24
Peak memory 217144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036190672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1036190672
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/49.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.4218111326
Short name T896
Test name
Test status
Simulation time 10373250183 ps
CPU time 245.7 seconds
Started Aug 23 03:21:10 AM UTC 24
Finished Aug 23 03:25:19 AM UTC 24
Peak memory 223044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218111326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.4218111326
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/49.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.3018760248
Short name T898
Test name
Test status
Simulation time 2423300842 ps
CPU time 278.28 seconds
Started Aug 23 03:21:13 AM UTC 24
Finished Aug 23 03:25:55 AM UTC 24
Peak memory 234008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018760248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.3018760248
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/49.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.2907480043
Short name T879
Test name
Test status
Simulation time 270449047 ps
CPU time 8.84 seconds
Started Aug 23 03:21:04 AM UTC 24
Finished Aug 23 03:21:14 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907480043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2907480043
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/49.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.810442140
Short name T83
Test name
Test status
Simulation time 1503617129 ps
CPU time 41.33 seconds
Started Aug 23 02:46:00 AM UTC 24
Finished Aug 23 02:46:42 AM UTC 24
Peak memory 218888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810442140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.810442140
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/5.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1365556242
Short name T194
Test name
Test status
Simulation time 84712128 ps
CPU time 18.35 seconds
Started Aug 23 02:46:30 AM UTC 24
Finished Aug 23 02:46:50 AM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365556242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1365556242
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/5.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.396581230
Short name T273
Test name
Test status
Simulation time 50768118 ps
CPU time 4.48 seconds
Started Aug 23 02:46:25 AM UTC 24
Finished Aug 23 02:46:31 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396581230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.396581230
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/5.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random.2678026492
Short name T271
Test name
Test status
Simulation time 686796222 ps
CPU time 34.8 seconds
Started Aug 23 02:45:49 AM UTC 24
Finished Aug 23 02:46:26 AM UTC 24
Peak memory 218820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678026492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2678026492
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/5.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.2986312979
Short name T286
Test name
Test status
Simulation time 73798708553 ps
CPU time 249.07 seconds
Started Aug 23 02:45:57 AM UTC 24
Finished Aug 23 02:50:09 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986312979 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2986312979
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/5.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.3120236442
Short name T108
Test name
Test status
Simulation time 13835869936 ps
CPU time 131.45 seconds
Started Aug 23 02:45:58 AM UTC 24
Finished Aug 23 02:48:11 AM UTC 24
Peak memory 217160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120236442 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3120236442
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/5.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.2744184014
Short name T58
Test name
Test status
Simulation time 38174181 ps
CPU time 4.91 seconds
Started Aug 23 02:45:49 AM UTC 24
Finished Aug 23 02:45:55 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744184014 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.2744184014
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/5.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.101472798
Short name T272
Test name
Test status
Simulation time 361643867 ps
CPU time 11.39 seconds
Started Aug 23 02:46:17 AM UTC 24
Finished Aug 23 02:46:30 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101472798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.101472798
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/5.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.930610591
Short name T173
Test name
Test status
Simulation time 28788953 ps
CPU time 2.96 seconds
Started Aug 23 02:45:43 AM UTC 24
Finished Aug 23 02:45:47 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930610591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.930610591
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/5.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.1726823871
Short name T270
Test name
Test status
Simulation time 29081756426 ps
CPU time 35.36 seconds
Started Aug 23 02:45:47 AM UTC 24
Finished Aug 23 02:46:24 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726823871 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.1726823871
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/5.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.787586315
Short name T59
Test name
Test status
Simulation time 14313363609 ps
CPU time 45.74 seconds
Started Aug 23 02:45:48 AM UTC 24
Finished Aug 23 02:46:35 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787586315 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.787586315
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/5.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.1249775351
Short name T4
Test name
Test status
Simulation time 27995254 ps
CPU time 3.16 seconds
Started Aug 23 02:45:44 AM UTC 24
Finished Aug 23 02:45:48 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249775351 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.1249775351
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/5.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.886043586
Short name T94
Test name
Test status
Simulation time 14815704961 ps
CPU time 220.35 seconds
Started Aug 23 02:46:32 AM UTC 24
Finished Aug 23 02:50:16 AM UTC 24
Peak memory 223296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886043586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.886043586
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/5.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2308496226
Short name T251
Test name
Test status
Simulation time 6607689038 ps
CPU time 72.21 seconds
Started Aug 23 02:46:36 AM UTC 24
Finished Aug 23 02:47:50 AM UTC 24
Peak memory 218952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308496226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2308496226
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/5.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.1915203354
Short name T176
Test name
Test status
Simulation time 2230006712 ps
CPU time 391.26 seconds
Started Aug 23 02:46:34 AM UTC 24
Finished Aug 23 02:53:10 AM UTC 24
Peak memory 220996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915203354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.1915203354
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/5.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.4271457925
Short name T253
Test name
Test status
Simulation time 256572052 ps
CPU time 75.71 seconds
Started Aug 23 02:46:40 AM UTC 24
Finished Aug 23 02:47:58 AM UTC 24
Peak memory 223236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271457925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.4271457925
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/5.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.2342049346
Short name T199
Test name
Test status
Simulation time 364319294 ps
CPU time 12.59 seconds
Started Aug 23 02:46:26 AM UTC 24
Finished Aug 23 02:46:40 AM UTC 24
Peak memory 216964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342049346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2342049346
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/5.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1701607788
Short name T120
Test name
Test status
Simulation time 90422547362 ps
CPU time 641.22 seconds
Started Aug 23 02:47:14 AM UTC 24
Finished Aug 23 02:58:03 AM UTC 24
Peak memory 222548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701607788 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.1701607788
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/6.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3154219552
Short name T275
Test name
Test status
Simulation time 317453548 ps
CPU time 14.56 seconds
Started Aug 23 02:47:36 AM UTC 24
Finished Aug 23 02:47:52 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154219552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3154219552
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/6.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random.1529790357
Short name T88
Test name
Test status
Simulation time 1126588982 ps
CPU time 30.6 seconds
Started Aug 23 02:46:48 AM UTC 24
Finished Aug 23 02:47:20 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529790357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1529790357
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/6.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.1463302600
Short name T169
Test name
Test status
Simulation time 17945702352 ps
CPU time 98.13 seconds
Started Aug 23 02:46:56 AM UTC 24
Finished Aug 23 02:48:36 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463302600 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1463302600
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/6.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.1576598459
Short name T302
Test name
Test status
Simulation time 87985048492 ps
CPU time 322.45 seconds
Started Aug 23 02:47:12 AM UTC 24
Finished Aug 23 02:52:39 AM UTC 24
Peak memory 218888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576598459 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.1576598459
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/6.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.1581471946
Short name T195
Test name
Test status
Simulation time 58999360 ps
CPU time 3.64 seconds
Started Aug 23 02:46:51 AM UTC 24
Finished Aug 23 02:46:55 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581471946 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1581471946
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/6.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.3118675128
Short name T227
Test name
Test status
Simulation time 1070281208 ps
CPU time 33.28 seconds
Started Aug 23 02:47:16 AM UTC 24
Finished Aug 23 02:47:50 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118675128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3118675128
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/6.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.893084571
Short name T192
Test name
Test status
Simulation time 196055928 ps
CPU time 3.19 seconds
Started Aug 23 02:46:41 AM UTC 24
Finished Aug 23 02:46:46 AM UTC 24
Peak memory 217072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893084571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.893084571
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/6.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3689718587
Short name T196
Test name
Test status
Simulation time 11022952287 ps
CPU time 25.48 seconds
Started Aug 23 02:46:44 AM UTC 24
Finished Aug 23 02:47:11 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689718587 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3689718587
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/6.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.634927423
Short name T197
Test name
Test status
Simulation time 3208963616 ps
CPU time 25.02 seconds
Started Aug 23 02:46:47 AM UTC 24
Finished Aug 23 02:47:13 AM UTC 24
Peak memory 217132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634927423 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.634927423
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/6.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.442430532
Short name T193
Test name
Test status
Simulation time 40653486 ps
CPU time 2.33 seconds
Started Aug 23 02:46:43 AM UTC 24
Finished Aug 23 02:46:47 AM UTC 24
Peak memory 216804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442430532 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.442430532
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/6.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.4044249276
Short name T95
Test name
Test status
Simulation time 10681708701 ps
CPU time 158.06 seconds
Started Aug 23 02:47:38 AM UTC 24
Finished Aug 23 02:50:19 AM UTC 24
Peak memory 220992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044249276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.4044249276
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/6.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.648914672
Short name T261
Test name
Test status
Simulation time 2447797412 ps
CPU time 155.43 seconds
Started Aug 23 02:47:44 AM UTC 24
Finished Aug 23 02:50:23 AM UTC 24
Peak memory 219204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648914672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.648914672
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/6.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2331487291
Short name T263
Test name
Test status
Simulation time 72099291 ps
CPU time 19.95 seconds
Started Aug 23 02:47:52 AM UTC 24
Finished Aug 23 02:48:13 AM UTC 24
Peak memory 218816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331487291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.2331487291
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/6.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.1251647173
Short name T234
Test name
Test status
Simulation time 578389953 ps
CPU time 9.79 seconds
Started Aug 23 02:47:24 AM UTC 24
Finished Aug 23 02:47:35 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251647173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1251647173
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/6.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.3247888143
Short name T200
Test name
Test status
Simulation time 136273969 ps
CPU time 13.25 seconds
Started Aug 23 02:48:09 AM UTC 24
Finished Aug 23 02:48:23 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247888143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.3247888143
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/7.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.523770581
Short name T117
Test name
Test status
Simulation time 22433390170 ps
CPU time 41.04 seconds
Started Aug 23 02:48:12 AM UTC 24
Finished Aug 23 02:48:55 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523770581 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.523770581
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/7.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.3169587099
Short name T116
Test name
Test status
Simulation time 1063726174 ps
CPU time 22.04 seconds
Started Aug 23 02:48:24 AM UTC 24
Finished Aug 23 02:48:48 AM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169587099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3169587099
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/7.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.2517056729
Short name T276
Test name
Test status
Simulation time 56391435 ps
CPU time 2.41 seconds
Started Aug 23 02:48:20 AM UTC 24
Finished Aug 23 02:48:24 AM UTC 24
Peak memory 217080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517056729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2517056729
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/7.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random.1902310878
Short name T149
Test name
Test status
Simulation time 164598612 ps
CPU time 9.24 seconds
Started Aug 23 02:47:57 AM UTC 24
Finished Aug 23 02:48:07 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902310878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.1902310878
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/7.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.3645783066
Short name T150
Test name
Test status
Simulation time 18387332801 ps
CPU time 136.46 seconds
Started Aug 23 02:47:58 AM UTC 24
Finished Aug 23 02:50:17 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645783066 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3645783066
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/7.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.199163524
Short name T63
Test name
Test status
Simulation time 48754468948 ps
CPU time 248.69 seconds
Started Aug 23 02:48:01 AM UTC 24
Finished Aug 23 02:52:13 AM UTC 24
Peak memory 218944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199163524 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.199163524
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/7.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.611685327
Short name T208
Test name
Test status
Simulation time 280229450 ps
CPU time 27.32 seconds
Started Aug 23 02:47:57 AM UTC 24
Finished Aug 23 02:48:26 AM UTC 24
Peak memory 218872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611685327 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.611685327
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/7.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.2576542770
Short name T250
Test name
Test status
Simulation time 196084644 ps
CPU time 4.52 seconds
Started Aug 23 02:48:14 AM UTC 24
Finished Aug 23 02:48:20 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576542770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2576542770
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/7.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.3376676425
Short name T243
Test name
Test status
Simulation time 217200937 ps
CPU time 3.61 seconds
Started Aug 23 02:47:52 AM UTC 24
Finished Aug 23 02:47:56 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376676425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3376676425
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/7.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.271997415
Short name T61
Test name
Test status
Simulation time 5004032739 ps
CPU time 29.56 seconds
Started Aug 23 02:47:54 AM UTC 24
Finished Aug 23 02:48:25 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271997415 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.271997415
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/7.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3086970317
Short name T174
Test name
Test status
Simulation time 6441190417 ps
CPU time 33.89 seconds
Started Aug 23 02:47:55 AM UTC 24
Finished Aug 23 02:48:30 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086970317 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3086970317
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/7.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3112637784
Short name T60
Test name
Test status
Simulation time 42491548 ps
CPU time 2.77 seconds
Started Aug 23 02:47:53 AM UTC 24
Finished Aug 23 02:47:57 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112637784 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3112637784
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/7.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.2110426238
Short name T110
Test name
Test status
Simulation time 40069171120 ps
CPU time 252.19 seconds
Started Aug 23 02:48:25 AM UTC 24
Finished Aug 23 02:52:42 AM UTC 24
Peak memory 223040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110426238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2110426238
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/7.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2327049834
Short name T257
Test name
Test status
Simulation time 5830016342 ps
CPU time 146.62 seconds
Started Aug 23 02:48:31 AM UTC 24
Finished Aug 23 02:51:00 AM UTC 24
Peak memory 221192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327049834 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2327049834
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/7.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.94900306
Short name T35
Test name
Test status
Simulation time 438632377 ps
CPU time 171.07 seconds
Started Aug 23 02:48:27 AM UTC 24
Finished Aug 23 02:51:21 AM UTC 24
Peak memory 220928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94900306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.94900306
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/7.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1078379718
Short name T39
Test name
Test status
Simulation time 237134687 ps
CPU time 68.13 seconds
Started Aug 23 02:48:34 AM UTC 24
Finished Aug 23 02:49:44 AM UTC 24
Peak memory 221024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078379718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.1078379718
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/7.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.1434820092
Short name T114
Test name
Test status
Simulation time 297420455 ps
CPU time 18.79 seconds
Started Aug 23 02:48:24 AM UTC 24
Finished Aug 23 02:48:44 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434820092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1434820092
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/7.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.2314011890
Short name T30
Test name
Test status
Simulation time 2017843942 ps
CPU time 60.4 seconds
Started Aug 23 02:49:12 AM UTC 24
Finished Aug 23 02:50:14 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314011890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.2314011890
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/8.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.2767533091
Short name T282
Test name
Test status
Simulation time 308953025 ps
CPU time 20.74 seconds
Started Aug 23 02:49:32 AM UTC 24
Finished Aug 23 02:49:54 AM UTC 24
Peak memory 216844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767533091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.2767533091
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/8.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.3491588160
Short name T279
Test name
Test status
Simulation time 254584611 ps
CPU time 15.16 seconds
Started Aug 23 02:49:21 AM UTC 24
Finished Aug 23 02:49:37 AM UTC 24
Peak memory 217020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491588160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3491588160
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/8.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random.216144155
Short name T91
Test name
Test status
Simulation time 303826243 ps
CPU time 7.71 seconds
Started Aug 23 02:48:49 AM UTC 24
Finished Aug 23 02:48:57 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216144155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.216144155
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/8.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.3246786373
Short name T314
Test name
Test status
Simulation time 105457535002 ps
CPU time 280.8 seconds
Started Aug 23 02:48:56 AM UTC 24
Finished Aug 23 02:53:40 AM UTC 24
Peak memory 216892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246786373 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3246786373
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/8.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.2134302516
Short name T292
Test name
Test status
Simulation time 20285336607 ps
CPU time 105.04 seconds
Started Aug 23 02:48:58 AM UTC 24
Finished Aug 23 02:50:45 AM UTC 24
Peak memory 217164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134302516 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2134302516
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/8.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.3952569270
Short name T118
Test name
Test status
Simulation time 260696210 ps
CPU time 24.69 seconds
Started Aug 23 02:48:49 AM UTC 24
Finished Aug 23 02:49:15 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952569270 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.3952569270
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/8.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.397043152
Short name T278
Test name
Test status
Simulation time 211148989 ps
CPU time 13.19 seconds
Started Aug 23 02:49:18 AM UTC 24
Finished Aug 23 02:49:33 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397043152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.397043152
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/8.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.1628078122
Short name T277
Test name
Test status
Simulation time 148763404 ps
CPU time 5.32 seconds
Started Aug 23 02:48:36 AM UTC 24
Finished Aug 23 02:48:43 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628078122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1628078122
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/8.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.2231513664
Short name T62
Test name
Test status
Simulation time 3847009232 ps
CPU time 25.77 seconds
Started Aug 23 02:48:44 AM UTC 24
Finished Aug 23 02:49:11 AM UTC 24
Peak memory 217136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231513664 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2231513664
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/8.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.408919067
Short name T6
Test name
Test status
Simulation time 2611268927 ps
CPU time 40.62 seconds
Started Aug 23 02:48:45 AM UTC 24
Finished Aug 23 02:49:28 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408919067 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.408919067
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/8.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.2426560532
Short name T115
Test name
Test status
Simulation time 35907539 ps
CPU time 3.5 seconds
Started Aug 23 02:48:43 AM UTC 24
Finished Aug 23 02:48:48 AM UTC 24
Peak memory 217068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426560532 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.2426560532
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/8.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.4053736528
Short name T284
Test name
Test status
Simulation time 485564107 ps
CPU time 23.59 seconds
Started Aug 23 02:49:33 AM UTC 24
Finished Aug 23 02:49:58 AM UTC 24
Peak memory 218812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053736528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.4053736528
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/8.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.209181386
Short name T36
Test name
Test status
Simulation time 1222586588 ps
CPU time 106.8 seconds
Started Aug 23 02:49:40 AM UTC 24
Finished Aug 23 02:51:29 AM UTC 24
Peak memory 220928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209181386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.209181386
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/8.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3220873055
Short name T212
Test name
Test status
Simulation time 811283617 ps
CPU time 263.75 seconds
Started Aug 23 02:49:38 AM UTC 24
Finished Aug 23 02:54:06 AM UTC 24
Peak memory 220872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220873055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.3220873055
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/8.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.4007854861
Short name T281
Test name
Test status
Simulation time 13784653 ps
CPU time 2.26 seconds
Started Aug 23 02:49:45 AM UTC 24
Finished Aug 23 02:49:48 AM UTC 24
Peak memory 217152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007854861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.4007854861
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/8.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.2360307990
Short name T280
Test name
Test status
Simulation time 323289445 ps
CPU time 9.47 seconds
Started Aug 23 02:49:29 AM UTC 24
Finished Aug 23 02:49:40 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360307990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2360307990
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/8.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.3470481173
Short name T230
Test name
Test status
Simulation time 436783659 ps
CPU time 8.62 seconds
Started Aug 23 02:50:17 AM UTC 24
Finished Aug 23 02:50:26 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470481173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.3470481173
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/9.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.3682275332
Short name T252
Test name
Test status
Simulation time 19004095901 ps
CPU time 161.35 seconds
Started Aug 23 02:50:18 AM UTC 24
Finished Aug 23 02:53:02 AM UTC 24
Peak memory 218952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682275332 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.3682275332
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/9.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1992310879
Short name T288
Test name
Test status
Simulation time 84446300 ps
CPU time 2.83 seconds
Started Aug 23 02:50:31 AM UTC 24
Finished Aug 23 02:50:35 AM UTC 24
Peak memory 217096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992310879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1992310879
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/9.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.421093271
Short name T291
Test name
Test status
Simulation time 1057390346 ps
CPU time 13.37 seconds
Started Aug 23 02:50:23 AM UTC 24
Finished Aug 23 02:50:38 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421093271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.421093271
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/9.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random.1256721173
Short name T93
Test name
Test status
Simulation time 159510281 ps
CPU time 8.43 seconds
Started Aug 23 02:50:00 AM UTC 24
Finished Aug 23 02:50:10 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256721173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.1256721173
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/9.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.3011393003
Short name T131
Test name
Test status
Simulation time 17429857636 ps
CPU time 112.42 seconds
Started Aug 23 02:50:11 AM UTC 24
Finished Aug 23 02:52:06 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011393003 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3011393003
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/9.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1931517202
Short name T315
Test name
Test status
Simulation time 21199887003 ps
CPU time 202.65 seconds
Started Aug 23 02:50:14 AM UTC 24
Finished Aug 23 02:53:41 AM UTC 24
Peak memory 216904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931517202 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1931517202
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/9.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.3740175765
Short name T290
Test name
Test status
Simulation time 323925241 ps
CPU time 25.61 seconds
Started Aug 23 02:50:10 AM UTC 24
Finished Aug 23 02:50:37 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740175765 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.3740175765
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/9.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.3060964668
Short name T294
Test name
Test status
Simulation time 1608718604 ps
CPU time 37.88 seconds
Started Aug 23 02:50:20 AM UTC 24
Finished Aug 23 02:50:59 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060964668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3060964668
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/9.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.2562621490
Short name T283
Test name
Test status
Simulation time 123150429 ps
CPU time 4.87 seconds
Started Aug 23 02:49:50 AM UTC 24
Finished Aug 23 02:49:56 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562621490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2562621490
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/9.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.1458123921
Short name T289
Test name
Test status
Simulation time 6285509383 ps
CPU time 37.14 seconds
Started Aug 23 02:49:57 AM UTC 24
Finished Aug 23 02:50:36 AM UTC 24
Peak memory 217136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458123921 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1458123921
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/9.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2635692162
Short name T287
Test name
Test status
Simulation time 3017404344 ps
CPU time 31.14 seconds
Started Aug 23 02:49:59 AM UTC 24
Finished Aug 23 02:50:32 AM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635692162 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2635692162
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/9.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.286505313
Short name T285
Test name
Test status
Simulation time 28084524 ps
CPU time 3.2 seconds
Started Aug 23 02:49:55 AM UTC 24
Finished Aug 23 02:49:59 AM UTC 24
Peak memory 216740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286505313 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.286505313
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/9.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.3746083874
Short name T130
Test name
Test status
Simulation time 1849351673 ps
CPU time 91.07 seconds
Started Aug 23 02:50:33 AM UTC 24
Finished Aug 23 02:52:06 AM UTC 24
Peak memory 222984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746083874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3746083874
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/9.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.1229961594
Short name T53
Test name
Test status
Simulation time 1844089184 ps
CPU time 194.43 seconds
Started Aug 23 02:50:37 AM UTC 24
Finished Aug 23 02:53:55 AM UTC 24
Peak memory 223352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229961594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1229961594
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/9.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1893047170
Short name T152
Test name
Test status
Simulation time 3917064371 ps
CPU time 422.6 seconds
Started Aug 23 02:50:36 AM UTC 24
Finished Aug 23 02:57:44 AM UTC 24
Peak memory 223676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893047170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.1893047170
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/9.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.4027365555
Short name T248
Test name
Test status
Simulation time 383643961 ps
CPU time 19.73 seconds
Started Aug 23 02:50:27 AM UTC 24
Finished Aug 23 02:50:48 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027365555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.4027365555
Directory /workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/9.xbar_unmapped_addr/latest
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