Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1878	1			T8	2		T19	2		T21	2
all_values[1]	1864	1			T8	1		T19	1		T21	1
all_values[2]	1835	1			T8	2		T19	1		T21	1
all_values[3]	1944	1			T8	3		T19	3		T21	1
all_values[4]	1821	1			T8	1		T19	1		T21	2
all_values[5]	1926	1			T8	1		T22	2		T24	7
all_values[6]	1908	1			T19	3		T21	1		T24	3
all_values[7]	1829	1			T8	2		T19	1		T21	1
all_values[8]	1946	1			T8	3		T19	1		T21	1
all_values[9]	1893	1			T8	2		T19	1		T21	3
all_values[10]	1914	1			T8	2		T19	2		T21	3
all_values[11]	1916	1			T8	4		T19	4		T21	2
all_values[12]	1875	1			T8	4		T19	1		T21	1
all_values[13]	1908	1			T8	3		T21	2		T24	9
all_values[14]	1842	1			T8	2		T19	3		T21	2
all_values[15]	1894	1			T8	3		T19	1		T21	3
all_values[16]	1893	1			T8	1		T19	2		T21	3
all_values[17]	1857	1			T8	1		T19	2		T24	4
all_values[18]	1943	1			T8	3		T19	2		T21	7
all_values[19]	1871	1			T8	2		T24	5		T196	4
all_values[20]	1936	1			T8	2		T19	3		T21	2
all_values[21]	1821	1			T8	2		T19	4		T21	5
all_values[22]	1896	1			T19	1		T21	2		T22	1
all_values[23]	1897	1			T8	1		T19	3		T21	2
all_values[24]	1938	1			T8	2		T19	4		T21	4
all_values[25]	1867	1			T8	2		T19	4		T21	2
all_values[26]	1848	1			T8	5		T19	2		T21	1
all_values[27]	1897	1			T8	6		T19	1		T21	4
all_values[28]	1908	1			T8	2		T19	2		T21	1
all_values[29]	1887	1			T8	1		T19	3		T21	1
all_values[30]	1954	1			T8	3		T19	3		T21	3
all_values[31]	1835	1			T8	3		T21	2		T24	4
all_values[32]	1909	1			T8	1		T19	4		T21	1
all_values[33]	1865	1			T8	1		T19	1		T21	1
all_values[34]	1946	1			T8	2		T19	3		T21	3
all_values[35]	1885	1			T8	1		T19	1		T21	3
all_values[36]	1894	1			T8	2		T19	3		T21	2
all_values[37]	1883	1			T8	4		T19	2		T21	4
all_values[38]	1980	1			T8	2		T19	1		T21	2
all_values[39]	1948	1			T8	3		T19	2		T24	6
all_values[40]	2002	1			T19	1		T21	3		T24	2
all_values[41]	1938	1			T8	6		T21	5		T22	1
all_values[42]	1905	1			T19	1		T21	4		T22	1
all_values[43]	1896	1			T8	3		T19	2		T24	4
all_values[44]	1970	1			T21	2		T22	1		T24	5
all_values[45]	1888	1			T8	1		T19	3		T24	3
all_values[46]	1869	1			T8	6		T19	3		T21	1
all_values[47]	1921	1			T8	2		T19	1		T22	2
all_values[48]	1881	1			T19	1		T22	1		T24	2
all_values[49]	1885	1			T8	3		T19	2		T22	1
all_values[50]	1947	1			T8	4		T19	2		T21	4
all_values[51]	1878	1			T8	2		T21	2		T22	2
all_values[52]	1924	1			T8	2		T21	2		T22	1
all_values[53]	1867	1			T8	1		T19	1		T21	1
all_values[54]	1784	1			T19	1		T21	3		T24	8
all_values[55]	1905	1			T8	4		T19	4		T21	1
all_values[56]	1889	1			T8	1		T19	3		T21	2
all_values[57]	1883	1			T8	1		T21	4		T24	7
all_values[58]	1904	1			T8	1		T19	4		T22	1
all_values[59]	1921	1			T8	2		T19	4		T21	3
all_values[60]	1834	1			T8	2		T19	2		T22	1
all_values[61]	1839	1			T8	1		T21	3		T24	14
all_values[62]	1914	1			T19	1		T21	2		T22	1
all_values[63]	1889	1			T8	7		T19	3		T24	4