Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	24	0	24	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	24	0	24	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	563	1			T47	2		T50	3		T257	3
all_values[1]	505	1			T47	1		T257	2		T99	1
all_values[2]	597	1			T96	2		T257	2		T99	1
all_values[3]	551	1			T47	2		T50	1		T257	2
all_values[4]	539	1			T47	2		T96	1		T257	1
all_values[5]	529	1			T64	1		T50	3		T86	2
all_values[6]	519	1			T96	1		T257	5		T99	1
all_values[7]	531	1			T64	1		T257	2		T166	2
all_values[8]	576	1			T25	1		T50	1		T257	3
all_values[9]	570	1			T99	1		T166	2		T158	4
all_values[10]	510	1			T25	1		T96	1		T50	1
all_values[11]	528	1			T86	1		T257	1		T162	1
all_values[12]	518	1			T64	1		T257	3		T99	1
all_values[13]	508	1			T47	2		T96	1		T257	4
all_values[14]	523	1			T25	1		T47	1		T257	2
all_values[15]	548	1			T86	1		T257	2		T99	1
all_values[16]	528	1			T47	2		T257	1		T99	1
all_values[17]	547	1			T50	1		T257	1		T125	1
all_values[18]	529	1			T64	1		T96	1		T50	1
all_values[19]	563	1			T47	1		T96	1		T50	3
all_values[20]	558	1			T64	1		T25	1		T96	1
all_values[21]	547	1			T96	1		T50	3		T99	1
all_values[22]	547	1			T86	1		T257	4		T125	1
all_values[23]	567	1			T25	2		T47	1		T50	1