Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1940	1			T16	2		T21	1		T182	4
all_values[1]	1929	1			T18	4		T21	2		T50	1
all_values[2]	1902	1			T18	4		T39	2		T95	3
all_values[3]	1931	1			T16	1		T18	1		T21	1
all_values[4]	1912	1			T18	2		T21	2		T39	3
all_values[5]	1955	1			T16	1		T18	4		T21	1
all_values[6]	1911	1			T16	1		T18	1		T21	2
all_values[7]	1850	1			T18	2		T21	2		T182	1
all_values[8]	1849	1			T21	1		T182	1		T39	1
all_values[9]	1948	1			T18	1		T39	1		T50	1
all_values[10]	1992	1			T18	2		T21	1		T182	1
all_values[11]	1879	1			T16	2		T18	2		T21	1
all_values[12]	1906	1			T18	6		T39	3		T50	1
all_values[13]	1876	1			T16	2		T18	2		T21	4
all_values[14]	1997	1			T18	1		T21	3		T39	1
all_values[15]	1865	1			T18	2		T21	1		T182	1
all_values[16]	1960	1			T18	2		T21	3		T39	2
all_values[17]	1947	1			T18	2		T21	1		T182	1
all_values[18]	1969	1			T39	2		T50	3		T257	9
all_values[19]	1952	1			T18	5		T21	1		T39	2
all_values[20]	1925	1			T16	2		T18	2		T39	1
all_values[21]	1865	1			T16	2		T18	1		T39	3
all_values[22]	1895	1			T16	2		T18	2		T21	1
all_values[23]	1966	1			T18	1		T21	2		T39	3
all_values[24]	1947	1			T16	2		T18	2		T21	1
all_values[25]	1952	1			T16	1		T18	1		T21	3
all_values[26]	1880	1			T16	1		T18	2		T21	1
all_values[27]	1925	1			T18	4		T21	1		T182	1
all_values[28]	1981	1			T16	1		T18	3		T21	2
all_values[29]	1914	1			T16	1		T18	2		T39	1
all_values[30]	1930	1			T16	1		T18	1		T21	2
all_values[31]	1912	1			T16	2		T39	2		T50	3
all_values[32]	1936	1			T16	1		T18	3		T21	1
all_values[33]	1879	1			T18	1		T21	1		T182	1
all_values[34]	1896	1			T16	2		T18	1		T21	3
all_values[35]	1910	1			T18	3		T21	1		T39	3
all_values[36]	1831	1			T18	3		T182	1		T39	4
all_values[37]	1940	1			T18	1		T21	1		T39	2
all_values[38]	1990	1			T18	1		T21	2		T182	1
all_values[39]	1956	1			T18	2		T21	4		T182	2
all_values[40]	1957	1			T18	3		T21	2		T39	3
all_values[41]	1872	1			T16	1		T18	1		T21	1
all_values[42]	1995	1			T18	5		T21	1		T39	4
all_values[43]	1982	1			T18	2		T21	2		T182	1
all_values[44]	1972	1			T18	3		T21	3		T39	4
all_values[45]	1914	1			T16	1		T18	1		T21	1
all_values[46]	1898	1			T16	2		T21	3		T182	1
all_values[47]	1969	1			T18	3		T21	1		T39	4
all_values[48]	1950	1			T18	1		T21	3		T182	1
all_values[49]	1902	1			T16	3		T18	2		T21	2
all_values[50]	1883	1			T18	1		T21	1		T182	1
all_values[51]	1853	1			T16	1		T21	1		T182	1
all_values[52]	1947	1			T18	3		T182	1		T39	2
all_values[53]	1988	1			T16	1		T18	3		T21	2
all_values[54]	1951	1			T16	1		T18	3		T21	4
all_values[55]	1894	1			T18	1		T21	1		T182	1
all_values[56]	2071	1			T16	4		T18	3		T21	2
all_values[57]	1973	1			T16	1		T18	4		T21	2
all_values[58]	1951	1			T16	1		T18	1		T21	2
all_values[59]	1991	1			T16	1		T18	2		T182	2
all_values[60]	1908	1			T16	1		T18	2		T21	2
all_values[61]	1981	1			T18	5		T21	3		T182	1
all_values[62]	1941	1			T18	2		T21	1		T182	1
all_values[63]	1894	1			T21	1		T182	4		T39	2