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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.04 99.26 89.02 98.80 95.88 99.26 100.00


Total test records in report: 900
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T769 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.3759881985 Aug 27 03:42:47 AM UTC 24 Aug 27 03:43:05 AM UTC 24 167702565 ps
T770 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2546929863 Aug 27 03:42:55 AM UTC 24 Aug 27 03:43:05 AM UTC 24 53175785 ps
T771 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.3806100301 Aug 27 03:42:52 AM UTC 24 Aug 27 03:43:08 AM UTC 24 598054437 ps
T772 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.2405225797 Aug 27 03:43:05 AM UTC 24 Aug 27 03:43:09 AM UTC 24 63655094 ps
T773 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3745041219 Aug 27 03:43:05 AM UTC 24 Aug 27 03:43:09 AM UTC 24 48893984 ps
T774 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3476902261 Aug 27 03:37:26 AM UTC 24 Aug 27 03:43:13 AM UTC 24 76208994776 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.3767663093 Aug 27 03:41:47 AM UTC 24 Aug 27 03:43:13 AM UTC 24 619257679 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2396890426 Aug 27 03:41:14 AM UTC 24 Aug 27 03:43:17 AM UTC 24 79399126441 ps
T775 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.2838730644 Aug 27 03:43:11 AM UTC 24 Aug 27 03:43:18 AM UTC 24 38720698 ps
T776 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.868239861 Aug 27 03:42:55 AM UTC 24 Aug 27 03:43:19 AM UTC 24 933010627 ps
T777 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3855369869 Aug 27 03:42:39 AM UTC 24 Aug 27 03:43:22 AM UTC 24 2650520406 ps
T778 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.1807863138 Aug 27 03:42:52 AM UTC 24 Aug 27 03:43:22 AM UTC 24 1477726133 ps
T779 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.609915275 Aug 27 03:42:22 AM UTC 24 Aug 27 03:43:27 AM UTC 24 40204544306 ps
T780 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1547772812 Aug 27 03:37:00 AM UTC 24 Aug 27 03:44:03 AM UTC 24 6490333209 ps
T781 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2225434385 Aug 27 03:40:00 AM UTC 24 Aug 27 03:43:27 AM UTC 24 981700893 ps
T782 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3688311399 Aug 27 03:42:11 AM UTC 24 Aug 27 03:43:27 AM UTC 24 22284820143 ps
T783 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.605307913 Aug 27 03:42:47 AM UTC 24 Aug 27 03:43:27 AM UTC 24 6960929335 ps
T784 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.2391638983 Aug 27 03:42:47 AM UTC 24 Aug 27 03:43:29 AM UTC 24 13599429464 ps
T785 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.1320365934 Aug 27 03:42:02 AM UTC 24 Aug 27 03:43:34 AM UTC 24 17091031620 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.215345493 Aug 27 03:41:11 AM UTC 24 Aug 27 03:43:35 AM UTC 24 46202294035 ps
T786 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.4063950731 Aug 27 03:41:24 AM UTC 24 Aug 27 03:43:36 AM UTC 24 1806841495 ps
T787 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3812500126 Aug 27 03:43:33 AM UTC 24 Aug 27 03:43:37 AM UTC 24 100597958 ps
T788 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.3676603778 Aug 27 03:43:33 AM UTC 24 Aug 27 03:43:38 AM UTC 24 170530431 ps
T789 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.1677362084 Aug 27 03:43:22 AM UTC 24 Aug 27 03:43:41 AM UTC 24 1428132889 ps
T790 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1098562083 Aug 27 03:43:08 AM UTC 24 Aug 27 03:43:42 AM UTC 24 5630717549 ps
T791 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3195619247 Aug 27 03:36:28 AM UTC 24 Aug 27 03:43:43 AM UTC 24 229096735353 ps
T792 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.4169058348 Aug 27 03:42:39 AM UTC 24 Aug 27 03:43:44 AM UTC 24 321226622 ps
T793 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.1039001261 Aug 27 03:42:15 AM UTC 24 Aug 27 03:43:47 AM UTC 24 9252568009 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.1502027282 Aug 27 03:43:08 AM UTC 24 Aug 27 03:43:48 AM UTC 24 2116571486 ps
T794 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.2963187385 Aug 27 03:43:22 AM UTC 24 Aug 27 03:43:48 AM UTC 24 2368501279 ps
T795 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.1401287518 Aug 27 03:43:22 AM UTC 24 Aug 27 03:43:48 AM UTC 24 804508979 ps
T796 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.438404261 Aug 27 03:43:25 AM UTC 24 Aug 27 03:43:49 AM UTC 24 1059378875 ps
T797 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.3557236412 Aug 27 03:42:35 AM UTC 24 Aug 27 03:43:52 AM UTC 24 3106280133 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.2084666334 Aug 27 03:43:15 AM UTC 24 Aug 27 03:43:55 AM UTC 24 392138696 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3389787641 Aug 27 03:43:37 AM UTC 24 Aug 27 03:44:03 AM UTC 24 7191920257 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.1555192514 Aug 27 03:43:48 AM UTC 24 Aug 27 03:44:03 AM UTC 24 746367638 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.193662147 Aug 27 03:41:29 AM UTC 24 Aug 27 03:44:06 AM UTC 24 257702017 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3044833896 Aug 27 03:33:20 AM UTC 24 Aug 27 03:44:06 AM UTC 24 98384778409 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1523923580 Aug 27 03:42:52 AM UTC 24 Aug 27 03:44:06 AM UTC 24 6783486446 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.2593050633 Aug 27 03:43:41 AM UTC 24 Aug 27 03:44:08 AM UTC 24 194805358 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2757932252 Aug 27 03:43:55 AM UTC 24 Aug 27 03:44:08 AM UTC 24 440033103 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1031698468 Aug 27 03:43:08 AM UTC 24 Aug 27 03:44:08 AM UTC 24 13296431204 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2024644182 Aug 27 03:44:07 AM UTC 24 Aug 27 03:44:11 AM UTC 24 39862403 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.1591357284 Aug 27 03:43:44 AM UTC 24 Aug 27 03:44:11 AM UTC 24 256181968 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.1121937375 Aug 27 03:43:41 AM UTC 24 Aug 27 03:44:14 AM UTC 24 263866838 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.1980023604 Aug 27 03:44:07 AM UTC 24 Aug 27 03:44:14 AM UTC 24 159114931 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.3323085599 Aug 27 03:43:55 AM UTC 24 Aug 27 03:44:16 AM UTC 24 885881524 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3348100175 Aug 27 03:38:48 AM UTC 24 Aug 27 03:44:18 AM UTC 24 100694846184 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.4057896708 Aug 27 03:44:17 AM UTC 24 Aug 27 03:44:23 AM UTC 24 102728523 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.3675565269 Aug 27 03:39:42 AM UTC 24 Aug 27 03:44:23 AM UTC 24 45798318196 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.198932743 Aug 27 03:43:28 AM UTC 24 Aug 27 03:44:24 AM UTC 24 1009533699 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2243525942 Aug 27 03:43:41 AM UTC 24 Aug 27 03:44:26 AM UTC 24 3223385617 ps
T815 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.2630369160 Aug 27 03:44:17 AM UTC 24 Aug 27 03:44:27 AM UTC 24 183424012 ps
T816 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.1346453028 Aug 27 03:44:21 AM UTC 24 Aug 27 03:44:27 AM UTC 24 134542046 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.2097360273 Aug 27 03:42:28 AM UTC 24 Aug 27 03:44:27 AM UTC 24 20765285494 ps
T818 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.2381568552 Aug 27 03:44:17 AM UTC 24 Aug 27 03:44:27 AM UTC 24 335410018 ps
T819 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.2543357700 Aug 27 03:44:18 AM UTC 24 Aug 27 03:44:30 AM UTC 24 101450229 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.1995436382 Aug 27 03:43:55 AM UTC 24 Aug 27 03:44:31 AM UTC 24 1296393664 ps
T821 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.259425272 Aug 27 03:43:11 AM UTC 24 Aug 27 03:44:32 AM UTC 24 50931074847 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.3854561074 Aug 27 03:42:55 AM UTC 24 Aug 27 03:44:34 AM UTC 24 8117183777 ps
T822 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.3355500566 Aug 27 03:44:31 AM UTC 24 Aug 27 03:44:35 AM UTC 24 29727701 ps
T823 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.1067480518 Aug 27 03:44:31 AM UTC 24 Aug 27 03:44:37 AM UTC 24 284800901 ps
T824 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.1037116144 Aug 27 03:33:52 AM UTC 24 Aug 27 03:44:38 AM UTC 24 84373777784 ps
T825 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.924662015 Aug 27 03:44:17 AM UTC 24 Aug 27 03:44:39 AM UTC 24 187611509 ps
T826 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3692689729 Aug 27 03:41:49 AM UTC 24 Aug 27 03:44:41 AM UTC 24 1272790318 ps
T827 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.1245355589 Aug 27 03:44:21 AM UTC 24 Aug 27 03:44:44 AM UTC 24 629779639 ps
T828 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.434853036 Aug 27 03:43:25 AM UTC 24 Aug 27 03:44:45 AM UTC 24 1480423589 ps
T829 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2579028794 Aug 27 03:42:12 AM UTC 24 Aug 27 03:44:45 AM UTC 24 1829739581 ps
T830 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.2142515093 Aug 27 03:44:31 AM UTC 24 Aug 27 03:44:49 AM UTC 24 152507066 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.1250915378 Aug 27 03:40:02 AM UTC 24 Aug 27 03:44:55 AM UTC 24 7353156919 ps
T831 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2766051187 Aug 27 03:43:28 AM UTC 24 Aug 27 03:44:56 AM UTC 24 3655747133 ps
T832 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1681479955 Aug 27 03:43:48 AM UTC 24 Aug 27 03:44:56 AM UTC 24 9708391299 ps
T833 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.1783425593 Aug 27 03:44:43 AM UTC 24 Aug 27 03:44:56 AM UTC 24 710311997 ps
T834 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3260580240 Aug 27 03:44:17 AM UTC 24 Aug 27 03:44:58 AM UTC 24 3270244768 ps
T835 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.3073932116 Aug 27 03:44:43 AM UTC 24 Aug 27 03:45:00 AM UTC 24 414380326 ps
T836 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.3998901884 Aug 27 03:44:34 AM UTC 24 Aug 27 03:45:04 AM UTC 24 172292831 ps
T837 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.4176176221 Aug 27 03:44:43 AM UTC 24 Aug 27 03:45:04 AM UTC 24 605681636 ps
T838 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3237001849 Aug 27 03:43:33 AM UTC 24 Aug 27 03:45:05 AM UTC 24 255693598 ps
T839 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.2967827591 Aug 27 03:44:45 AM UTC 24 Aug 27 03:45:05 AM UTC 24 384127142 ps
T840 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.4052486567 Aug 27 03:44:38 AM UTC 24 Aug 27 03:45:05 AM UTC 24 2743945954 ps
T841 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.1850645701 Aug 27 03:45:03 AM UTC 24 Aug 27 03:45:06 AM UTC 24 28145521 ps
T842 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2244775828 Aug 27 03:45:03 AM UTC 24 Aug 27 03:45:07 AM UTC 24 34569747 ps
T843 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.2942348076 Aug 27 03:41:24 AM UTC 24 Aug 27 03:45:10 AM UTC 24 9021107691 ps
T844 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.301186917 Aug 27 03:40:34 AM UTC 24 Aug 27 03:45:11 AM UTC 24 68107488696 ps
T845 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.3569663033 Aug 27 03:44:07 AM UTC 24 Aug 27 03:45:14 AM UTC 24 6720615460 ps
T846 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3679932327 Aug 27 03:43:58 AM UTC 24 Aug 27 03:45:17 AM UTC 24 2995272705 ps
T847 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.756178952 Aug 27 03:44:31 AM UTC 24 Aug 27 03:45:19 AM UTC 24 7808891039 ps
T848 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.2048695599 Aug 27 03:45:03 AM UTC 24 Aug 27 03:45:21 AM UTC 24 482660544 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.4183835594 Aug 27 03:30:51 AM UTC 24 Aug 27 03:45:22 AM UTC 24 105704940495 ps
T849 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3425131463 Aug 27 03:44:31 AM UTC 24 Aug 27 03:45:25 AM UTC 24 5544504372 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.2892751170 Aug 27 03:44:23 AM UTC 24 Aug 27 03:45:27 AM UTC 24 4105755571 ps
T850 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.2566340062 Aug 27 03:45:17 AM UTC 24 Aug 27 03:45:32 AM UTC 24 308588716 ps
T851 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.1842613271 Aug 27 03:45:11 AM UTC 24 Aug 27 03:45:35 AM UTC 24 2034194781 ps
T852 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1793171806 Aug 27 03:45:17 AM UTC 24 Aug 27 03:45:38 AM UTC 24 522725430 ps
T853 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.1723039557 Aug 27 03:45:11 AM UTC 24 Aug 27 03:45:42 AM UTC 24 134196507 ps
T854 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2046020685 Aug 27 03:45:03 AM UTC 24 Aug 27 03:45:46 AM UTC 24 2584232196 ps
T855 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.3282629539 Aug 27 03:40:55 AM UTC 24 Aug 27 03:45:46 AM UTC 24 2258097454 ps
T856 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1288327770 Aug 27 03:40:20 AM UTC 24 Aug 27 03:45:46 AM UTC 24 1324114614 ps
T857 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.2131841116 Aug 27 03:45:11 AM UTC 24 Aug 27 03:45:52 AM UTC 24 2526262405 ps
T858 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.1278264911 Aug 27 03:42:11 AM UTC 24 Aug 27 03:45:57 AM UTC 24 6623962122 ps
T859 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.272535822 Aug 27 03:45:03 AM UTC 24 Aug 27 03:45:59 AM UTC 24 6173822935 ps
T860 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.770210734 Aug 27 03:45:21 AM UTC 24 Aug 27 03:46:02 AM UTC 24 255935477 ps
T861 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.4176226517 Aug 27 03:45:17 AM UTC 24 Aug 27 03:46:03 AM UTC 24 144360574 ps
T862 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.4055379980 Aug 27 03:42:47 AM UTC 24 Aug 27 03:46:05 AM UTC 24 96235182332 ps
T863 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.381454287 Aug 27 03:43:05 AM UTC 24 Aug 27 03:46:08 AM UTC 24 5670920523 ps
T864 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.877283801 Aug 27 03:45:03 AM UTC 24 Aug 27 03:46:08 AM UTC 24 8974208801 ps
T865 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3949136944 Aug 27 03:44:26 AM UTC 24 Aug 27 03:46:11 AM UTC 24 6275953820 ps
T866 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.663674461 Aug 27 03:44:49 AM UTC 24 Aug 27 03:46:14 AM UTC 24 2977773564 ps
T867 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.982574951 Aug 27 03:41:35 AM UTC 24 Aug 27 03:46:16 AM UTC 24 95775796316 ps
T868 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.1790283474 Aug 27 03:37:09 AM UTC 24 Aug 27 03:46:20 AM UTC 24 14450837803 ps
T869 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.2426975430 Aug 27 03:43:55 AM UTC 24 Aug 27 03:46:24 AM UTC 24 15008439005 ps
T870 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1614051065 Aug 27 03:43:01 AM UTC 24 Aug 27 03:46:27 AM UTC 24 5763889163 ps
T871 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3591575665 Aug 27 03:42:15 AM UTC 24 Aug 27 03:46:34 AM UTC 24 4048219355 ps
T872 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.3714790792 Aug 27 03:45:17 AM UTC 24 Aug 27 03:46:36 AM UTC 24 1220263186 ps
T873 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.4288263524 Aug 27 03:43:01 AM UTC 24 Aug 27 03:46:37 AM UTC 24 7850322219 ps
T874 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.653581751 Aug 27 03:42:52 AM UTC 24 Aug 27 03:46:53 AM UTC 24 74417463155 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.4055586106 Aug 27 03:43:41 AM UTC 24 Aug 27 03:46:57 AM UTC 24 28516208187 ps
T875 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3392574568 Aug 27 03:43:11 AM UTC 24 Aug 27 03:47:00 AM UTC 24 67378816391 ps
T876 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.2587934767 Aug 27 03:44:17 AM UTC 24 Aug 27 03:47:07 AM UTC 24 92159378401 ps
T877 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3413867031 Aug 27 03:44:38 AM UTC 24 Aug 27 03:47:08 AM UTC 24 48381603067 ps
T878 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2517770921 Aug 27 03:45:19 AM UTC 24 Aug 27 03:47:09 AM UTC 24 3834894086 ps
T879 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.593631257 Aug 27 03:43:44 AM UTC 24 Aug 27 03:47:09 AM UTC 24 26519981743 ps
T880 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.635563548 Aug 27 03:44:45 AM UTC 24 Aug 27 03:47:09 AM UTC 24 8089795880 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2885286389 Aug 27 03:39:28 AM UTC 24 Aug 27 03:47:12 AM UTC 24 5375255923 ps
T881 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.3222694634 Aug 27 03:43:55 AM UTC 24 Aug 27 03:47:13 AM UTC 24 3140512549 ps
T882 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1549593401 Aug 27 03:44:26 AM UTC 24 Aug 27 03:47:17 AM UTC 24 7307655880 ps
T883 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3644498795 Aug 27 03:42:30 AM UTC 24 Aug 27 03:47:19 AM UTC 24 90177294005 ps
T884 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.3649161406 Aug 27 03:40:36 AM UTC 24 Aug 27 03:47:19 AM UTC 24 132081654691 ps
T885 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.638598749 Aug 27 03:40:11 AM UTC 24 Aug 27 03:47:26 AM UTC 24 179557066664 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2100339343 Aug 27 03:41:53 AM UTC 24 Aug 27 03:47:36 AM UTC 24 2008497072 ps
T886 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.3399576858 Aug 27 03:42:26 AM UTC 24 Aug 27 03:47:51 AM UTC 24 91182673199 ps
T887 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.4268792301 Aug 27 03:44:38 AM UTC 24 Aug 27 03:47:53 AM UTC 24 83936200208 ps
T888 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.530658782 Aug 27 03:45:11 AM UTC 24 Aug 27 03:48:03 AM UTC 24 31094133156 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1782048539 Aug 27 03:42:39 AM UTC 24 Aug 27 03:48:18 AM UTC 24 15269217324 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3784677948 Aug 27 03:38:18 AM UTC 24 Aug 27 03:48:26 AM UTC 24 100967700636 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.980164267 Aug 27 03:44:17 AM UTC 24 Aug 27 03:48:30 AM UTC 24 41180099455 ps
T889 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.4028880258 Aug 27 03:45:11 AM UTC 24 Aug 27 03:48:30 AM UTC 24 15729368996 ps
T890 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.4276294834 Aug 27 03:44:34 AM UTC 24 Aug 27 03:49:05 AM UTC 24 243069589354 ps
T891 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2545100235 Aug 27 03:37:48 AM UTC 24 Aug 27 03:49:05 AM UTC 24 129694522532 ps
T892 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1431797573 Aug 27 03:44:26 AM UTC 24 Aug 27 03:49:35 AM UTC 24 811057555 ps
T893 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2515435269 Aug 27 03:43:15 AM UTC 24 Aug 27 03:50:51 AM UTC 24 45763838580 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.921471167 Aug 27 03:43:58 AM UTC 24 Aug 27 03:50:59 AM UTC 24 8479975112 ps
T894 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3057018508 Aug 27 03:44:51 AM UTC 24 Aug 27 03:51:43 AM UTC 24 10196651509 ps
T895 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3207607323 Aug 27 03:44:49 AM UTC 24 Aug 27 03:51:47 AM UTC 24 9823193531 ps
T896 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2947875202 Aug 27 03:44:17 AM UTC 24 Aug 27 03:51:59 AM UTC 24 117591013841 ps
T897 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3183821952 Aug 27 03:41:17 AM UTC 24 Aug 27 03:51:59 AM UTC 24 64461241158 ps
T898 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2673388261 Aug 27 03:45:11 AM UTC 24 Aug 27 03:52:36 AM UTC 24 143408147131 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.2048858414 Aug 27 03:41:43 AM UTC 24 Aug 27 03:53:14 AM UTC 24 97726324518 ps
T899 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.128347598 Aug 27 03:39:46 AM UTC 24 Aug 27 03:57:05 AM UTC 24 465376258052 ps
T900 /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.4030195453 Aug 27 03:42:11 AM UTC 24 Aug 27 04:03:32 AM UTC 24 379126008063 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.3085394517
Short name T7
Test name
Test status
Simulation time 86915869 ps
CPU time 2.9 seconds
Started Aug 27 03:24:32 AM UTC 24
Finished Aug 27 03:24:43 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085394517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3085394517
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/1.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.1561705430
Short name T103
Test name
Test status
Simulation time 5857825177 ps
CPU time 135.52 seconds
Started Aug 27 03:25:04 AM UTC 24
Finished Aug 27 03:27:22 AM UTC 24
Peak memory 219204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561705430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1561705430
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/4.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.3257189208
Short name T308
Test name
Test status
Simulation time 97878526539 ps
CPU time 501.22 seconds
Started Aug 27 03:28:06 AM UTC 24
Finished Aug 27 03:36:33 AM UTC 24
Peak memory 220496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257189208 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.3257189208
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/12.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.83860352
Short name T305
Test name
Test status
Simulation time 40741149175 ps
CPU time 419.46 seconds
Started Aug 27 03:25:28 AM UTC 24
Finished Aug 27 03:32:33 AM UTC 24
Peak memory 218952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83860352 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.83860352
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/6.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3119753636
Short name T13
Test name
Test status
Simulation time 18600362 ps
CPU time 2.77 seconds
Started Aug 27 03:24:44 AM UTC 24
Finished Aug 27 03:24:48 AM UTC 24
Peak memory 216440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119753636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3119753636
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/2.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.84794995
Short name T104
Test name
Test status
Simulation time 4350298971 ps
CPU time 72.88 seconds
Started Aug 27 03:26:12 AM UTC 24
Finished Aug 27 03:27:26 AM UTC 24
Peak memory 218940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84794995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.84794995
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/8.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.2712648456
Short name T96
Test name
Test status
Simulation time 4941434964 ps
CPU time 34.18 seconds
Started Aug 27 03:24:32 AM UTC 24
Finished Aug 27 03:25:15 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712648456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2712648456
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/1.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.151673560
Short name T120
Test name
Test status
Simulation time 62256042887 ps
CPU time 448.38 seconds
Started Aug 27 03:24:32 AM UTC 24
Finished Aug 27 03:32:13 AM UTC 24
Peak memory 220556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151673560 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.151673560
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/1.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1642809261
Short name T143
Test name
Test status
Simulation time 91564000328 ps
CPU time 740.95 seconds
Started Aug 27 03:28:51 AM UTC 24
Finished Aug 27 03:41:21 AM UTC 24
Peak memory 222608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642809261 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.1642809261
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/14.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.3489641116
Short name T4
Test name
Test status
Simulation time 411413350 ps
CPU time 21.21 seconds
Started Aug 27 03:26:43 AM UTC 24
Finished Aug 27 03:27:05 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489641116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3489641116
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/9.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.2422021971
Short name T29
Test name
Test status
Simulation time 1698032770 ps
CPU time 15.08 seconds
Started Aug 27 03:24:28 AM UTC 24
Finished Aug 27 03:24:57 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422021971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.2422021971
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/0.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.2047732182
Short name T257
Test name
Test status
Simulation time 192896205 ps
CPU time 67.7 seconds
Started Aug 27 03:24:32 AM UTC 24
Finished Aug 27 03:25:48 AM UTC 24
Peak memory 220404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047732182 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.2047732182
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/0.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.1656859927
Short name T9
Test name
Test status
Simulation time 2165601376 ps
CPU time 13.14 seconds
Started Aug 27 03:24:26 AM UTC 24
Finished Aug 27 03:24:54 AM UTC 24
Peak memory 216892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656859927 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1656859927
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/0.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3068377087
Short name T115
Test name
Test status
Simulation time 23779927933 ps
CPU time 231.81 seconds
Started Aug 27 03:24:44 AM UTC 24
Finished Aug 27 03:28:39 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068377087 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.3068377087
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/2.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.3045032280
Short name T99
Test name
Test status
Simulation time 1392545102 ps
CPU time 51.68 seconds
Started Aug 27 03:25:00 AM UTC 24
Finished Aug 27 03:25:53 AM UTC 24
Peak memory 218820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045032280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.3045032280
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/4.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2918354603
Short name T309
Test name
Test status
Simulation time 2071139455 ps
CPU time 319.27 seconds
Started Aug 27 03:25:38 AM UTC 24
Finished Aug 27 03:31:02 AM UTC 24
Peak memory 233852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918354603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.2918354603
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/6.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.3868594086
Short name T14
Test name
Test status
Simulation time 184955131 ps
CPU time 5.46 seconds
Started Aug 27 03:24:44 AM UTC 24
Finished Aug 27 03:24:50 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868594086 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3868594086
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/2.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random.1053290737
Short name T30
Test name
Test status
Simulation time 1007408550 ps
CPU time 15.35 seconds
Started Aug 27 03:24:44 AM UTC 24
Finished Aug 27 03:25:00 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053290737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.1053290737
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/2.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.3122758857
Short name T310
Test name
Test status
Simulation time 2669991457 ps
CPU time 317.06 seconds
Started Aug 27 03:24:41 AM UTC 24
Finished Aug 27 03:30:03 AM UTC 24
Peak memory 233592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122758857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.3122758857
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/1.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.189116238
Short name T32
Test name
Test status
Simulation time 28149927055 ps
CPU time 131.44 seconds
Started Aug 27 03:25:08 AM UTC 24
Finished Aug 27 03:27:21 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189116238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.189116238
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/4.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.2173357775
Short name T178
Test name
Test status
Simulation time 7451515674 ps
CPU time 152.85 seconds
Started Aug 27 03:35:11 AM UTC 24
Finished Aug 27 03:37:47 AM UTC 24
Peak memory 220992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173357775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2173357775
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/27.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.281778653
Short name T56
Test name
Test status
Simulation time 8238757465 ps
CPU time 245.04 seconds
Started Aug 27 03:34:13 AM UTC 24
Finished Aug 27 03:38:22 AM UTC 24
Peak memory 235700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281778653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.281778653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/25.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.1552356445
Short name T42
Test name
Test status
Simulation time 9582847060 ps
CPU time 568.65 seconds
Started Aug 27 03:25:09 AM UTC 24
Finished Aug 27 03:34:45 AM UTC 24
Peak memory 237320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552356445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.1552356445
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/4.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.3210351240
Short name T33
Test name
Test status
Simulation time 5632923445 ps
CPU time 212.17 seconds
Started Aug 27 03:24:28 AM UTC 24
Finished Aug 27 03:28:16 AM UTC 24
Peak memory 224448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210351240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.3210351240
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/0.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2100339343
Short name T36
Test name
Test status
Simulation time 2008497072 ps
CPU time 338.8 seconds
Started Aug 27 03:41:53 AM UTC 24
Finished Aug 27 03:47:36 AM UTC 24
Peak memory 233592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100339343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.2100339343
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/41.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random.3143497699
Short name T102
Test name
Test status
Simulation time 6512418052 ps
CPU time 44.32 seconds
Started Aug 27 03:26:02 AM UTC 24
Finished Aug 27 03:26:48 AM UTC 24
Peak memory 219204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143497699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.3143497699
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/8.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.1931488174
Short name T52
Test name
Test status
Simulation time 562877012 ps
CPU time 380.06 seconds
Started Aug 27 03:35:12 AM UTC 24
Finished Aug 27 03:41:37 AM UTC 24
Peak memory 220936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931488174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.1931488174
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/27.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.1250915378
Short name T54
Test name
Test status
Simulation time 7353156919 ps
CPU time 289.02 seconds
Started Aug 27 03:40:02 AM UTC 24
Finished Aug 27 03:44:55 AM UTC 24
Peak memory 233656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250915378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.1250915378
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/37.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.1153571602
Short name T49
Test name
Test status
Simulation time 5806617112 ps
CPU time 388.31 seconds
Started Aug 27 03:26:23 AM UTC 24
Finished Aug 27 03:32:57 AM UTC 24
Peak memory 233592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153571602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.1153571602
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/8.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.819992059
Short name T187
Test name
Test status
Simulation time 19364841535 ps
CPU time 49.06 seconds
Started Aug 27 03:24:32 AM UTC 24
Finished Aug 27 03:25:30 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819992059 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.819992059
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/1.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3616148623
Short name T146
Test name
Test status
Simulation time 84213168833 ps
CPU time 771.83 seconds
Started Aug 27 03:29:38 AM UTC 24
Finished Aug 27 03:42:38 AM UTC 24
Peak memory 222544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616148623 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.3616148623
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/16.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.1459274603
Short name T3
Test name
Test status
Simulation time 56916984 ps
CPU time 1.83 seconds
Started Aug 27 03:24:26 AM UTC 24
Finished Aug 27 03:24:42 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459274603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1459274603
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/0.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.1113804448
Short name T47
Test name
Test status
Simulation time 437517552 ps
CPU time 29.87 seconds
Started Aug 27 03:24:26 AM UTC 24
Finished Aug 27 03:25:11 AM UTC 24
Peak memory 217096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113804448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.1113804448
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/0.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2588951328
Short name T697
Test name
Test status
Simulation time 546808488349 ps
CPU time 987.7 seconds
Started Aug 27 03:24:26 AM UTC 24
Finished Aug 27 03:41:18 AM UTC 24
Peak memory 222612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588951328 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.2588951328
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/0.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.4153088
Short name T17
Test name
Test status
Simulation time 94450439 ps
CPU time 10.61 seconds
Started Aug 27 03:24:27 AM UTC 24
Finished Aug 27 03:24:52 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_
TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.4153088
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/0.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random.3008825324
Short name T24
Test name
Test status
Simulation time 862161945 ps
CPU time 25.91 seconds
Started Aug 27 03:24:26 AM UTC 24
Finished Aug 27 03:25:07 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008825324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3008825324
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/0.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1607315228
Short name T216
Test name
Test status
Simulation time 48381804758 ps
CPU time 148.78 seconds
Started Aug 27 03:24:26 AM UTC 24
Finished Aug 27 03:27:11 AM UTC 24
Peak memory 218516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607315228 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1607315228
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/0.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.3781657608
Short name T23
Test name
Test status
Simulation time 237600314 ps
CPU time 23.3 seconds
Started Aug 27 03:24:26 AM UTC 24
Finished Aug 27 03:25:04 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781657608 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3781657608
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/0.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.2994574056
Short name T21
Test name
Test status
Simulation time 1147607359 ps
CPU time 21.65 seconds
Started Aug 27 03:24:26 AM UTC 24
Finished Aug 27 03:25:03 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994574056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2994574056
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/0.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.210581811
Short name T185
Test name
Test status
Simulation time 7608575028 ps
CPU time 32.13 seconds
Started Aug 27 03:24:26 AM UTC 24
Finished Aug 27 03:25:13 AM UTC 24
Peak memory 217260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210581811 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.210581811
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/0.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1670109622
Short name T298
Test name
Test status
Simulation time 10209861027 ps
CPU time 41.06 seconds
Started Aug 27 03:24:26 AM UTC 24
Finished Aug 27 03:25:22 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670109622 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1670109622
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/0.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.1161772214
Short name T10
Test name
Test status
Simulation time 117480868 ps
CPU time 2.04 seconds
Started Aug 27 03:24:26 AM UTC 24
Finished Aug 27 03:24:43 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161772214 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1161772214
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/0.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.1462329689
Short name T101
Test name
Test status
Simulation time 2818814106 ps
CPU time 108.33 seconds
Started Aug 27 03:24:28 AM UTC 24
Finished Aug 27 03:26:31 AM UTC 24
Peak memory 220980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462329689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1462329689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/0.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.4273195935
Short name T133
Test name
Test status
Simulation time 19790800646 ps
CPU time 304.13 seconds
Started Aug 27 03:24:28 AM UTC 24
Finished Aug 27 03:29:47 AM UTC 24
Peak memory 222540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273195935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.4273195935
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/0.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.2019290681
Short name T20
Test name
Test status
Simulation time 1800863119 ps
CPU time 17.02 seconds
Started Aug 27 03:24:27 AM UTC 24
Finished Aug 27 03:24:59 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019290681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2019290681
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/0.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1363692143
Short name T22
Test name
Test status
Simulation time 762253115 ps
CPU time 23.45 seconds
Started Aug 27 03:24:36 AM UTC 24
Finished Aug 27 03:25:04 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363692143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1363692143
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/1.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.3731502381
Short name T31
Test name
Test status
Simulation time 596723433 ps
CPU time 22.21 seconds
Started Aug 27 03:24:32 AM UTC 24
Finished Aug 27 03:25:03 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731502381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.3731502381
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/1.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random.2271018313
Short name T97
Test name
Test status
Simulation time 1369997870 ps
CPU time 43.61 seconds
Started Aug 27 03:24:32 AM UTC 24
Finished Aug 27 03:25:24 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271018313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.2271018313
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/1.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2100288
Short name T170
Test name
Test status
Simulation time 20646729529 ps
CPU time 109.76 seconds
Started Aug 27 03:24:32 AM UTC 24
Finished Aug 27 03:26:31 AM UTC 24
Peak memory 217160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100288 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2100288
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/1.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.273340862
Short name T19
Test name
Test status
Simulation time 285059323 ps
CPU time 16.38 seconds
Started Aug 27 03:24:32 AM UTC 24
Finished Aug 27 03:24:56 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273340862 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.273340862
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/1.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.3708423538
Short name T18
Test name
Test status
Simulation time 175195982 ps
CPU time 12.34 seconds
Started Aug 27 03:24:32 AM UTC 24
Finished Aug 27 03:24:53 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708423538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3708423538
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/1.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.2867821366
Short name T2
Test name
Test status
Simulation time 32876393 ps
CPU time 2.07 seconds
Started Aug 27 03:24:32 AM UTC 24
Finished Aug 27 03:24:42 AM UTC 24
Peak memory 216420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867821366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2867821366
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/1.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1014598794
Short name T183
Test name
Test status
Simulation time 11501244331 ps
CPU time 30.79 seconds
Started Aug 27 03:24:32 AM UTC 24
Finished Aug 27 03:25:11 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014598794 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1014598794
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/1.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.706081149
Short name T314
Test name
Test status
Simulation time 5979823525 ps
CPU time 38.73 seconds
Started Aug 27 03:24:32 AM UTC 24
Finished Aug 27 03:25:19 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706081149 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.706081149
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/1.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1233925207
Short name T1
Test name
Test status
Simulation time 68126460 ps
CPU time 1.97 seconds
Started Aug 27 03:24:32 AM UTC 24
Finished Aug 27 03:24:42 AM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233925207 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1233925207
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/1.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.2583596015
Short name T118
Test name
Test status
Simulation time 15412144468 ps
CPU time 346.3 seconds
Started Aug 27 03:24:36 AM UTC 24
Finished Aug 27 03:30:31 AM UTC 24
Peak memory 223488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583596015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2583596015
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/1.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2963438572
Short name T37
Test name
Test status
Simulation time 6983940797 ps
CPU time 151.11 seconds
Started Aug 27 03:24:38 AM UTC 24
Finished Aug 27 03:27:13 AM UTC 24
Peak memory 218940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963438572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2963438572
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/1.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.3829340933
Short name T50
Test name
Test status
Simulation time 167362287 ps
CPU time 54.38 seconds
Started Aug 27 03:24:36 AM UTC 24
Finished Aug 27 03:25:35 AM UTC 24
Peak memory 218876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829340933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.3829340933
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/1.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.4281335190
Short name T224
Test name
Test status
Simulation time 3854772066 ps
CPU time 51.71 seconds
Started Aug 27 03:27:05 AM UTC 24
Finished Aug 27 03:27:59 AM UTC 24
Peak memory 219208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281335190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.4281335190
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/10.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1190469752
Short name T297
Test name
Test status
Simulation time 14232662242 ps
CPU time 89.43 seconds
Started Aug 27 03:27:05 AM UTC 24
Finished Aug 27 03:28:37 AM UTC 24
Peak memory 218944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190469752 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.1190469752
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/10.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.4258907120
Short name T325
Test name
Test status
Simulation time 109959707 ps
CPU time 3.26 seconds
Started Aug 27 03:27:10 AM UTC 24
Finished Aug 27 03:27:14 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258907120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.4258907120
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/10.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.2690404267
Short name T330
Test name
Test status
Simulation time 608214103 ps
CPU time 11.73 seconds
Started Aug 27 03:27:06 AM UTC 24
Finished Aug 27 03:27:20 AM UTC 24
Peak memory 217080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690404267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2690404267
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/10.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random.486240299
Short name T321
Test name
Test status
Simulation time 100989967 ps
CPU time 8.93 seconds
Started Aug 27 03:26:55 AM UTC 24
Finished Aug 27 03:27:05 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486240299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.486240299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/10.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.1863624741
Short name T415
Test name
Test status
Simulation time 234254065590 ps
CPU time 299.39 seconds
Started Aug 27 03:27:03 AM UTC 24
Finished Aug 27 03:32:06 AM UTC 24
Peak memory 217160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863624741 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1863624741
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/10.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3722065999
Short name T218
Test name
Test status
Simulation time 11797600311 ps
CPU time 62.76 seconds
Started Aug 27 03:27:04 AM UTC 24
Finished Aug 27 03:28:09 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722065999 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3722065999
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/10.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.1895222824
Short name T327
Test name
Test status
Simulation time 132376900 ps
CPU time 21.15 seconds
Started Aug 27 03:26:55 AM UTC 24
Finished Aug 27 03:27:17 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895222824 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.1895222824
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/10.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.3863508525
Short name T160
Test name
Test status
Simulation time 1101395072 ps
CPU time 16.93 seconds
Started Aug 27 03:27:05 AM UTC 24
Finished Aug 27 03:27:24 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863508525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3863508525
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/10.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.890645594
Short name T265
Test name
Test status
Simulation time 243181953 ps
CPU time 4.62 seconds
Started Aug 27 03:26:48 AM UTC 24
Finished Aug 27 03:26:54 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890645594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.890645594
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/10.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1843718932
Short name T206
Test name
Test status
Simulation time 5394528742 ps
CPU time 58.77 seconds
Started Aug 27 03:26:50 AM UTC 24
Finished Aug 27 03:27:51 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843718932 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1843718932
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/10.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.758087311
Short name T129
Test name
Test status
Simulation time 8399162596 ps
CPU time 39.93 seconds
Started Aug 27 03:26:54 AM UTC 24
Finished Aug 27 03:27:35 AM UTC 24
Peak memory 217200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758087311 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.758087311
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/10.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3879161902
Short name T263
Test name
Test status
Simulation time 33618687 ps
CPU time 3.02 seconds
Started Aug 27 03:26:48 AM UTC 24
Finished Aug 27 03:26:52 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879161902 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3879161902
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/10.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.2950812415
Short name T110
Test name
Test status
Simulation time 21574166766 ps
CPU time 136.34 seconds
Started Aug 27 03:27:12 AM UTC 24
Finished Aug 27 03:29:31 AM UTC 24
Peak memory 220928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950812415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2950812415
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/10.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.1436523539
Short name T307
Test name
Test status
Simulation time 1023442411 ps
CPU time 126.16 seconds
Started Aug 27 03:27:13 AM UTC 24
Finished Aug 27 03:29:22 AM UTC 24
Peak memory 223240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436523539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1436523539
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/10.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.154455209
Short name T233
Test name
Test status
Simulation time 1221360410 ps
CPU time 469.78 seconds
Started Aug 27 03:27:13 AM UTC 24
Finished Aug 27 03:35:09 AM UTC 24
Peak memory 224592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154455209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.154455209
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/10.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.3052568060
Short name T61
Test name
Test status
Simulation time 587865548 ps
CPU time 110.27 seconds
Started Aug 27 03:27:13 AM UTC 24
Finished Aug 27 03:29:06 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052568060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.3052568060
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/10.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.3638630599
Short name T326
Test name
Test status
Simulation time 64953846 ps
CPU time 6.71 seconds
Started Aug 27 03:27:08 AM UTC 24
Finished Aug 27 03:27:16 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638630599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3638630599
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/10.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.1830652838
Short name T106
Test name
Test status
Simulation time 3722221768 ps
CPU time 41.63 seconds
Started Aug 27 03:27:22 AM UTC 24
Finished Aug 27 03:28:05 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830652838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.1830652838
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/11.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.3269283553
Short name T300
Test name
Test status
Simulation time 30206095289 ps
CPU time 278.23 seconds
Started Aug 27 03:27:23 AM UTC 24
Finished Aug 27 03:32:05 AM UTC 24
Peak memory 218940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269283553 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.3269283553
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/11.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.760628990
Short name T5
Test name
Test status
Simulation time 119994350 ps
CPU time 6.95 seconds
Started Aug 27 03:27:37 AM UTC 24
Finished Aug 27 03:27:45 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760628990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.760628990
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/11.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.2302041412
Short name T270
Test name
Test status
Simulation time 1546798636 ps
CPU time 26.49 seconds
Started Aug 27 03:27:27 AM UTC 24
Finished Aug 27 03:27:55 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302041412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2302041412
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/11.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random.4204827139
Short name T215
Test name
Test status
Simulation time 1265746691 ps
CPU time 46.95 seconds
Started Aug 27 03:27:19 AM UTC 24
Finished Aug 27 03:28:07 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204827139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.4204827139
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/11.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.2689723232
Short name T114
Test name
Test status
Simulation time 13152898301 ps
CPU time 51.8 seconds
Started Aug 27 03:27:20 AM UTC 24
Finished Aug 27 03:28:13 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689723232 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2689723232
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/11.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3805460824
Short name T366
Test name
Test status
Simulation time 23267736391 ps
CPU time 174.42 seconds
Started Aug 27 03:27:21 AM UTC 24
Finished Aug 27 03:30:19 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805460824 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3805460824
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/11.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.2331264669
Short name T205
Test name
Test status
Simulation time 203169644 ps
CPU time 20.35 seconds
Started Aug 27 03:27:20 AM UTC 24
Finished Aug 27 03:27:42 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331264669 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2331264669
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/11.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.2938122649
Short name T203
Test name
Test status
Simulation time 374956056 ps
CPU time 10.38 seconds
Started Aug 27 03:27:24 AM UTC 24
Finished Aug 27 03:27:36 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938122649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2938122649
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/11.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.16876477
Short name T328
Test name
Test status
Simulation time 33599095 ps
CPU time 2.82 seconds
Started Aug 27 03:27:14 AM UTC 24
Finished Aug 27 03:27:18 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16876477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs
/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.16876477
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/11.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.3747877981
Short name T333
Test name
Test status
Simulation time 4921524690 ps
CPU time 52.66 seconds
Started Aug 27 03:27:16 AM UTC 24
Finished Aug 27 03:28:11 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747877981 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3747877981
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/11.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.15824794
Short name T230
Test name
Test status
Simulation time 11637865400 ps
CPU time 58.62 seconds
Started Aug 27 03:27:18 AM UTC 24
Finished Aug 27 03:28:18 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15824794 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.15824794
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/11.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.3352836672
Short name T329
Test name
Test status
Simulation time 64366139 ps
CPU time 2.29 seconds
Started Aug 27 03:27:15 AM UTC 24
Finished Aug 27 03:27:19 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352836672 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.3352836672
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/11.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.1064063104
Short name T235
Test name
Test status
Simulation time 401004942 ps
CPU time 13.82 seconds
Started Aug 27 03:27:40 AM UTC 24
Finished Aug 27 03:27:55 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064063104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1064063104
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/11.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2340951313
Short name T59
Test name
Test status
Simulation time 6013218306 ps
CPU time 199.98 seconds
Started Aug 27 03:27:45 AM UTC 24
Finished Aug 27 03:31:09 AM UTC 24
Peak memory 223044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340951313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2340951313
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/11.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.2686797389
Short name T362
Test name
Test status
Simulation time 172547628 ps
CPU time 141.6 seconds
Started Aug 27 03:27:43 AM UTC 24
Finished Aug 27 03:30:07 AM UTC 24
Peak memory 220936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686797389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.2686797389
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/11.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1249903559
Short name T194
Test name
Test status
Simulation time 2650276457 ps
CPU time 63.04 seconds
Started Aug 27 03:27:47 AM UTC 24
Finished Aug 27 03:28:52 AM UTC 24
Peak memory 216904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249903559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.1249903559
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/11.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.1881803042
Short name T200
Test name
Test status
Simulation time 465641663 ps
CPU time 21.59 seconds
Started Aug 27 03:27:36 AM UTC 24
Finished Aug 27 03:27:59 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881803042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1881803042
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/11.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.2382350779
Short name T241
Test name
Test status
Simulation time 2568623329 ps
CPU time 26.22 seconds
Started Aug 27 03:28:05 AM UTC 24
Finished Aug 27 03:28:33 AM UTC 24
Peak memory 218952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382350779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2382350779
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/12.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.122094321
Short name T249
Test name
Test status
Simulation time 189043820 ps
CPU time 5.38 seconds
Started Aug 27 03:28:12 AM UTC 24
Finished Aug 27 03:28:18 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122094321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.122094321
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/12.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.2541630407
Short name T338
Test name
Test status
Simulation time 408272281 ps
CPU time 21.19 seconds
Started Aug 27 03:28:10 AM UTC 24
Finished Aug 27 03:28:32 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541630407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.2541630407
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/12.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random.4077117942
Short name T248
Test name
Test status
Simulation time 338215069 ps
CPU time 15.22 seconds
Started Aug 27 03:28:00 AM UTC 24
Finished Aug 27 03:28:16 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077117942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.4077117942
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/12.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.3217083908
Short name T365
Test name
Test status
Simulation time 21469252789 ps
CPU time 132.28 seconds
Started Aug 27 03:28:00 AM UTC 24
Finished Aug 27 03:30:14 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217083908 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3217083908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/12.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.4229438981
Short name T351
Test name
Test status
Simulation time 11385659009 ps
CPU time 80.3 seconds
Started Aug 27 03:28:01 AM UTC 24
Finished Aug 27 03:29:23 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229438981 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.4229438981
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/12.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.1340008626
Short name T341
Test name
Test status
Simulation time 172710169 ps
CPU time 34.01 seconds
Started Aug 27 03:28:00 AM UTC 24
Finished Aug 27 03:28:35 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340008626 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.1340008626
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/12.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.4111095273
Short name T336
Test name
Test status
Simulation time 157929820 ps
CPU time 13.39 seconds
Started Aug 27 03:28:08 AM UTC 24
Finished Aug 27 03:28:23 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111095273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.4111095273
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/12.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.3269719034
Short name T70
Test name
Test status
Simulation time 731456664 ps
CPU time 6.43 seconds
Started Aug 27 03:27:51 AM UTC 24
Finished Aug 27 03:27:59 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269719034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3269719034
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/12.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.622860705
Short name T337
Test name
Test status
Simulation time 3681585680 ps
CPU time 27.2 seconds
Started Aug 27 03:27:57 AM UTC 24
Finished Aug 27 03:28:25 AM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622860705 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.622860705
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/12.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.390139708
Short name T340
Test name
Test status
Simulation time 10699301692 ps
CPU time 32.55 seconds
Started Aug 27 03:28:00 AM UTC 24
Finished Aug 27 03:28:34 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390139708 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.390139708
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/12.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.1945956301
Short name T331
Test name
Test status
Simulation time 26110648 ps
CPU time 3.43 seconds
Started Aug 27 03:27:56 AM UTC 24
Finished Aug 27 03:28:00 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945956301 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.1945956301
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/12.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.3946095451
Short name T207
Test name
Test status
Simulation time 2655279986 ps
CPU time 148.74 seconds
Started Aug 27 03:28:13 AM UTC 24
Finished Aug 27 03:30:44 AM UTC 24
Peak memory 223040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946095451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3946095451
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/12.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.1834087262
Short name T384
Test name
Test status
Simulation time 1038479599 ps
CPU time 152.16 seconds
Started Aug 27 03:28:14 AM UTC 24
Finished Aug 27 03:30:49 AM UTC 24
Peak memory 222980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834087262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1834087262
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/12.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1660252315
Short name T281
Test name
Test status
Simulation time 2121835463 ps
CPU time 455.4 seconds
Started Aug 27 03:28:14 AM UTC 24
Finished Aug 27 03:35:56 AM UTC 24
Peak memory 233972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660252315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.1660252315
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/12.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3657988750
Short name T312
Test name
Test status
Simulation time 3767203708 ps
CPU time 264.72 seconds
Started Aug 27 03:28:17 AM UTC 24
Finished Aug 27 03:32:45 AM UTC 24
Peak memory 233660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657988750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.3657988750
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/12.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.2072474519
Short name T71
Test name
Test status
Simulation time 575976194 ps
CPU time 10.47 seconds
Started Aug 27 03:28:12 AM UTC 24
Finished Aug 27 03:28:24 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072474519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2072474519
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/12.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.3569182466
Short name T108
Test name
Test status
Simulation time 5159026290 ps
CPU time 57.72 seconds
Started Aug 27 03:28:24 AM UTC 24
Finished Aug 27 03:29:23 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569182466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.3569182466
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/13.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.1914998688
Short name T296
Test name
Test status
Simulation time 17798798845 ps
CPU time 164.8 seconds
Started Aug 27 03:28:25 AM UTC 24
Finished Aug 27 03:31:12 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914998688 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.1914998688
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/13.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.1741504352
Short name T193
Test name
Test status
Simulation time 179350582 ps
CPU time 16.04 seconds
Started Aug 27 03:28:33 AM UTC 24
Finished Aug 27 03:28:51 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741504352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.1741504352
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/13.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.3792816670
Short name T342
Test name
Test status
Simulation time 867001174 ps
CPU time 31.23 seconds
Started Aug 27 03:28:33 AM UTC 24
Finished Aug 27 03:29:06 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792816670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3792816670
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/13.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random.1966020038
Short name T271
Test name
Test status
Simulation time 381435002 ps
CPU time 19.73 seconds
Started Aug 27 03:28:18 AM UTC 24
Finished Aug 27 03:28:39 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966020038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.1966020038
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/13.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.101143262
Short name T78
Test name
Test status
Simulation time 173691620010 ps
CPU time 209.36 seconds
Started Aug 27 03:28:22 AM UTC 24
Finished Aug 27 03:31:54 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101143262 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.101143262
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/13.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2064243316
Short name T79
Test name
Test status
Simulation time 43710649300 ps
CPU time 284.35 seconds
Started Aug 27 03:28:23 AM UTC 24
Finished Aug 27 03:33:11 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064243316 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2064243316
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/13.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.768189852
Short name T272
Test name
Test status
Simulation time 129193215 ps
CPU time 20.78 seconds
Started Aug 27 03:28:19 AM UTC 24
Finished Aug 27 03:28:41 AM UTC 24
Peak memory 217152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768189852 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.768189852
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/13.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.1549751486
Short name T116
Test name
Test status
Simulation time 3943229321 ps
CPU time 33.8 seconds
Started Aug 27 03:28:26 AM UTC 24
Finished Aug 27 03:29:01 AM UTC 24
Peak memory 216892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549751486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1549751486
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/13.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.3118766327
Short name T335
Test name
Test status
Simulation time 184920167 ps
CPU time 3.95 seconds
Started Aug 27 03:28:17 AM UTC 24
Finished Aug 27 03:28:22 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118766327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.3118766327
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/13.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.1435240495
Short name T196
Test name
Test status
Simulation time 6862140952 ps
CPU time 35.84 seconds
Started Aug 27 03:28:17 AM UTC 24
Finished Aug 27 03:28:54 AM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435240495 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.1435240495
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/13.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2637331961
Short name T195
Test name
Test status
Simulation time 7207099439 ps
CPU time 33.99 seconds
Started Aug 27 03:28:18 AM UTC 24
Finished Aug 27 03:28:54 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637331961 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2637331961
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/13.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.2748292364
Short name T334
Test name
Test status
Simulation time 35174953 ps
CPU time 2.46 seconds
Started Aug 27 03:28:17 AM UTC 24
Finished Aug 27 03:28:20 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748292364 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.2748292364
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/13.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.503154889
Short name T373
Test name
Test status
Simulation time 744493664 ps
CPU time 118.53 seconds
Started Aug 27 03:28:33 AM UTC 24
Finished Aug 27 03:30:34 AM UTC 24
Peak memory 220864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503154889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.503154889
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/13.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2315199990
Short name T379
Test name
Test status
Simulation time 20722876413 ps
CPU time 125.34 seconds
Started Aug 27 03:28:36 AM UTC 24
Finished Aug 27 03:30:44 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315199990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2315199990
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/13.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1305234537
Short name T410
Test name
Test status
Simulation time 2935305317 ps
CPU time 199.35 seconds
Started Aug 27 03:28:35 AM UTC 24
Finished Aug 27 03:31:57 AM UTC 24
Peak memory 223116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305234537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.1305234537
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/13.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.4245484141
Short name T304
Test name
Test status
Simulation time 8076395638 ps
CPU time 197.92 seconds
Started Aug 27 03:28:36 AM UTC 24
Finished Aug 27 03:31:57 AM UTC 24
Peak memory 223376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245484141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.4245484141
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/13.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.3821166819
Short name T274
Test name
Test status
Simulation time 185961338 ps
CPU time 7.92 seconds
Started Aug 27 03:28:33 AM UTC 24
Finished Aug 27 03:28:42 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821166819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3821166819
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/13.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.4135167521
Short name T74
Test name
Test status
Simulation time 608899282 ps
CPU time 47.27 seconds
Started Aug 27 03:28:51 AM UTC 24
Finished Aug 27 03:29:40 AM UTC 24
Peak memory 218888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135167521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.4135167521
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/14.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.1393033596
Short name T348
Test name
Test status
Simulation time 116476947 ps
CPU time 17.04 seconds
Started Aug 27 03:28:55 AM UTC 24
Finished Aug 27 03:29:14 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393033596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.1393033596
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/14.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.3603502081
Short name T197
Test name
Test status
Simulation time 70845540 ps
CPU time 4.61 seconds
Started Aug 27 03:28:53 AM UTC 24
Finished Aug 27 03:28:59 AM UTC 24
Peak memory 217076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603502081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3603502081
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/14.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random.3854597710
Short name T107
Test name
Test status
Simulation time 2100828656 ps
CPU time 27.33 seconds
Started Aug 27 03:28:42 AM UTC 24
Finished Aug 27 03:29:11 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854597710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.3854597710
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/14.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.2134250137
Short name T416
Test name
Test status
Simulation time 111576851627 ps
CPU time 202.54 seconds
Started Aug 27 03:28:45 AM UTC 24
Finished Aug 27 03:32:10 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134250137 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2134250137
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/14.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3794918548
Short name T344
Test name
Test status
Simulation time 2310148617 ps
CPU time 19.97 seconds
Started Aug 27 03:28:49 AM UTC 24
Finished Aug 27 03:29:10 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794918548 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3794918548
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/14.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.441249994
Short name T276
Test name
Test status
Simulation time 21250030 ps
CPU time 3.25 seconds
Started Aug 27 03:28:44 AM UTC 24
Finished Aug 27 03:28:48 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441249994 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.441249994
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/14.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.1134281745
Short name T349
Test name
Test status
Simulation time 431994872 ps
CPU time 21.59 seconds
Started Aug 27 03:28:52 AM UTC 24
Finished Aug 27 03:29:15 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134281745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1134281745
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/14.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.2446526033
Short name T273
Test name
Test status
Simulation time 52749507 ps
CPU time 2.78 seconds
Started Aug 27 03:28:38 AM UTC 24
Finished Aug 27 03:28:42 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446526033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2446526033
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/14.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.460847230
Short name T346
Test name
Test status
Simulation time 13676418864 ps
CPU time 30.22 seconds
Started Aug 27 03:28:40 AM UTC 24
Finished Aug 27 03:29:12 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460847230 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.460847230
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/14.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.3927733946
Short name T72
Test name
Test status
Simulation time 13539340565 ps
CPU time 34.3 seconds
Started Aug 27 03:28:42 AM UTC 24
Finished Aug 27 03:29:18 AM UTC 24
Peak memory 216804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927733946 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.3927733946
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/14.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.4156383308
Short name T275
Test name
Test status
Simulation time 43699421 ps
CPU time 2.83 seconds
Started Aug 27 03:28:40 AM UTC 24
Finished Aug 27 03:28:44 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156383308 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.4156383308
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/14.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.1957688115
Short name T302
Test name
Test status
Simulation time 2312845889 ps
CPU time 87.75 seconds
Started Aug 27 03:29:00 AM UTC 24
Finished Aug 27 03:30:29 AM UTC 24
Peak memory 220996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957688115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1957688115
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/14.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.3029385292
Short name T364
Test name
Test status
Simulation time 2074576118 ps
CPU time 70.52 seconds
Started Aug 27 03:29:02 AM UTC 24
Finished Aug 27 03:30:14 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029385292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3029385292
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/14.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.156188221
Short name T448
Test name
Test status
Simulation time 618007754 ps
CPU time 240.7 seconds
Started Aug 27 03:29:02 AM UTC 24
Finished Aug 27 03:33:06 AM UTC 24
Peak memory 222972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156188221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.156188221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/14.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.3928505992
Short name T456
Test name
Test status
Simulation time 1153870252 ps
CPU time 248.89 seconds
Started Aug 27 03:29:06 AM UTC 24
Finished Aug 27 03:33:19 AM UTC 24
Peak memory 233588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928505992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.3928505992
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/14.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.1960551195
Short name T343
Test name
Test status
Simulation time 73650972 ps
CPU time 12.38 seconds
Started Aug 27 03:28:54 AM UTC 24
Finished Aug 27 03:29:08 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960551195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1960551195
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/14.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.38335676
Short name T295
Test name
Test status
Simulation time 290791871 ps
CPU time 14.31 seconds
Started Aug 27 03:29:16 AM UTC 24
Finished Aug 27 03:29:32 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38335676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.38335676
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/15.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.68802004
Short name T603
Test name
Test status
Simulation time 79845018438 ps
CPU time 545.04 seconds
Started Aug 27 03:29:16 AM UTC 24
Finished Aug 27 03:38:28 AM UTC 24
Peak memory 220500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68802004 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.68802004
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/15.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.4068394756
Short name T353
Test name
Test status
Simulation time 293363762 ps
CPU time 5.33 seconds
Started Aug 27 03:29:24 AM UTC 24
Finished Aug 27 03:29:30 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068394756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.4068394756
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/15.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.936449104
Short name T354
Test name
Test status
Simulation time 99894016 ps
CPU time 13.44 seconds
Started Aug 27 03:29:18 AM UTC 24
Finished Aug 27 03:29:33 AM UTC 24
Peak memory 216756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936449104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.936449104
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/15.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random.2593376693
Short name T109
Test name
Test status
Simulation time 1030462378 ps
CPU time 11.93 seconds
Started Aug 27 03:29:12 AM UTC 24
Finished Aug 27 03:29:25 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593376693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2593376693
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/15.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.2306389679
Short name T255
Test name
Test status
Simulation time 26934980642 ps
CPU time 176.67 seconds
Started Aug 27 03:29:14 AM UTC 24
Finished Aug 27 03:32:13 AM UTC 24
Peak memory 217028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306389679 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2306389679
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/15.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.491382842
Short name T442
Test name
Test status
Simulation time 27449075872 ps
CPU time 217.28 seconds
Started Aug 27 03:29:15 AM UTC 24
Finished Aug 27 03:32:55 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491382842 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.491382842
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/15.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.884977098
Short name T202
Test name
Test status
Simulation time 551756496 ps
CPU time 16.83 seconds
Started Aug 27 03:29:13 AM UTC 24
Finished Aug 27 03:29:31 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884977098 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.884977098
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/15.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.59627665
Short name T352
Test name
Test status
Simulation time 152282521 ps
CPU time 5.52 seconds
Started Aug 27 03:29:18 AM UTC 24
Finished Aug 27 03:29:25 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59627665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.59627665
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/15.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.3712167512
Short name T345
Test name
Test status
Simulation time 37740224 ps
CPU time 3.04 seconds
Started Aug 27 03:29:06 AM UTC 24
Finished Aug 27 03:29:11 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712167512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3712167512
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/15.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3390568758
Short name T132
Test name
Test status
Simulation time 5747420769 ps
CPU time 33 seconds
Started Aug 27 03:29:10 AM UTC 24
Finished Aug 27 03:29:45 AM UTC 24
Peak memory 217204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390568758 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3390568758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/15.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.681487323
Short name T350
Test name
Test status
Simulation time 3733949268 ps
CPU time 39.54 seconds
Started Aug 27 03:29:12 AM UTC 24
Finished Aug 27 03:29:53 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681487323 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.681487323
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/15.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.1695831937
Short name T347
Test name
Test status
Simulation time 52803030 ps
CPU time 3.2 seconds
Started Aug 27 03:29:08 AM UTC 24
Finished Aug 27 03:29:13 AM UTC 24
Peak memory 217068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695831937 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1695831937
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/15.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.387343135
Short name T387
Test name
Test status
Simulation time 510478904 ps
CPU time 83.96 seconds
Started Aug 27 03:29:24 AM UTC 24
Finished Aug 27 03:30:50 AM UTC 24
Peak memory 221252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387343135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.387343135
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/15.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3112506669
Short name T420
Test name
Test status
Simulation time 18384053572 ps
CPU time 165.91 seconds
Started Aug 27 03:29:26 AM UTC 24
Finished Aug 27 03:32:15 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112506669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3112506669
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/15.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3683299398
Short name T250
Test name
Test status
Simulation time 565778866 ps
CPU time 307.74 seconds
Started Aug 27 03:29:26 AM UTC 24
Finished Aug 27 03:34:38 AM UTC 24
Peak memory 222984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683299398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.3683299398
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/15.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.963110999
Short name T502
Test name
Test status
Simulation time 2205793912 ps
CPU time 330.41 seconds
Started Aug 27 03:29:26 AM UTC 24
Finished Aug 27 03:35:01 AM UTC 24
Peak memory 238004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963110999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.963110999
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/15.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.4195271679
Short name T75
Test name
Test status
Simulation time 680212501 ps
CPU time 20.92 seconds
Started Aug 27 03:29:23 AM UTC 24
Finished Aug 27 03:29:45 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195271679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.4195271679
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/15.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.4225497554
Short name T135
Test name
Test status
Simulation time 226642174 ps
CPU time 11.15 seconds
Started Aug 27 03:29:38 AM UTC 24
Finished Aug 27 03:29:50 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225497554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.4225497554
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/16.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.2995436599
Short name T356
Test name
Test status
Simulation time 19147462 ps
CPU time 3.35 seconds
Started Aug 27 03:29:47 AM UTC 24
Finished Aug 27 03:29:51 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995436599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.2995436599
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/16.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.1850071990
Short name T371
Test name
Test status
Simulation time 1739614083 ps
CPU time 43.73 seconds
Started Aug 27 03:29:45 AM UTC 24
Finished Aug 27 03:30:31 AM UTC 24
Peak memory 217076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850071990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1850071990
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/16.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random.434649389
Short name T131
Test name
Test status
Simulation time 65299021 ps
CPU time 4.11 seconds
Started Aug 27 03:29:33 AM UTC 24
Finished Aug 27 03:29:38 AM UTC 24
Peak memory 217080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434649389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.434649389
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/16.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.1603430413
Short name T136
Test name
Test status
Simulation time 75810596187 ps
CPU time 235.52 seconds
Started Aug 27 03:29:36 AM UTC 24
Finished Aug 27 03:33:35 AM UTC 24
Peak memory 216892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603430413 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1603430413
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/16.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1293583935
Short name T382
Test name
Test status
Simulation time 7875339462 ps
CPU time 69.5 seconds
Started Aug 27 03:29:37 AM UTC 24
Finished Aug 27 03:30:48 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293583935 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1293583935
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/16.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.354102465
Short name T134
Test name
Test status
Simulation time 92442603 ps
CPU time 12.49 seconds
Started Aug 27 03:29:34 AM UTC 24
Finished Aug 27 03:29:47 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354102465 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.354102465
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/16.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.361496367
Short name T368
Test name
Test status
Simulation time 4593336819 ps
CPU time 38.92 seconds
Started Aug 27 03:29:41 AM UTC 24
Finished Aug 27 03:30:21 AM UTC 24
Peak memory 216892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361496367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.361496367
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/16.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.2861052702
Short name T130
Test name
Test status
Simulation time 325689745 ps
CPU time 5 seconds
Started Aug 27 03:29:31 AM UTC 24
Finished Aug 27 03:29:37 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861052702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2861052702
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/16.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2642311630
Short name T361
Test name
Test status
Simulation time 6376000900 ps
CPU time 30.18 seconds
Started Aug 27 03:29:31 AM UTC 24
Finished Aug 27 03:30:03 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642311630 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2642311630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/16.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1250957343
Short name T359
Test name
Test status
Simulation time 2636096017 ps
CPU time 26.43 seconds
Started Aug 27 03:29:32 AM UTC 24
Finished Aug 27 03:30:00 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250957343 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1250957343
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/16.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2917379951
Short name T355
Test name
Test status
Simulation time 33039426 ps
CPU time 3.04 seconds
Started Aug 27 03:29:31 AM UTC 24
Finished Aug 27 03:29:35 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917379951 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2917379951
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/16.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.2669769868
Short name T363
Test name
Test status
Simulation time 478245736 ps
CPU time 18.8 seconds
Started Aug 27 03:29:48 AM UTC 24
Finished Aug 27 03:30:08 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669769868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.2669769868
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/16.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.2623969646
Short name T443
Test name
Test status
Simulation time 14976631153 ps
CPU time 185.45 seconds
Started Aug 27 03:29:51 AM UTC 24
Finished Aug 27 03:33:00 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623969646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2623969646
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/16.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.4085288101
Short name T485
Test name
Test status
Simulation time 563115037 ps
CPU time 270.2 seconds
Started Aug 27 03:29:48 AM UTC 24
Finished Aug 27 03:34:22 AM UTC 24
Peak memory 222988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085288101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.4085288101
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/16.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.2005406799
Short name T358
Test name
Test status
Simulation time 7569060 ps
CPU time 6.59 seconds
Started Aug 27 03:29:52 AM UTC 24
Finished Aug 27 03:30:00 AM UTC 24
Peak memory 217148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005406799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.2005406799
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/16.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.4263559316
Short name T290
Test name
Test status
Simulation time 306583032 ps
CPU time 17.3 seconds
Started Aug 27 03:29:45 AM UTC 24
Finished Aug 27 03:30:04 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263559316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.4263559316
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/16.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.1677773942
Short name T299
Test name
Test status
Simulation time 1869461728 ps
CPU time 37.44 seconds
Started Aug 27 03:30:04 AM UTC 24
Finished Aug 27 03:30:43 AM UTC 24
Peak memory 218888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677773942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.1677773942
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/17.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1587797784
Short name T139
Test name
Test status
Simulation time 52365504592 ps
CPU time 440.24 seconds
Started Aug 27 03:30:09 AM UTC 24
Finished Aug 27 03:37:35 AM UTC 24
Peak memory 218944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587797784 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.1587797784
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/17.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3444169937
Short name T378
Test name
Test status
Simulation time 725214204 ps
CPU time 22.42 seconds
Started Aug 27 03:30:19 AM UTC 24
Finished Aug 27 03:30:43 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444169937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3444169937
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/17.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.3782515366
Short name T375
Test name
Test status
Simulation time 257326994 ps
CPU time 19.86 seconds
Started Aug 27 03:30:15 AM UTC 24
Finished Aug 27 03:30:36 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782515366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3782515366
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/17.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random.4096263417
Short name T242
Test name
Test status
Simulation time 2112136803 ps
CPU time 31.86 seconds
Started Aug 27 03:30:01 AM UTC 24
Finished Aug 27 03:30:34 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096263417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.4096263417
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/17.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.919122918
Short name T462
Test name
Test status
Simulation time 132237154300 ps
CPU time 214.7 seconds
Started Aug 27 03:30:04 AM UTC 24
Finished Aug 27 03:33:42 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919122918 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.919122918
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/17.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.130016218
Short name T513
Test name
Test status
Simulation time 128245485744 ps
CPU time 324.3 seconds
Started Aug 27 03:30:04 AM UTC 24
Finished Aug 27 03:35:33 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130016218 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.130016218
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/17.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.753685343
Short name T367
Test name
Test status
Simulation time 216413172 ps
CPU time 18.26 seconds
Started Aug 27 03:30:02 AM UTC 24
Finished Aug 27 03:30:21 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753685343 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.753685343
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/17.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.4234342936
Short name T370
Test name
Test status
Simulation time 704875614 ps
CPU time 20.51 seconds
Started Aug 27 03:30:09 AM UTC 24
Finished Aug 27 03:30:31 AM UTC 24
Peak memory 217152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234342936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.4234342936
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/17.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.3159824101
Short name T357
Test name
Test status
Simulation time 410451238 ps
CPU time 4.92 seconds
Started Aug 27 03:29:53 AM UTC 24
Finished Aug 27 03:29:59 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159824101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3159824101
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/17.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1996226542
Short name T77
Test name
Test status
Simulation time 9338787764 ps
CPU time 32.55 seconds
Started Aug 27 03:30:01 AM UTC 24
Finished Aug 27 03:30:34 AM UTC 24
Peak memory 217140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996226542 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1996226542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/17.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.376411534
Short name T376
Test name
Test status
Simulation time 13545920842 ps
CPU time 36.61 seconds
Started Aug 27 03:30:01 AM UTC 24
Finished Aug 27 03:30:39 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376411534 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.376411534
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/17.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.297108567
Short name T360
Test name
Test status
Simulation time 28016136 ps
CPU time 3.13 seconds
Started Aug 27 03:29:56 AM UTC 24
Finished Aug 27 03:30:01 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297108567 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.297108567
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/17.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.2096145510
Short name T377
Test name
Test status
Simulation time 121609584 ps
CPU time 20.56 seconds
Started Aug 27 03:30:20 AM UTC 24
Finished Aug 27 03:30:41 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096145510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2096145510
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/17.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3415359706
Short name T399
Test name
Test status
Simulation time 11022704046 ps
CPU time 51.87 seconds
Started Aug 27 03:30:22 AM UTC 24
Finished Aug 27 03:31:15 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415359706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3415359706
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/17.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3271387969
Short name T374
Test name
Test status
Simulation time 8227647 ps
CPU time 13.63 seconds
Started Aug 27 03:30:21 AM UTC 24
Finished Aug 27 03:30:35 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271387969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.3271387969
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/17.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.1993265201
Short name T427
Test name
Test status
Simulation time 413143555 ps
CPU time 130.55 seconds
Started Aug 27 03:30:23 AM UTC 24
Finished Aug 27 03:32:36 AM UTC 24
Peak memory 222984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993265201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.1993265201
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/17.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.3192578088
Short name T372
Test name
Test status
Simulation time 1648837828 ps
CPU time 17.89 seconds
Started Aug 27 03:30:15 AM UTC 24
Finished Aug 27 03:30:34 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192578088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3192578088
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/17.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.4261469803
Short name T403
Test name
Test status
Simulation time 496848464 ps
CPU time 51.83 seconds
Started Aug 27 03:30:35 AM UTC 24
Finished Aug 27 03:31:29 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261469803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.4261469803
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/18.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.4260669290
Short name T221
Test name
Test status
Simulation time 155284135703 ps
CPU time 406.99 seconds
Started Aug 27 03:30:35 AM UTC 24
Finished Aug 27 03:37:27 AM UTC 24
Peak memory 218940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260669290 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.4260669290
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/18.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3994165404
Short name T390
Test name
Test status
Simulation time 662475020 ps
CPU time 21.16 seconds
Started Aug 27 03:30:37 AM UTC 24
Finished Aug 27 03:30:59 AM UTC 24
Peak memory 217096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994165404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3994165404
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/18.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.3493875279
Short name T380
Test name
Test status
Simulation time 157586723 ps
CPU time 10.31 seconds
Started Aug 27 03:30:35 AM UTC 24
Finished Aug 27 03:30:47 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493875279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3493875279
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/18.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random.838741098
Short name T383
Test name
Test status
Simulation time 277787936 ps
CPU time 15.65 seconds
Started Aug 27 03:30:32 AM UTC 24
Finished Aug 27 03:30:49 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838741098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.838741098
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/18.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.1402117072
Short name T451
Test name
Test status
Simulation time 32451960837 ps
CPU time 160.86 seconds
Started Aug 27 03:30:32 AM UTC 24
Finished Aug 27 03:33:15 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402117072 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1402117072
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/18.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.272818271
Short name T480
Test name
Test status
Simulation time 79089322616 ps
CPU time 215.1 seconds
Started Aug 27 03:30:35 AM UTC 24
Finished Aug 27 03:34:14 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272818271 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.272818271
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/18.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.2198434769
Short name T388
Test name
Test status
Simulation time 392330947 ps
CPU time 17.32 seconds
Started Aug 27 03:30:32 AM UTC 24
Finished Aug 27 03:30:50 AM UTC 24
Peak memory 217080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198434769 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.2198434769
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/18.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.3607724695
Short name T389
Test name
Test status
Simulation time 222998104 ps
CPU time 15.69 seconds
Started Aug 27 03:30:35 AM UTC 24
Finished Aug 27 03:30:52 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607724695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3607724695
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/18.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.3223677599
Short name T369
Test name
Test status
Simulation time 31003639 ps
CPU time 3.36 seconds
Started Aug 27 03:30:26 AM UTC 24
Finished Aug 27 03:30:31 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223677599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3223677599
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/18.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.4137285945
Short name T404
Test name
Test status
Simulation time 25029550405 ps
CPU time 61.16 seconds
Started Aug 27 03:30:30 AM UTC 24
Finished Aug 27 03:31:33 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137285945 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.4137285945
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/18.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.4276736809
Short name T396
Test name
Test status
Simulation time 4248938745 ps
CPU time 36.75 seconds
Started Aug 27 03:30:32 AM UTC 24
Finished Aug 27 03:31:10 AM UTC 24
Peak memory 217136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276736809 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.4276736809
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/18.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1741236473
Short name T76
Test name
Test status
Simulation time 49899662 ps
CPU time 2.92 seconds
Started Aug 27 03:30:30 AM UTC 24
Finished Aug 27 03:30:34 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741236473 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1741236473
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/18.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.2748478003
Short name T35
Test name
Test status
Simulation time 9459893512 ps
CPU time 356.95 seconds
Started Aug 27 03:30:40 AM UTC 24
Finished Aug 27 03:36:42 AM UTC 24
Peak memory 223344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748478003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2748478003
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/18.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3849910683
Short name T469
Test name
Test status
Simulation time 6876689519 ps
CPU time 180.28 seconds
Started Aug 27 03:30:44 AM UTC 24
Finished Aug 27 03:33:47 AM UTC 24
Peak memory 219272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849910683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3849910683
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/18.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.3787863841
Short name T55
Test name
Test status
Simulation time 6038752885 ps
CPU time 349.66 seconds
Started Aug 27 03:30:42 AM UTC 24
Finished Aug 27 03:36:37 AM UTC 24
Peak memory 223052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787863841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.3787863841
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/18.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.4063044508
Short name T492
Test name
Test status
Simulation time 3425445010 ps
CPU time 223.93 seconds
Started Aug 27 03:30:44 AM UTC 24
Finished Aug 27 03:34:31 AM UTC 24
Peak memory 233592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063044508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.4063044508
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/18.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.2142016475
Short name T381
Test name
Test status
Simulation time 165033934 ps
CPU time 9.59 seconds
Started Aug 27 03:30:37 AM UTC 24
Finished Aug 27 03:30:48 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142016475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2142016475
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/18.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.4024362165
Short name T303
Test name
Test status
Simulation time 1795500013 ps
CPU time 56.85 seconds
Started Aug 27 03:30:51 AM UTC 24
Finished Aug 27 03:31:50 AM UTC 24
Peak memory 217096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024362165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.4024362165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/19.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.4183835594
Short name T152
Test name
Test status
Simulation time 105704940495 ps
CPU time 860.95 seconds
Started Aug 27 03:30:51 AM UTC 24
Finished Aug 27 03:45:22 AM UTC 24
Peak memory 222680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183835594 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.4183835594
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/19.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.1873653488
Short name T395
Test name
Test status
Simulation time 188002002 ps
CPU time 5.81 seconds
Started Aug 27 03:31:03 AM UTC 24
Finished Aug 27 03:31:10 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873653488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.1873653488
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/19.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.1513053857
Short name T391
Test name
Test status
Simulation time 301873900 ps
CPU time 6.98 seconds
Started Aug 27 03:30:53 AM UTC 24
Finished Aug 27 03:31:02 AM UTC 24
Peak memory 217080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513053857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1513053857
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/19.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random.1559776962
Short name T393
Test name
Test status
Simulation time 1204494300 ps
CPU time 18.65 seconds
Started Aug 27 03:30:49 AM UTC 24
Finished Aug 27 03:31:08 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559776962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.1559776962
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/19.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.1913447161
Short name T405
Test name
Test status
Simulation time 4162705370 ps
CPU time 48.04 seconds
Started Aug 27 03:30:50 AM UTC 24
Finished Aug 27 03:31:39 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913447161 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1913447161
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/19.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.1021991695
Short name T461
Test name
Test status
Simulation time 57265991565 ps
CPU time 168.84 seconds
Started Aug 27 03:30:50 AM UTC 24
Finished Aug 27 03:33:41 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021991695 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1021991695
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/19.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.4047541406
Short name T392
Test name
Test status
Simulation time 222041019 ps
CPU time 11.52 seconds
Started Aug 27 03:30:50 AM UTC 24
Finished Aug 27 03:31:02 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047541406 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.4047541406
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/19.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.771859562
Short name T397
Test name
Test status
Simulation time 313274323 ps
CPU time 21.33 seconds
Started Aug 27 03:30:51 AM UTC 24
Finished Aug 27 03:31:14 AM UTC 24
Peak memory 216956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771859562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.771859562
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/19.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.2325947491
Short name T386
Test name
Test status
Simulation time 66187460 ps
CPU time 3.05 seconds
Started Aug 27 03:30:45 AM UTC 24
Finished Aug 27 03:30:50 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325947491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2325947491
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/19.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3008364586
Short name T407
Test name
Test status
Simulation time 6784839438 ps
CPU time 55.41 seconds
Started Aug 27 03:30:47 AM UTC 24
Finished Aug 27 03:31:44 AM UTC 24
Peak memory 217204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008364586 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3008364586
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/19.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1051616867
Short name T418
Test name
Test status
Simulation time 34833532629 ps
CPU time 82.93 seconds
Started Aug 27 03:30:49 AM UTC 24
Finished Aug 27 03:32:13 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051616867 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1051616867
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/19.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1891982674
Short name T385
Test name
Test status
Simulation time 30686166 ps
CPU time 2.86 seconds
Started Aug 27 03:30:45 AM UTC 24
Finished Aug 27 03:30:49 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891982674 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1891982674
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/19.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.561427045
Short name T528
Test name
Test status
Simulation time 12774370601 ps
CPU time 303.14 seconds
Started Aug 27 03:31:03 AM UTC 24
Finished Aug 27 03:36:11 AM UTC 24
Peak memory 223300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561427045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.561427045
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/19.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.2413913080
Short name T435
Test name
Test status
Simulation time 13426004454 ps
CPU time 98.87 seconds
Started Aug 27 03:31:09 AM UTC 24
Finished Aug 27 03:32:51 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413913080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2413913080
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/19.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.416602898
Short name T394
Test name
Test status
Simulation time 14446702 ps
CPU time 4.94 seconds
Started Aug 27 03:31:03 AM UTC 24
Finished Aug 27 03:31:09 AM UTC 24
Peak memory 217068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416602898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.416602898
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/19.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.4261799535
Short name T519
Test name
Test status
Simulation time 2334864650 ps
CPU time 286.95 seconds
Started Aug 27 03:31:09 AM UTC 24
Finished Aug 27 03:36:01 AM UTC 24
Peak memory 235704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261799535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.4261799535
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/19.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.3744470551
Short name T119
Test name
Test status
Simulation time 412799867 ps
CPU time 22.08 seconds
Started Aug 27 03:31:00 AM UTC 24
Finished Aug 27 03:31:24 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744470551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3744470551
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/19.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.4212305828
Short name T64
Test name
Test status
Simulation time 1850026324 ps
CPU time 16.18 seconds
Started Aug 27 03:24:44 AM UTC 24
Finished Aug 27 03:25:01 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212305828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.4212305828
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/2.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.3401776155
Short name T256
Test name
Test status
Simulation time 5650523459 ps
CPU time 31.87 seconds
Started Aug 27 03:24:44 AM UTC 24
Finished Aug 27 03:25:17 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401776155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3401776155
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/2.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.2994191071
Short name T217
Test name
Test status
Simulation time 24697125250 ps
CPU time 191.83 seconds
Started Aug 27 03:24:44 AM UTC 24
Finished Aug 27 03:27:59 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994191071 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2994191071
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/2.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.2669674600
Short name T150
Test name
Test status
Simulation time 35953066734 ps
CPU time 243.35 seconds
Started Aug 27 03:24:44 AM UTC 24
Finished Aug 27 03:28:50 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669674600 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2669674600
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/2.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.3795795165
Short name T16
Test name
Test status
Simulation time 72837302 ps
CPU time 6.43 seconds
Started Aug 27 03:24:44 AM UTC 24
Finished Aug 27 03:24:51 AM UTC 24
Peak memory 216956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795795165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3795795165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/2.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.4070339051
Short name T11
Test name
Test status
Simulation time 69329764 ps
CPU time 1.75 seconds
Started Aug 27 03:24:41 AM UTC 24
Finished Aug 27 03:24:44 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070339051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.4070339051
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/2.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.1359603274
Short name T289
Test name
Test status
Simulation time 10790535611 ps
CPU time 31.46 seconds
Started Aug 27 03:24:43 AM UTC 24
Finished Aug 27 03:25:16 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359603274 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1359603274
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/2.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.4049736624
Short name T190
Test name
Test status
Simulation time 6542658465 ps
CPU time 49.85 seconds
Started Aug 27 03:24:43 AM UTC 24
Finished Aug 27 03:25:35 AM UTC 24
Peak memory 217204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049736624 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.4049736624
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/2.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3893887260
Short name T12
Test name
Test status
Simulation time 28199041 ps
CPU time 3.07 seconds
Started Aug 27 03:24:43 AM UTC 24
Finished Aug 27 03:24:48 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893887260 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3893887260
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/2.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.3087333514
Short name T323
Test name
Test status
Simulation time 2329234780 ps
CPU time 145.33 seconds
Started Aug 27 03:24:44 AM UTC 24
Finished Aug 27 03:27:12 AM UTC 24
Peak memory 222756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087333514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3087333514
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/2.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.785747924
Short name T244
Test name
Test status
Simulation time 40210790491 ps
CPU time 205.43 seconds
Started Aug 27 03:24:44 AM UTC 24
Finished Aug 27 03:28:13 AM UTC 24
Peak memory 222868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785747924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.785747924
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/2.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1026711223
Short name T158
Test name
Test status
Simulation time 274908206 ps
CPU time 98.18 seconds
Started Aug 27 03:24:44 AM UTC 24
Finished Aug 27 03:26:24 AM UTC 24
Peak memory 221016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026711223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.1026711223
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/2.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.134214833
Short name T60
Test name
Test status
Simulation time 1466299196 ps
CPU time 226.67 seconds
Started Aug 27 03:24:44 AM UTC 24
Finished Aug 27 03:28:34 AM UTC 24
Peak memory 223096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134214833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.134214833
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/2.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.693193247
Short name T28
Test name
Test status
Simulation time 228238970 ps
CPU time 10.26 seconds
Started Aug 27 03:24:44 AM UTC 24
Finished Aug 27 03:24:56 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693193247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.693193247
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/2.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.600218441
Short name T292
Test name
Test status
Simulation time 2635339354 ps
CPU time 75.9 seconds
Started Aug 27 03:31:20 AM UTC 24
Finished Aug 27 03:32:38 AM UTC 24
Peak memory 218944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600218441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.600218441
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/20.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.566326633
Short name T765
Test name
Test status
Simulation time 75531440092 ps
CPU time 687.91 seconds
Started Aug 27 03:31:25 AM UTC 24
Finished Aug 27 03:43:00 AM UTC 24
Peak memory 222612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566326633 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.566326633
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/20.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1567650671
Short name T414
Test name
Test status
Simulation time 818702427 ps
CPU time 23.92 seconds
Started Aug 27 03:31:40 AM UTC 24
Finished Aug 27 03:32:05 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567650671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1567650671
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/20.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.3422073742
Short name T413
Test name
Test status
Simulation time 2166809528 ps
CPU time 30.15 seconds
Started Aug 27 03:31:30 AM UTC 24
Finished Aug 27 03:32:01 AM UTC 24
Peak memory 217148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422073742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3422073742
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/20.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random.814838621
Short name T401
Test name
Test status
Simulation time 130501898 ps
CPU time 3.51 seconds
Started Aug 27 03:31:15 AM UTC 24
Finished Aug 27 03:31:19 AM UTC 24
Peak memory 216756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814838621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.814838621
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/20.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.915078123
Short name T269
Test name
Test status
Simulation time 39882809883 ps
CPU time 229.11 seconds
Started Aug 27 03:31:16 AM UTC 24
Finished Aug 27 03:35:09 AM UTC 24
Peak memory 217224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915078123 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.915078123
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/20.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1113470272
Short name T232
Test name
Test status
Simulation time 20266524277 ps
CPU time 94.97 seconds
Started Aug 27 03:31:17 AM UTC 24
Finished Aug 27 03:32:54 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113470272 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1113470272
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/20.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.3161899678
Short name T402
Test name
Test status
Simulation time 140738250 ps
CPU time 10.39 seconds
Started Aug 27 03:31:16 AM UTC 24
Finished Aug 27 03:31:28 AM UTC 24
Peak memory 217080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161899678 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.3161899678
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/20.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.924799646
Short name T408
Test name
Test status
Simulation time 234687632 ps
CPU time 21.21 seconds
Started Aug 27 03:31:29 AM UTC 24
Finished Aug 27 03:31:51 AM UTC 24
Peak memory 216756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924799646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.924799646
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/20.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.1288950186
Short name T400
Test name
Test status
Simulation time 181610207 ps
CPU time 4.94 seconds
Started Aug 27 03:31:11 AM UTC 24
Finished Aug 27 03:31:17 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288950186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1288950186
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/20.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.2398850938
Short name T240
Test name
Test status
Simulation time 7110932591 ps
CPU time 31.68 seconds
Started Aug 27 03:31:11 AM UTC 24
Finished Aug 27 03:31:44 AM UTC 24
Peak memory 216924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398850938 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2398850938
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/20.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.3432238043
Short name T409
Test name
Test status
Simulation time 4235817969 ps
CPU time 41.91 seconds
Started Aug 27 03:31:13 AM UTC 24
Finished Aug 27 03:31:56 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432238043 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.3432238043
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/20.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2653357014
Short name T398
Test name
Test status
Simulation time 28352421 ps
CPU time 3.02 seconds
Started Aug 27 03:31:11 AM UTC 24
Finished Aug 27 03:31:15 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653357014 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2653357014
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/20.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.3070683529
Short name T479
Test name
Test status
Simulation time 5105866404 ps
CPU time 146 seconds
Started Aug 27 03:31:44 AM UTC 24
Finished Aug 27 03:34:13 AM UTC 24
Peak memory 223044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070683529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3070683529
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/20.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.2352462297
Short name T429
Test name
Test status
Simulation time 617828837 ps
CPU time 51.62 seconds
Started Aug 27 03:31:45 AM UTC 24
Finished Aug 27 03:32:38 AM UTC 24
Peak memory 219208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352462297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2352462297
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/20.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.3985307659
Short name T227
Test name
Test status
Simulation time 2036723505 ps
CPU time 340.5 seconds
Started Aug 27 03:31:45 AM UTC 24
Finished Aug 27 03:37:30 AM UTC 24
Peak memory 222984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985307659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.3985307659
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/20.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1477029176
Short name T282
Test name
Test status
Simulation time 2062478822 ps
CPU time 242.5 seconds
Started Aug 27 03:31:50 AM UTC 24
Finished Aug 27 03:35:56 AM UTC 24
Peak memory 235964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477029176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.1477029176
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/20.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.2406804286
Short name T406
Test name
Test status
Simulation time 197205560 ps
CPU time 9.43 seconds
Started Aug 27 03:31:34 AM UTC 24
Finished Aug 27 03:31:44 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406804286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.2406804286
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/20.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.1557571898
Short name T231
Test name
Test status
Simulation time 86355185 ps
CPU time 10.6 seconds
Started Aug 27 03:32:05 AM UTC 24
Finished Aug 27 03:32:17 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557571898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.1557571898
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/21.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2348823108
Short name T743
Test name
Test status
Simulation time 64498980509 ps
CPU time 616.42 seconds
Started Aug 27 03:32:06 AM UTC 24
Finished Aug 27 03:42:29 AM UTC 24
Peak memory 222544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348823108 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.2348823108
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/21.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.1762294429
Short name T426
Test name
Test status
Simulation time 455179615 ps
CPU time 16.83 seconds
Started Aug 27 03:32:12 AM UTC 24
Finished Aug 27 03:32:30 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762294429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.1762294429
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/21.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.2711013281
Short name T424
Test name
Test status
Simulation time 189105790 ps
CPU time 14.78 seconds
Started Aug 27 03:32:07 AM UTC 24
Finished Aug 27 03:32:23 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711013281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2711013281
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/21.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random.1409719173
Short name T421
Test name
Test status
Simulation time 184061108 ps
CPU time 17.36 seconds
Started Aug 27 03:31:58 AM UTC 24
Finished Aug 27 03:32:17 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409719173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.1409719173
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/21.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.2895079717
Short name T510
Test name
Test status
Simulation time 75519967415 ps
CPU time 202.86 seconds
Started Aug 27 03:31:59 AM UTC 24
Finished Aug 27 03:35:25 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895079717 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2895079717
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/21.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1179401575
Short name T198
Test name
Test status
Simulation time 36771533134 ps
CPU time 185.55 seconds
Started Aug 27 03:32:02 AM UTC 24
Finished Aug 27 03:35:10 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179401575 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1179401575
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/21.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.4273222337
Short name T417
Test name
Test status
Simulation time 159100615 ps
CPU time 10.88 seconds
Started Aug 27 03:31:59 AM UTC 24
Finished Aug 27 03:32:11 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273222337 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.4273222337
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/21.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.1977876382
Short name T419
Test name
Test status
Simulation time 647602104 ps
CPU time 6.71 seconds
Started Aug 27 03:32:06 AM UTC 24
Finished Aug 27 03:32:14 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977876382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1977876382
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/21.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.4103311273
Short name T411
Test name
Test status
Simulation time 259608391 ps
CPU time 4.72 seconds
Started Aug 27 03:31:52 AM UTC 24
Finished Aug 27 03:31:58 AM UTC 24
Peak memory 217068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103311273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.4103311273
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/21.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.766928693
Short name T432
Test name
Test status
Simulation time 4111269374 ps
CPU time 48.93 seconds
Started Aug 27 03:31:57 AM UTC 24
Finished Aug 27 03:32:47 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766928693 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.766928693
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/21.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.3801503914
Short name T425
Test name
Test status
Simulation time 6065105683 ps
CPU time 26.08 seconds
Started Aug 27 03:31:58 AM UTC 24
Finished Aug 27 03:32:25 AM UTC 24
Peak memory 217136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801503914 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3801503914
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/21.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.1928143245
Short name T412
Test name
Test status
Simulation time 42592635 ps
CPU time 3.2 seconds
Started Aug 27 03:31:55 AM UTC 24
Finished Aug 27 03:31:59 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928143245 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.1928143245
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/21.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.3017146713
Short name T506
Test name
Test status
Simulation time 2078931370 ps
CPU time 169.1 seconds
Started Aug 27 03:32:13 AM UTC 24
Finished Aug 27 03:35:05 AM UTC 24
Peak memory 223004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017146713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3017146713
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/21.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.1666701293
Short name T463
Test name
Test status
Simulation time 696271405 ps
CPU time 87.15 seconds
Started Aug 27 03:32:15 AM UTC 24
Finished Aug 27 03:33:44 AM UTC 24
Peak memory 219208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666701293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1666701293
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/21.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.360635265
Short name T501
Test name
Test status
Simulation time 335943193 ps
CPU time 161.52 seconds
Started Aug 27 03:32:15 AM UTC 24
Finished Aug 27 03:35:00 AM UTC 24
Peak memory 220928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360635265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.360635265
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/21.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1978917817
Short name T696
Test name
Test status
Simulation time 20528576378 ps
CPU time 535.09 seconds
Started Aug 27 03:32:15 AM UTC 24
Finished Aug 27 03:41:17 AM UTC 24
Peak memory 233656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978917817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.1978917817
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/21.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.1650389900
Short name T430
Test name
Test status
Simulation time 868887421 ps
CPU time 29.86 seconds
Started Aug 27 03:32:11 AM UTC 24
Finished Aug 27 03:32:42 AM UTC 24
Peak memory 218816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650389900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1650389900
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/21.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.1983851585
Short name T452
Test name
Test status
Simulation time 615692950 ps
CPU time 40.77 seconds
Started Aug 27 03:32:34 AM UTC 24
Finished Aug 27 03:33:16 AM UTC 24
Peak memory 219144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983851585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1983851585
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/22.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3823244978
Short name T283
Test name
Test status
Simulation time 27500417408 ps
CPU time 196.74 seconds
Started Aug 27 03:32:37 AM UTC 24
Finished Aug 27 03:35:57 AM UTC 24
Peak memory 218940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823244978 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.3823244978
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/22.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2030691378
Short name T436
Test name
Test status
Simulation time 39177936 ps
CPU time 6.15 seconds
Started Aug 27 03:32:44 AM UTC 24
Finished Aug 27 03:32:51 AM UTC 24
Peak memory 217096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030691378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.2030691378
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/22.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.802328625
Short name T433
Test name
Test status
Simulation time 1128662142 ps
CPU time 8.16 seconds
Started Aug 27 03:32:39 AM UTC 24
Finished Aug 27 03:32:49 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802328625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.802328625
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/22.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random.3631903683
Short name T434
Test name
Test status
Simulation time 873110870 ps
CPU time 25.13 seconds
Started Aug 27 03:32:22 AM UTC 24
Finished Aug 27 03:32:49 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631903683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.3631903683
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/22.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.412537113
Short name T438
Test name
Test status
Simulation time 9241081439 ps
CPU time 24.76 seconds
Started Aug 27 03:32:27 AM UTC 24
Finished Aug 27 03:32:53 AM UTC 24
Peak memory 216892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412537113 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.412537113
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/22.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1612523437
Short name T449
Test name
Test status
Simulation time 8440272462 ps
CPU time 36.07 seconds
Started Aug 27 03:32:32 AM UTC 24
Finished Aug 27 03:33:09 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612523437 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1612523437
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/22.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.3988173153
Short name T428
Test name
Test status
Simulation time 81505620 ps
CPU time 12.15 seconds
Started Aug 27 03:32:24 AM UTC 24
Finished Aug 27 03:32:38 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988173153 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.3988173153
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/22.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.3301837702
Short name T431
Test name
Test status
Simulation time 127983960 ps
CPU time 5.25 seconds
Started Aug 27 03:32:38 AM UTC 24
Finished Aug 27 03:32:45 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301837702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3301837702
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/22.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.3904894433
Short name T423
Test name
Test status
Simulation time 202959317 ps
CPU time 4.57 seconds
Started Aug 27 03:32:16 AM UTC 24
Finished Aug 27 03:32:22 AM UTC 24
Peak memory 217068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904894433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3904894433
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/22.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1865016048
Short name T439
Test name
Test status
Simulation time 10401786822 ps
CPU time 34.4 seconds
Started Aug 27 03:32:18 AM UTC 24
Finished Aug 27 03:32:54 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865016048 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1865016048
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/22.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.2726966208
Short name T445
Test name
Test status
Simulation time 4846648006 ps
CPU time 39.16 seconds
Started Aug 27 03:32:22 AM UTC 24
Finished Aug 27 03:33:03 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726966208 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2726966208
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/22.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1000168506
Short name T422
Test name
Test status
Simulation time 34249115 ps
CPU time 2.88 seconds
Started Aug 27 03:32:17 AM UTC 24
Finished Aug 27 03:32:21 AM UTC 24
Peak memory 217132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000168506 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1000168506
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/22.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.2174430670
Short name T219
Test name
Test status
Simulation time 1321241917 ps
CPU time 99.82 seconds
Started Aug 27 03:32:46 AM UTC 24
Finished Aug 27 03:34:28 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174430670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2174430670
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/22.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3963872304
Short name T509
Test name
Test status
Simulation time 1133388530 ps
CPU time 151.99 seconds
Started Aug 27 03:32:48 AM UTC 24
Finished Aug 27 03:35:23 AM UTC 24
Peak memory 222980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963872304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3963872304
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/22.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.3853291709
Short name T521
Test name
Test status
Simulation time 522650584 ps
CPU time 192.18 seconds
Started Aug 27 03:32:47 AM UTC 24
Finished Aug 27 03:36:02 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853291709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.3853291709
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/22.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2964089590
Short name T523
Test name
Test status
Simulation time 1014942871 ps
CPU time 189.84 seconds
Started Aug 27 03:32:50 AM UTC 24
Finished Aug 27 03:36:03 AM UTC 24
Peak memory 222956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964089590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.2964089590
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/22.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.283413840
Short name T437
Test name
Test status
Simulation time 345323799 ps
CPU time 11.81 seconds
Started Aug 27 03:32:39 AM UTC 24
Finished Aug 27 03:32:53 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283413840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.283413840
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/22.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.1167459578
Short name T447
Test name
Test status
Simulation time 130614699 ps
CPU time 9.24 seconds
Started Aug 27 03:32:56 AM UTC 24
Finished Aug 27 03:33:06 AM UTC 24
Peak memory 217060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167459578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1167459578
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/23.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.4006356188
Short name T592
Test name
Test status
Simulation time 32911089782 ps
CPU time 314.45 seconds
Started Aug 27 03:32:56 AM UTC 24
Finished Aug 27 03:38:15 AM UTC 24
Peak memory 218944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006356188 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.4006356188
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/23.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.847336800
Short name T457
Test name
Test status
Simulation time 111831036 ps
CPU time 15.91 seconds
Started Aug 27 03:33:03 AM UTC 24
Finished Aug 27 03:33:20 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847336800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.847336800
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/23.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.2988893611
Short name T446
Test name
Test status
Simulation time 37898532 ps
CPU time 3.91 seconds
Started Aug 27 03:32:58 AM UTC 24
Finished Aug 27 03:33:03 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988893611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2988893611
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/23.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random.3167305849
Short name T454
Test name
Test status
Simulation time 195502296 ps
CPU time 21.56 seconds
Started Aug 27 03:32:55 AM UTC 24
Finished Aug 27 03:33:17 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167305849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3167305849
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/23.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.2284562718
Short name T278
Test name
Test status
Simulation time 33982367512 ps
CPU time 175.93 seconds
Started Aug 27 03:32:56 AM UTC 24
Finished Aug 27 03:35:55 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284562718 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2284562718
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/23.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.2929361679
Short name T586
Test name
Test status
Simulation time 36345159760 ps
CPU time 290.06 seconds
Started Aug 27 03:32:56 AM UTC 24
Finished Aug 27 03:37:50 AM UTC 24
Peak memory 218808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929361679 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2929361679
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/23.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.3592786648
Short name T223
Test name
Test status
Simulation time 277601981 ps
CPU time 32.07 seconds
Started Aug 27 03:32:55 AM UTC 24
Finished Aug 27 03:33:28 AM UTC 24
Peak memory 219192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592786648 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.3592786648
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/23.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.147666304
Short name T444
Test name
Test status
Simulation time 35851035 ps
CPU time 4.59 seconds
Started Aug 27 03:32:56 AM UTC 24
Finished Aug 27 03:33:02 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147666304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.147666304
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/23.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.3019465672
Short name T440
Test name
Test status
Simulation time 81885451 ps
CPU time 3.35 seconds
Started Aug 27 03:32:50 AM UTC 24
Finished Aug 27 03:32:55 AM UTC 24
Peak memory 216272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019465672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3019465672
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/23.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.1319202216
Short name T459
Test name
Test status
Simulation time 10765697119 ps
CPU time 41 seconds
Started Aug 27 03:32:51 AM UTC 24
Finished Aug 27 03:33:34 AM UTC 24
Peak memory 217140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319202216 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1319202216
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/23.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.3787315259
Short name T467
Test name
Test status
Simulation time 4903143671 ps
CPU time 49.97 seconds
Started Aug 27 03:32:53 AM UTC 24
Finished Aug 27 03:33:45 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787315259 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3787315259
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/23.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.2029707305
Short name T441
Test name
Test status
Simulation time 27932686 ps
CPU time 2.82 seconds
Started Aug 27 03:32:51 AM UTC 24
Finished Aug 27 03:32:55 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029707305 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.2029707305
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/23.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.562217114
Short name T458
Test name
Test status
Simulation time 937251981 ps
CPU time 26.43 seconds
Started Aug 27 03:33:04 AM UTC 24
Finished Aug 27 03:33:31 AM UTC 24
Peak memory 219204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562217114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.562217114
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/23.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.3027974374
Short name T473
Test name
Test status
Simulation time 4845425086 ps
CPU time 50.52 seconds
Started Aug 27 03:33:07 AM UTC 24
Finished Aug 27 03:33:59 AM UTC 24
Peak memory 216904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027974374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3027974374
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/23.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3825922546
Short name T179
Test name
Test status
Simulation time 13168684408 ps
CPU time 307.63 seconds
Started Aug 27 03:33:04 AM UTC 24
Finished Aug 27 03:38:16 AM UTC 24
Peak memory 223308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825922546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.3825922546
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/23.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.2752773903
Short name T639
Test name
Test status
Simulation time 3117622365 ps
CPU time 386.02 seconds
Started Aug 27 03:33:07 AM UTC 24
Finished Aug 27 03:39:38 AM UTC 24
Peak memory 233656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752773903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.2752773903
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/23.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.2758280360
Short name T455
Test name
Test status
Simulation time 494014176 ps
CPU time 16.13 seconds
Started Aug 27 03:33:01 AM UTC 24
Finished Aug 27 03:33:18 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758280360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2758280360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/23.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.978046316
Short name T460
Test name
Test status
Simulation time 371837179 ps
CPU time 14.33 seconds
Started Aug 27 03:33:18 AM UTC 24
Finished Aug 27 03:33:34 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978046316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.978046316
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/24.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3044833896
Short name T147
Test name
Test status
Simulation time 98384778409 ps
CPU time 638.95 seconds
Started Aug 27 03:33:20 AM UTC 24
Finished Aug 27 03:44:06 AM UTC 24
Peak memory 222544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044833896 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.3044833896
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/24.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.178072543
Short name T468
Test name
Test status
Simulation time 89779224 ps
CPU time 9.88 seconds
Started Aug 27 03:33:34 AM UTC 24
Finished Aug 27 03:33:45 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178072543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.178072543
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/24.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.2231677480
Short name T465
Test name
Test status
Simulation time 752639463 ps
CPU time 13.88 seconds
Started Aug 27 03:33:29 AM UTC 24
Finished Aug 27 03:33:44 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231677480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2231677480
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/24.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random.3969066667
Short name T474
Test name
Test status
Simulation time 3330606502 ps
CPU time 41.95 seconds
Started Aug 27 03:33:16 AM UTC 24
Finished Aug 27 03:33:59 AM UTC 24
Peak memory 217152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969066667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.3969066667
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/24.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.1989885884
Short name T550
Test name
Test status
Simulation time 33660831420 ps
CPU time 201.94 seconds
Started Aug 27 03:33:17 AM UTC 24
Finished Aug 27 03:36:42 AM UTC 24
Peak memory 219272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989885884 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1989885884
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/24.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.3952297832
Short name T515
Test name
Test status
Simulation time 17863028507 ps
CPU time 140.52 seconds
Started Aug 27 03:33:18 AM UTC 24
Finished Aug 27 03:35:41 AM UTC 24
Peak memory 217224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952297832 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3952297832
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/24.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.2509934318
Short name T472
Test name
Test status
Simulation time 417525572 ps
CPU time 32.02 seconds
Started Aug 27 03:33:17 AM UTC 24
Finished Aug 27 03:33:51 AM UTC 24
Peak memory 216756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509934318 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.2509934318
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/24.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.4264358507
Short name T466
Test name
Test status
Simulation time 236234977 ps
CPU time 22.84 seconds
Started Aug 27 03:33:21 AM UTC 24
Finished Aug 27 03:33:45 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264358507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.4264358507
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/24.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.3706475269
Short name T453
Test name
Test status
Simulation time 137869521 ps
CPU time 5.07 seconds
Started Aug 27 03:33:11 AM UTC 24
Finished Aug 27 03:33:17 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706475269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3706475269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/24.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.1143229789
Short name T464
Test name
Test status
Simulation time 5295761679 ps
CPU time 30.95 seconds
Started Aug 27 03:33:12 AM UTC 24
Finished Aug 27 03:33:44 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143229789 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1143229789
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/24.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.496619149
Short name T243
Test name
Test status
Simulation time 3627130150 ps
CPU time 45.23 seconds
Started Aug 27 03:33:15 AM UTC 24
Finished Aug 27 03:34:02 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496619149 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.496619149
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/24.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.4263900661
Short name T450
Test name
Test status
Simulation time 29369503 ps
CPU time 2.9 seconds
Started Aug 27 03:33:11 AM UTC 24
Finished Aug 27 03:33:14 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263900661 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.4263900661
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/24.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.488331209
Short name T478
Test name
Test status
Simulation time 875848845 ps
CPU time 36.59 seconds
Started Aug 27 03:33:34 AM UTC 24
Finished Aug 27 03:34:12 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488331209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.488331209
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/24.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2189500299
Short name T516
Test name
Test status
Simulation time 5726355191 ps
CPU time 120.73 seconds
Started Aug 27 03:33:43 AM UTC 24
Finished Aug 27 03:35:46 AM UTC 24
Peak memory 219208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189500299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2189500299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/24.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.1952101818
Short name T647
Test name
Test status
Simulation time 1619163946 ps
CPU time 371.96 seconds
Started Aug 27 03:33:35 AM UTC 24
Finished Aug 27 03:39:52 AM UTC 24
Peak memory 222984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952101818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.1952101818
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/24.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.702031421
Short name T34
Test name
Test status
Simulation time 338344857 ps
CPU time 123.88 seconds
Started Aug 27 03:33:43 AM UTC 24
Finished Aug 27 03:35:49 AM UTC 24
Peak memory 223232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702031421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.702031421
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/24.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.4114980503
Short name T477
Test name
Test status
Simulation time 3857003140 ps
CPU time 37.22 seconds
Started Aug 27 03:33:32 AM UTC 24
Finished Aug 27 03:34:11 AM UTC 24
Peak memory 219260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114980503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.4114980503
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/24.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.1732007509
Short name T493
Test name
Test status
Simulation time 373110393 ps
CPU time 40.31 seconds
Started Aug 27 03:33:50 AM UTC 24
Finished Aug 27 03:34:32 AM UTC 24
Peak memory 218888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732007509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.1732007509
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/25.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.1037116144
Short name T824
Test name
Test status
Simulation time 84373777784 ps
CPU time 638.51 seconds
Started Aug 27 03:33:52 AM UTC 24
Finished Aug 27 03:44:38 AM UTC 24
Peak memory 220432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037116144 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.1037116144
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/25.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.2221601435
Short name T491
Test name
Test status
Simulation time 263216991 ps
CPU time 20.45 seconds
Started Aug 27 03:34:06 AM UTC 24
Finished Aug 27 03:34:28 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221601435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.2221601435
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/25.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.2270932155
Short name T487
Test name
Test status
Simulation time 328962554 ps
CPU time 23.31 seconds
Started Aug 27 03:34:01 AM UTC 24
Finished Aug 27 03:34:25 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270932155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2270932155
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/25.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random.1394056620
Short name T481
Test name
Test status
Simulation time 200269822 ps
CPU time 26.47 seconds
Started Aug 27 03:33:46 AM UTC 24
Finished Aug 27 03:34:14 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394056620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.1394056620
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/25.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.2514150969
Short name T579
Test name
Test status
Simulation time 34217800837 ps
CPU time 232.62 seconds
Started Aug 27 03:33:48 AM UTC 24
Finished Aug 27 03:37:44 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514150969 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2514150969
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/25.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1327646620
Short name T83
Test name
Test status
Simulation time 37803053059 ps
CPU time 240.94 seconds
Started Aug 27 03:33:49 AM UTC 24
Finished Aug 27 03:37:54 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327646620 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1327646620
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/25.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.3218475758
Short name T475
Test name
Test status
Simulation time 167696896 ps
CPU time 17.59 seconds
Started Aug 27 03:33:46 AM UTC 24
Finished Aug 27 03:34:05 AM UTC 24
Peak memory 217080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218475758 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.3218475758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/25.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.1642681543
Short name T476
Test name
Test status
Simulation time 93112274 ps
CPU time 8.33 seconds
Started Aug 27 03:34:00 AM UTC 24
Finished Aug 27 03:34:09 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642681543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1642681543
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/25.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.402145086
Short name T471
Test name
Test status
Simulation time 168176617 ps
CPU time 3.88 seconds
Started Aug 27 03:33:45 AM UTC 24
Finished Aug 27 03:33:50 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402145086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.402145086
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/25.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.702239956
Short name T486
Test name
Test status
Simulation time 8635209727 ps
CPU time 36.78 seconds
Started Aug 27 03:33:45 AM UTC 24
Finished Aug 27 03:34:23 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702239956 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.702239956
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/25.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.662472676
Short name T494
Test name
Test status
Simulation time 4576036152 ps
CPU time 48.27 seconds
Started Aug 27 03:33:46 AM UTC 24
Finished Aug 27 03:34:36 AM UTC 24
Peak memory 217136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662472676 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.662472676
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/25.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2842980043
Short name T470
Test name
Test status
Simulation time 33637012 ps
CPU time 3.16 seconds
Started Aug 27 03:33:45 AM UTC 24
Finished Aug 27 03:33:49 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842980043 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2842980043
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/25.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.4114073747
Short name T522
Test name
Test status
Simulation time 1185643758 ps
CPU time 109.85 seconds
Started Aug 27 03:34:10 AM UTC 24
Finished Aug 27 03:36:03 AM UTC 24
Peak memory 219140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114073747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.4114073747
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/25.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.3598811108
Short name T627
Test name
Test status
Simulation time 49053138267 ps
CPU time 297.23 seconds
Started Aug 27 03:34:13 AM UTC 24
Finished Aug 27 03:39:15 AM UTC 24
Peak memory 223048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598811108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3598811108
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/25.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1013102679
Short name T43
Test name
Test status
Simulation time 14099086092 ps
CPU time 453.2 seconds
Started Aug 27 03:34:12 AM UTC 24
Finished Aug 27 03:41:51 AM UTC 24
Peak memory 220936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013102679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.1013102679
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/25.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.3623067041
Short name T482
Test name
Test status
Simulation time 81742867 ps
CPU time 9.65 seconds
Started Aug 27 03:34:03 AM UTC 24
Finished Aug 27 03:34:14 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623067041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3623067041
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/25.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.1381898831
Short name T210
Test name
Test status
Simulation time 196969837 ps
CPU time 28.66 seconds
Started Aug 27 03:34:28 AM UTC 24
Finished Aug 27 03:34:58 AM UTC 24
Peak memory 217160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381898831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.1381898831
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/26.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.4162498800
Short name T554
Test name
Test status
Simulation time 37801912183 ps
CPU time 134.36 seconds
Started Aug 27 03:34:29 AM UTC 24
Finished Aug 27 03:36:45 AM UTC 24
Peak memory 219268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162498800 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.4162498800
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/26.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1024525342
Short name T499
Test name
Test status
Simulation time 436411268 ps
CPU time 21.36 seconds
Started Aug 27 03:34:33 AM UTC 24
Finished Aug 27 03:34:56 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024525342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1024525342
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/26.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.627243641
Short name T505
Test name
Test status
Simulation time 6692833041 ps
CPU time 35.2 seconds
Started Aug 27 03:34:29 AM UTC 24
Finished Aug 27 03:35:05 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627243641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.627243641
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/26.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random.895139152
Short name T489
Test name
Test status
Simulation time 34461810 ps
CPU time 5.42 seconds
Started Aug 27 03:34:20 AM UTC 24
Finished Aug 27 03:34:27 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895139152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.895139152
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/26.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.201720419
Short name T572
Test name
Test status
Simulation time 44348436547 ps
CPU time 180.28 seconds
Started Aug 27 03:34:24 AM UTC 24
Finished Aug 27 03:37:28 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201720419 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.201720419
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/26.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.2843126777
Short name T84
Test name
Test status
Simulation time 30717188288 ps
CPU time 221.06 seconds
Started Aug 27 03:34:26 AM UTC 24
Finished Aug 27 03:38:11 AM UTC 24
Peak memory 218952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843126777 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2843126777
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/26.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.3487802885
Short name T490
Test name
Test status
Simulation time 17364829 ps
CPU time 2.92 seconds
Started Aug 27 03:34:23 AM UTC 24
Finished Aug 27 03:34:28 AM UTC 24
Peak memory 216752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487802885 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3487802885
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/26.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.2091757141
Short name T495
Test name
Test status
Simulation time 932369110 ps
CPU time 9.3 seconds
Started Aug 27 03:34:29 AM UTC 24
Finished Aug 27 03:34:39 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091757141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2091757141
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/26.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.1850196211
Short name T484
Test name
Test status
Simulation time 38594887 ps
CPU time 3.36 seconds
Started Aug 27 03:34:15 AM UTC 24
Finished Aug 27 03:34:19 AM UTC 24
Peak memory 217068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850196211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1850196211
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/26.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.1756904892
Short name T154
Test name
Test status
Simulation time 28573039359 ps
CPU time 55.38 seconds
Started Aug 27 03:34:15 AM UTC 24
Finished Aug 27 03:35:12 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756904892 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1756904892
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/26.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.1745667088
Short name T504
Test name
Test status
Simulation time 5325794545 ps
CPU time 42.05 seconds
Started Aug 27 03:34:20 AM UTC 24
Finished Aug 27 03:35:04 AM UTC 24
Peak memory 217072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745667088 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1745667088
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/26.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1939720822
Short name T483
Test name
Test status
Simulation time 27683391 ps
CPU time 3 seconds
Started Aug 27 03:34:15 AM UTC 24
Finished Aug 27 03:34:19 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939720822 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1939720822
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/26.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.2573567252
Short name T500
Test name
Test status
Simulation time 659420215 ps
CPU time 18.84 seconds
Started Aug 27 03:34:36 AM UTC 24
Finished Aug 27 03:34:56 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573567252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2573567252
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/26.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.4134064867
Short name T535
Test name
Test status
Simulation time 5586125378 ps
CPU time 99.95 seconds
Started Aug 27 03:34:40 AM UTC 24
Finished Aug 27 03:36:23 AM UTC 24
Peak memory 221320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134064867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.4134064867
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/26.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.3035740549
Short name T721
Test name
Test status
Simulation time 8193580047 ps
CPU time 436.27 seconds
Started Aug 27 03:34:39 AM UTC 24
Finished Aug 27 03:42:01 AM UTC 24
Peak memory 223048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035740549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.3035740549
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/26.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2772295238
Short name T524
Test name
Test status
Simulation time 2440721260 ps
CPU time 78.06 seconds
Started Aug 27 03:34:43 AM UTC 24
Finished Aug 27 03:36:03 AM UTC 24
Peak memory 218888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772295238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.2772295238
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/26.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.3468416067
Short name T496
Test name
Test status
Simulation time 700129822 ps
CPU time 8.78 seconds
Started Aug 27 03:34:32 AM UTC 24
Finished Aug 27 03:34:42 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468416067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3468416067
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/26.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.2815181556
Short name T137
Test name
Test status
Simulation time 1682148202 ps
CPU time 42.3 seconds
Started Aug 27 03:35:04 AM UTC 24
Finished Aug 27 03:35:48 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815181556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.2815181556
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/27.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.944569418
Short name T252
Test name
Test status
Simulation time 3846810686 ps
CPU time 32.83 seconds
Started Aug 27 03:35:06 AM UTC 24
Finished Aug 27 03:35:40 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944569418 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.944569418
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/27.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.516560833
Short name T514
Test name
Test status
Simulation time 2824272689 ps
CPU time 27.69 seconds
Started Aug 27 03:35:11 AM UTC 24
Finished Aug 27 03:35:40 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516560833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.516560833
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/27.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.324832760
Short name T508
Test name
Test status
Simulation time 95398591 ps
CPU time 11.95 seconds
Started Aug 27 03:35:09 AM UTC 24
Finished Aug 27 03:35:23 AM UTC 24
Peak memory 216992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324832760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.324832760
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/27.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random.1992764234
Short name T507
Test name
Test status
Simulation time 339120754 ps
CPU time 10.7 seconds
Started Aug 27 03:34:57 AM UTC 24
Finished Aug 27 03:35:09 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992764234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.1992764234
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/27.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.2191983494
Short name T518
Test name
Test status
Simulation time 12800746579 ps
CPU time 56.45 seconds
Started Aug 27 03:35:00 AM UTC 24
Finished Aug 27 03:35:58 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191983494 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2191983494
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/27.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.4140691450
Short name T177
Test name
Test status
Simulation time 4429156158 ps
CPU time 63.13 seconds
Started Aug 27 03:35:02 AM UTC 24
Finished Aug 27 03:36:07 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140691450 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.4140691450
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/27.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.3917749651
Short name T80
Test name
Test status
Simulation time 65301214 ps
CPU time 14.48 seconds
Started Aug 27 03:34:58 AM UTC 24
Finished Aug 27 03:35:14 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917749651 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.3917749651
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/27.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.1456967971
Short name T517
Test name
Test status
Simulation time 6209890453 ps
CPU time 39.29 seconds
Started Aug 27 03:35:06 AM UTC 24
Finished Aug 27 03:35:47 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456967971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1456967971
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/27.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.2226551299
Short name T497
Test name
Test status
Simulation time 45617380 ps
CPU time 2.83 seconds
Started Aug 27 03:34:46 AM UTC 24
Finished Aug 27 03:34:49 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226551299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2226551299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/27.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1475492003
Short name T279
Test name
Test status
Simulation time 18897522662 ps
CPU time 57.6 seconds
Started Aug 27 03:34:56 AM UTC 24
Finished Aug 27 03:35:55 AM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475492003 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1475492003
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/27.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.572202129
Short name T539
Test name
Test status
Simulation time 22954361025 ps
CPU time 88.74 seconds
Started Aug 27 03:34:57 AM UTC 24
Finished Aug 27 03:36:28 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572202129 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.572202129
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/27.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.2629380882
Short name T498
Test name
Test status
Simulation time 64915269 ps
CPU time 3.41 seconds
Started Aug 27 03:34:51 AM UTC 24
Finished Aug 27 03:34:55 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629380882 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.2629380882
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/27.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2910944715
Short name T277
Test name
Test status
Simulation time 940139897 ps
CPU time 34.08 seconds
Started Aug 27 03:35:14 AM UTC 24
Finished Aug 27 03:35:50 AM UTC 24
Peak memory 217096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910944715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2910944715
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/27.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.1577028656
Short name T549
Test name
Test status
Simulation time 2289169021 ps
CPU time 76.57 seconds
Started Aug 27 03:35:24 AM UTC 24
Finished Aug 27 03:36:42 AM UTC 24
Peak memory 221192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577028656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.1577028656
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/27.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.2324608919
Short name T284
Test name
Test status
Simulation time 3746173886 ps
CPU time 46.97 seconds
Started Aug 27 03:35:09 AM UTC 24
Finished Aug 27 03:35:58 AM UTC 24
Peak memory 216796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324608919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2324608919
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/27.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.1899411780
Short name T520
Test name
Test status
Simulation time 167873639 ps
CPU time 13.8 seconds
Started Aug 27 03:35:46 AM UTC 24
Finished Aug 27 03:36:02 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899411780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1899411780
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/28.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2582410676
Short name T735
Test name
Test status
Simulation time 119089398335 ps
CPU time 387.58 seconds
Started Aug 27 03:35:48 AM UTC 24
Finished Aug 27 03:42:20 AM UTC 24
Peak memory 219208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582410676 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.2582410676
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/28.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.3506621754
Short name T538
Test name
Test status
Simulation time 672431809 ps
CPU time 29.42 seconds
Started Aug 27 03:35:55 AM UTC 24
Finished Aug 27 03:36:26 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506621754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.3506621754
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/28.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.2413026105
Short name T533
Test name
Test status
Simulation time 1031378258 ps
CPU time 30.19 seconds
Started Aug 27 03:35:50 AM UTC 24
Finished Aug 27 03:36:22 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413026105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2413026105
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/28.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random.3190662831
Short name T527
Test name
Test status
Simulation time 399802728 ps
CPU time 29.11 seconds
Started Aug 27 03:35:34 AM UTC 24
Finished Aug 27 03:36:04 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190662831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.3190662831
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/28.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.3328389221
Short name T590
Test name
Test status
Simulation time 24348385990 ps
CPU time 150.33 seconds
Started Aug 27 03:35:41 AM UTC 24
Finished Aug 27 03:38:14 AM UTC 24
Peak memory 217160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328389221 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3328389221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/28.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2889691631
Short name T141
Test name
Test status
Simulation time 23457625579 ps
CPU time 170.39 seconds
Started Aug 27 03:35:42 AM UTC 24
Finished Aug 27 03:38:35 AM UTC 24
Peak memory 219208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889691631 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2889691631
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/28.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.2250910220
Short name T280
Test name
Test status
Simulation time 292561010 ps
CPU time 13.14 seconds
Started Aug 27 03:35:41 AM UTC 24
Finished Aug 27 03:35:55 AM UTC 24
Peak memory 216756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250910220 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2250910220
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/28.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.2651801386
Short name T503
Test name
Test status
Simulation time 1750179782 ps
CPU time 30.99 seconds
Started Aug 27 03:35:49 AM UTC 24
Finished Aug 27 03:36:21 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651801386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2651801386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/28.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.1359173513
Short name T512
Test name
Test status
Simulation time 158158407 ps
CPU time 5.58 seconds
Started Aug 27 03:35:24 AM UTC 24
Finished Aug 27 03:35:30 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359173513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1359173513
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/28.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.1273447991
Short name T529
Test name
Test status
Simulation time 6689805905 ps
CPU time 40.85 seconds
Started Aug 27 03:35:31 AM UTC 24
Finished Aug 27 03:36:13 AM UTC 24
Peak memory 217140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273447991 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1273447991
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/28.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.1610358187
Short name T488
Test name
Test status
Simulation time 4401046503 ps
CPU time 42.67 seconds
Started Aug 27 03:35:31 AM UTC 24
Finished Aug 27 03:36:15 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610358187 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1610358187
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/28.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1501444572
Short name T511
Test name
Test status
Simulation time 39551081 ps
CPU time 3.02 seconds
Started Aug 27 03:35:26 AM UTC 24
Finished Aug 27 03:35:30 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501444572 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1501444572
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/28.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.470942758
Short name T537
Test name
Test status
Simulation time 324949305 ps
CPU time 27.7 seconds
Started Aug 27 03:35:56 AM UTC 24
Finished Aug 27 03:36:25 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470942758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.470942758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/28.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.2890281495
Short name T556
Test name
Test status
Simulation time 1780827181 ps
CPU time 52.66 seconds
Started Aug 27 03:35:58 AM UTC 24
Finished Aug 27 03:36:52 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890281495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2890281495
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/28.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1496671385
Short name T734
Test name
Test status
Simulation time 3272369160 ps
CPU time 377.93 seconds
Started Aug 27 03:35:56 AM UTC 24
Finished Aug 27 03:42:20 AM UTC 24
Peak memory 221324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496671385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.1496671385
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/28.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.3280487235
Short name T543
Test name
Test status
Simulation time 155033894 ps
CPU time 37.2 seconds
Started Aug 27 03:35:58 AM UTC 24
Finished Aug 27 03:36:37 AM UTC 24
Peak memory 218820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280487235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.3280487235
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/28.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.3663597899
Short name T534
Test name
Test status
Simulation time 1123559486 ps
CPU time 29.18 seconds
Started Aug 27 03:35:51 AM UTC 24
Finished Aug 27 03:36:22 AM UTC 24
Peak memory 218876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663597899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3663597899
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/28.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.1830052766
Short name T138
Test name
Test status
Simulation time 5280883673 ps
CPU time 61.29 seconds
Started Aug 27 03:36:05 AM UTC 24
Finished Aug 27 03:37:08 AM UTC 24
Peak memory 221256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830052766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1830052766
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/29.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3121588044
Short name T577
Test name
Test status
Simulation time 35201978914 ps
CPU time 96.29 seconds
Started Aug 27 03:36:05 AM UTC 24
Finished Aug 27 03:37:44 AM UTC 24
Peak memory 216904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121588044 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.3121588044
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/29.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.2036700332
Short name T531
Test name
Test status
Simulation time 101227714 ps
CPU time 2.82 seconds
Started Aug 27 03:36:11 AM UTC 24
Finished Aug 27 03:36:15 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036700332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.2036700332
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/29.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.3374509526
Short name T542
Test name
Test status
Simulation time 1436476433 ps
CPU time 30.4 seconds
Started Aug 27 03:36:05 AM UTC 24
Finished Aug 27 03:36:37 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374509526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3374509526
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/29.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random.401086849
Short name T544
Test name
Test status
Simulation time 873074828 ps
CPU time 32.59 seconds
Started Aug 27 03:36:03 AM UTC 24
Finished Aug 27 03:36:38 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401086849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.401086849
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/29.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.1745111999
Short name T636
Test name
Test status
Simulation time 51409381398 ps
CPU time 208.19 seconds
Started Aug 27 03:36:03 AM UTC 24
Finished Aug 27 03:39:35 AM UTC 24
Peak memory 218944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745111999 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1745111999
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/29.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.2715901116
Short name T567
Test name
Test status
Simulation time 20331208213 ps
CPU time 70.93 seconds
Started Aug 27 03:36:05 AM UTC 24
Finished Aug 27 03:37:18 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715901116 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2715901116
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/29.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.2179956601
Short name T532
Test name
Test status
Simulation time 69524887 ps
CPU time 11.66 seconds
Started Aug 27 03:36:03 AM UTC 24
Finished Aug 27 03:36:16 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179956601 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.2179956601
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/29.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.198874397
Short name T530
Test name
Test status
Simulation time 144891187 ps
CPU time 12.28 seconds
Started Aug 27 03:36:05 AM UTC 24
Finished Aug 27 03:36:19 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198874397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.198874397
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/29.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.1237415688
Short name T526
Test name
Test status
Simulation time 247575926 ps
CPU time 4.73 seconds
Started Aug 27 03:35:58 AM UTC 24
Finished Aug 27 03:36:04 AM UTC 24
Peak memory 216676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237415688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.1237415688
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/29.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.4247597426
Short name T547
Test name
Test status
Simulation time 4845186217 ps
CPU time 39.41 seconds
Started Aug 27 03:35:59 AM UTC 24
Finished Aug 27 03:36:40 AM UTC 24
Peak memory 217140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247597426 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.4247597426
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/29.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.3051450756
Short name T546
Test name
Test status
Simulation time 7692351227 ps
CPU time 35.55 seconds
Started Aug 27 03:36:02 AM UTC 24
Finished Aug 27 03:36:39 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051450756 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3051450756
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/29.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.1546087003
Short name T525
Test name
Test status
Simulation time 50201862 ps
CPU time 3.41 seconds
Started Aug 27 03:35:59 AM UTC 24
Finished Aug 27 03:36:04 AM UTC 24
Peak memory 217068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546087003 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.1546087003
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/29.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.4086149836
Short name T628
Test name
Test status
Simulation time 1503602753 ps
CPU time 178.58 seconds
Started Aug 27 03:36:13 AM UTC 24
Finished Aug 27 03:39:15 AM UTC 24
Peak memory 223616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086149836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.4086149836
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/29.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.114757275
Short name T576
Test name
Test status
Simulation time 3120763259 ps
CPU time 83.37 seconds
Started Aug 27 03:36:16 AM UTC 24
Finished Aug 27 03:37:41 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114757275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.114757275
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/29.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.4281835511
Short name T722
Test name
Test status
Simulation time 3420746392 ps
CPU time 340.86 seconds
Started Aug 27 03:36:16 AM UTC 24
Finished Aug 27 03:42:01 AM UTC 24
Peak memory 223188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281835511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.4281835511
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/29.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.1750152017
Short name T613
Test name
Test status
Simulation time 387915679 ps
CPU time 149.26 seconds
Started Aug 27 03:36:18 AM UTC 24
Finished Aug 27 03:38:50 AM UTC 24
Peak memory 222980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750152017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.1750152017
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/29.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.1214474414
Short name T220
Test name
Test status
Simulation time 1434272372 ps
CPU time 25.55 seconds
Started Aug 27 03:36:07 AM UTC 24
Finished Aug 27 03:36:34 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214474414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.1214474414
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/29.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.1269171657
Short name T25
Test name
Test status
Simulation time 688534745 ps
CPU time 20.11 seconds
Started Aug 27 03:24:46 AM UTC 24
Finished Aug 27 03:25:08 AM UTC 24
Peak memory 218820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269171657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1269171657
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/3.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.434311597
Short name T125
Test name
Test status
Simulation time 6738899748 ps
CPU time 69.41 seconds
Started Aug 27 03:24:46 AM UTC 24
Finished Aug 27 03:25:58 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434311597 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.434311597
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/3.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.708541912
Short name T291
Test name
Test status
Simulation time 1193116882 ps
CPU time 27.96 seconds
Started Aug 27 03:24:49 AM UTC 24
Finished Aug 27 03:25:18 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708541912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.708541912
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/3.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.3173666679
Short name T213
Test name
Test status
Simulation time 3509823532 ps
CPU time 39.18 seconds
Started Aug 27 03:24:47 AM UTC 24
Finished Aug 27 03:25:27 AM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173666679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3173666679
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/3.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random.1884825636
Short name T234
Test name
Test status
Simulation time 185943842 ps
CPU time 29.25 seconds
Started Aug 27 03:24:46 AM UTC 24
Finished Aug 27 03:25:17 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884825636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.1884825636
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/3.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.2111466058
Short name T105
Test name
Test status
Simulation time 86769451100 ps
CPU time 177.88 seconds
Started Aug 27 03:24:46 AM UTC 24
Finished Aug 27 03:27:47 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111466058 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2111466058
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/3.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.2003067764
Short name T266
Test name
Test status
Simulation time 19969123099 ps
CPU time 132.94 seconds
Started Aug 27 03:24:46 AM UTC 24
Finished Aug 27 03:27:02 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003067764 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.2003067764
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/3.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.1055543102
Short name T27
Test name
Test status
Simulation time 540872770 ps
CPU time 23.9 seconds
Started Aug 27 03:24:46 AM UTC 24
Finished Aug 27 03:25:12 AM UTC 24
Peak memory 217148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055543102 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.1055543102
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/3.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.2617089344
Short name T39
Test name
Test status
Simulation time 1604159048 ps
CPU time 26.65 seconds
Started Aug 27 03:24:47 AM UTC 24
Finished Aug 27 03:25:15 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617089344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2617089344
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/3.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.984707833
Short name T8
Test name
Test status
Simulation time 382198767 ps
CPU time 4.16 seconds
Started Aug 27 03:24:46 AM UTC 24
Finished Aug 27 03:24:51 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984707833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.984707833
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/3.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3306630132
Short name T124
Test name
Test status
Simulation time 34095450562 ps
CPU time 69.53 seconds
Started Aug 27 03:24:46 AM UTC 24
Finished Aug 27 03:25:58 AM UTC 24
Peak memory 217008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306630132 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3306630132
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/3.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1125670888
Short name T66
Test name
Test status
Simulation time 5913931796 ps
CPU time 39.14 seconds
Started Aug 27 03:24:46 AM UTC 24
Finished Aug 27 03:25:27 AM UTC 24
Peak memory 217016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125670888 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1125670888
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/3.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3295939111
Short name T15
Test name
Test status
Simulation time 74924484 ps
CPU time 3.14 seconds
Started Aug 27 03:24:46 AM UTC 24
Finished Aug 27 03:24:50 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295939111 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3295939111
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/3.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.3729974142
Short name T162
Test name
Test status
Simulation time 1441093223 ps
CPU time 82.94 seconds
Started Aug 27 03:24:50 AM UTC 24
Finished Aug 27 03:26:15 AM UTC 24
Peak memory 220868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729974142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3729974142
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/3.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3472444621
Short name T48
Test name
Test status
Simulation time 153397712 ps
CPU time 22.46 seconds
Started Aug 27 03:24:51 AM UTC 24
Finished Aug 27 03:25:18 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472444621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3472444621
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/3.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.2772485607
Short name T169
Test name
Test status
Simulation time 2015801097 ps
CPU time 328.98 seconds
Started Aug 27 03:24:51 AM UTC 24
Finished Aug 27 03:30:25 AM UTC 24
Peak memory 221004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772485607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.2772485607
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/3.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1023454489
Short name T247
Test name
Test status
Simulation time 887382434 ps
CPU time 197.48 seconds
Started Aug 27 03:24:52 AM UTC 24
Finished Aug 27 03:28:16 AM UTC 24
Peak memory 223352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023454489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.1023454489
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/3.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.2742425941
Short name T26
Test name
Test status
Simulation time 163573337 ps
CPU time 18.49 seconds
Started Aug 27 03:24:49 AM UTC 24
Finished Aug 27 03:25:08 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742425941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2742425941
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/3.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.1140103365
Short name T557
Test name
Test status
Simulation time 2669016235 ps
CPU time 24.19 seconds
Started Aug 27 03:36:28 AM UTC 24
Finished Aug 27 03:36:53 AM UTC 24
Peak memory 217160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140103365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1140103365
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/30.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.519273751
Short name T654
Test name
Test status
Simulation time 20819666074 ps
CPU time 211.42 seconds
Started Aug 27 03:36:29 AM UTC 24
Finished Aug 27 03:40:03 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519273751 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.519273751
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/30.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.427232975
Short name T548
Test name
Test status
Simulation time 79458849 ps
CPU time 4.79 seconds
Started Aug 27 03:36:35 AM UTC 24
Finished Aug 27 03:36:41 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427232975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.427232975
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/30.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.1918282237
Short name T553
Test name
Test status
Simulation time 475657869 ps
CPU time 9.22 seconds
Started Aug 27 03:36:34 AM UTC 24
Finished Aug 27 03:36:44 AM UTC 24
Peak memory 217080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918282237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1918282237
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/30.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random.673091572
Short name T540
Test name
Test status
Simulation time 32612924 ps
CPU time 5.69 seconds
Started Aug 27 03:36:23 AM UTC 24
Finished Aug 27 03:36:30 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673091572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.673091572
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/30.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.1722959704
Short name T142
Test name
Test status
Simulation time 157715442094 ps
CPU time 262.37 seconds
Started Aug 27 03:36:27 AM UTC 24
Finished Aug 27 03:40:52 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722959704 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1722959704
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/30.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3195619247
Short name T791
Test name
Test status
Simulation time 229096735353 ps
CPU time 430.5 seconds
Started Aug 27 03:36:28 AM UTC 24
Finished Aug 27 03:43:43 AM UTC 24
Peak memory 219204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195619247 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3195619247
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/30.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.1313333642
Short name T541
Test name
Test status
Simulation time 43921635 ps
CPU time 6.56 seconds
Started Aug 27 03:36:25 AM UTC 24
Finished Aug 27 03:36:33 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313333642 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.1313333642
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/30.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.2434158397
Short name T545
Test name
Test status
Simulation time 297058704 ps
CPU time 6.18 seconds
Started Aug 27 03:36:31 AM UTC 24
Finished Aug 27 03:36:38 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434158397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2434158397
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/30.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.1918664092
Short name T536
Test name
Test status
Simulation time 34872944 ps
CPU time 3.42 seconds
Started Aug 27 03:36:20 AM UTC 24
Finished Aug 27 03:36:24 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918664092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1918664092
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/30.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.561978724
Short name T555
Test name
Test status
Simulation time 4400552321 ps
CPU time 21.84 seconds
Started Aug 27 03:36:23 AM UTC 24
Finished Aug 27 03:36:46 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561978724 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.561978724
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/30.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2435724822
Short name T562
Test name
Test status
Simulation time 9225542987 ps
CPU time 44.82 seconds
Started Aug 27 03:36:23 AM UTC 24
Finished Aug 27 03:37:10 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435724822 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2435724822
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/30.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.1210164221
Short name T155
Test name
Test status
Simulation time 78994542 ps
CPU time 3.21 seconds
Started Aug 27 03:36:22 AM UTC 24
Finished Aug 27 03:36:26 AM UTC 24
Peak memory 217068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210164221 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.1210164221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/30.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.3332564066
Short name T238
Test name
Test status
Simulation time 980504039 ps
CPU time 105.3 seconds
Started Aug 27 03:36:38 AM UTC 24
Finished Aug 27 03:38:25 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332564066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3332564066
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/30.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3714119297
Short name T569
Test name
Test status
Simulation time 433335043 ps
CPU time 44.37 seconds
Started Aug 27 03:36:38 AM UTC 24
Finished Aug 27 03:37:24 AM UTC 24
Peak memory 218820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714119297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3714119297
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/30.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.3767777334
Short name T648
Test name
Test status
Simulation time 978501810 ps
CPU time 194.46 seconds
Started Aug 27 03:36:38 AM UTC 24
Finished Aug 27 03:39:55 AM UTC 24
Peak memory 222920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767777334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.3767777334
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/30.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1193816383
Short name T650
Test name
Test status
Simulation time 691481486 ps
CPU time 196.34 seconds
Started Aug 27 03:36:39 AM UTC 24
Finished Aug 27 03:39:59 AM UTC 24
Peak memory 233524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193816383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.1193816383
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/30.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.205453315
Short name T563
Test name
Test status
Simulation time 1299769293 ps
CPU time 35.82 seconds
Started Aug 27 03:36:34 AM UTC 24
Finished Aug 27 03:37:11 AM UTC 24
Peak memory 218876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205453315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.205453315
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/30.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.734576583
Short name T570
Test name
Test status
Simulation time 297301351 ps
CPU time 38.53 seconds
Started Aug 27 03:36:45 AM UTC 24
Finished Aug 27 03:37:25 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734576583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.734576583
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/31.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.639685911
Short name T596
Test name
Test status
Simulation time 22407025731 ps
CPU time 90.54 seconds
Started Aug 27 03:36:45 AM UTC 24
Finished Aug 27 03:38:17 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639685911 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.639685911
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/31.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.996537942
Short name T560
Test name
Test status
Simulation time 474296281 ps
CPU time 13.13 seconds
Started Aug 27 03:36:54 AM UTC 24
Finished Aug 27 03:37:08 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996537942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.996537942
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/31.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.1318481705
Short name T561
Test name
Test status
Simulation time 755815508 ps
CPU time 20.07 seconds
Started Aug 27 03:36:47 AM UTC 24
Finished Aug 27 03:37:09 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318481705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1318481705
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/31.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random.2646308329
Short name T566
Test name
Test status
Simulation time 2458127054 ps
CPU time 32.13 seconds
Started Aug 27 03:36:43 AM UTC 24
Finished Aug 27 03:37:16 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646308329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.2646308329
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/31.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.3195478818
Short name T676
Test name
Test status
Simulation time 36748339986 ps
CPU time 229.19 seconds
Started Aug 27 03:36:43 AM UTC 24
Finished Aug 27 03:40:35 AM UTC 24
Peak memory 219208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195478818 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3195478818
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/31.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.707343047
Short name T700
Test name
Test status
Simulation time 43839706344 ps
CPU time 273.74 seconds
Started Aug 27 03:36:44 AM UTC 24
Finished Aug 27 03:41:21 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707343047 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.707343047
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/31.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.768519190
Short name T558
Test name
Test status
Simulation time 426169655 ps
CPU time 13.27 seconds
Started Aug 27 03:36:43 AM UTC 24
Finished Aug 27 03:36:57 AM UTC 24
Peak memory 216892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768519190 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.768519190
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/31.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.1079379872
Short name T571
Test name
Test status
Simulation time 6528647681 ps
CPU time 39.61 seconds
Started Aug 27 03:36:46 AM UTC 24
Finished Aug 27 03:37:27 AM UTC 24
Peak memory 216892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079379872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1079379872
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/31.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.440056867
Short name T551
Test name
Test status
Simulation time 21724758 ps
CPU time 2.64 seconds
Started Aug 27 03:36:39 AM UTC 24
Finished Aug 27 03:36:43 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440056867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.440056867
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/31.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.4108087371
Short name T575
Test name
Test status
Simulation time 23304964768 ps
CPU time 54.16 seconds
Started Aug 27 03:36:41 AM UTC 24
Finished Aug 27 03:37:37 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108087371 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.4108087371
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/31.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.3361486035
Short name T82
Test name
Test status
Simulation time 9224036367 ps
CPU time 40.94 seconds
Started Aug 27 03:36:43 AM UTC 24
Finished Aug 27 03:37:25 AM UTC 24
Peak memory 217136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361486035 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3361486035
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/31.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.2820478718
Short name T552
Test name
Test status
Simulation time 59590491 ps
CPU time 3.04 seconds
Started Aug 27 03:36:40 AM UTC 24
Finished Aug 27 03:36:44 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820478718 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.2820478718
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/31.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.404477954
Short name T694
Test name
Test status
Simulation time 11621919562 ps
CPU time 253.5 seconds
Started Aug 27 03:36:58 AM UTC 24
Finished Aug 27 03:41:15 AM UTC 24
Peak memory 220928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404477954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.404477954
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/31.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.939288853
Short name T568
Test name
Test status
Simulation time 194241276 ps
CPU time 13.08 seconds
Started Aug 27 03:37:09 AM UTC 24
Finished Aug 27 03:37:23 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939288853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.939288853
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/31.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1547772812
Short name T780
Test name
Test status
Simulation time 6490333209 ps
CPU time 417.56 seconds
Started Aug 27 03:37:00 AM UTC 24
Finished Aug 27 03:44:03 AM UTC 24
Peak memory 223048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547772812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.1547772812
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/31.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.1790283474
Short name T868
Test name
Test status
Simulation time 14450837803 ps
CPU time 543.76 seconds
Started Aug 27 03:37:09 AM UTC 24
Finished Aug 27 03:46:20 AM UTC 24
Peak memory 235208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790283474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.1790283474
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/31.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.1473997001
Short name T559
Test name
Test status
Simulation time 52840180 ps
CPU time 4.04 seconds
Started Aug 27 03:36:54 AM UTC 24
Finished Aug 27 03:36:59 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473997001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1473997001
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/31.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.317442668
Short name T574
Test name
Test status
Simulation time 87761576 ps
CPU time 5.91 seconds
Started Aug 27 03:37:25 AM UTC 24
Finished Aug 27 03:37:32 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317442668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.317442668
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/32.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3476902261
Short name T774
Test name
Test status
Simulation time 76208994776 ps
CPU time 342.06 seconds
Started Aug 27 03:37:26 AM UTC 24
Finished Aug 27 03:43:13 AM UTC 24
Peak memory 218952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476902261 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.3476902261
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/32.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.371048820
Short name T581
Test name
Test status
Simulation time 459691285 ps
CPU time 15.96 seconds
Started Aug 27 03:37:28 AM UTC 24
Finished Aug 27 03:37:46 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371048820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.371048820
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/32.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.1659329877
Short name T582
Test name
Test status
Simulation time 265899758 ps
CPU time 17.28 seconds
Started Aug 27 03:37:28 AM UTC 24
Finished Aug 27 03:37:47 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659329877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1659329877
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/32.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random.2763258371
Short name T585
Test name
Test status
Simulation time 1659010691 ps
CPU time 30.69 seconds
Started Aug 27 03:37:15 AM UTC 24
Finished Aug 27 03:37:47 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763258371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.2763258371
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/32.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.125968286
Short name T632
Test name
Test status
Simulation time 26333661703 ps
CPU time 121.7 seconds
Started Aug 27 03:37:19 AM UTC 24
Finished Aug 27 03:39:23 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125968286 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.125968286
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/32.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1049743136
Short name T695
Test name
Test status
Simulation time 25436854403 ps
CPU time 228.1 seconds
Started Aug 27 03:37:24 AM UTC 24
Finished Aug 27 03:41:15 AM UTC 24
Peak memory 218888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049743136 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1049743136
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/32.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.2403075107
Short name T573
Test name
Test status
Simulation time 227962241 ps
CPU time 10.59 seconds
Started Aug 27 03:37:18 AM UTC 24
Finished Aug 27 03:37:29 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403075107 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.2403075107
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/32.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.4170532147
Short name T587
Test name
Test status
Simulation time 770534092 ps
CPU time 22.85 seconds
Started Aug 27 03:37:26 AM UTC 24
Finished Aug 27 03:37:50 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170532147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.4170532147
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/32.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.1065738816
Short name T564
Test name
Test status
Simulation time 230862889 ps
CPU time 4.48 seconds
Started Aug 27 03:37:09 AM UTC 24
Finished Aug 27 03:37:15 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065738816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1065738816
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/32.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.2926820645
Short name T594
Test name
Test status
Simulation time 10205631633 ps
CPU time 62.27 seconds
Started Aug 27 03:37:12 AM UTC 24
Finished Aug 27 03:38:16 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926820645 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2926820645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/32.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2261963926
Short name T580
Test name
Test status
Simulation time 3031764049 ps
CPU time 28.28 seconds
Started Aug 27 03:37:15 AM UTC 24
Finished Aug 27 03:37:45 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261963926 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2261963926
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/32.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.792046694
Short name T565
Test name
Test status
Simulation time 67141648 ps
CPU time 3.36 seconds
Started Aug 27 03:37:10 AM UTC 24
Finished Aug 27 03:37:15 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792046694 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.792046694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/32.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.3638700812
Short name T634
Test name
Test status
Simulation time 1172805896 ps
CPU time 114.04 seconds
Started Aug 27 03:37:30 AM UTC 24
Finished Aug 27 03:39:27 AM UTC 24
Peak memory 223236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638700812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.3638700812
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/32.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.2006863794
Short name T630
Test name
Test status
Simulation time 12614814876 ps
CPU time 105.04 seconds
Started Aug 27 03:37:33 AM UTC 24
Finished Aug 27 03:39:21 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006863794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2006863794
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/32.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3268118339
Short name T619
Test name
Test status
Simulation time 288860090 ps
CPU time 90.19 seconds
Started Aug 27 03:37:32 AM UTC 24
Finished Aug 27 03:39:04 AM UTC 24
Peak memory 220872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268118339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.3268118339
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/32.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.1355370018
Short name T755
Test name
Test status
Simulation time 2877172063 ps
CPU time 304.16 seconds
Started Aug 27 03:37:36 AM UTC 24
Finished Aug 27 03:42:45 AM UTC 24
Peak memory 233656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355370018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.1355370018
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/32.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.3427120507
Short name T584
Test name
Test status
Simulation time 222452153 ps
CPU time 17.46 seconds
Started Aug 27 03:37:28 AM UTC 24
Finished Aug 27 03:37:47 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427120507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3427120507
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/32.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.2651538370
Short name T222
Test name
Test status
Simulation time 804021927 ps
CPU time 56.44 seconds
Started Aug 27 03:37:48 AM UTC 24
Finished Aug 27 03:38:47 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651538370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.2651538370
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/33.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2545100235
Short name T891
Test name
Test status
Simulation time 129694522532 ps
CPU time 668.84 seconds
Started Aug 27 03:37:48 AM UTC 24
Finished Aug 27 03:49:05 AM UTC 24
Peak memory 222936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545100235 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.2545100235
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/33.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.4116923217
Short name T597
Test name
Test status
Simulation time 3244475852 ps
CPU time 26.77 seconds
Started Aug 27 03:37:51 AM UTC 24
Finished Aug 27 03:38:20 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116923217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.4116923217
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/33.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.60021615
Short name T588
Test name
Test status
Simulation time 130642873 ps
CPU time 9.71 seconds
Started Aug 27 03:37:48 AM UTC 24
Finished Aug 27 03:37:59 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60021615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.60021615
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/33.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random.4277873514
Short name T237
Test name
Test status
Simulation time 144624844 ps
CPU time 14.61 seconds
Started Aug 27 03:37:45 AM UTC 24
Finished Aug 27 03:38:00 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277873514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.4277873514
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/33.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.2780342498
Short name T228
Test name
Test status
Simulation time 33807564743 ps
CPU time 151.71 seconds
Started Aug 27 03:37:46 AM UTC 24
Finished Aug 27 03:40:20 AM UTC 24
Peak memory 216892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780342498 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2780342498
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/33.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3058833391
Short name T589
Test name
Test status
Simulation time 3650725321 ps
CPU time 20.91 seconds
Started Aug 27 03:37:47 AM UTC 24
Finished Aug 27 03:38:09 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058833391 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3058833391
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/33.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.1770928611
Short name T595
Test name
Test status
Simulation time 294862225 ps
CPU time 29.54 seconds
Started Aug 27 03:37:46 AM UTC 24
Finished Aug 27 03:38:17 AM UTC 24
Peak memory 218808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770928611 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1770928611
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/33.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.3880225553
Short name T602
Test name
Test status
Simulation time 3038387075 ps
CPU time 37.74 seconds
Started Aug 27 03:37:48 AM UTC 24
Finished Aug 27 03:38:28 AM UTC 24
Peak memory 216892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880225553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3880225553
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/33.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.3675867856
Short name T578
Test name
Test status
Simulation time 324438368 ps
CPU time 4.77 seconds
Started Aug 27 03:37:38 AM UTC 24
Finished Aug 27 03:37:44 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675867856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.3675867856
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/33.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.3755403616
Short name T600
Test name
Test status
Simulation time 8603237458 ps
CPU time 37.11 seconds
Started Aug 27 03:37:44 AM UTC 24
Finished Aug 27 03:38:23 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755403616 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3755403616
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/33.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1422071173
Short name T610
Test name
Test status
Simulation time 17048240093 ps
CPU time 60.48 seconds
Started Aug 27 03:37:45 AM UTC 24
Finished Aug 27 03:38:47 AM UTC 24
Peak memory 217008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422071173 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1422071173
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/33.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.1586151081
Short name T583
Test name
Test status
Simulation time 144822149 ps
CPU time 3.64 seconds
Started Aug 27 03:37:42 AM UTC 24
Finished Aug 27 03:37:47 AM UTC 24
Peak memory 217072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586151081 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.1586151081
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/33.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.1193203748
Short name T741
Test name
Test status
Simulation time 21460631638 ps
CPU time 271.26 seconds
Started Aug 27 03:37:52 AM UTC 24
Finished Aug 27 03:42:27 AM UTC 24
Peak memory 220928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193203748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1193203748
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/33.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.4099982460
Short name T649
Test name
Test status
Simulation time 1251396908 ps
CPU time 115.74 seconds
Started Aug 27 03:38:00 AM UTC 24
Finished Aug 27 03:39:58 AM UTC 24
Peak memory 220936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099982460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.4099982460
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/33.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1036648160
Short name T729
Test name
Test status
Simulation time 1931550700 ps
CPU time 248 seconds
Started Aug 27 03:37:55 AM UTC 24
Finished Aug 27 03:42:07 AM UTC 24
Peak memory 223052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036648160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.1036648160
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/33.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.3593422333
Short name T686
Test name
Test status
Simulation time 1369095604 ps
CPU time 180.33 seconds
Started Aug 27 03:38:01 AM UTC 24
Finished Aug 27 03:41:04 AM UTC 24
Peak memory 222984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593422333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.3593422333
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/33.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.908391872
Short name T599
Test name
Test status
Simulation time 790748312 ps
CPU time 32.81 seconds
Started Aug 27 03:37:48 AM UTC 24
Finished Aug 27 03:38:23 AM UTC 24
Peak memory 218944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908391872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.908391872
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/33.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.717628774
Short name T625
Test name
Test status
Simulation time 920530020 ps
CPU time 52.89 seconds
Started Aug 27 03:38:18 AM UTC 24
Finished Aug 27 03:39:12 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717628774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.717628774
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/34.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3784677948
Short name T85
Test name
Test status
Simulation time 100967700636 ps
CPU time 601.42 seconds
Started Aug 27 03:38:18 AM UTC 24
Finished Aug 27 03:48:26 AM UTC 24
Peak memory 222544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784677948 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.3784677948
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/34.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.3920697140
Short name T604
Test name
Test status
Simulation time 49513055 ps
CPU time 4.85 seconds
Started Aug 27 03:38:24 AM UTC 24
Finished Aug 27 03:38:29 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920697140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.3920697140
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/34.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.1451822157
Short name T607
Test name
Test status
Simulation time 503250302 ps
CPU time 18.71 seconds
Started Aug 27 03:38:21 AM UTC 24
Finished Aug 27 03:38:41 AM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451822157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1451822157
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/34.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random.3920192704
Short name T598
Test name
Test status
Simulation time 33531708 ps
CPU time 4.27 seconds
Started Aug 27 03:38:15 AM UTC 24
Finished Aug 27 03:38:21 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920192704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3920192704
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/34.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.41770546
Short name T742
Test name
Test status
Simulation time 40448532206 ps
CPU time 248.98 seconds
Started Aug 27 03:38:17 AM UTC 24
Finished Aug 27 03:42:29 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41770546 -assert nopostproc +UVM_TESTNAME=xbar_base_
test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.41770546
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/34.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.3832674423
Short name T693
Test name
Test status
Simulation time 29162499048 ps
CPU time 173.12 seconds
Started Aug 27 03:38:17 AM UTC 24
Finished Aug 27 03:41:12 AM UTC 24
Peak memory 216904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832674423 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.3832674423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/34.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.3959834163
Short name T601
Test name
Test status
Simulation time 50829402 ps
CPU time 5.57 seconds
Started Aug 27 03:38:17 AM UTC 24
Finished Aug 27 03:38:23 AM UTC 24
Peak memory 217080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959834163 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3959834163
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/34.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.3852629549
Short name T608
Test name
Test status
Simulation time 1304094891 ps
CPU time 21.57 seconds
Started Aug 27 03:38:21 AM UTC 24
Finished Aug 27 03:38:44 AM UTC 24
Peak memory 216756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852629549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3852629549
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/34.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.1306957518
Short name T591
Test name
Test status
Simulation time 47907055 ps
CPU time 3.12 seconds
Started Aug 27 03:38:10 AM UTC 24
Finished Aug 27 03:38:14 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306957518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1306957518
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/34.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.1860000723
Short name T612
Test name
Test status
Simulation time 4763329534 ps
CPU time 32.56 seconds
Started Aug 27 03:38:15 AM UTC 24
Finished Aug 27 03:38:49 AM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860000723 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1860000723
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/34.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.750791366
Short name T617
Test name
Test status
Simulation time 3955322445 ps
CPU time 43.75 seconds
Started Aug 27 03:38:15 AM UTC 24
Finished Aug 27 03:39:00 AM UTC 24
Peak memory 217200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750791366 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.750791366
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/34.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3894717250
Short name T593
Test name
Test status
Simulation time 103159690 ps
CPU time 2.93 seconds
Started Aug 27 03:38:12 AM UTC 24
Finished Aug 27 03:38:16 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894717250 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3894717250
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/34.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.169768689
Short name T144
Test name
Test status
Simulation time 16977837529 ps
CPU time 184.47 seconds
Started Aug 27 03:38:24 AM UTC 24
Finished Aug 27 03:41:31 AM UTC 24
Peak memory 223048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169768689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.169768689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/34.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.2205666983
Short name T767
Test name
Test status
Simulation time 13362482850 ps
CPU time 272.36 seconds
Started Aug 27 03:38:26 AM UTC 24
Finished Aug 27 03:43:02 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205666983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2205666983
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/34.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1563395297
Short name T253
Test name
Test status
Simulation time 1142331036 ps
CPU time 181.61 seconds
Started Aug 27 03:38:25 AM UTC 24
Finished Aug 27 03:41:29 AM UTC 24
Peak memory 223308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563395297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.1563395297
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/34.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3191440638
Short name T611
Test name
Test status
Simulation time 594417576 ps
CPU time 18.93 seconds
Started Aug 27 03:38:29 AM UTC 24
Finished Aug 27 03:38:49 AM UTC 24
Peak memory 217096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191440638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.3191440638
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/34.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.3730478385
Short name T609
Test name
Test status
Simulation time 157976425 ps
CPU time 19.58 seconds
Started Aug 27 03:38:23 AM UTC 24
Finished Aug 27 03:38:44 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730478385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3730478385
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/34.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.1541367888
Short name T621
Test name
Test status
Simulation time 257438486 ps
CPU time 17.81 seconds
Started Aug 27 03:38:48 AM UTC 24
Finished Aug 27 03:39:07 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541367888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.1541367888
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/35.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3348100175
Short name T810
Test name
Test status
Simulation time 100694846184 ps
CPU time 326.7 seconds
Started Aug 27 03:38:48 AM UTC 24
Finished Aug 27 03:44:18 AM UTC 24
Peak memory 219272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348100175 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.3348100175
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/35.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.2989929765
Short name T633
Test name
Test status
Simulation time 1328801374 ps
CPU time 26.95 seconds
Started Aug 27 03:38:58 AM UTC 24
Finished Aug 27 03:39:27 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989929765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.2989929765
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/35.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.2267887234
Short name T614
Test name
Test status
Simulation time 168044332 ps
CPU time 6.19 seconds
Started Aug 27 03:38:50 AM UTC 24
Finished Aug 27 03:38:57 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267887234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2267887234
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/35.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random.3120990724
Short name T626
Test name
Test status
Simulation time 1406118547 ps
CPU time 35.04 seconds
Started Aug 27 03:38:36 AM UTC 24
Finished Aug 27 03:39:13 AM UTC 24
Peak memory 217096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120990724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.3120990724
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/35.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.2167306739
Short name T286
Test name
Test status
Simulation time 4882958710 ps
CPU time 46.61 seconds
Started Aug 27 03:38:45 AM UTC 24
Finished Aug 27 03:39:33 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167306739 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2167306739
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/35.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3723365446
Short name T618
Test name
Test status
Simulation time 1928539623 ps
CPU time 15.22 seconds
Started Aug 27 03:38:45 AM UTC 24
Finished Aug 27 03:39:01 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723365446 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3723365446
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/35.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.1206389076
Short name T620
Test name
Test status
Simulation time 231124176 ps
CPU time 23.69 seconds
Started Aug 27 03:38:41 AM UTC 24
Finished Aug 27 03:39:06 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206389076 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1206389076
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/35.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.2623714102
Short name T615
Test name
Test status
Simulation time 79701139 ps
CPU time 8.3 seconds
Started Aug 27 03:38:50 AM UTC 24
Finished Aug 27 03:38:59 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623714102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2623714102
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/35.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.1021591271
Short name T606
Test name
Test status
Simulation time 183539632 ps
CPU time 4.77 seconds
Started Aug 27 03:38:29 AM UTC 24
Finished Aug 27 03:38:35 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021591271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1021591271
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/35.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1966507136
Short name T631
Test name
Test status
Simulation time 4488884809 ps
CPU time 45.6 seconds
Started Aug 27 03:38:35 AM UTC 24
Finished Aug 27 03:39:22 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966507136 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1966507136
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/35.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.2939426289
Short name T622
Test name
Test status
Simulation time 3898240922 ps
CPU time 31.76 seconds
Started Aug 27 03:38:35 AM UTC 24
Finished Aug 27 03:39:08 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939426289 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2939426289
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/35.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1157454508
Short name T605
Test name
Test status
Simulation time 159237687 ps
CPU time 3.53 seconds
Started Aug 27 03:38:30 AM UTC 24
Finished Aug 27 03:38:35 AM UTC 24
Peak memory 216940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157454508 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1157454508
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/35.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.2485313070
Short name T637
Test name
Test status
Simulation time 835902351 ps
CPU time 34.28 seconds
Started Aug 27 03:39:01 AM UTC 24
Finished Aug 27 03:39:36 AM UTC 24
Peak memory 219204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485313070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2485313070
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/35.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3393159863
Short name T652
Test name
Test status
Simulation time 6826384132 ps
CPU time 57.84 seconds
Started Aug 27 03:39:02 AM UTC 24
Finished Aug 27 03:40:01 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393159863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3393159863
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/35.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.3418544843
Short name T702
Test name
Test status
Simulation time 265018236 ps
CPU time 142.95 seconds
Started Aug 27 03:39:01 AM UTC 24
Finished Aug 27 03:41:26 AM UTC 24
Peak memory 220936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418544843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.3418544843
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/35.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.2574962564
Short name T665
Test name
Test status
Simulation time 248899628 ps
CPU time 73.61 seconds
Started Aug 27 03:39:02 AM UTC 24
Finished Aug 27 03:40:17 AM UTC 24
Peak memory 221064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574962564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.2574962564
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/35.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.3518165899
Short name T616
Test name
Test status
Simulation time 139644414 ps
CPU time 7.26 seconds
Started Aug 27 03:38:51 AM UTC 24
Finished Aug 27 03:39:00 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518165899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3518165899
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/35.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.1961431446
Short name T251
Test name
Test status
Simulation time 121358517 ps
CPU time 5.68 seconds
Started Aug 27 03:39:16 AM UTC 24
Finished Aug 27 03:39:23 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961431446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.1961431446
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/36.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3231904796
Short name T662
Test name
Test status
Simulation time 4767883463 ps
CPU time 52.51 seconds
Started Aug 27 03:39:16 AM UTC 24
Finished Aug 27 03:40:10 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231904796 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.3231904796
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/36.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.413238639
Short name T641
Test name
Test status
Simulation time 962454951 ps
CPU time 15.68 seconds
Started Aug 27 03:39:23 AM UTC 24
Finished Aug 27 03:39:41 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413238639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.413238639
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/36.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.1968138795
Short name T655
Test name
Test status
Simulation time 1178964707 ps
CPU time 39.74 seconds
Started Aug 27 03:39:22 AM UTC 24
Finished Aug 27 03:40:04 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968138795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1968138795
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/36.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random.3828290992
Short name T643
Test name
Test status
Simulation time 623480307 ps
CPU time 31.6 seconds
Started Aug 27 03:39:12 AM UTC 24
Finished Aug 27 03:39:45 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828290992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.3828290992
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/36.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.3713481165
Short name T151
Test name
Test status
Simulation time 23442092605 ps
CPU time 154.47 seconds
Started Aug 27 03:39:13 AM UTC 24
Finished Aug 27 03:41:51 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713481165 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3713481165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/36.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.3081548173
Short name T764
Test name
Test status
Simulation time 43898234398 ps
CPU time 221.77 seconds
Started Aug 27 03:39:14 AM UTC 24
Finished Aug 27 03:42:59 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081548173 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3081548173
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/36.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.4136723179
Short name T629
Test name
Test status
Simulation time 28985119 ps
CPU time 2.68 seconds
Started Aug 27 03:39:12 AM UTC 24
Finished Aug 27 03:39:16 AM UTC 24
Peak memory 216752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136723179 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.4136723179
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/36.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.396668254
Short name T635
Test name
Test status
Simulation time 819318390 ps
CPU time 11.67 seconds
Started Aug 27 03:39:17 AM UTC 24
Finished Aug 27 03:39:30 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396668254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.396668254
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/36.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.2738091227
Short name T623
Test name
Test status
Simulation time 150311379 ps
CPU time 5.29 seconds
Started Aug 27 03:39:05 AM UTC 24
Finished Aug 27 03:39:11 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738091227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2738091227
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/36.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2602645492
Short name T642
Test name
Test status
Simulation time 12841097210 ps
CPU time 35.45 seconds
Started Aug 27 03:39:08 AM UTC 24
Finished Aug 27 03:39:45 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602645492 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2602645492
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/36.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.1707793722
Short name T645
Test name
Test status
Simulation time 3208431338 ps
CPU time 35.06 seconds
Started Aug 27 03:39:09 AM UTC 24
Finished Aug 27 03:39:46 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707793722 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1707793722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/36.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1032563630
Short name T624
Test name
Test status
Simulation time 123448303 ps
CPU time 3.25 seconds
Started Aug 27 03:39:07 AM UTC 24
Finished Aug 27 03:39:11 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032563630 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1032563630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/36.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.1282839440
Short name T657
Test name
Test status
Simulation time 313692845 ps
CPU time 41.93 seconds
Started Aug 27 03:39:23 AM UTC 24
Finished Aug 27 03:40:07 AM UTC 24
Peak memory 219076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282839440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1282839440
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/36.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1308487018
Short name T683
Test name
Test status
Simulation time 19548306834 ps
CPU time 84.99 seconds
Started Aug 27 03:39:28 AM UTC 24
Finished Aug 27 03:40:55 AM UTC 24
Peak memory 218952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308487018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1308487018
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/36.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2885286389
Short name T44
Test name
Test status
Simulation time 5375255923 ps
CPU time 458.32 seconds
Started Aug 27 03:39:28 AM UTC 24
Finished Aug 27 03:47:12 AM UTC 24
Peak memory 233660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885286389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.2885286389
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/36.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.19099268
Short name T704
Test name
Test status
Simulation time 334477508 ps
CPU time 117.46 seconds
Started Aug 27 03:39:31 AM UTC 24
Finished Aug 27 03:41:31 AM UTC 24
Peak memory 223240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19099268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.19099268
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/36.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.699997976
Short name T646
Test name
Test status
Simulation time 140619189 ps
CPU time 26.59 seconds
Started Aug 27 03:39:23 AM UTC 24
Finished Aug 27 03:39:52 AM UTC 24
Peak memory 218876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699997976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.699997976
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/36.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.1358339750
Short name T656
Test name
Test status
Simulation time 595187223 ps
CPU time 16.53 seconds
Started Aug 27 03:39:46 AM UTC 24
Finished Aug 27 03:40:04 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358339750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1358339750
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/37.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.128347598
Short name T899
Test name
Test status
Simulation time 465376258052 ps
CPU time 1027.33 seconds
Started Aug 27 03:39:46 AM UTC 24
Finished Aug 27 03:57:05 AM UTC 24
Peak memory 222548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128347598 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.128347598
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/37.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.3084320812
Short name T663
Test name
Test status
Simulation time 551823008 ps
CPU time 18.94 seconds
Started Aug 27 03:39:56 AM UTC 24
Finished Aug 27 03:40:16 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084320812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.3084320812
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/37.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.278753042
Short name T664
Test name
Test status
Simulation time 2343616667 ps
CPU time 23.56 seconds
Started Aug 27 03:39:52 AM UTC 24
Finished Aug 27 03:40:17 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278753042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.278753042
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/37.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random.1176313309
Short name T644
Test name
Test status
Simulation time 143321878 ps
CPU time 4.72 seconds
Started Aug 27 03:39:40 AM UTC 24
Finished Aug 27 03:39:45 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176313309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1176313309
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/37.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.3675565269
Short name T812
Test name
Test status
Simulation time 45798318196 ps
CPU time 277.73 seconds
Started Aug 27 03:39:42 AM UTC 24
Finished Aug 27 03:44:23 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675565269 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3675565269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/37.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2767916883
Short name T699
Test name
Test status
Simulation time 8613605438 ps
CPU time 91.76 seconds
Started Aug 27 03:39:46 AM UTC 24
Finished Aug 27 03:41:20 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767916883 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2767916883
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/37.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.3559600342
Short name T653
Test name
Test status
Simulation time 117317598 ps
CPU time 18.92 seconds
Started Aug 27 03:39:42 AM UTC 24
Finished Aug 27 03:40:02 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559600342 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3559600342
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/37.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.3371634163
Short name T659
Test name
Test status
Simulation time 1437908062 ps
CPU time 20.62 seconds
Started Aug 27 03:39:47 AM UTC 24
Finished Aug 27 03:40:09 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371634163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3371634163
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/37.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.2759242805
Short name T638
Test name
Test status
Simulation time 55046204 ps
CPU time 3.27 seconds
Started Aug 27 03:39:34 AM UTC 24
Finished Aug 27 03:39:38 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759242805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2759242805
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/37.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.978272254
Short name T661
Test name
Test status
Simulation time 5084659633 ps
CPU time 30.98 seconds
Started Aug 27 03:39:37 AM UTC 24
Finished Aug 27 03:40:10 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978272254 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.978272254
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/37.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.417021693
Short name T81
Test name
Test status
Simulation time 2569823943 ps
CPU time 34.56 seconds
Started Aug 27 03:39:39 AM UTC 24
Finished Aug 27 03:40:16 AM UTC 24
Peak memory 217136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417021693 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.417021693
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/37.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3584454764
Short name T640
Test name
Test status
Simulation time 105112320 ps
CPU time 3.35 seconds
Started Aug 27 03:39:36 AM UTC 24
Finished Aug 27 03:39:40 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584454764 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3584454764
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/37.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.1076857632
Short name T145
Test name
Test status
Simulation time 8886901615 ps
CPU time 114.64 seconds
Started Aug 27 03:40:00 AM UTC 24
Finished Aug 27 03:41:56 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076857632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1076857632
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/37.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1049374396
Short name T670
Test name
Test status
Simulation time 279480518 ps
CPU time 27.3 seconds
Started Aug 27 03:40:01 AM UTC 24
Finished Aug 27 03:40:29 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049374396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1049374396
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/37.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2225434385
Short name T781
Test name
Test status
Simulation time 981700893 ps
CPU time 203.88 seconds
Started Aug 27 03:40:00 AM UTC 24
Finished Aug 27 03:43:27 AM UTC 24
Peak memory 222920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225434385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.2225434385
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/37.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.1304963310
Short name T651
Test name
Test status
Simulation time 194082926 ps
CPU time 5.38 seconds
Started Aug 27 03:39:54 AM UTC 24
Finished Aug 27 03:40:00 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304963310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1304963310
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/37.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.1936341025
Short name T680
Test name
Test status
Simulation time 1388583965 ps
CPU time 35.98 seconds
Started Aug 27 03:40:11 AM UTC 24
Finished Aug 27 03:40:48 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936341025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1936341025
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/38.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.638598749
Short name T885
Test name
Test status
Simulation time 179557066664 ps
CPU time 430.28 seconds
Started Aug 27 03:40:11 AM UTC 24
Finished Aug 27 03:47:26 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638598749 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.638598749
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/38.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.2790818230
Short name T667
Test name
Test status
Simulation time 29970192 ps
CPU time 5.87 seconds
Started Aug 27 03:40:18 AM UTC 24
Finished Aug 27 03:40:25 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790818230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.2790818230
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/38.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.2124150400
Short name T678
Test name
Test status
Simulation time 689073940 ps
CPU time 23.45 seconds
Started Aug 27 03:40:17 AM UTC 24
Finished Aug 27 03:40:42 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124150400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2124150400
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/38.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random.1627733965
Short name T671
Test name
Test status
Simulation time 1714813773 ps
CPU time 22.04 seconds
Started Aug 27 03:40:08 AM UTC 24
Finished Aug 27 03:40:32 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627733965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.1627733965
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/38.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.381573891
Short name T761
Test name
Test status
Simulation time 25377194195 ps
CPU time 157.4 seconds
Started Aug 27 03:40:09 AM UTC 24
Finished Aug 27 03:42:50 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381573891 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.381573891
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/38.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.3742491093
Short name T669
Test name
Test status
Simulation time 2700187884 ps
CPU time 14.53 seconds
Started Aug 27 03:40:11 AM UTC 24
Finished Aug 27 03:40:26 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742491093 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3742491093
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/38.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.4104996762
Short name T666
Test name
Test status
Simulation time 210332547 ps
CPU time 9.3 seconds
Started Aug 27 03:40:08 AM UTC 24
Finished Aug 27 03:40:19 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104996762 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.4104996762
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/38.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.393428477
Short name T673
Test name
Test status
Simulation time 775486006 ps
CPU time 15.49 seconds
Started Aug 27 03:40:17 AM UTC 24
Finished Aug 27 03:40:34 AM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393428477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.393428477
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/38.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.2491807785
Short name T660
Test name
Test status
Simulation time 251145821 ps
CPU time 5.47 seconds
Started Aug 27 03:40:03 AM UTC 24
Finished Aug 27 03:40:09 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491807785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2491807785
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/38.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.4072012232
Short name T677
Test name
Test status
Simulation time 8374160690 ps
CPU time 32.81 seconds
Started Aug 27 03:40:04 AM UTC 24
Finished Aug 27 03:40:38 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072012232 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.4072012232
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/38.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.394746354
Short name T675
Test name
Test status
Simulation time 5507271220 ps
CPU time 27.33 seconds
Started Aug 27 03:40:05 AM UTC 24
Finished Aug 27 03:40:34 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394746354 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.394746354
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/38.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.4057173965
Short name T658
Test name
Test status
Simulation time 27022119 ps
CPU time 2.83 seconds
Started Aug 27 03:40:04 AM UTC 24
Finished Aug 27 03:40:08 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057173965 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.4057173965
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/38.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.3702179305
Short name T679
Test name
Test status
Simulation time 1457943080 ps
CPU time 26.08 seconds
Started Aug 27 03:40:19 AM UTC 24
Finished Aug 27 03:40:47 AM UTC 24
Peak memory 218876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702179305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3702179305
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/38.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1297181653
Short name T688
Test name
Test status
Simulation time 474540319 ps
CPU time 37.88 seconds
Started Aug 27 03:40:26 AM UTC 24
Finished Aug 27 03:41:05 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297181653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1297181653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/38.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1288327770
Short name T856
Test name
Test status
Simulation time 1324114614 ps
CPU time 321.3 seconds
Started Aug 27 03:40:20 AM UTC 24
Finished Aug 27 03:45:46 AM UTC 24
Peak memory 222992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288327770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.1288327770
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/38.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1518714755
Short name T757
Test name
Test status
Simulation time 841909373 ps
CPU time 136.73 seconds
Started Aug 27 03:40:27 AM UTC 24
Finished Aug 27 03:42:46 AM UTC 24
Peak memory 220872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518714755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.1518714755
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/38.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.3212416858
Short name T668
Test name
Test status
Simulation time 28701569 ps
CPU time 6.06 seconds
Started Aug 27 03:40:18 AM UTC 24
Finished Aug 27 03:40:25 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212416858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3212416858
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/38.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.223714838
Short name T684
Test name
Test status
Simulation time 607994937 ps
CPU time 20.8 seconds
Started Aug 27 03:40:39 AM UTC 24
Finished Aug 27 03:41:01 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223714838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.223714838
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/39.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.2731272636
Short name T716
Test name
Test status
Simulation time 17770802940 ps
CPU time 67.56 seconds
Started Aug 27 03:40:43 AM UTC 24
Finished Aug 27 03:41:52 AM UTC 24
Peak memory 217160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731272636 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.2731272636
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/39.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.3800754814
Short name T689
Test name
Test status
Simulation time 135197495 ps
CPU time 12.8 seconds
Started Aug 27 03:40:53 AM UTC 24
Finished Aug 27 03:41:07 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800754814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.3800754814
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/39.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.2152683207
Short name T681
Test name
Test status
Simulation time 24537914 ps
CPU time 2.83 seconds
Started Aug 27 03:40:49 AM UTC 24
Finished Aug 27 03:40:53 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152683207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2152683207
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/39.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random.3821224231
Short name T682
Test name
Test status
Simulation time 761008314 ps
CPU time 18.96 seconds
Started Aug 27 03:40:34 AM UTC 24
Finished Aug 27 03:40:54 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821224231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.3821224231
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/39.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.301186917
Short name T844
Test name
Test status
Simulation time 68107488696 ps
CPU time 272.98 seconds
Started Aug 27 03:40:34 AM UTC 24
Finished Aug 27 03:45:11 AM UTC 24
Peak memory 216904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301186917 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.301186917
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/39.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.3649161406
Short name T884
Test name
Test status
Simulation time 132081654691 ps
CPU time 397.49 seconds
Started Aug 27 03:40:36 AM UTC 24
Finished Aug 27 03:47:19 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649161406 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3649161406
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/39.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.2529120265
Short name T685
Test name
Test status
Simulation time 294198691 ps
CPU time 25.3 seconds
Started Aug 27 03:40:34 AM UTC 24
Finished Aug 27 03:41:01 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529120265 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.2529120265
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/39.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.3831842236
Short name T687
Test name
Test status
Simulation time 208888128 ps
CPU time 15.42 seconds
Started Aug 27 03:40:48 AM UTC 24
Finished Aug 27 03:41:04 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831842236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3831842236
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/39.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.4150298935
Short name T672
Test name
Test status
Simulation time 125898945 ps
CPU time 3.11 seconds
Started Aug 27 03:40:28 AM UTC 24
Finished Aug 27 03:40:32 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150298935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.4150298935
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/39.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3518429104
Short name T703
Test name
Test status
Simulation time 22582000374 ps
CPU time 53 seconds
Started Aug 27 03:40:32 AM UTC 24
Finished Aug 27 03:41:27 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518429104 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3518429104
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/39.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3163609390
Short name T698
Test name
Test status
Simulation time 8621648179 ps
CPU time 44.2 seconds
Started Aug 27 03:40:33 AM UTC 24
Finished Aug 27 03:41:19 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163609390 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3163609390
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/39.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2058541675
Short name T674
Test name
Test status
Simulation time 49304358 ps
CPU time 2.57 seconds
Started Aug 27 03:40:30 AM UTC 24
Finished Aug 27 03:40:34 AM UTC 24
Peak memory 217004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058541675 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2058541675
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/39.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.2374266898
Short name T751
Test name
Test status
Simulation time 4355253849 ps
CPU time 106.35 seconds
Started Aug 27 03:40:55 AM UTC 24
Finished Aug 27 03:42:44 AM UTC 24
Peak memory 218944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374266898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.2374266898
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/39.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.4144655350
Short name T710
Test name
Test status
Simulation time 446797059 ps
CPU time 34.01 seconds
Started Aug 27 03:41:01 AM UTC 24
Finished Aug 27 03:41:37 AM UTC 24
Peak memory 217160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144655350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.4144655350
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/39.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.3282629539
Short name T855
Test name
Test status
Simulation time 2258097454 ps
CPU time 286.82 seconds
Started Aug 27 03:40:55 AM UTC 24
Finished Aug 27 03:45:46 AM UTC 24
Peak memory 223308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282629539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.3282629539
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/39.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3371885704
Short name T712
Test name
Test status
Simulation time 191013680 ps
CPU time 41.49 seconds
Started Aug 27 03:41:01 AM UTC 24
Finished Aug 27 03:41:44 AM UTC 24
Peak memory 218820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371885704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.3371885704
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/39.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.1794238799
Short name T690
Test name
Test status
Simulation time 109422648 ps
CPU time 14.61 seconds
Started Aug 27 03:40:53 AM UTC 24
Finished Aug 27 03:41:09 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794238799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1794238799
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/39.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.2253996790
Short name T306
Test name
Test status
Simulation time 44838233273 ps
CPU time 467.95 seconds
Started Aug 27 03:25:01 AM UTC 24
Finished Aug 27 03:32:55 AM UTC 24
Peak memory 220500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253996790 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.2253996790
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/4.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3066064578
Short name T214
Test name
Test status
Simulation time 542520811 ps
CPU time 23.35 seconds
Started Aug 27 03:25:03 AM UTC 24
Finished Aug 27 03:25:28 AM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066064578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3066064578
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/4.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.986719071
Short name T184
Test name
Test status
Simulation time 200509928 ps
CPU time 9.2 seconds
Started Aug 27 03:25:02 AM UTC 24
Finished Aug 27 03:25:12 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986719071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.986719071
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/4.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random.1838623305
Short name T317
Test name
Test status
Simulation time 293782298 ps
CPU time 23.31 seconds
Started Aug 27 03:24:57 AM UTC 24
Finished Aug 27 03:25:21 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838623305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.1838623305
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/4.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.1085720611
Short name T164
Test name
Test status
Simulation time 22150428464 ps
CPU time 80 seconds
Started Aug 27 03:24:58 AM UTC 24
Finished Aug 27 03:26:19 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085720611 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1085720611
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/4.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.4112659696
Short name T332
Test name
Test status
Simulation time 39257665126 ps
CPU time 182.87 seconds
Started Aug 27 03:24:59 AM UTC 24
Finished Aug 27 03:28:04 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112659696 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.4112659696
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/4.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.1501811459
Short name T315
Test name
Test status
Simulation time 458467069 ps
CPU time 20.4 seconds
Started Aug 27 03:24:58 AM UTC 24
Finished Aug 27 03:25:19 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501811459 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1501811459
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/4.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.2928150758
Short name T182
Test name
Test status
Simulation time 648017331 ps
CPU time 11.22 seconds
Started Aug 27 03:25:01 AM UTC 24
Finished Aug 27 03:25:13 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928150758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.2928150758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/4.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.537032949
Short name T63
Test name
Test status
Simulation time 28026393 ps
CPU time 3.46 seconds
Started Aug 27 03:24:52 AM UTC 24
Finished Aug 27 03:25:00 AM UTC 24
Peak memory 217072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537032949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.537032949
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/4.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.4157603176
Short name T122
Test name
Test status
Simulation time 6396287647 ps
CPU time 60.29 seconds
Started Aug 27 03:24:53 AM UTC 24
Finished Aug 27 03:25:56 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157603176 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.4157603176
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/4.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.1320784367
Short name T65
Test name
Test status
Simulation time 3572359431 ps
CPU time 27.84 seconds
Started Aug 27 03:24:54 AM UTC 24
Finished Aug 27 03:25:24 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320784367 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1320784367
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/4.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2184046294
Short name T157
Test name
Test status
Simulation time 45139155 ps
CPU time 2.58 seconds
Started Aug 27 03:24:53 AM UTC 24
Finished Aug 27 03:24:58 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184046294 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2184046294
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/4.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1846317289
Short name T188
Test name
Test status
Simulation time 647237419 ps
CPU time 231.75 seconds
Started Aug 27 03:25:05 AM UTC 24
Finished Aug 27 03:29:01 AM UTC 24
Peak memory 221256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846317289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.1846317289
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/4.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.3033211194
Short name T87
Test name
Test status
Simulation time 1452278919 ps
CPU time 36.13 seconds
Started Aug 27 03:25:03 AM UTC 24
Finished Aug 27 03:25:41 AM UTC 24
Peak memory 218812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033211194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3033211194
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/4.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.4009118429
Short name T728
Test name
Test status
Simulation time 5015535106 ps
CPU time 46.76 seconds
Started Aug 27 03:41:16 AM UTC 24
Finished Aug 27 03:42:04 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009118429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.4009118429
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/40.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3183821952
Short name T897
Test name
Test status
Simulation time 64461241158 ps
CPU time 635.42 seconds
Started Aug 27 03:41:17 AM UTC 24
Finished Aug 27 03:51:59 AM UTC 24
Peak memory 220496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183821952 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.3183821952
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/40.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.3696880833
Short name T709
Test name
Test status
Simulation time 100665939 ps
CPU time 11.2 seconds
Started Aug 27 03:41:24 AM UTC 24
Finished Aug 27 03:41:37 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696880833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.3696880833
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/40.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.3355812366
Short name T706
Test name
Test status
Simulation time 137742252 ps
CPU time 9.99 seconds
Started Aug 27 03:41:21 AM UTC 24
Finished Aug 27 03:41:32 AM UTC 24
Peak memory 216756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355812366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3355812366
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/40.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random.1947636311
Short name T701
Test name
Test status
Simulation time 245033541 ps
CPU time 13.83 seconds
Started Aug 27 03:41:10 AM UTC 24
Finished Aug 27 03:41:25 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947636311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.1947636311
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/40.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.215345493
Short name T288
Test name
Test status
Simulation time 46202294035 ps
CPU time 141.32 seconds
Started Aug 27 03:41:11 AM UTC 24
Finished Aug 27 03:43:35 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215345493 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.215345493
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/40.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2396890426
Short name T181
Test name
Test status
Simulation time 79399126441 ps
CPU time 121.49 seconds
Started Aug 27 03:41:14 AM UTC 24
Finished Aug 27 03:43:17 AM UTC 24
Peak memory 217160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396890426 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2396890426
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/40.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.2652392798
Short name T705
Test name
Test status
Simulation time 129994807 ps
CPU time 18.92 seconds
Started Aug 27 03:41:11 AM UTC 24
Finished Aug 27 03:41:32 AM UTC 24
Peak memory 217080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652392798 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.2652392798
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/40.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.302632742
Short name T723
Test name
Test status
Simulation time 1635156613 ps
CPU time 41.95 seconds
Started Aug 27 03:41:18 AM UTC 24
Finished Aug 27 03:42:02 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302632742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.302632742
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/40.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.3034332385
Short name T691
Test name
Test status
Simulation time 31509285 ps
CPU time 3.32 seconds
Started Aug 27 03:41:06 AM UTC 24
Finished Aug 27 03:41:10 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034332385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3034332385
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/40.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.292663725
Short name T717
Test name
Test status
Simulation time 6540037689 ps
CPU time 46.13 seconds
Started Aug 27 03:41:06 AM UTC 24
Finished Aug 27 03:41:54 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292663725 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.292663725
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/40.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1880309613
Short name T725
Test name
Test status
Simulation time 5276274831 ps
CPU time 53.11 seconds
Started Aug 27 03:41:08 AM UTC 24
Finished Aug 27 03:42:03 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880309613 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1880309613
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/40.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.3553063463
Short name T692
Test name
Test status
Simulation time 26618349 ps
CPU time 3.26 seconds
Started Aug 27 03:41:06 AM UTC 24
Finished Aug 27 03:41:10 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553063463 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.3553063463
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/40.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.2942348076
Short name T843
Test name
Test status
Simulation time 9021107691 ps
CPU time 222.59 seconds
Started Aug 27 03:41:24 AM UTC 24
Finished Aug 27 03:45:10 AM UTC 24
Peak memory 220568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942348076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2942348076
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/40.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.4063950731
Short name T786
Test name
Test status
Simulation time 1806841495 ps
CPU time 129.07 seconds
Started Aug 27 03:41:24 AM UTC 24
Finished Aug 27 03:43:36 AM UTC 24
Peak memory 220932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063950731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.4063950731
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/40.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.175873570
Short name T711
Test name
Test status
Simulation time 24516009 ps
CPU time 15.86 seconds
Started Aug 27 03:41:24 AM UTC 24
Finished Aug 27 03:41:41 AM UTC 24
Peak memory 218420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175873570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.175873570
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/40.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.193662147
Short name T57
Test name
Test status
Simulation time 257702017 ps
CPU time 154.22 seconds
Started Aug 27 03:41:29 AM UTC 24
Finished Aug 27 03:44:06 AM UTC 24
Peak memory 222980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193662147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.193662147
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/40.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.3976567293
Short name T713
Test name
Test status
Simulation time 506051860 ps
CPU time 22.6 seconds
Started Aug 27 03:41:21 AM UTC 24
Finished Aug 27 03:41:45 AM UTC 24
Peak memory 218816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976567293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3976567293
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/40.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.1304326727
Short name T737
Test name
Test status
Simulation time 1088225068 ps
CPU time 42.22 seconds
Started Aug 27 03:41:38 AM UTC 24
Finished Aug 27 03:42:22 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304326727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1304326727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/41.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.2048858414
Short name T149
Test name
Test status
Simulation time 97726324518 ps
CPU time 682.59 seconds
Started Aug 27 03:41:43 AM UTC 24
Finished Aug 27 03:53:14 AM UTC 24
Peak memory 222544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048858414 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.2048858414
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/41.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.2372070128
Short name T731
Test name
Test status
Simulation time 889238047 ps
CPU time 22.83 seconds
Started Aug 27 03:41:47 AM UTC 24
Finished Aug 27 03:42:11 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372070128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.2372070128
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/41.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.1243807596
Short name T714
Test name
Test status
Simulation time 46444123 ps
CPU time 3.2 seconds
Started Aug 27 03:41:43 AM UTC 24
Finished Aug 27 03:41:47 AM UTC 24
Peak memory 216756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243807596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1243807596
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/41.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random.4146555300
Short name T726
Test name
Test status
Simulation time 385301174 ps
CPU time 27.19 seconds
Started Aug 27 03:41:35 AM UTC 24
Finished Aug 27 03:42:03 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146555300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.4146555300
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/41.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.982574951
Short name T867
Test name
Test status
Simulation time 95775796316 ps
CPU time 277.7 seconds
Started Aug 27 03:41:35 AM UTC 24
Finished Aug 27 03:46:16 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982574951 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.982574951
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/41.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3823619198
Short name T720
Test name
Test status
Simulation time 1702615145 ps
CPU time 20.42 seconds
Started Aug 27 03:41:38 AM UTC 24
Finished Aug 27 03:42:00 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823619198 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3823619198
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/41.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.1096235383
Short name T715
Test name
Test status
Simulation time 208290010 ps
CPU time 14.44 seconds
Started Aug 27 03:41:35 AM UTC 24
Finished Aug 27 03:41:50 AM UTC 24
Peak memory 217080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096235383 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1096235383
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/41.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.1307185273
Short name T718
Test name
Test status
Simulation time 148594552 ps
CPU time 10.72 seconds
Started Aug 27 03:41:43 AM UTC 24
Finished Aug 27 03:41:55 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307185273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1307185273
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/41.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.3124287806
Short name T708
Test name
Test status
Simulation time 102111038 ps
CPU time 4.26 seconds
Started Aug 27 03:41:29 AM UTC 24
Finished Aug 27 03:41:34 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124287806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3124287806
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/41.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2141920084
Short name T733
Test name
Test status
Simulation time 6954121198 ps
CPU time 40.82 seconds
Started Aug 27 03:41:35 AM UTC 24
Finished Aug 27 03:42:17 AM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141920084 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2141920084
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/41.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2201466623
Short name T745
Test name
Test status
Simulation time 4785518787 ps
CPU time 54.43 seconds
Started Aug 27 03:41:35 AM UTC 24
Finished Aug 27 03:42:31 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201466623 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2201466623
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/41.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2505740228
Short name T707
Test name
Test status
Simulation time 92410153 ps
CPU time 2.84 seconds
Started Aug 27 03:41:29 AM UTC 24
Finished Aug 27 03:41:33 AM UTC 24
Peak memory 217132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505740228 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2505740228
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/41.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.3767663093
Short name T229
Test name
Test status
Simulation time 619257679 ps
CPU time 84.34 seconds
Started Aug 27 03:41:47 AM UTC 24
Finished Aug 27 03:43:13 AM UTC 24
Peak memory 222980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767663093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3767663093
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/41.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2001736926
Short name T719
Test name
Test status
Simulation time 32290723 ps
CPU time 1.97 seconds
Started Aug 27 03:41:53 AM UTC 24
Finished Aug 27 03:41:56 AM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001736926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2001736926
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/41.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3692689729
Short name T826
Test name
Test status
Simulation time 1272790318 ps
CPU time 168.93 seconds
Started Aug 27 03:41:49 AM UTC 24
Finished Aug 27 03:44:41 AM UTC 24
Peak memory 220872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692689729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.3692689729
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/41.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.2148606970
Short name T732
Test name
Test status
Simulation time 129959983 ps
CPU time 28.69 seconds
Started Aug 27 03:41:43 AM UTC 24
Finished Aug 27 03:42:13 AM UTC 24
Peak memory 219132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148606970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2148606970
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/41.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.1053256483
Short name T239
Test name
Test status
Simulation time 305533188 ps
CPU time 46.33 seconds
Started Aug 27 03:42:11 AM UTC 24
Finished Aug 27 03:42:59 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053256483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.1053256483
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/42.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.4030195453
Short name T900
Test name
Test status
Simulation time 379126008063 ps
CPU time 1266.43 seconds
Started Aug 27 03:42:11 AM UTC 24
Finished Aug 27 04:03:32 AM UTC 24
Peak memory 222616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030195453 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.4030195453
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/42.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.4279219275
Short name T747
Test name
Test status
Simulation time 662866165 ps
CPU time 22.29 seconds
Started Aug 27 03:42:11 AM UTC 24
Finished Aug 27 03:42:35 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279219275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.4279219275
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/42.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.3713460483
Short name T739
Test name
Test status
Simulation time 520593635 ps
CPU time 13.72 seconds
Started Aug 27 03:42:11 AM UTC 24
Finished Aug 27 03:42:26 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713460483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3713460483
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/42.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random.2838645039
Short name T730
Test name
Test status
Simulation time 86726331 ps
CPU time 6.4 seconds
Started Aug 27 03:41:59 AM UTC 24
Finished Aug 27 03:42:07 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838645039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2838645039
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/42.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.1320365934
Short name T785
Test name
Test status
Simulation time 17091031620 ps
CPU time 90.49 seconds
Started Aug 27 03:42:02 AM UTC 24
Finished Aug 27 03:43:34 AM UTC 24
Peak memory 216892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320365934 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1320365934
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/42.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3688311399
Short name T782
Test name
Test status
Simulation time 22284820143 ps
CPU time 74.41 seconds
Started Aug 27 03:42:11 AM UTC 24
Finished Aug 27 03:43:27 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688311399 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.3688311399
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/42.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.2007853359
Short name T748
Test name
Test status
Simulation time 232603798 ps
CPU time 32.58 seconds
Started Aug 27 03:42:02 AM UTC 24
Finished Aug 27 03:42:36 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007853359 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.2007853359
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/42.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.2591939983
Short name T753
Test name
Test status
Simulation time 4675560490 ps
CPU time 31.54 seconds
Started Aug 27 03:42:11 AM UTC 24
Finished Aug 27 03:42:44 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591939983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2591939983
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/42.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.270423542
Short name T724
Test name
Test status
Simulation time 26396266 ps
CPU time 1.93 seconds
Started Aug 27 03:41:59 AM UTC 24
Finished Aug 27 03:42:02 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270423542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.270423542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/42.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.619978327
Short name T746
Test name
Test status
Simulation time 5157588659 ps
CPU time 32.78 seconds
Started Aug 27 03:41:59 AM UTC 24
Finished Aug 27 03:42:33 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619978327 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.619978327
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/42.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3625359312
Short name T744
Test name
Test status
Simulation time 3451158193 ps
CPU time 30.37 seconds
Started Aug 27 03:41:59 AM UTC 24
Finished Aug 27 03:42:31 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625359312 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3625359312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/42.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.4118996095
Short name T727
Test name
Test status
Simulation time 33130045 ps
CPU time 3.34 seconds
Started Aug 27 03:41:59 AM UTC 24
Finished Aug 27 03:42:03 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118996095 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.4118996095
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/42.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.1278264911
Short name T858
Test name
Test status
Simulation time 6623962122 ps
CPU time 221.71 seconds
Started Aug 27 03:42:11 AM UTC 24
Finished Aug 27 03:45:57 AM UTC 24
Peak memory 223044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278264911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1278264911
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/42.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.1039001261
Short name T793
Test name
Test status
Simulation time 9252568009 ps
CPU time 89.78 seconds
Started Aug 27 03:42:15 AM UTC 24
Finished Aug 27 03:43:47 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039001261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1039001261
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/42.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2579028794
Short name T829
Test name
Test status
Simulation time 1829739581 ps
CPU time 151.39 seconds
Started Aug 27 03:42:12 AM UTC 24
Finished Aug 27 03:44:45 AM UTC 24
Peak memory 220876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579028794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.2579028794
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/42.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3591575665
Short name T871
Test name
Test status
Simulation time 4048219355 ps
CPU time 255.18 seconds
Started Aug 27 03:42:15 AM UTC 24
Finished Aug 27 03:46:34 AM UTC 24
Peak memory 233656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591575665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.3591575665
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/42.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.1389122782
Short name T740
Test name
Test status
Simulation time 664577147 ps
CPU time 13.9 seconds
Started Aug 27 03:42:11 AM UTC 24
Finished Aug 27 03:42:26 AM UTC 24
Peak memory 216620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389122782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.1389122782
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/42.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.2996186688
Short name T758
Test name
Test status
Simulation time 655166223 ps
CPU time 18.91 seconds
Started Aug 27 03:42:28 AM UTC 24
Finished Aug 27 03:42:48 AM UTC 24
Peak memory 216968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996186688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.2996186688
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/43.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3644498795
Short name T883
Test name
Test status
Simulation time 90177294005 ps
CPU time 284.41 seconds
Started Aug 27 03:42:30 AM UTC 24
Finished Aug 27 03:47:19 AM UTC 24
Peak memory 218952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644498795 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.3644498795
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/43.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.974090565
Short name T749
Test name
Test status
Simulation time 63133036 ps
CPU time 2.88 seconds
Started Aug 27 03:42:33 AM UTC 24
Finished Aug 27 03:42:38 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974090565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.974090565
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/43.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.59460564
Short name T760
Test name
Test status
Simulation time 914058321 ps
CPU time 13.93 seconds
Started Aug 27 03:42:33 AM UTC 24
Finished Aug 27 03:42:49 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59460564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.59460564
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/43.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random.3015425942
Short name T754
Test name
Test status
Simulation time 374285763 ps
CPU time 17.9 seconds
Started Aug 27 03:42:26 AM UTC 24
Finished Aug 27 03:42:45 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015425942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.3015425942
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/43.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.3399576858
Short name T886
Test name
Test status
Simulation time 91182673199 ps
CPU time 320.53 seconds
Started Aug 27 03:42:26 AM UTC 24
Finished Aug 27 03:47:51 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399576858 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3399576858
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/43.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.2097360273
Short name T817
Test name
Test status
Simulation time 20765285494 ps
CPU time 116.7 seconds
Started Aug 27 03:42:28 AM UTC 24
Finished Aug 27 03:44:27 AM UTC 24
Peak memory 217028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097360273 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2097360273
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/43.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.720477723
Short name T750
Test name
Test status
Simulation time 89391681 ps
CPU time 11.69 seconds
Started Aug 27 03:42:26 AM UTC 24
Finished Aug 27 03:42:38 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720477723 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.720477723
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/43.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.2902903727
Short name T752
Test name
Test status
Simulation time 220215291 ps
CPU time 12.13 seconds
Started Aug 27 03:42:30 AM UTC 24
Finished Aug 27 03:42:44 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902903727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2902903727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/43.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.2136253539
Short name T736
Test name
Test status
Simulation time 52968400 ps
CPU time 3.54 seconds
Started Aug 27 03:42:15 AM UTC 24
Finished Aug 27 03:42:20 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136253539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2136253539
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/43.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.609915275
Short name T779
Test name
Test status
Simulation time 40204544306 ps
CPU time 63.21 seconds
Started Aug 27 03:42:22 AM UTC 24
Finished Aug 27 03:43:27 AM UTC 24
Peak memory 217140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609915275 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.609915275
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/43.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.500482145
Short name T768
Test name
Test status
Simulation time 4406640380 ps
CPU time 40.76 seconds
Started Aug 27 03:42:22 AM UTC 24
Finished Aug 27 03:43:04 AM UTC 24
Peak memory 217136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500482145 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.500482145
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/43.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3212594148
Short name T738
Test name
Test status
Simulation time 32746796 ps
CPU time 3.27 seconds
Started Aug 27 03:42:18 AM UTC 24
Finished Aug 27 03:42:22 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212594148 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3212594148
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/43.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.3557236412
Short name T797
Test name
Test status
Simulation time 3106280133 ps
CPU time 74.54 seconds
Started Aug 27 03:42:35 AM UTC 24
Finished Aug 27 03:43:52 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557236412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3557236412
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/43.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3855369869
Short name T777
Test name
Test status
Simulation time 2650520406 ps
CPU time 40.85 seconds
Started Aug 27 03:42:39 AM UTC 24
Finished Aug 27 03:43:22 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855369869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.3855369869
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/43.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1782048539
Short name T153
Test name
Test status
Simulation time 15269217324 ps
CPU time 333.56 seconds
Started Aug 27 03:42:39 AM UTC 24
Finished Aug 27 03:48:18 AM UTC 24
Peak memory 223676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782048539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.1782048539
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/43.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.4169058348
Short name T792
Test name
Test status
Simulation time 321226622 ps
CPU time 62.94 seconds
Started Aug 27 03:42:39 AM UTC 24
Finished Aug 27 03:43:44 AM UTC 24
Peak memory 220868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169058348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.4169058348
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/43.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.4093021420
Short name T763
Test name
Test status
Simulation time 897418577 ps
CPU time 17.74 seconds
Started Aug 27 03:42:33 AM UTC 24
Finished Aug 27 03:42:52 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093021420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.4093021420
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/43.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.1807863138
Short name T778
Test name
Test status
Simulation time 1477726133 ps
CPU time 28.5 seconds
Started Aug 27 03:42:52 AM UTC 24
Finished Aug 27 03:43:22 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807863138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.1807863138
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/44.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1523923580
Short name T801
Test name
Test status
Simulation time 6783486446 ps
CPU time 72.41 seconds
Started Aug 27 03:42:52 AM UTC 24
Finished Aug 27 03:44:06 AM UTC 24
Peak memory 217224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523923580 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.1523923580
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/44.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2546929863
Short name T770
Test name
Test status
Simulation time 53175785 ps
CPU time 9 seconds
Started Aug 27 03:42:55 AM UTC 24
Finished Aug 27 03:43:05 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546929863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2546929863
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/44.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.3806100301
Short name T771
Test name
Test status
Simulation time 598054437 ps
CPU time 14.45 seconds
Started Aug 27 03:42:52 AM UTC 24
Finished Aug 27 03:43:08 AM UTC 24
Peak memory 217144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806100301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3806100301
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/44.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.4063752646
Short name T762
Test name
Test status
Simulation time 35685213 ps
CPU time 3.04 seconds
Started Aug 27 03:42:47 AM UTC 24
Finished Aug 27 03:42:52 AM UTC 24
Peak memory 216732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063752646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.4063752646
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/44.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.4055379980
Short name T862
Test name
Test status
Simulation time 96235182332 ps
CPU time 194.31 seconds
Started Aug 27 03:42:47 AM UTC 24
Finished Aug 27 03:46:05 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055379980 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.4055379980
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/44.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.653581751
Short name T874
Test name
Test status
Simulation time 74417463155 ps
CPU time 237.9 seconds
Started Aug 27 03:42:52 AM UTC 24
Finished Aug 27 03:46:53 AM UTC 24
Peak memory 219268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653581751 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.653581751
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/44.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.3759881985
Short name T769
Test name
Test status
Simulation time 167702565 ps
CPU time 16.27 seconds
Started Aug 27 03:42:47 AM UTC 24
Finished Aug 27 03:43:05 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759881985 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.3759881985
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/44.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.1266821203
Short name T766
Test name
Test status
Simulation time 227357063 ps
CPU time 8.01 seconds
Started Aug 27 03:42:52 AM UTC 24
Finished Aug 27 03:43:01 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266821203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1266821203
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/44.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.677573701
Short name T759
Test name
Test status
Simulation time 161165959 ps
CPU time 5.23 seconds
Started Aug 27 03:42:42 AM UTC 24
Finished Aug 27 03:42:48 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677573701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.677573701
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/44.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.2391638983
Short name T784
Test name
Test status
Simulation time 13599429464 ps
CPU time 40.39 seconds
Started Aug 27 03:42:47 AM UTC 24
Finished Aug 27 03:43:29 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391638983 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2391638983
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/44.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.605307913
Short name T783
Test name
Test status
Simulation time 6960929335 ps
CPU time 38.54 seconds
Started Aug 27 03:42:47 AM UTC 24
Finished Aug 27 03:43:27 AM UTC 24
Peak memory 216892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605307913 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.605307913
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/44.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3336985609
Short name T756
Test name
Test status
Simulation time 71787519 ps
CPU time 2.28 seconds
Started Aug 27 03:42:42 AM UTC 24
Finished Aug 27 03:42:45 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336985609 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.3336985609
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/44.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.3854561074
Short name T148
Test name
Test status
Simulation time 8117183777 ps
CPU time 96.54 seconds
Started Aug 27 03:42:55 AM UTC 24
Finished Aug 27 03:44:34 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854561074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3854561074
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/44.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1614051065
Short name T870
Test name
Test status
Simulation time 5763889163 ps
CPU time 202.37 seconds
Started Aug 27 03:43:01 AM UTC 24
Finished Aug 27 03:46:27 AM UTC 24
Peak memory 219204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614051065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1614051065
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/44.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.4288263524
Short name T873
Test name
Test status
Simulation time 7850322219 ps
CPU time 212.13 seconds
Started Aug 27 03:43:01 AM UTC 24
Finished Aug 27 03:46:37 AM UTC 24
Peak memory 223040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288263524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.4288263524
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/44.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.381454287
Short name T863
Test name
Test status
Simulation time 5670920523 ps
CPU time 180.32 seconds
Started Aug 27 03:43:05 AM UTC 24
Finished Aug 27 03:46:08 AM UTC 24
Peak memory 221072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381454287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.381454287
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/44.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.868239861
Short name T776
Test name
Test status
Simulation time 933010627 ps
CPU time 22.3 seconds
Started Aug 27 03:42:55 AM UTC 24
Finished Aug 27 03:43:19 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868239861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.868239861
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/44.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.2084666334
Short name T798
Test name
Test status
Simulation time 392138696 ps
CPU time 38.93 seconds
Started Aug 27 03:43:15 AM UTC 24
Finished Aug 27 03:43:55 AM UTC 24
Peak memory 218952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084666334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.2084666334
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/45.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2515435269
Short name T893
Test name
Test status
Simulation time 45763838580 ps
CPU time 450.7 seconds
Started Aug 27 03:43:15 AM UTC 24
Finished Aug 27 03:50:51 AM UTC 24
Peak memory 219208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515435269 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.2515435269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/45.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.438404261
Short name T796
Test name
Test status
Simulation time 1059378875 ps
CPU time 22.49 seconds
Started Aug 27 03:43:25 AM UTC 24
Finished Aug 27 03:43:49 AM UTC 24
Peak memory 216964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438404261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.438404261
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/45.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.2963187385
Short name T794
Test name
Test status
Simulation time 2368501279 ps
CPU time 25.22 seconds
Started Aug 27 03:43:22 AM UTC 24
Finished Aug 27 03:43:48 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963187385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2963187385
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/45.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.1502027282
Short name T287
Test name
Test status
Simulation time 2116571486 ps
CPU time 37.86 seconds
Started Aug 27 03:43:08 AM UTC 24
Finished Aug 27 03:43:48 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502027282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.1502027282
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/45.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.259425272
Short name T821
Test name
Test status
Simulation time 50931074847 ps
CPU time 79.06 seconds
Started Aug 27 03:43:11 AM UTC 24
Finished Aug 27 03:44:32 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259425272 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.259425272
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/45.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3392574568
Short name T875
Test name
Test status
Simulation time 67378816391 ps
CPU time 226.05 seconds
Started Aug 27 03:43:11 AM UTC 24
Finished Aug 27 03:47:00 AM UTC 24
Peak memory 217156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392574568 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3392574568
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/45.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.2838730644
Short name T775
Test name
Test status
Simulation time 38720698 ps
CPU time 6.03 seconds
Started Aug 27 03:43:11 AM UTC 24
Finished Aug 27 03:43:18 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838730644 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2838730644
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/45.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.1677362084
Short name T789
Test name
Test status
Simulation time 1428132889 ps
CPU time 17.82 seconds
Started Aug 27 03:43:22 AM UTC 24
Finished Aug 27 03:43:41 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677362084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1677362084
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/45.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.2405225797
Short name T772
Test name
Test status
Simulation time 63655094 ps
CPU time 3.11 seconds
Started Aug 27 03:43:05 AM UTC 24
Finished Aug 27 03:43:09 AM UTC 24
Peak memory 217000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405225797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2405225797
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/45.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1098562083
Short name T790
Test name
Test status
Simulation time 5630717549 ps
CPU time 32.19 seconds
Started Aug 27 03:43:08 AM UTC 24
Finished Aug 27 03:43:42 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098562083 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1098562083
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/45.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1031698468
Short name T804
Test name
Test status
Simulation time 13296431204 ps
CPU time 58.51 seconds
Started Aug 27 03:43:08 AM UTC 24
Finished Aug 27 03:44:08 AM UTC 24
Peak memory 217136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031698468 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1031698468
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/45.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3745041219
Short name T773
Test name
Test status
Simulation time 48893984 ps
CPU time 3.07 seconds
Started Aug 27 03:43:05 AM UTC 24
Finished Aug 27 03:43:09 AM UTC 24
Peak memory 217068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745041219 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.3745041219
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/45.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.434853036
Short name T828
Test name
Test status
Simulation time 1480423589 ps
CPU time 78.48 seconds
Started Aug 27 03:43:25 AM UTC 24
Finished Aug 27 03:44:45 AM UTC 24
Peak memory 219140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434853036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.434853036
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/45.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2766051187
Short name T831
Test name
Test status
Simulation time 3655747133 ps
CPU time 85.34 seconds
Started Aug 27 03:43:28 AM UTC 24
Finished Aug 27 03:44:56 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766051187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2766051187
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/45.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.198932743
Short name T813
Test name
Test status
Simulation time 1009533699 ps
CPU time 53.96 seconds
Started Aug 27 03:43:28 AM UTC 24
Finished Aug 27 03:44:24 AM UTC 24
Peak memory 220924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198932743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.198932743
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/45.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3237001849
Short name T838
Test name
Test status
Simulation time 255693598 ps
CPU time 89.53 seconds
Started Aug 27 03:43:33 AM UTC 24
Finished Aug 27 03:45:05 AM UTC 24
Peak memory 223308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237001849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.3237001849
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/45.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.1401287518
Short name T795
Test name
Test status
Simulation time 804508979 ps
CPU time 25.3 seconds
Started Aug 27 03:43:22 AM UTC 24
Finished Aug 27 03:43:48 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401287518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1401287518
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/45.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.1591357284
Short name T806
Test name
Test status
Simulation time 256181968 ps
CPU time 25.25 seconds
Started Aug 27 03:43:44 AM UTC 24
Finished Aug 27 03:44:11 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591357284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.1591357284
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/46.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1681479955
Short name T832
Test name
Test status
Simulation time 9708391299 ps
CPU time 66.31 seconds
Started Aug 27 03:43:48 AM UTC 24
Finished Aug 27 03:44:56 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681479955 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.1681479955
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/46.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2757932252
Short name T803
Test name
Test status
Simulation time 440033103 ps
CPU time 11.72 seconds
Started Aug 27 03:43:55 AM UTC 24
Finished Aug 27 03:44:08 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757932252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2757932252
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/46.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.3323085599
Short name T809
Test name
Test status
Simulation time 885881524 ps
CPU time 19.37 seconds
Started Aug 27 03:43:55 AM UTC 24
Finished Aug 27 03:44:16 AM UTC 24
Peak memory 216752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323085599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.3323085599
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/46.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.2593050633
Short name T802
Test name
Test status
Simulation time 194805358 ps
CPU time 25.97 seconds
Started Aug 27 03:43:41 AM UTC 24
Finished Aug 27 03:44:08 AM UTC 24
Peak memory 216500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593050633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2593050633
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/46.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.4055586106
Short name T156
Test name
Test status
Simulation time 28516208187 ps
CPU time 193.28 seconds
Started Aug 27 03:43:41 AM UTC 24
Finished Aug 27 03:46:57 AM UTC 24
Peak memory 217224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055586106 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.4055586106
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/46.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.593631257
Short name T879
Test name
Test status
Simulation time 26519981743 ps
CPU time 201.46 seconds
Started Aug 27 03:43:44 AM UTC 24
Finished Aug 27 03:47:09 AM UTC 24
Peak memory 216964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593631257 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.593631257
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/46.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.1121937375
Short name T807
Test name
Test status
Simulation time 263866838 ps
CPU time 31.32 seconds
Started Aug 27 03:43:41 AM UTC 24
Finished Aug 27 03:44:14 AM UTC 24
Peak memory 218876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121937375 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.1121937375
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/46.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.1555192514
Short name T800
Test name
Test status
Simulation time 746367638 ps
CPU time 14.35 seconds
Started Aug 27 03:43:48 AM UTC 24
Finished Aug 27 03:44:03 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555192514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1555192514
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/46.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.3676603778
Short name T788
Test name
Test status
Simulation time 170530431 ps
CPU time 3.38 seconds
Started Aug 27 03:43:33 AM UTC 24
Finished Aug 27 03:43:38 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676603778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3676603778
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/46.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3389787641
Short name T799
Test name
Test status
Simulation time 7191920257 ps
CPU time 24.9 seconds
Started Aug 27 03:43:37 AM UTC 24
Finished Aug 27 03:44:03 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389787641 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3389787641
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/46.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2243525942
Short name T814
Test name
Test status
Simulation time 3223385617 ps
CPU time 43.81 seconds
Started Aug 27 03:43:41 AM UTC 24
Finished Aug 27 03:44:26 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243525942 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2243525942
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/46.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3812500126
Short name T787
Test name
Test status
Simulation time 100597958 ps
CPU time 2.98 seconds
Started Aug 27 03:43:33 AM UTC 24
Finished Aug 27 03:43:37 AM UTC 24
Peak memory 217068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812500126 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.3812500126
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/46.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.2426975430
Short name T869
Test name
Test status
Simulation time 15008439005 ps
CPU time 146.33 seconds
Started Aug 27 03:43:55 AM UTC 24
Finished Aug 27 03:46:24 AM UTC 24
Peak memory 222976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426975430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2426975430
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/46.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3679932327
Short name T846
Test name
Test status
Simulation time 2995272705 ps
CPU time 77.78 seconds
Started Aug 27 03:43:58 AM UTC 24
Finished Aug 27 03:45:17 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679932327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.3679932327
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/46.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.3222694634
Short name T881
Test name
Test status
Simulation time 3140512549 ps
CPU time 194.88 seconds
Started Aug 27 03:43:55 AM UTC 24
Finished Aug 27 03:47:13 AM UTC 24
Peak memory 220936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222694634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.3222694634
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/46.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.921471167
Short name T53
Test name
Test status
Simulation time 8479975112 ps
CPU time 415.33 seconds
Started Aug 27 03:43:58 AM UTC 24
Finished Aug 27 03:50:59 AM UTC 24
Peak memory 233588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921471167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.921471167
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/46.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.1995436382
Short name T820
Test name
Test status
Simulation time 1296393664 ps
CPU time 34.56 seconds
Started Aug 27 03:43:55 AM UTC 24
Finished Aug 27 03:44:31 AM UTC 24
Peak memory 218876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995436382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1995436382
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/46.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.2381568552
Short name T818
Test name
Test status
Simulation time 335410018 ps
CPU time 8.48 seconds
Started Aug 27 03:44:17 AM UTC 24
Finished Aug 27 03:44:27 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381568552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.2381568552
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/47.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2947875202
Short name T896
Test name
Test status
Simulation time 117591013841 ps
CPU time 456.12 seconds
Started Aug 27 03:44:17 AM UTC 24
Finished Aug 27 03:51:59 AM UTC 24
Peak memory 220496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947875202 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.2947875202
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/47.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.1245355589
Short name T827
Test name
Test status
Simulation time 629779639 ps
CPU time 21.69 seconds
Started Aug 27 03:44:21 AM UTC 24
Finished Aug 27 03:44:44 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245355589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.1245355589
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/47.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.2543357700
Short name T819
Test name
Test status
Simulation time 101450229 ps
CPU time 11.62 seconds
Started Aug 27 03:44:18 AM UTC 24
Finished Aug 27 03:44:30 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543357700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2543357700
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/47.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.924662015
Short name T825
Test name
Test status
Simulation time 187611509 ps
CPU time 20.78 seconds
Started Aug 27 03:44:17 AM UTC 24
Finished Aug 27 03:44:39 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924662015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.924662015
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/47.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.2587934767
Short name T876
Test name
Test status
Simulation time 92159378401 ps
CPU time 166.97 seconds
Started Aug 27 03:44:17 AM UTC 24
Finished Aug 27 03:47:07 AM UTC 24
Peak memory 216964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587934767 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.2587934767
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/47.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.980164267
Short name T285
Test name
Test status
Simulation time 41180099455 ps
CPU time 248.93 seconds
Started Aug 27 03:44:17 AM UTC 24
Finished Aug 27 03:48:30 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980164267 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.980164267
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/47.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.2630369160
Short name T815
Test name
Test status
Simulation time 183424012 ps
CPU time 8.25 seconds
Started Aug 27 03:44:17 AM UTC 24
Finished Aug 27 03:44:27 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630369160 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.2630369160
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/47.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.4057896708
Short name T811
Test name
Test status
Simulation time 102728523 ps
CPU time 4.29 seconds
Started Aug 27 03:44:17 AM UTC 24
Finished Aug 27 03:44:23 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057896708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.4057896708
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/47.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.1980023604
Short name T808
Test name
Test status
Simulation time 159114931 ps
CPU time 5.55 seconds
Started Aug 27 03:44:07 AM UTC 24
Finished Aug 27 03:44:14 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980023604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1980023604
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/47.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.3569663033
Short name T845
Test name
Test status
Simulation time 6720615460 ps
CPU time 64.91 seconds
Started Aug 27 03:44:07 AM UTC 24
Finished Aug 27 03:45:14 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569663033 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3569663033
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/47.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3260580240
Short name T834
Test name
Test status
Simulation time 3270244768 ps
CPU time 39.68 seconds
Started Aug 27 03:44:17 AM UTC 24
Finished Aug 27 03:44:58 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260580240 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3260580240
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/47.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2024644182
Short name T805
Test name
Test status
Simulation time 39862403 ps
CPU time 2.31 seconds
Started Aug 27 03:44:07 AM UTC 24
Finished Aug 27 03:44:11 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024644182 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.2024644182
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/47.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.2892751170
Short name T180
Test name
Test status
Simulation time 4105755571 ps
CPU time 61.83 seconds
Started Aug 27 03:44:23 AM UTC 24
Finished Aug 27 03:45:27 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892751170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2892751170
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/47.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3949136944
Short name T865
Test name
Test status
Simulation time 6275953820 ps
CPU time 102.41 seconds
Started Aug 27 03:44:26 AM UTC 24
Finished Aug 27 03:46:11 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949136944 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3949136944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/47.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1431797573
Short name T892
Test name
Test status
Simulation time 811057555 ps
CPU time 304.24 seconds
Started Aug 27 03:44:26 AM UTC 24
Finished Aug 27 03:49:35 AM UTC 24
Peak memory 220872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431797573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.1431797573
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/47.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1549593401
Short name T882
Test name
Test status
Simulation time 7307655880 ps
CPU time 167.27 seconds
Started Aug 27 03:44:26 AM UTC 24
Finished Aug 27 03:47:17 AM UTC 24
Peak memory 223048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549593401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.1549593401
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/47.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.1346453028
Short name T816
Test name
Test status
Simulation time 134542046 ps
CPU time 4.75 seconds
Started Aug 27 03:44:21 AM UTC 24
Finished Aug 27 03:44:27 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346453028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1346453028
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/47.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.4052486567
Short name T840
Test name
Test status
Simulation time 2743945954 ps
CPU time 25.83 seconds
Started Aug 27 03:44:38 AM UTC 24
Finished Aug 27 03:45:05 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052486567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.4052486567
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/48.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.4268792301
Short name T887
Test name
Test status
Simulation time 83936200208 ps
CPU time 192.15 seconds
Started Aug 27 03:44:38 AM UTC 24
Finished Aug 27 03:47:53 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268792301 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.4268792301
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/48.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.2967827591
Short name T839
Test name
Test status
Simulation time 384127142 ps
CPU time 18.49 seconds
Started Aug 27 03:44:45 AM UTC 24
Finished Aug 27 03:45:05 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967827591 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.2967827591
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/48.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.3073932116
Short name T835
Test name
Test status
Simulation time 414380326 ps
CPU time 15.99 seconds
Started Aug 27 03:44:43 AM UTC 24
Finished Aug 27 03:45:00 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073932116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3073932116
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/48.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.2142515093
Short name T830
Test name
Test status
Simulation time 152507066 ps
CPU time 16.01 seconds
Started Aug 27 03:44:31 AM UTC 24
Finished Aug 27 03:44:49 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142515093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.2142515093
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/48.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.4276294834
Short name T890
Test name
Test status
Simulation time 243069589354 ps
CPU time 267.36 seconds
Started Aug 27 03:44:34 AM UTC 24
Finished Aug 27 03:49:05 AM UTC 24
Peak memory 217220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276294834 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.4276294834
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/48.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3413867031
Short name T877
Test name
Test status
Simulation time 48381603067 ps
CPU time 147.07 seconds
Started Aug 27 03:44:38 AM UTC 24
Finished Aug 27 03:47:08 AM UTC 24
Peak memory 219204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413867031 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3413867031
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/48.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.3998901884
Short name T836
Test name
Test status
Simulation time 172292831 ps
CPU time 28.65 seconds
Started Aug 27 03:44:34 AM UTC 24
Finished Aug 27 03:45:04 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998901884 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.3998901884
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/48.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.1783425593
Short name T833
Test name
Test status
Simulation time 710311997 ps
CPU time 11.88 seconds
Started Aug 27 03:44:43 AM UTC 24
Finished Aug 27 03:44:56 AM UTC 24
Peak memory 216468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783425593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1783425593
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/48.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.1067480518
Short name T823
Test name
Test status
Simulation time 284800901 ps
CPU time 4.58 seconds
Started Aug 27 03:44:31 AM UTC 24
Finished Aug 27 03:44:37 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067480518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1067480518
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/48.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.756178952
Short name T847
Test name
Test status
Simulation time 7808891039 ps
CPU time 46.11 seconds
Started Aug 27 03:44:31 AM UTC 24
Finished Aug 27 03:45:19 AM UTC 24
Peak memory 216720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756178952 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.756178952
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/48.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3425131463
Short name T849
Test name
Test status
Simulation time 5544504372 ps
CPU time 51.83 seconds
Started Aug 27 03:44:31 AM UTC 24
Finished Aug 27 03:45:25 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425131463 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3425131463
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/48.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.3355500566
Short name T822
Test name
Test status
Simulation time 29727701 ps
CPU time 2.78 seconds
Started Aug 27 03:44:31 AM UTC 24
Finished Aug 27 03:44:35 AM UTC 24
Peak memory 217068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355500566 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.3355500566
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/48.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.635563548
Short name T880
Test name
Test status
Simulation time 8089795880 ps
CPU time 141.1 seconds
Started Aug 27 03:44:45 AM UTC 24
Finished Aug 27 03:47:09 AM UTC 24
Peak memory 223048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635563548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.635563548
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/48.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.663674461
Short name T866
Test name
Test status
Simulation time 2977773564 ps
CPU time 83.25 seconds
Started Aug 27 03:44:49 AM UTC 24
Finished Aug 27 03:46:14 AM UTC 24
Peak memory 218956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663674461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.663674461
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/48.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3207607323
Short name T895
Test name
Test status
Simulation time 9823193531 ps
CPU time 413.16 seconds
Started Aug 27 03:44:49 AM UTC 24
Finished Aug 27 03:51:47 AM UTC 24
Peak memory 222984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207607323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.3207607323
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/48.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3057018508
Short name T894
Test name
Test status
Simulation time 10196651509 ps
CPU time 406.52 seconds
Started Aug 27 03:44:51 AM UTC 24
Finished Aug 27 03:51:43 AM UTC 24
Peak memory 239804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057018508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.3057018508
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/48.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.4176176221
Short name T837
Test name
Test status
Simulation time 605681636 ps
CPU time 19.86 seconds
Started Aug 27 03:44:43 AM UTC 24
Finished Aug 27 03:45:04 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176176221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.4176176221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/48.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.1723039557
Short name T853
Test name
Test status
Simulation time 134196507 ps
CPU time 29.09 seconds
Started Aug 27 03:45:11 AM UTC 24
Finished Aug 27 03:45:42 AM UTC 24
Peak memory 216904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723039557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.1723039557
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/49.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2673388261
Short name T898
Test name
Test status
Simulation time 143408147131 ps
CPU time 439.19 seconds
Started Aug 27 03:45:11 AM UTC 24
Finished Aug 27 03:52:36 AM UTC 24
Peak memory 219260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673388261 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.2673388261
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/49.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1793171806
Short name T852
Test name
Test status
Simulation time 522725430 ps
CPU time 19.96 seconds
Started Aug 27 03:45:17 AM UTC 24
Finished Aug 27 03:45:38 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793171806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.1793171806
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/49.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.2131841116
Short name T857
Test name
Test status
Simulation time 2526262405 ps
CPU time 38.91 seconds
Started Aug 27 03:45:11 AM UTC 24
Finished Aug 27 03:45:52 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131841116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2131841116
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/49.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2046020685
Short name T854
Test name
Test status
Simulation time 2584232196 ps
CPU time 41.25 seconds
Started Aug 27 03:45:03 AM UTC 24
Finished Aug 27 03:45:46 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046020685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.2046020685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/49.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.530658782
Short name T888
Test name
Test status
Simulation time 31094133156 ps
CPU time 169.74 seconds
Started Aug 27 03:45:11 AM UTC 24
Finished Aug 27 03:48:03 AM UTC 24
Peak memory 216704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530658782 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.530658782
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/49.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.4028880258
Short name T889
Test name
Test status
Simulation time 15729368996 ps
CPU time 195.87 seconds
Started Aug 27 03:45:11 AM UTC 24
Finished Aug 27 03:48:30 AM UTC 24
Peak memory 216960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028880258 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.4028880258
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/49.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.2048695599
Short name T848
Test name
Test status
Simulation time 482660544 ps
CPU time 16.93 seconds
Started Aug 27 03:45:03 AM UTC 24
Finished Aug 27 03:45:21 AM UTC 24
Peak memory 217072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048695599 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.2048695599
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/49.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.1842613271
Short name T851
Test name
Test status
Simulation time 2034194781 ps
CPU time 22.24 seconds
Started Aug 27 03:45:11 AM UTC 24
Finished Aug 27 03:45:35 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842613271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1842613271
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/49.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.1850645701
Short name T841
Test name
Test status
Simulation time 28145521 ps
CPU time 2.72 seconds
Started Aug 27 03:45:03 AM UTC 24
Finished Aug 27 03:45:06 AM UTC 24
Peak memory 216644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850645701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1850645701
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/49.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.272535822
Short name T859
Test name
Test status
Simulation time 6173822935 ps
CPU time 54.61 seconds
Started Aug 27 03:45:03 AM UTC 24
Finished Aug 27 03:45:59 AM UTC 24
Peak memory 216672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272535822 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.272535822
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/49.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.877283801
Short name T864
Test name
Test status
Simulation time 8974208801 ps
CPU time 63.76 seconds
Started Aug 27 03:45:03 AM UTC 24
Finished Aug 27 03:46:08 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877283801 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.877283801
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/49.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2244775828
Short name T842
Test name
Test status
Simulation time 34569747 ps
CPU time 3.16 seconds
Started Aug 27 03:45:03 AM UTC 24
Finished Aug 27 03:45:07 AM UTC 24
Peak memory 217132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244775828 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.2244775828
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/49.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.3714790792
Short name T872
Test name
Test status
Simulation time 1220263186 ps
CPU time 76.88 seconds
Started Aug 27 03:45:17 AM UTC 24
Finished Aug 27 03:46:36 AM UTC 24
Peak memory 219204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714790792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3714790792
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/49.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2517770921
Short name T878
Test name
Test status
Simulation time 3834894086 ps
CPU time 107.57 seconds
Started Aug 27 03:45:19 AM UTC 24
Finished Aug 27 03:47:09 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517770921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2517770921
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/49.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.4176226517
Short name T861
Test name
Test status
Simulation time 144360574 ps
CPU time 44.76 seconds
Started Aug 27 03:45:17 AM UTC 24
Finished Aug 27 03:46:03 AM UTC 24
Peak memory 219144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176226517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.4176226517
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/49.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.770210734
Short name T860
Test name
Test status
Simulation time 255935477 ps
CPU time 39.67 seconds
Started Aug 27 03:45:21 AM UTC 24
Finished Aug 27 03:46:02 AM UTC 24
Peak memory 220864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770210734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.770210734
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/49.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.2566340062
Short name T850
Test name
Test status
Simulation time 308588716 ps
CPU time 14.04 seconds
Started Aug 27 03:45:17 AM UTC 24
Finished Aug 27 03:45:32 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566340062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2566340062
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/49.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.3690002741
Short name T86
Test name
Test status
Simulation time 2108471429 ps
CPU time 23.21 seconds
Started Aug 27 03:25:15 AM UTC 24
Finished Aug 27 03:25:40 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690002741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3690002741
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/5.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.1907180705
Short name T73
Test name
Test status
Simulation time 49432859572 ps
CPU time 252.08 seconds
Started Aug 27 03:25:15 AM UTC 24
Finished Aug 27 03:29:31 AM UTC 24
Peak memory 218952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907180705 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.1907180705
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/5.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.472504525
Short name T41
Test name
Test status
Simulation time 84722479 ps
CPU time 9.71 seconds
Started Aug 27 03:25:18 AM UTC 24
Finished Aug 27 03:25:29 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472504525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.472504525
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/5.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.891430518
Short name T191
Test name
Test status
Simulation time 1057994798 ps
CPU time 17.13 seconds
Started Aug 27 03:25:18 AM UTC 24
Finished Aug 27 03:25:36 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891430518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.891430518
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/5.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random.2311517512
Short name T98
Test name
Test status
Simulation time 623083421 ps
CPU time 11.72 seconds
Started Aug 27 03:25:13 AM UTC 24
Finished Aug 27 03:25:26 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311517512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2311517512
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/5.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.3948347100
Short name T167
Test name
Test status
Simulation time 16985478001 ps
CPU time 66.22 seconds
Started Aug 27 03:25:14 AM UTC 24
Finished Aug 27 03:26:22 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948347100 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3948347100
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/5.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1653238342
Short name T117
Test name
Test status
Simulation time 25720340277 ps
CPU time 237.89 seconds
Started Aug 27 03:25:14 AM UTC 24
Finished Aug 27 03:29:16 AM UTC 24
Peak memory 218888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653238342 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1653238342
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/5.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.1607249569
Short name T316
Test name
Test status
Simulation time 36978361 ps
CPU time 4.53 seconds
Started Aug 27 03:25:14 AM UTC 24
Finished Aug 27 03:25:20 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607249569 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.1607249569
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/5.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.3660921659
Short name T259
Test name
Test status
Simulation time 7680534602 ps
CPU time 34.81 seconds
Started Aug 27 03:25:17 AM UTC 24
Finished Aug 27 03:25:53 AM UTC 24
Peak memory 216888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660921659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3660921659
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/5.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.3950083532
Short name T186
Test name
Test status
Simulation time 140821352 ps
CPU time 2.79 seconds
Started Aug 27 03:25:10 AM UTC 24
Finished Aug 27 03:25:14 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950083532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3950083532
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/5.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.3040510677
Short name T93
Test name
Test status
Simulation time 5137618298 ps
CPU time 33.5 seconds
Started Aug 27 03:25:12 AM UTC 24
Finished Aug 27 03:25:47 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040510677 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3040510677
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/5.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.553973242
Short name T89
Test name
Test status
Simulation time 4320798509 ps
CPU time 31.17 seconds
Started Aug 27 03:25:13 AM UTC 24
Finished Aug 27 03:25:45 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553973242 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.553973242
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/5.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.2915846527
Short name T313
Test name
Test status
Simulation time 24392683 ps
CPU time 2.66 seconds
Started Aug 27 03:25:12 AM UTC 24
Finished Aug 27 03:25:15 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915846527 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.2915846527
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/5.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.8670661
Short name T38
Test name
Test status
Simulation time 4957790282 ps
CPU time 190.13 seconds
Started Aug 27 03:25:19 AM UTC 24
Finished Aug 27 03:28:32 AM UTC 24
Peak memory 218544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8670661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T
EST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.8670661
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/5.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.4039685216
Short name T267
Test name
Test status
Simulation time 1288022981 ps
CPU time 101.31 seconds
Started Aug 27 03:25:20 AM UTC 24
Finished Aug 27 03:27:03 AM UTC 24
Peak memory 219076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039685216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.4039685216
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/5.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.618461796
Short name T311
Test name
Test status
Simulation time 709433822 ps
CPU time 295.26 seconds
Started Aug 27 03:25:19 AM UTC 24
Finished Aug 27 03:30:19 AM UTC 24
Peak memory 220936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618461796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.618461796
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/5.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.2788023770
Short name T46
Test name
Test status
Simulation time 10171550707 ps
CPU time 167.39 seconds
Started Aug 27 03:25:20 AM UTC 24
Finished Aug 27 03:28:10 AM UTC 24
Peak memory 223192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788023770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.2788023770
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/5.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.974209905
Short name T211
Test name
Test status
Simulation time 586667233 ps
CPU time 6.94 seconds
Started Aug 27 03:25:18 AM UTC 24
Finished Aug 27 03:25:26 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974209905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.974209905
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/5.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.1975917915
Short name T159
Test name
Test status
Simulation time 5511348996 ps
CPU time 62.06 seconds
Started Aug 27 03:25:28 AM UTC 24
Finished Aug 27 03:26:32 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975917915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.1975917915
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/6.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.1424706327
Short name T318
Test name
Test status
Simulation time 286995340 ps
CPU time 21.28 seconds
Started Aug 27 03:25:30 AM UTC 24
Finished Aug 27 03:25:53 AM UTC 24
Peak memory 217096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424706327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.1424706327
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/6.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.2814938685
Short name T91
Test name
Test status
Simulation time 466473764 ps
CPU time 15.15 seconds
Started Aug 27 03:25:29 AM UTC 24
Finished Aug 27 03:25:46 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814938685 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2814938685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/6.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random.269942324
Short name T90
Test name
Test status
Simulation time 695824326 ps
CPU time 18.71 seconds
Started Aug 27 03:25:26 AM UTC 24
Finished Aug 27 03:25:46 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269942324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.269942324
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/6.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.110386507
Short name T319
Test name
Test status
Simulation time 11028111108 ps
CPU time 72.92 seconds
Started Aug 27 03:25:27 AM UTC 24
Finished Aug 27 03:26:42 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110386507 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.110386507
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/6.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.1674447670
Short name T113
Test name
Test status
Simulation time 17493181613 ps
CPU time 78.87 seconds
Started Aug 27 03:25:27 AM UTC 24
Finished Aug 27 03:26:48 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674447670 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.1674447670
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/6.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.1003808225
Short name T94
Test name
Test status
Simulation time 219701294 ps
CPU time 19.36 seconds
Started Aug 27 03:25:27 AM UTC 24
Finished Aug 27 03:25:48 AM UTC 24
Peak memory 217144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003808225 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1003808225
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/6.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.1197557322
Short name T95
Test name
Test status
Simulation time 258819530 ps
CPU time 17.99 seconds
Started Aug 27 03:25:28 AM UTC 24
Finished Aug 27 03:25:48 AM UTC 24
Peak memory 217148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197557322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.1197557322
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/6.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.2609186942
Short name T212
Test name
Test status
Simulation time 117155829 ps
CPU time 3.52 seconds
Started Aug 27 03:25:21 AM UTC 24
Finished Aug 27 03:25:26 AM UTC 24
Peak memory 217132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609186942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2609186942
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/6.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.1931909651
Short name T161
Test name
Test status
Simulation time 10296158300 ps
CPU time 45.2 seconds
Started Aug 27 03:25:23 AM UTC 24
Finished Aug 27 03:26:11 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931909651 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1931909651
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/6.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.1573851514
Short name T121
Test name
Test status
Simulation time 5180991429 ps
CPU time 28.26 seconds
Started Aug 27 03:25:24 AM UTC 24
Finished Aug 27 03:25:54 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573851514 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1573851514
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/6.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2149704176
Short name T40
Test name
Test status
Simulation time 43473146 ps
CPU time 3.6 seconds
Started Aug 27 03:25:22 AM UTC 24
Finished Aug 27 03:25:27 AM UTC 24
Peak memory 217064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149704176 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2149704176
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/6.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.1940621215
Short name T62
Test name
Test status
Simulation time 47990210 ps
CPU time 7.91 seconds
Started Aug 27 03:25:35 AM UTC 24
Finished Aug 27 03:25:45 AM UTC 24
Peak memory 218876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940621215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1940621215
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/6.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.2100048051
Short name T268
Test name
Test status
Simulation time 10619708610 ps
CPU time 85.4 seconds
Started Aug 27 03:25:37 AM UTC 24
Finished Aug 27 03:27:04 AM UTC 24
Peak memory 218876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100048051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.2100048051
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/6.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.2464725166
Short name T166
Test name
Test status
Simulation time 150879878 ps
CPU time 43.14 seconds
Started Aug 27 03:25:37 AM UTC 24
Finished Aug 27 03:26:21 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464725166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.2464725166
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/6.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.417108945
Short name T192
Test name
Test status
Simulation time 44890360 ps
CPU time 6.61 seconds
Started Aug 27 03:25:29 AM UTC 24
Finished Aug 27 03:25:37 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417108945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.417108945
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/6.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.3562374272
Short name T67
Test name
Test status
Simulation time 1879519155 ps
CPU time 40.42 seconds
Started Aug 27 03:25:48 AM UTC 24
Finished Aug 27 03:26:30 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562374272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.3562374272
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/7.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3147715117
Short name T140
Test name
Test status
Simulation time 73417833368 ps
CPU time 706.85 seconds
Started Aug 27 03:25:49 AM UTC 24
Finished Aug 27 03:37:44 AM UTC 24
Peak memory 222616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147715117 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.3147715117
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/7.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.4150475062
Short name T128
Test name
Test status
Simulation time 132904443 ps
CPU time 13.11 seconds
Started Aug 27 03:25:53 AM UTC 24
Finished Aug 27 03:26:08 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150475062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.4150475062
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/7.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.639205676
Short name T174
Test name
Test status
Simulation time 5015758476 ps
CPU time 45.95 seconds
Started Aug 27 03:25:49 AM UTC 24
Finished Aug 27 03:26:37 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639205676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.639205676
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/7.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random.2332107281
Short name T100
Test name
Test status
Simulation time 1184819233 ps
CPU time 19.18 seconds
Started Aug 27 03:25:46 AM UTC 24
Finished Aug 27 03:26:07 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332107281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.2332107281
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/7.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.2344551308
Short name T163
Test name
Test status
Simulation time 15766095486 ps
CPU time 28.69 seconds
Started Aug 27 03:25:48 AM UTC 24
Finished Aug 27 03:26:18 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344551308 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2344551308
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/7.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.1718168491
Short name T189
Test name
Test status
Simulation time 25322959287 ps
CPU time 243.99 seconds
Started Aug 27 03:25:48 AM UTC 24
Finished Aug 27 03:29:56 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718168491 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1718168491
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/7.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.3155484132
Short name T258
Test name
Test status
Simulation time 44874042 ps
CPU time 4.91 seconds
Started Aug 27 03:25:46 AM UTC 24
Finished Aug 27 03:25:52 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155484132 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3155484132
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/7.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.3308128531
Short name T260
Test name
Test status
Simulation time 32931981 ps
CPU time 2.81 seconds
Started Aug 27 03:25:49 AM UTC 24
Finished Aug 27 03:25:53 AM UTC 24
Peak memory 217144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308128531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3308128531
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/7.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.901461935
Short name T88
Test name
Test status
Simulation time 54477755 ps
CPU time 2.95 seconds
Started Aug 27 03:25:41 AM UTC 24
Finished Aug 27 03:25:45 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901461935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.901461935
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/7.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.1429719582
Short name T226
Test name
Test status
Simulation time 8876847019 ps
CPU time 41.04 seconds
Started Aug 27 03:25:45 AM UTC 24
Finished Aug 27 03:26:28 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429719582 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.1429719582
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/7.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.4001018268
Short name T199
Test name
Test status
Simulation time 15630685621 ps
CPU time 36.89 seconds
Started Aug 27 03:25:46 AM UTC 24
Finished Aug 27 03:26:25 AM UTC 24
Peak memory 217140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001018268 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.4001018268
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/7.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.867587637
Short name T92
Test name
Test status
Simulation time 69372432 ps
CPU time 3.21 seconds
Started Aug 27 03:25:42 AM UTC 24
Finished Aug 27 03:25:46 AM UTC 24
Peak memory 217068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867587637 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.867587637
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/7.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.2049274714
Short name T165
Test name
Test status
Simulation time 1119464702 ps
CPU time 25.05 seconds
Started Aug 27 03:25:53 AM UTC 24
Finished Aug 27 03:26:20 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049274714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2049274714
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/7.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.831984303
Short name T6
Test name
Test status
Simulation time 4950649932 ps
CPU time 173.88 seconds
Started Aug 27 03:25:55 AM UTC 24
Finished Aug 27 03:28:51 AM UTC 24
Peak memory 220996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831984303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.831984303
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/7.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.942787465
Short name T208
Test name
Test status
Simulation time 2744349365 ps
CPU time 364.33 seconds
Started Aug 27 03:25:55 AM UTC 24
Finished Aug 27 03:32:04 AM UTC 24
Peak memory 222980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942787465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.942787465
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/7.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3288858083
Short name T204
Test name
Test status
Simulation time 165910178 ps
CPU time 101.74 seconds
Started Aug 27 03:25:56 AM UTC 24
Finished Aug 27 03:27:39 AM UTC 24
Peak memory 223240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288858083 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.3288858083
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/7.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.1984837220
Short name T123
Test name
Test status
Simulation time 31649014 ps
CPU time 1.97 seconds
Started Aug 27 03:25:53 AM UTC 24
Finished Aug 27 03:25:56 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984837220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1984837220
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/7.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.2113657630
Short name T112
Test name
Test status
Simulation time 24979874518 ps
CPU time 239.85 seconds
Started Aug 27 03:26:16 AM UTC 24
Finished Aug 27 03:30:19 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113657630 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.2113657630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/8.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.181892995
Short name T261
Test name
Test status
Simulation time 1064458857 ps
CPU time 24.63 seconds
Started Aug 27 03:26:22 AM UTC 24
Finished Aug 27 03:26:48 AM UTC 24
Peak memory 217096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181892995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.181892995
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/8.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.3154417345
Short name T171
Test name
Test status
Simulation time 233097597 ps
CPU time 10.79 seconds
Started Aug 27 03:26:20 AM UTC 24
Finished Aug 27 03:26:32 AM UTC 24
Peak memory 216756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154417345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3154417345
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/8.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.919378737
Short name T201
Test name
Test status
Simulation time 21679552017 ps
CPU time 122.81 seconds
Started Aug 27 03:26:07 AM UTC 24
Finished Aug 27 03:28:12 AM UTC 24
Peak memory 217216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919378737 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.919378737
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/8.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.355552916
Short name T293
Test name
Test status
Simulation time 5797948058 ps
CPU time 35.53 seconds
Started Aug 27 03:26:08 AM UTC 24
Finished Aug 27 03:26:45 AM UTC 24
Peak memory 217152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355552916 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.355552916
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/8.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.4003599557
Short name T168
Test name
Test status
Simulation time 102133529 ps
CPU time 18.96 seconds
Started Aug 27 03:26:02 AM UTC 24
Finished Aug 27 03:26:22 AM UTC 24
Peak memory 217144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003599557 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.4003599557
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/8.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.720423266
Short name T262
Test name
Test status
Simulation time 3368428788 ps
CPU time 29.31 seconds
Started Aug 27 03:26:19 AM UTC 24
Finished Aug 27 03:26:49 AM UTC 24
Peak memory 217152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720423266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.720423266
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/8.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.1950582666
Short name T126
Test name
Test status
Simulation time 48715623 ps
CPU time 3.26 seconds
Started Aug 27 03:25:57 AM UTC 24
Finished Aug 27 03:26:01 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950582666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1950582666
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/8.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.928402236
Short name T225
Test name
Test status
Simulation time 5316855247 ps
CPU time 27.52 seconds
Started Aug 27 03:25:58 AM UTC 24
Finished Aug 27 03:26:27 AM UTC 24
Peak memory 217140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928402236 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.928402236
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/8.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2260667250
Short name T176
Test name
Test status
Simulation time 14653107290 ps
CPU time 41.52 seconds
Started Aug 27 03:25:58 AM UTC 24
Finished Aug 27 03:26:41 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260667250 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2260667250
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/8.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.419053191
Short name T127
Test name
Test status
Simulation time 42733714 ps
CPU time 3.57 seconds
Started Aug 27 03:25:57 AM UTC 24
Finished Aug 27 03:26:01 AM UTC 24
Peak memory 216940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419053191 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.419053191
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/8.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.282054425
Short name T111
Test name
Test status
Simulation time 16673500949 ps
CPU time 190.06 seconds
Started Aug 27 03:26:23 AM UTC 24
Finished Aug 27 03:29:36 AM UTC 24
Peak memory 220992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282054425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.282054425
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/8.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.1071201838
Short name T301
Test name
Test status
Simulation time 6661178493 ps
CPU time 168.94 seconds
Started Aug 27 03:26:26 AM UTC 24
Finished Aug 27 03:29:17 AM UTC 24
Peak memory 222980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071201838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1071201838
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/8.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.1663037614
Short name T45
Test name
Test status
Simulation time 128905216 ps
CPU time 37.21 seconds
Started Aug 27 03:26:26 AM UTC 24
Finished Aug 27 03:27:04 AM UTC 24
Peak memory 221192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663037614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.1663037614
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/8.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.4232662356
Short name T68
Test name
Test status
Simulation time 147193687 ps
CPU time 19.8 seconds
Started Aug 27 03:26:21 AM UTC 24
Finished Aug 27 03:26:42 AM UTC 24
Peak memory 219136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232662356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.4232662356
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/8.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.620718478
Short name T320
Test name
Test status
Simulation time 119351802 ps
CPU time 7.05 seconds
Started Aug 27 03:26:35 AM UTC 24
Finished Aug 27 03:26:44 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620718478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.620718478
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/9.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.644283379
Short name T294
Test name
Test status
Simulation time 25735724574 ps
CPU time 165.19 seconds
Started Aug 27 03:26:38 AM UTC 24
Finished Aug 27 03:29:25 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644283379 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.644283379
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/9.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.254080954
Short name T322
Test name
Test status
Simulation time 1752150151 ps
CPU time 24.47 seconds
Started Aug 27 03:26:43 AM UTC 24
Finished Aug 27 03:27:09 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254080954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.254080954
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/9.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.47149857
Short name T264
Test name
Test status
Simulation time 134926959 ps
CPU time 11.03 seconds
Started Aug 27 03:26:42 AM UTC 24
Finished Aug 27 03:26:54 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47149857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.47149857
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/9.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random.1498523028
Short name T175
Test name
Test status
Simulation time 76808551 ps
CPU time 4.02 seconds
Started Aug 27 03:26:32 AM UTC 24
Finished Aug 27 03:26:37 AM UTC 24
Peak memory 217148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498523028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.1498523028
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/9.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.4108560229
Short name T236
Test name
Test status
Simulation time 67105078505 ps
CPU time 233.42 seconds
Started Aug 27 03:26:33 AM UTC 24
Finished Aug 27 03:30:30 AM UTC 24
Peak memory 216900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108560229 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.4108560229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/9.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2233663172
Short name T246
Test name
Test status
Simulation time 13042518914 ps
CPU time 99.34 seconds
Started Aug 27 03:26:34 AM UTC 24
Finished Aug 27 03:28:16 AM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233663172 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2233663172
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/9.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.1432962012
Short name T51
Test name
Test status
Simulation time 44638411 ps
CPU time 7.53 seconds
Started Aug 27 03:26:33 AM UTC 24
Finished Aug 27 03:26:42 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432962012 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1432962012
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/9.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.3292160120
Short name T254
Test name
Test status
Simulation time 1166657996 ps
CPU time 33.24 seconds
Started Aug 27 03:26:38 AM UTC 24
Finished Aug 27 03:27:12 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292160120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3292160120
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/9.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.1932160967
Short name T173
Test name
Test status
Simulation time 274549396 ps
CPU time 5.54 seconds
Started Aug 27 03:26:28 AM UTC 24
Finished Aug 27 03:26:34 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932160967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1932160967
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/9.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.4249398169
Short name T324
Test name
Test status
Simulation time 8572861130 ps
CPU time 39.77 seconds
Started Aug 27 03:26:31 AM UTC 24
Finished Aug 27 03:27:12 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249398169 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.4249398169
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/9.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.3435309934
Short name T69
Test name
Test status
Simulation time 2713440997 ps
CPU time 33.45 seconds
Started Aug 27 03:26:32 AM UTC 24
Finished Aug 27 03:27:07 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435309934 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3435309934
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/9.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.3260492939
Short name T172
Test name
Test status
Simulation time 31880237 ps
CPU time 3.58 seconds
Started Aug 27 03:26:29 AM UTC 24
Finished Aug 27 03:26:33 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260492939 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.3260492939
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/9.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.1914541383
Short name T339
Test name
Test status
Simulation time 956552029 ps
CPU time 107.54 seconds
Started Aug 27 03:26:43 AM UTC 24
Finished Aug 27 03:28:33 AM UTC 24
Peak memory 220864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914541383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1914541383
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/9.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.764121924
Short name T245
Test name
Test status
Simulation time 1190159166 ps
CPU time 87.13 seconds
Started Aug 27 03:26:46 AM UTC 24
Finished Aug 27 03:28:15 AM UTC 24
Peak memory 219080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764121924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.764121924
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/9.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.4096863520
Short name T209
Test name
Test status
Simulation time 1677947423 ps
CPU time 380.38 seconds
Started Aug 27 03:26:44 AM UTC 24
Finished Aug 27 03:33:09 AM UTC 24
Peak memory 223244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096863520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.4096863520
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/9.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.3593274258
Short name T58
Test name
Test status
Simulation time 763028182 ps
CPU time 174.45 seconds
Started Aug 27 03:26:48 AM UTC 24
Finished Aug 27 03:29:46 AM UTC 24
Peak memory 222988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593274258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.3593274258
Directory /workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/9.xbar_stress_all_with_reset_error/latest
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