Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1844	1			T18	2		T88	1		T59	3
all_values[1]	1871	1			T18	2		T59	3		T52	4
all_values[2]	1865	1			T55	1		T18	2		T88	1
all_values[3]	1848	1			T55	1		T18	2		T59	1
all_values[4]	1849	1			T10	1		T55	1		T18	1
all_values[5]	1881	1			T55	1		T18	6		T88	1
all_values[6]	1862	1			T55	1		T18	5		T59	3
all_values[7]	1941	1			T55	1		T18	8		T59	3
all_values[8]	1807	1			T10	1		T55	1		T18	4
all_values[9]	1869	1			T55	1		T18	4		T59	1
all_values[10]	1913	1			T55	2		T18	3		T88	1
all_values[11]	1877	1			T10	1		T18	2		T59	1
all_values[12]	1858	1			T18	2		T52	2		T53	1
all_values[13]	1829	1			T55	1		T18	4		T59	3
all_values[14]	1893	1			T10	1		T55	1		T18	6
all_values[15]	1784	1			T10	2		T18	1		T59	5
all_values[16]	1827	1			T55	1		T18	2		T59	1
all_values[17]	1769	1			T55	2		T18	5		T52	5
all_values[18]	1838	1			T59	4		T52	6		T39	2
all_values[19]	1852	1			T10	1		T59	2		T52	4
all_values[20]	1779	1			T10	2		T18	6		T59	2
all_values[21]	1798	1			T18	3		T52	3		T39	1
all_values[22]	1780	1			T10	1		T18	1		T59	2
all_values[23]	1850	1			T18	3		T59	4		T52	2
all_values[24]	1817	1			T55	1		T18	3		T59	2
all_values[25]	1839	1			T10	3		T55	2		T18	3
all_values[26]	1826	1			T10	2		T55	1		T18	8
all_values[27]	1797	1			T10	3		T55	1		T18	3
all_values[28]	1847	1			T10	1		T18	4		T59	1
all_values[29]	1821	1			T10	2		T55	2		T18	3
all_values[30]	1922	1			T10	1		T55	2		T18	4
all_values[31]	1904	1			T55	1		T18	2		T59	1
all_values[32]	1885	1			T10	1		T18	4		T59	1
all_values[33]	1849	1			T55	2		T18	6		T52	3
all_values[34]	1813	1			T55	3		T18	3		T59	4
all_values[35]	1848	1			T10	1		T55	1		T18	2
all_values[36]	1870	1			T55	3		T18	4		T59	3
all_values[37]	1884	1			T10	2		T55	3		T18	5
all_values[38]	1860	1			T55	1		T18	1		T88	1
all_values[39]	1883	1			T55	1		T18	5		T59	3
all_values[40]	1838	1			T55	1		T18	2		T59	1
all_values[41]	1874	1			T55	2		T18	3		T88	1
all_values[42]	1874	1			T10	1		T55	2		T18	6
all_values[43]	1836	1			T10	1		T55	3		T18	3
all_values[44]	1814	1			T10	2		T18	4		T59	2
all_values[45]	1861	1			T10	1		T18	1		T59	1
all_values[46]	1900	1			T10	2		T55	1		T18	4
all_values[47]	1849	1			T10	1		T55	1		T18	2
all_values[48]	1845	1			T10	3		T55	1		T18	6
all_values[49]	1847	1			T55	1		T18	5		T59	2
all_values[50]	1823	1			T10	2		T18	6		T59	3
all_values[51]	1870	1			T18	2		T59	2		T52	3
all_values[52]	1845	1			T10	3		T18	2		T59	2
all_values[53]	1827	1			T10	2		T18	4		T59	1
all_values[54]	1914	1			T10	2		T55	1		T18	2
all_values[55]	1875	1			T18	2		T59	1		T52	4
all_values[56]	1782	1			T55	2		T18	3		T59	2
all_values[57]	1836	1			T10	4		T18	4		T88	1
all_values[58]	1804	1			T55	1		T18	1		T59	4
all_values[59]	1803	1			T10	1		T18	3		T59	1
all_values[60]	1889	1			T55	1		T18	5		T59	3
all_values[61]	1841	1			T10	1		T55	3		T18	2
all_values[62]	1736	1			T55	1		T18	4		T59	2
all_values[63]	1887	1			T10	4		T55	1		T18	5