| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.02 | 99.26 | 88.89 | 98.80 | 95.88 | 99.26 | 100.00 |
| T778 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.3206079168 | Aug 28 07:43:20 PM UTC 24 | Aug 28 07:43:25 PM UTC 24 | 206655780 ps | ||
| T779 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1939953939 | Aug 28 07:40:56 PM UTC 24 | Aug 28 07:43:28 PM UTC 24 | 11161184281 ps | ||
| T780 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.222495409 | Aug 28 07:38:42 PM UTC 24 | Aug 28 07:43:30 PM UTC 24 | 29848226267 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.374100865 | Aug 28 07:43:26 PM UTC 24 | Aug 28 07:43:31 PM UTC 24 | 18990038 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.2121370736 | Aug 28 07:42:21 PM UTC 24 | Aug 28 07:43:33 PM UTC 24 | 1296866884 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.4183058745 | Aug 28 07:39:36 PM UTC 24 | Aug 28 07:43:34 PM UTC 24 | 50955256356 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1161443396 | Aug 28 07:42:35 PM UTC 24 | Aug 28 07:43:35 PM UTC 24 | 100315152 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.173696991 | Aug 28 07:42:41 PM UTC 24 | Aug 28 07:43:36 PM UTC 24 | 21349608818 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1938262535 | Aug 28 07:42:40 PM UTC 24 | Aug 28 07:43:47 PM UTC 24 | 24521222648 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1680443660 | Aug 28 07:43:37 PM UTC 24 | Aug 28 07:43:50 PM UTC 24 | 175225719 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.2886318380 | Aug 28 07:40:33 PM UTC 24 | Aug 28 07:43:50 PM UTC 24 | 92893615598 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.393712224 | Aug 28 07:43:26 PM UTC 24 | Aug 28 07:43:52 PM UTC 24 | 188341843 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.3973103278 | Aug 28 07:42:53 PM UTC 24 | Aug 28 07:43:52 PM UTC 24 | 2315590775 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.449099593 | Aug 28 07:40:42 PM UTC 24 | Aug 28 07:43:52 PM UTC 24 | 4049878694 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.4199648469 | Aug 28 07:43:33 PM UTC 24 | Aug 28 07:43:58 PM UTC 24 | 279465296 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2816116278 | Aug 28 07:43:22 PM UTC 24 | Aug 28 07:43:58 PM UTC 24 | 4039115443 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1011939996 | Aug 28 07:41:37 PM UTC 24 | Aug 28 07:43:59 PM UTC 24 | 359182419 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.2217297153 | Aug 28 07:42:17 PM UTC 24 | Aug 28 07:43:59 PM UTC 24 | 29711084621 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.2087905289 | Aug 28 07:43:57 PM UTC 24 | Aug 28 07:44:01 PM UTC 24 | 50276062 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.3673650850 | Aug 28 07:43:37 PM UTC 24 | Aug 28 07:44:01 PM UTC 24 | 1180550661 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.1695223199 | Aug 28 07:43:37 PM UTC 24 | Aug 28 07:44:02 PM UTC 24 | 168710954 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.2285581894 | Aug 28 07:43:57 PM UTC 24 | Aug 28 07:44:02 PM UTC 24 | 158510444 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1258032505 | Aug 28 07:34:11 PM UTC 24 | Aug 28 07:44:05 PM UTC 24 | 69814381528 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.2361395921 | Aug 28 07:41:32 PM UTC 24 | Aug 28 07:44:05 PM UTC 24 | 1696266181 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.996545316 | Aug 28 07:43:26 PM UTC 24 | Aug 28 07:44:06 PM UTC 24 | 2962722166 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3207971150 | Aug 28 07:41:37 PM UTC 24 | Aug 28 07:44:08 PM UTC 24 | 272843350 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1474877953 | Aug 28 07:43:16 PM UTC 24 | Aug 28 07:44:08 PM UTC 24 | 1670173497 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1827608855 | Aug 28 07:43:30 PM UTC 24 | Aug 28 07:44:11 PM UTC 24 | 4560107340 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.4152056080 | Aug 28 07:43:34 PM UTC 24 | Aug 28 07:44:17 PM UTC 24 | 1510001113 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.271855207 | Aug 28 07:44:05 PM UTC 24 | Aug 28 07:44:18 PM UTC 24 | 93986109 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2820548605 | Aug 28 07:44:12 PM UTC 24 | Aug 28 07:44:19 PM UTC 24 | 140827634 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3244635939 | Aug 28 07:39:55 PM UTC 24 | Aug 28 07:44:19 PM UTC 24 | 10930427495 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2434530283 | Aug 28 07:41:53 PM UTC 24 | Aug 28 07:44:20 PM UTC 24 | 24740385434 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2264492236 | Aug 28 07:44:20 PM UTC 24 | Aug 28 07:44:24 PM UTC 24 | 101654564 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3913820966 | Aug 28 07:37:18 PM UTC 24 | Aug 28 07:44:24 PM UTC 24 | 42022408672 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.2348094639 | Aug 28 07:32:45 PM UTC 24 | Aug 28 07:44:27 PM UTC 24 | 65085673343 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.740544864 | Aug 28 07:38:29 PM UTC 24 | Aug 28 07:44:27 PM UTC 24 | 5023245223 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.956290342 | Aug 28 07:44:20 PM UTC 24 | Aug 28 07:44:27 PM UTC 24 | 620003965 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.2709133042 | Aug 28 07:44:05 PM UTC 24 | Aug 28 07:44:27 PM UTC 24 | 564590977 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.3891635036 | Aug 28 07:44:26 PM UTC 24 | Aug 28 07:44:30 PM UTC 24 | 15028544 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.4162412573 | Aug 28 07:40:01 PM UTC 24 | Aug 28 07:44:30 PM UTC 24 | 35046564471 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1230538353 | Aug 28 07:38:57 PM UTC 24 | Aug 28 07:44:34 PM UTC 24 | 888963686 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.2059240077 | Aug 28 07:44:05 PM UTC 24 | Aug 28 07:44:35 PM UTC 24 | 968299831 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.1799056975 | Aug 28 07:44:05 PM UTC 24 | Aug 28 07:44:35 PM UTC 24 | 973784164 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3901382901 | Aug 28 07:33:10 PM UTC 24 | Aug 28 07:44:37 PM UTC 24 | 91129444142 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1584925037 | Aug 28 07:44:33 PM UTC 24 | Aug 28 07:44:40 PM UTC 24 | 348839550 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.4001834353 | Aug 28 07:44:12 PM UTC 24 | Aug 28 07:44:41 PM UTC 24 | 386455431 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2751315839 | Aug 28 07:39:14 PM UTC 24 | Aug 28 07:44:44 PM UTC 24 | 28956795523 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1836688996 | Aug 28 07:44:00 PM UTC 24 | Aug 28 07:44:44 PM UTC 24 | 5657530936 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.465511358 | Aug 28 07:44:12 PM UTC 24 | Aug 28 07:44:48 PM UTC 24 | 274401901 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.2768830131 | Aug 28 07:44:31 PM UTC 24 | Aug 28 07:44:49 PM UTC 24 | 295367951 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2704549203 | Aug 28 07:44:37 PM UTC 24 | Aug 28 07:44:50 PM UTC 24 | 1162446134 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2776686923 | Aug 28 07:44:46 PM UTC 24 | Aug 28 07:44:51 PM UTC 24 | 49756677 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.2236387920 | Aug 28 07:44:46 PM UTC 24 | Aug 28 07:44:53 PM UTC 24 | 438151145 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.3683891490 | Aug 28 07:44:31 PM UTC 24 | Aug 28 07:44:55 PM UTC 24 | 2527988286 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.4199348635 | Aug 28 07:44:12 PM UTC 24 | Aug 28 07:44:56 PM UTC 24 | 108019495 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.4227817807 | Aug 28 07:44:00 PM UTC 24 | Aug 28 07:44:57 PM UTC 24 | 25208406050 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.1229772830 | Aug 28 07:44:23 PM UTC 24 | Aug 28 07:44:57 PM UTC 24 | 2866642878 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.3838152940 | Aug 28 07:44:54 PM UTC 24 | Aug 28 07:44:59 PM UTC 24 | 82756575 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.2145649309 | Aug 28 07:44:12 PM UTC 24 | Aug 28 07:45:00 PM UTC 24 | 4554362998 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2607180792 | Aug 28 07:41:08 PM UTC 24 | Aug 28 07:45:01 PM UTC 24 | 2513482223 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.862610961 | Aug 28 07:44:37 PM UTC 24 | Aug 28 07:45:01 PM UTC 24 | 126678011 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3719549676 | Aug 28 07:40:24 PM UTC 24 | Aug 28 07:45:02 PM UTC 24 | 8067446086 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.3121954403 | Aug 28 07:44:26 PM UTC 24 | Aug 28 07:45:03 PM UTC 24 | 328876288 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1756661411 | Aug 28 07:42:52 PM UTC 24 | Aug 28 07:45:03 PM UTC 24 | 8472556732 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.1989517818 | Aug 28 07:44:58 PM UTC 24 | Aug 28 07:45:04 PM UTC 24 | 90327590 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1124504761 | Aug 28 07:42:37 PM UTC 24 | Aug 28 07:45:05 PM UTC 24 | 4258808435 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.4018375553 | Aug 28 07:42:18 PM UTC 24 | Aug 28 07:45:05 PM UTC 24 | 20102926303 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1037368182 | Aug 28 07:44:23 PM UTC 24 | Aug 28 07:45:07 PM UTC 24 | 13248994348 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.4267107296 | Aug 28 07:39:44 PM UTC 24 | Aug 28 07:45:08 PM UTC 24 | 31700948206 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.2401682663 | Aug 28 07:44:53 PM UTC 24 | Aug 28 07:45:09 PM UTC 24 | 144407163 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1594036369 | Aug 28 07:39:23 PM UTC 24 | Aug 28 07:45:09 PM UTC 24 | 516883409 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.2312983001 | Aug 28 07:42:31 PM UTC 24 | Aug 28 07:45:11 PM UTC 24 | 1204022659 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.234401945 | Aug 28 07:44:12 PM UTC 24 | Aug 28 07:45:11 PM UTC 24 | 425922603 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.651258682 | Aug 28 07:45:03 PM UTC 24 | Aug 28 07:45:13 PM UTC 24 | 277528484 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.75337222 | Aug 28 07:45:10 PM UTC 24 | Aug 28 07:45:13 PM UTC 24 | 33405614 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2726138604 | Aug 28 07:45:10 PM UTC 24 | Aug 28 07:45:15 PM UTC 24 | 106066937 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.3109707482 | Aug 28 07:45:03 PM UTC 24 | Aug 28 07:45:19 PM UTC 24 | 598798316 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.1652357048 | Aug 28 07:45:13 PM UTC 24 | Aug 28 07:45:23 PM UTC 24 | 65732463 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.2100146988 | Aug 28 07:45:03 PM UTC 24 | Aug 28 07:45:24 PM UTC 24 | 300254370 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.3230056766 | Aug 28 07:45:13 PM UTC 24 | Aug 28 07:45:25 PM UTC 24 | 189021408 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3065045392 | Aug 28 07:44:49 PM UTC 24 | Aug 28 07:45:26 PM UTC 24 | 3743348208 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.980487804 | Aug 28 07:45:13 PM UTC 24 | Aug 28 07:45:28 PM UTC 24 | 317928373 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.3245426418 | Aug 28 07:45:17 PM UTC 24 | Aug 28 07:45:32 PM UTC 24 | 99933787 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.2281458476 | Aug 28 07:45:09 PM UTC 24 | Aug 28 07:45:32 PM UTC 24 | 808270631 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.4020489211 | Aug 28 07:45:10 PM UTC 24 | Aug 28 07:45:34 PM UTC 24 | 128635118 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.4057418681 | Aug 28 07:44:05 PM UTC 24 | Aug 28 07:45:36 PM UTC 24 | 10399452281 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.1571328520 | Aug 28 07:42:05 PM UTC 24 | Aug 28 07:45:36 PM UTC 24 | 4768371713 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.997902988 | Aug 28 07:40:46 PM UTC 24 | Aug 28 07:45:39 PM UTC 24 | 12381612313 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.3668370172 | Aug 28 07:40:21 PM UTC 24 | Aug 28 07:45:41 PM UTC 24 | 4799461463 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3832878795 | Aug 28 07:40:46 PM UTC 24 | Aug 28 07:45:42 PM UTC 24 | 1644432734 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.398529621 | Aug 28 07:44:53 PM UTC 24 | Aug 28 07:45:45 PM UTC 24 | 10401851691 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.450367636 | Aug 28 07:39:02 PM UTC 24 | Aug 28 07:45:45 PM UTC 24 | 6776059322 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.4204074160 | Aug 28 07:42:56 PM UTC 24 | Aug 28 07:45:46 PM UTC 24 | 35164383237 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.87249520 | Aug 28 07:45:25 PM UTC 24 | Aug 28 07:45:47 PM UTC 24 | 1613248733 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.332196097 | Aug 28 07:45:10 PM UTC 24 | Aug 28 07:45:50 PM UTC 24 | 3736186339 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.694002689 | Aug 28 07:44:05 PM UTC 24 | Aug 28 07:45:51 PM UTC 24 | 16888631971 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.1154012011 | Aug 28 07:45:21 PM UTC 24 | Aug 28 07:45:57 PM UTC 24 | 845498635 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.2008604967 | Aug 28 07:39:52 PM UTC 24 | Aug 28 07:45:58 PM UTC 24 | 10170390790 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.3327425908 | Aug 28 07:45:16 PM UTC 24 | Aug 28 07:45:59 PM UTC 24 | 5847831855 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3627396159 | Aug 28 07:38:19 PM UTC 24 | Aug 28 07:46:00 PM UTC 24 | 106135720354 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.493991425 | Aug 28 07:43:54 PM UTC 24 | Aug 28 07:46:01 PM UTC 24 | 3074149027 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.162130022 | Aug 28 07:45:10 PM UTC 24 | Aug 28 07:46:02 PM UTC 24 | 5676575717 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.3655618746 | Aug 28 07:40:41 PM UTC 24 | Aug 28 07:46:05 PM UTC 24 | 10672258127 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.2310052113 | Aug 28 07:45:09 PM UTC 24 | Aug 28 07:46:06 PM UTC 24 | 2077378116 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3832862443 | Aug 28 07:42:07 PM UTC 24 | Aug 28 07:46:14 PM UTC 24 | 15952437171 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2514347348 | Aug 28 07:44:18 PM UTC 24 | Aug 28 07:46:17 PM UTC 24 | 310333823 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.2014989251 | Aug 28 07:43:28 PM UTC 24 | Aug 28 07:46:19 PM UTC 24 | 21674205266 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.1194285375 | Aug 28 07:43:03 PM UTC 24 | Aug 28 07:46:28 PM UTC 24 | 7742652519 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2415117141 | Aug 28 07:45:13 PM UTC 24 | Aug 28 07:46:41 PM UTC 24 | 18306282269 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.3616499094 | Aug 28 07:44:31 PM UTC 24 | Aug 28 07:46:45 PM UTC 24 | 16218190891 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3704267100 | Aug 28 07:43:54 PM UTC 24 | Aug 28 07:46:47 PM UTC 24 | 510995379 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.1308365656 | Aug 28 07:42:46 PM UTC 24 | Aug 28 07:46:49 PM UTC 24 | 32540373894 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1816779841 | Aug 28 07:45:09 PM UTC 24 | Aug 28 07:46:56 PM UTC 24 | 1047494350 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3591065000 | Aug 28 07:42:10 PM UTC 24 | Aug 28 07:47:09 PM UTC 24 | 9795781936 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1672538863 | Aug 28 07:40:05 PM UTC 24 | Aug 28 07:47:20 PM UTC 24 | 68646046098 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.2948160140 | Aug 28 07:38:33 PM UTC 24 | Aug 28 07:47:22 PM UTC 24 | 4452611251 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3464949207 | Aug 28 07:37:34 PM UTC 24 | Aug 28 07:47:28 PM UTC 24 | 4229833134 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2902247635 | Aug 28 07:36:43 PM UTC 24 | Aug 28 07:47:28 PM UTC 24 | 131076269345 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.445685129 | Aug 28 07:42:37 PM UTC 24 | Aug 28 07:47:36 PM UTC 24 | 2284571787 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.1493056779 | Aug 28 07:43:48 PM UTC 24 | Aug 28 07:47:37 PM UTC 24 | 5309859497 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.950758268 | Aug 28 07:45:31 PM UTC 24 | Aug 28 07:47:42 PM UTC 24 | 1296036715 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2486393168 | Aug 28 07:43:18 PM UTC 24 | Aug 28 07:47:43 PM UTC 24 | 806133879 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.966679519 | Aug 28 07:43:54 PM UTC 24 | Aug 28 07:47:54 PM UTC 24 | 642304258 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3586170847 | Aug 28 07:44:58 PM UTC 24 | Aug 28 07:47:54 PM UTC 24 | 20279773894 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3652796619 | Aug 28 07:44:39 PM UTC 24 | Aug 28 07:48:27 PM UTC 24 | 10782919976 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.3647194616 | Aug 28 07:44:56 PM UTC 24 | Aug 28 07:48:32 PM UTC 24 | 51215932157 ps | ||
| T882 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1959040031 | Aug 28 07:44:44 PM UTC 24 | Aug 28 07:48:38 PM UTC 24 | 837766201 ps | ||
| T883 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.1482243949 | Aug 28 07:44:05 PM UTC 24 | Aug 28 07:48:58 PM UTC 24 | 38666295964 ps | ||
| T884 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.784939252 | Aug 28 07:45:13 PM UTC 24 | Aug 28 07:49:00 PM UTC 24 | 145497879358 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.122817620 | Aug 28 07:44:31 PM UTC 24 | Aug 28 07:49:13 PM UTC 24 | 29153462437 ps | ||
| T885 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.4186584159 | Aug 28 07:44:43 PM UTC 24 | Aug 28 07:49:16 PM UTC 24 | 14986571992 ps | ||
| T886 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.2071603784 | Aug 28 07:41:10 PM UTC 24 | Aug 28 07:49:17 PM UTC 24 | 3077587871 ps | ||
| T887 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.2049122392 | Aug 28 07:45:28 PM UTC 24 | Aug 28 07:49:32 PM UTC 24 | 5721617808 ps | ||
| T888 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.581278120 | Aug 28 07:45:31 PM UTC 24 | Aug 28 07:49:34 PM UTC 24 | 14756872696 ps | ||
| T889 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1391821749 | Aug 28 07:44:31 PM UTC 24 | Aug 28 07:49:39 PM UTC 24 | 35316629997 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2944575132 | Aug 28 07:41:21 PM UTC 24 | Aug 28 07:50:29 PM UTC 24 | 141553862489 ps | ||
| T890 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1667587165 | Aug 28 07:42:23 PM UTC 24 | Aug 28 07:51:05 PM UTC 24 | 42779375417 ps | ||
| T891 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2246248237 | Aug 28 07:38:45 PM UTC 24 | Aug 28 07:51:18 PM UTC 24 | 97940459558 ps | ||
| T892 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2271192110 | Aug 28 07:41:55 PM UTC 24 | Aug 28 07:52:14 PM UTC 24 | 149111255392 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1117247753 | Aug 28 07:43:04 PM UTC 24 | Aug 28 07:52:36 PM UTC 24 | 6763331271 ps | ||
| T893 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1761747744 | Aug 28 07:41:08 PM UTC 24 | Aug 28 07:53:08 PM UTC 24 | 2541775447 ps | ||
| T894 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1229650223 | Aug 28 07:42:07 PM UTC 24 | Aug 28 07:54:37 PM UTC 24 | 3799933318 ps | ||
| T895 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.138231150 | Aug 28 07:39:19 PM UTC 24 | Aug 28 07:55:10 PM UTC 24 | 207186872429 ps | ||
| T896 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3337997288 | Aug 28 07:44:58 PM UTC 24 | Aug 28 07:55:20 PM UTC 24 | 69011362793 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3596024156 | Aug 28 07:45:28 PM UTC 24 | Aug 28 07:55:52 PM UTC 24 | 4852526635 ps | ||
| T897 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2288371984 | Aug 28 07:45:09 PM UTC 24 | Aug 28 07:56:12 PM UTC 24 | 10789195598 ps | ||
| T898 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3716599345 | Aug 28 07:41:25 PM UTC 24 | Aug 28 07:56:38 PM UTC 24 | 101210405229 ps | ||
| T899 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1221917952 | Aug 28 07:43:33 PM UTC 24 | Aug 28 07:57:37 PM UTC 24 | 75385369789 ps | ||
| T900 | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3352242580 | Aug 28 07:45:16 PM UTC 24 | Aug 28 07:59:13 PM UTC 24 | 128109278174 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.1487106732 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 279638695 ps |
| CPU time | 11.65 seconds |
| Started | Aug 28 07:21:32 PM UTC 24 |
| Finished | Aug 28 07:21:45 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487106732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.1487106732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1821256539 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 202133795760 ps |
| CPU time | 621.49 seconds |
| Started | Aug 28 07:22:28 PM UTC 24 |
| Finished | Aug 28 07:32:58 PM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821256539 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.1821256539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.3303535586 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2733963810 ps |
| CPU time | 42.11 seconds |
| Started | Aug 28 07:21:47 PM UTC 24 |
| Finished | Aug 28 07:22:31 PM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303535586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.3303535586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/1.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.1246535138 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 236093723526 ps |
| CPU time | 793.48 seconds |
| Started | Aug 28 07:22:08 PM UTC 24 |
| Finished | Aug 28 07:35:33 PM UTC 24 |
| Peak memory | 219148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246535138 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.1246535138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.1216310921 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 1378018605 ps |
| CPU time | 177.89 seconds |
| Started | Aug 28 07:21:55 PM UTC 24 |
| Finished | Aug 28 07:24:57 PM UTC 24 |
| Peak memory | 220860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216310921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1216310921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/1.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.3840948519 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 101907328 ps |
| CPU time | 13.57 seconds |
| Started | Aug 28 07:21:25 PM UTC 24 |
| Finished | Aug 28 07:21:40 PM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840948519 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3840948519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/0.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1245054880 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 40204296018 ps |
| CPU time | 113.78 seconds |
| Started | Aug 28 07:21:49 PM UTC 24 |
| Finished | Aug 28 07:23:45 PM UTC 24 |
| Peak memory | 216312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245054880 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.1245054880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.666430547 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 905716378 ps |
| CPU time | 129.06 seconds |
| Started | Aug 28 07:23:41 PM UTC 24 |
| Finished | Aug 28 07:25:53 PM UTC 24 |
| Peak memory | 219140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666430547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.666430547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/5.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.1598999807 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 95065155971 ps |
| CPU time | 900.85 seconds |
| Started | Aug 28 07:25:39 PM UTC 24 |
| Finished | Aug 28 07:40:52 PM UTC 24 |
| Peak memory | 221260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598999807 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.1598999807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.1855480262 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 4107124733 ps |
| CPU time | 59.68 seconds |
| Started | Aug 28 07:21:26 PM UTC 24 |
| Finished | Aug 28 07:22:28 PM UTC 24 |
| Peak memory | 218944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855480262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.1855480262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/0.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.3850074032 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 4986767590 ps |
| CPU time | 58.27 seconds |
| Started | Aug 28 07:26:37 PM UTC 24 |
| Finished | Aug 28 07:27:37 PM UTC 24 |
| Peak memory | 218972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850074032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3850074032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/11.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.297589671 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 291752962 ps |
| CPU time | 98.37 seconds |
| Started | Aug 28 07:22:16 PM UTC 24 |
| Finished | Aug 28 07:23:56 PM UTC 24 |
| Peak memory | 221192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297589671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.297589671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.772703369 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 6762916265 ps |
| CPU time | 41.22 seconds |
| Started | Aug 28 07:21:22 PM UTC 24 |
| Finished | Aug 28 07:22:05 PM UTC 24 |
| Peak memory | 217200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772703369 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.772703369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/0.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.1266370867 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 788362451 ps |
| CPU time | 28.13 seconds |
| Started | Aug 28 07:21:37 PM UTC 24 |
| Finished | Aug 28 07:22:07 PM UTC 24 |
| Peak memory | 218872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266370867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1266370867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/0.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.3426922894 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 10282404511 ps |
| CPU time | 349.69 seconds |
| Started | Aug 28 07:30:07 PM UTC 24 |
| Finished | Aug 28 07:36:03 PM UTC 24 |
| Peak memory | 233652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426922894 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.3426922894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1862768120 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 11993882449 ps |
| CPU time | 524.81 seconds |
| Started | Aug 28 07:24:06 PM UTC 24 |
| Finished | Aug 28 07:33:00 PM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862768120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.1862768120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.3312307445 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 3193652642 ps |
| CPU time | 141.29 seconds |
| Started | Aug 28 07:23:37 PM UTC 24 |
| Finished | Aug 28 07:26:01 PM UTC 24 |
| Peak memory | 218940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312307445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3312307445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/5.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.682609670 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3216044964 ps |
| CPU time | 38.26 seconds |
| Started | Aug 28 07:22:10 PM UTC 24 |
| Finished | Aug 28 07:22:49 PM UTC 24 |
| Peak memory | 218640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682609670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.682609670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/2.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.2712043298 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 11370762148 ps |
| CPU time | 771.28 seconds |
| Started | Aug 28 07:25:48 PM UTC 24 |
| Finished | Aug 28 07:38:52 PM UTC 24 |
| Peak memory | 233592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712043298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.2712043298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.2190034843 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 796778507 ps |
| CPU time | 15.18 seconds |
| Started | Aug 28 07:21:29 PM UTC 24 |
| Finished | Aug 28 07:21:46 PM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190034843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2190034843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/0.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1117247753 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 6763331271 ps |
| CPU time | 563.99 seconds |
| Started | Aug 28 07:43:04 PM UTC 24 |
| Finished | Aug 28 07:52:36 PM UTC 24 |
| Peak memory | 221004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117247753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.1117247753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.3822128802 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 565557100 ps |
| CPU time | 315.7 seconds |
| Started | Aug 28 07:21:55 PM UTC 24 |
| Finished | Aug 28 07:27:16 PM UTC 24 |
| Peak memory | 220932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822128802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.3822128802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.2031824525 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1285794084 ps |
| CPU time | 228.61 seconds |
| Started | Aug 28 07:23:23 PM UTC 24 |
| Finished | Aug 28 07:27:15 PM UTC 24 |
| Peak memory | 222864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031824525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.2031824525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.762557672 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 264752279 ps |
| CPU time | 34.89 seconds |
| Started | Aug 28 07:27:42 PM UTC 24 |
| Finished | Aug 28 07:28:19 PM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762557672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.762557672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/13.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1565585708 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 62754732 ps |
| CPU time | 35.7 seconds |
| Started | Aug 28 07:27:51 PM UTC 24 |
| Finished | Aug 28 07:28:28 PM UTC 24 |
| Peak memory | 218824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565585708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.1565585708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.4160709179 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 867646694 ps |
| CPU time | 539.92 seconds |
| Started | Aug 28 07:33:53 PM UTC 24 |
| Finished | Aug 28 07:43:01 PM UTC 24 |
| Peak memory | 220872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160709179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.4160709179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.3655618746 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 10672258127 ps |
| CPU time | 317.9 seconds |
| Started | Aug 28 07:40:41 PM UTC 24 |
| Finished | Aug 28 07:46:05 PM UTC 24 |
| Peak memory | 220992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655618746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3655618746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/39.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.1078092388 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 106349287109 ps |
| CPU time | 399.87 seconds |
| Started | Aug 28 07:21:27 PM UTC 24 |
| Finished | Aug 28 07:28:13 PM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078092388 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.1078092388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.2225817194 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 51187621 ps |
| CPU time | 6.09 seconds |
| Started | Aug 28 07:21:29 PM UTC 24 |
| Finished | Aug 28 07:21:36 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225817194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2225817194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/0.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random.2884207397 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 249565623 ps |
| CPU time | 12.4 seconds |
| Started | Aug 28 07:21:22 PM UTC 24 |
| Finished | Aug 28 07:21:36 PM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884207397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.2884207397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/0.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.2337733228 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 40057700544 ps |
| CPU time | 328.71 seconds |
| Started | Aug 28 07:21:25 PM UTC 24 |
| Finished | Aug 28 07:26:59 PM UTC 24 |
| Peak memory | 219204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337733228 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2337733228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/0.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.387441932 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 39180405265 ps |
| CPU time | 286.96 seconds |
| Started | Aug 28 07:21:26 PM UTC 24 |
| Finished | Aug 28 07:26:18 PM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387441932 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.387441932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/0.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.3775603217 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 207078098 ps |
| CPU time | 5.85 seconds |
| Started | Aug 28 07:21:21 PM UTC 24 |
| Finished | Aug 28 07:21:28 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775603217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3775603217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/0.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.2951796393 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7206664503 ps |
| CPU time | 52.99 seconds |
| Started | Aug 28 07:21:22 PM UTC 24 |
| Finished | Aug 28 07:22:17 PM UTC 24 |
| Peak memory | 217132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951796393 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2951796393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.1451528521 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 21728215 ps |
| CPU time | 2.72 seconds |
| Started | Aug 28 07:21:21 PM UTC 24 |
| Finished | Aug 28 07:21:24 PM UTC 24 |
| Peak memory | 216852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451528521 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1451528521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/0.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.4130783378 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1321378709 ps |
| CPU time | 88.65 seconds |
| Started | Aug 28 07:21:37 PM UTC 24 |
| Finished | Aug 28 07:23:08 PM UTC 24 |
| Peak memory | 218824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130783378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.4130783378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/0.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.565969711 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 2298050311 ps |
| CPU time | 218.5 seconds |
| Started | Aug 28 07:21:37 PM UTC 24 |
| Finished | Aug 28 07:25:20 PM UTC 24 |
| Peak memory | 220996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565969711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.565969711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.651455928 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 61743524 ps |
| CPU time | 32.92 seconds |
| Started | Aug 28 07:21:39 PM UTC 24 |
| Finished | Aug 28 07:22:13 PM UTC 24 |
| Peak memory | 218824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651455928 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.651455928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.573683762 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 403859439 ps |
| CPU time | 23.65 seconds |
| Started | Aug 28 07:21:32 PM UTC 24 |
| Finished | Aug 28 07:21:57 PM UTC 24 |
| Peak memory | 218812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573683762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.573683762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/0.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.3141137361 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 94638311 ps |
| CPU time | 9.64 seconds |
| Started | Aug 28 07:21:52 PM UTC 24 |
| Finished | Aug 28 07:22:02 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141137361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.3141137361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.2694696763 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 150588371 ps |
| CPU time | 10.32 seconds |
| Started | Aug 28 07:21:50 PM UTC 24 |
| Finished | Aug 28 07:22:02 PM UTC 24 |
| Peak memory | 217072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694696763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2694696763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/1.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random.1547160884 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 226681907 ps |
| CPU time | 27.82 seconds |
| Started | Aug 28 07:21:44 PM UTC 24 |
| Finished | Aug 28 07:22:14 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547160884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.1547160884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/1.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.3190701608 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 97479467041 ps |
| CPU time | 397.37 seconds |
| Started | Aug 28 07:21:45 PM UTC 24 |
| Finished | Aug 28 07:28:30 PM UTC 24 |
| Peak memory | 216864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190701608 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3190701608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/1.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2750871518 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 52752181842 ps |
| CPU time | 293.53 seconds |
| Started | Aug 28 07:21:47 PM UTC 24 |
| Finished | Aug 28 07:26:45 PM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750871518 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2750871518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/1.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.2144174777 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 25519755 ps |
| CPU time | 2.89 seconds |
| Started | Aug 28 07:21:44 PM UTC 24 |
| Finished | Aug 28 07:21:49 PM UTC 24 |
| Peak memory | 216756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144174777 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.2144174777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/1.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.910247890 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1196957655 ps |
| CPU time | 18.89 seconds |
| Started | Aug 28 07:21:49 PM UTC 24 |
| Finished | Aug 28 07:22:09 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910247890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.910247890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/1.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.143464363 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 207143603 ps |
| CPU time | 4.91 seconds |
| Started | Aug 28 07:21:40 PM UTC 24 |
| Finished | Aug 28 07:21:47 PM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143464363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.143464363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/1.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1434130855 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 21702802419 ps |
| CPU time | 64.23 seconds |
| Started | Aug 28 07:21:44 PM UTC 24 |
| Finished | Aug 28 07:22:51 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434130855 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1434130855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/1.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1542474607 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 3791423799 ps |
| CPU time | 48.25 seconds |
| Started | Aug 28 07:21:44 PM UTC 24 |
| Finished | Aug 28 07:22:34 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542474607 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1542474607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.2143410768 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 40351397 ps |
| CPU time | 3.47 seconds |
| Started | Aug 28 07:21:44 PM UTC 24 |
| Finished | Aug 28 07:21:49 PM UTC 24 |
| Peak memory | 216732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143410768 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.2143410768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/1.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.1874795841 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 4159007476 ps |
| CPU time | 84.84 seconds |
| Started | Aug 28 07:21:55 PM UTC 24 |
| Finished | Aug 28 07:23:22 PM UTC 24 |
| Peak memory | 219212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874795841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1874795841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/1.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.2926180163 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 5634536126 ps |
| CPU time | 446.72 seconds |
| Started | Aug 28 07:21:57 PM UTC 24 |
| Finished | Aug 28 07:29:31 PM UTC 24 |
| Peak memory | 233652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926180163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.2926180163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.2490434471 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 156312576 ps |
| CPU time | 17.42 seconds |
| Started | Aug 28 07:21:50 PM UTC 24 |
| Finished | Aug 28 07:22:09 PM UTC 24 |
| Peak memory | 217076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490434471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2490434471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/1.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.3794982315 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 905826308 ps |
| CPU time | 43.6 seconds |
| Started | Aug 28 07:26:03 PM UTC 24 |
| Finished | Aug 28 07:26:49 PM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794982315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3794982315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/10.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2941004283 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 50604070184 ps |
| CPU time | 444.22 seconds |
| Started | Aug 28 07:26:04 PM UTC 24 |
| Finished | Aug 28 07:33:35 PM UTC 24 |
| Peak memory | 219212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941004283 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.2941004283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2071830340 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 668083947 ps |
| CPU time | 27.34 seconds |
| Started | Aug 28 07:26:12 PM UTC 24 |
| Finished | Aug 28 07:26:41 PM UTC 24 |
| Peak memory | 216572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071830340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2071830340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.71076955 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 55163491 ps |
| CPU time | 3.71 seconds |
| Started | Aug 28 07:26:06 PM UTC 24 |
| Finished | Aug 28 07:26:11 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71076955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.71076955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/10.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random.1232909800 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 353810816 ps |
| CPU time | 15.68 seconds |
| Started | Aug 28 07:25:57 PM UTC 24 |
| Finished | Aug 28 07:26:14 PM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232909800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.1232909800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/10.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.3254139243 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 16536495078 ps |
| CPU time | 128.54 seconds |
| Started | Aug 28 07:25:58 PM UTC 24 |
| Finished | Aug 28 07:28:10 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254139243 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3254139243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/10.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3568864586 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 46395763823 ps |
| CPU time | 312.68 seconds |
| Started | Aug 28 07:26:02 PM UTC 24 |
| Finished | Aug 28 07:31:20 PM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568864586 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3568864586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/10.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.1388079558 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 304970087 ps |
| CPU time | 29.27 seconds |
| Started | Aug 28 07:25:57 PM UTC 24 |
| Finished | Aug 28 07:26:28 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388079558 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.1388079558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/10.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.1503710098 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 429506643 ps |
| CPU time | 23.84 seconds |
| Started | Aug 28 07:26:04 PM UTC 24 |
| Finished | Aug 28 07:26:29 PM UTC 24 |
| Peak memory | 217024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503710098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1503710098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/10.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.4140957607 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 26930687 ps |
| CPU time | 3.22 seconds |
| Started | Aug 28 07:25:52 PM UTC 24 |
| Finished | Aug 28 07:25:56 PM UTC 24 |
| Peak memory | 217072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140957607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.4140957607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/10.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3559001503 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 4617811840 ps |
| CPU time | 40.31 seconds |
| Started | Aug 28 07:25:54 PM UTC 24 |
| Finished | Aug 28 07:26:36 PM UTC 24 |
| Peak memory | 217140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559001503 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3559001503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/10.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.573841336 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 6970583599 ps |
| CPU time | 49.29 seconds |
| Started | Aug 28 07:25:55 PM UTC 24 |
| Finished | Aug 28 07:26:46 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573841336 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.573841336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.4042466268 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 41473114 ps |
| CPU time | 3.7 seconds |
| Started | Aug 28 07:25:52 PM UTC 24 |
| Finished | Aug 28 07:25:56 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042466268 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.4042466268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/10.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.3318392099 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 3225741749 ps |
| CPU time | 66.08 seconds |
| Started | Aug 28 07:26:13 PM UTC 24 |
| Finished | Aug 28 07:27:22 PM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318392099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3318392099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/10.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3015882758 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2844375442 ps |
| CPU time | 61.35 seconds |
| Started | Aug 28 07:26:17 PM UTC 24 |
| Finished | Aug 28 07:27:21 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015882758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3015882758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/10.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3462792557 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 1372280623 ps |
| CPU time | 270.21 seconds |
| Started | Aug 28 07:26:15 PM UTC 24 |
| Finished | Aug 28 07:30:50 PM UTC 24 |
| Peak memory | 223240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462792557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.3462792557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.665281027 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 925130361 ps |
| CPU time | 253.89 seconds |
| Started | Aug 28 07:26:19 PM UTC 24 |
| Finished | Aug 28 07:30:37 PM UTC 24 |
| Peak memory | 233528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665281027 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.665281027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.2224968721 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 563131388 ps |
| CPU time | 22.3 seconds |
| Started | Aug 28 07:26:12 PM UTC 24 |
| Finished | Aug 28 07:26:36 PM UTC 24 |
| Peak memory | 218552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224968721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2224968721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/10.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.2651280003 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 124802328627 ps |
| CPU time | 726.35 seconds |
| Started | Aug 28 07:26:40 PM UTC 24 |
| Finished | Aug 28 07:38:57 PM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651280003 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.2651280003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.3079713025 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 166225757 ps |
| CPU time | 11.6 seconds |
| Started | Aug 28 07:26:49 PM UTC 24 |
| Finished | Aug 28 07:27:02 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079713025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.3079713025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.3410395211 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 844511637 ps |
| CPU time | 11.58 seconds |
| Started | Aug 28 07:26:46 PM UTC 24 |
| Finished | Aug 28 07:26:59 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410395211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3410395211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/11.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random.1237771607 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 483699785 ps |
| CPU time | 19.32 seconds |
| Started | Aug 28 07:26:28 PM UTC 24 |
| Finished | Aug 28 07:26:48 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237771607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1237771607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/11.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.3212483906 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 21993461319 ps |
| CPU time | 128.03 seconds |
| Started | Aug 28 07:26:30 PM UTC 24 |
| Finished | Aug 28 07:28:41 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212483906 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3212483906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/11.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.978592693 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 8799806802 ps |
| CPU time | 68.51 seconds |
| Started | Aug 28 07:26:37 PM UTC 24 |
| Finished | Aug 28 07:27:48 PM UTC 24 |
| Peak memory | 216420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978592693 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.978592693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/11.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.993781026 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 433233902 ps |
| CPU time | 29.56 seconds |
| Started | Aug 28 07:26:29 PM UTC 24 |
| Finished | Aug 28 07:27:00 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993781026 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.993781026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/11.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.1720610952 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1064721853 ps |
| CPU time | 24.51 seconds |
| Started | Aug 28 07:26:42 PM UTC 24 |
| Finished | Aug 28 07:27:08 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720610952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1720610952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/11.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.552457562 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 39176982 ps |
| CPU time | 3.23 seconds |
| Started | Aug 28 07:26:22 PM UTC 24 |
| Finished | Aug 28 07:26:27 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552457562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.552457562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/11.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.1282082932 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 4295642122 ps |
| CPU time | 49.36 seconds |
| Started | Aug 28 07:26:26 PM UTC 24 |
| Finished | Aug 28 07:27:17 PM UTC 24 |
| Peak memory | 217140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282082932 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.1282082932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/11.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.1759544126 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 3740077133 ps |
| CPU time | 29.72 seconds |
| Started | Aug 28 07:26:28 PM UTC 24 |
| Finished | Aug 28 07:26:59 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759544126 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.1759544126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.1439932847 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 28396935 ps |
| CPU time | 3.26 seconds |
| Started | Aug 28 07:26:22 PM UTC 24 |
| Finished | Aug 28 07:26:27 PM UTC 24 |
| Peak memory | 217132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439932847 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.1439932847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/11.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.4126051820 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2143250792 ps |
| CPU time | 152.29 seconds |
| Started | Aug 28 07:26:50 PM UTC 24 |
| Finished | Aug 28 07:29:25 PM UTC 24 |
| Peak memory | 218876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126051820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.4126051820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/11.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1928758958 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 1034144972 ps |
| CPU time | 46.64 seconds |
| Started | Aug 28 07:26:56 PM UTC 24 |
| Finished | Aug 28 07:27:45 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928758958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1928758958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/11.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3620099783 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 137238274 ps |
| CPU time | 84.56 seconds |
| Started | Aug 28 07:26:56 PM UTC 24 |
| Finished | Aug 28 07:28:23 PM UTC 24 |
| Peak memory | 220936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620099783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.3620099783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.2107966527 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 5044230480 ps |
| CPU time | 275.26 seconds |
| Started | Aug 28 07:26:59 PM UTC 24 |
| Finished | Aug 28 07:31:39 PM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107966527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.2107966527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.2232392345 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 721929513 ps |
| CPU time | 25.34 seconds |
| Started | Aug 28 07:26:46 PM UTC 24 |
| Finished | Aug 28 07:27:13 PM UTC 24 |
| Peak memory | 217164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232392345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2232392345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/11.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.1414765079 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 259387686 ps |
| CPU time | 25.56 seconds |
| Started | Aug 28 07:27:10 PM UTC 24 |
| Finished | Aug 28 07:27:37 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414765079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1414765079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/12.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.4096491631 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 60422282220 ps |
| CPU time | 878.07 seconds |
| Started | Aug 28 07:27:14 PM UTC 24 |
| Finished | Aug 28 07:42:04 PM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096491631 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.4096491631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.4154519952 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 218650167 ps |
| CPU time | 13.39 seconds |
| Started | Aug 28 07:27:19 PM UTC 24 |
| Finished | Aug 28 07:27:34 PM UTC 24 |
| Peak memory | 216964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154519952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.4154519952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.2119794056 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 431108359 ps |
| CPU time | 11.38 seconds |
| Started | Aug 28 07:27:17 PM UTC 24 |
| Finished | Aug 28 07:27:30 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119794056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.2119794056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/12.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random.559864956 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 1293960685 ps |
| CPU time | 46.76 seconds |
| Started | Aug 28 07:27:06 PM UTC 24 |
| Finished | Aug 28 07:27:54 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559864956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.559864956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/12.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.1604107737 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 21041683720 ps |
| CPU time | 135.63 seconds |
| Started | Aug 28 07:27:06 PM UTC 24 |
| Finished | Aug 28 07:29:24 PM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604107737 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1604107737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/12.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3462423292 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 10916847406 ps |
| CPU time | 45.44 seconds |
| Started | Aug 28 07:27:08 PM UTC 24 |
| Finished | Aug 28 07:27:55 PM UTC 24 |
| Peak memory | 217216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462423292 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3462423292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/12.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.1436810827 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 194297868 ps |
| CPU time | 22.24 seconds |
| Started | Aug 28 07:27:06 PM UTC 24 |
| Finished | Aug 28 07:27:29 PM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436810827 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.1436810827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/12.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.247438580 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 487649984 ps |
| CPU time | 15.41 seconds |
| Started | Aug 28 07:27:17 PM UTC 24 |
| Finished | Aug 28 07:27:34 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247438580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.247438580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/12.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.2785949506 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 41375867 ps |
| CPU time | 3.65 seconds |
| Started | Aug 28 07:26:59 PM UTC 24 |
| Finished | Aug 28 07:27:04 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785949506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2785949506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/12.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.1920194986 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 7160237265 ps |
| CPU time | 37.23 seconds |
| Started | Aug 28 07:27:02 PM UTC 24 |
| Finished | Aug 28 07:27:40 PM UTC 24 |
| Peak memory | 216884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920194986 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1920194986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/12.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1014361411 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 4251248636 ps |
| CPU time | 43.4 seconds |
| Started | Aug 28 07:27:04 PM UTC 24 |
| Finished | Aug 28 07:27:49 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014361411 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1014361411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2710674129 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 32305009 ps |
| CPU time | 2.85 seconds |
| Started | Aug 28 07:27:02 PM UTC 24 |
| Finished | Aug 28 07:27:05 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710674129 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2710674129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/12.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.2471450204 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1122237349 ps |
| CPU time | 44.82 seconds |
| Started | Aug 28 07:27:21 PM UTC 24 |
| Finished | Aug 28 07:28:08 PM UTC 24 |
| Peak memory | 218872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471450204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2471450204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/12.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3058378760 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 490114072 ps |
| CPU time | 17.99 seconds |
| Started | Aug 28 07:27:24 PM UTC 24 |
| Finished | Aug 28 07:27:43 PM UTC 24 |
| Peak memory | 217024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058378760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3058378760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/12.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1410741601 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 4502959492 ps |
| CPU time | 295.39 seconds |
| Started | Aug 28 07:27:24 PM UTC 24 |
| Finished | Aug 28 07:32:24 PM UTC 24 |
| Peak memory | 221000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410741601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.1410741601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3323756003 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3030249879 ps |
| CPU time | 378.73 seconds |
| Started | Aug 28 07:27:26 PM UTC 24 |
| Finished | Aug 28 07:33:52 PM UTC 24 |
| Peak memory | 223324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323756003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.3323756003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.3976395139 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 88741129 ps |
| CPU time | 5.25 seconds |
| Started | Aug 28 07:27:17 PM UTC 24 |
| Finished | Aug 28 07:27:24 PM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976395139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3976395139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/12.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3428215499 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 148033549363 ps |
| CPU time | 927.81 seconds |
| Started | Aug 28 07:27:45 PM UTC 24 |
| Finished | Aug 28 07:43:24 PM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428215499 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.3428215499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.794682250 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 413087066 ps |
| CPU time | 20.61 seconds |
| Started | Aug 28 07:27:49 PM UTC 24 |
| Finished | Aug 28 07:28:11 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794682250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.794682250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.2221129832 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 248191065 ps |
| CPU time | 11.64 seconds |
| Started | Aug 28 07:27:47 PM UTC 24 |
| Finished | Aug 28 07:28:00 PM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221129832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2221129832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/13.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random.2755197107 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 875927819 ps |
| CPU time | 28.05 seconds |
| Started | Aug 28 07:27:36 PM UTC 24 |
| Finished | Aug 28 07:28:06 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755197107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.2755197107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/13.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.2923509046 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 3042925944 ps |
| CPU time | 21.08 seconds |
| Started | Aug 28 07:27:38 PM UTC 24 |
| Finished | Aug 28 07:28:01 PM UTC 24 |
| Peak memory | 216884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923509046 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2923509046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/13.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2078472133 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 105680594069 ps |
| CPU time | 419.4 seconds |
| Started | Aug 28 07:27:38 PM UTC 24 |
| Finished | Aug 28 07:34:45 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078472133 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2078472133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/13.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.2457290696 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 24075400 ps |
| CPU time | 3.08 seconds |
| Started | Aug 28 07:27:38 PM UTC 24 |
| Finished | Aug 28 07:27:43 PM UTC 24 |
| Peak memory | 216952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457290696 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.2457290696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/13.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.2247132276 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 3992987684 ps |
| CPU time | 26.98 seconds |
| Started | Aug 28 07:27:45 PM UTC 24 |
| Finished | Aug 28 07:28:13 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247132276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2247132276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/13.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.2397223488 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 77234337 ps |
| CPU time | 3.83 seconds |
| Started | Aug 28 07:27:30 PM UTC 24 |
| Finished | Aug 28 07:27:35 PM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397223488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2397223488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/13.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2438234062 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 27928002222 ps |
| CPU time | 66.27 seconds |
| Started | Aug 28 07:27:36 PM UTC 24 |
| Finished | Aug 28 07:28:45 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438234062 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2438234062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/13.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.1374896061 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 8273373688 ps |
| CPU time | 43.79 seconds |
| Started | Aug 28 07:27:36 PM UTC 24 |
| Finished | Aug 28 07:28:22 PM UTC 24 |
| Peak memory | 217008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374896061 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1374896061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.665590741 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 36490583 ps |
| CPU time | 3.61 seconds |
| Started | Aug 28 07:27:32 PM UTC 24 |
| Finished | Aug 28 07:27:37 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665590741 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.665590741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/13.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.3428546058 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 714468767 ps |
| CPU time | 55.93 seconds |
| Started | Aug 28 07:27:51 PM UTC 24 |
| Finished | Aug 28 07:28:49 PM UTC 24 |
| Peak memory | 219136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428546058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3428546058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/13.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.549473011 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 1162035966 ps |
| CPU time | 65.36 seconds |
| Started | Aug 28 07:27:55 PM UTC 24 |
| Finished | Aug 28 07:29:03 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549473011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.549473011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/13.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1052308033 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 97556925 ps |
| CPU time | 27.5 seconds |
| Started | Aug 28 07:27:57 PM UTC 24 |
| Finished | Aug 28 07:28:26 PM UTC 24 |
| Peak memory | 218816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052308033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.1052308033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.1853387625 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 961141837 ps |
| CPU time | 35.38 seconds |
| Started | Aug 28 07:27:49 PM UTC 24 |
| Finished | Aug 28 07:28:26 PM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853387625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1853387625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/13.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.3877416234 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 2832683615 ps |
| CPU time | 32.01 seconds |
| Started | Aug 28 07:28:09 PM UTC 24 |
| Finished | Aug 28 07:28:43 PM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877416234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.3877416234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/14.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1051357630 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 23777236758 ps |
| CPU time | 181.49 seconds |
| Started | Aug 28 07:28:11 PM UTC 24 |
| Finished | Aug 28 07:31:16 PM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051357630 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.1051357630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2110220463 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 48681563 ps |
| CPU time | 3.29 seconds |
| Started | Aug 28 07:28:16 PM UTC 24 |
| Finished | Aug 28 07:28:20 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110220463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2110220463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.471157907 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 1193453441 ps |
| CPU time | 34.67 seconds |
| Started | Aug 28 07:28:11 PM UTC 24 |
| Finished | Aug 28 07:28:48 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471157907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.471157907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/14.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random.845148374 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 109619776 ps |
| CPU time | 22.72 seconds |
| Started | Aug 28 07:28:06 PM UTC 24 |
| Finished | Aug 28 07:28:30 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845148374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.845148374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/14.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.3355133735 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 11798008847 ps |
| CPU time | 98.07 seconds |
| Started | Aug 28 07:28:08 PM UTC 24 |
| Finished | Aug 28 07:29:48 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355133735 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3355133735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/14.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3110598990 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 30981710008 ps |
| CPU time | 222.64 seconds |
| Started | Aug 28 07:28:09 PM UTC 24 |
| Finished | Aug 28 07:31:56 PM UTC 24 |
| Peak memory | 218584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110598990 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3110598990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/14.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.4137730687 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 224336432 ps |
| CPU time | 18.87 seconds |
| Started | Aug 28 07:28:08 PM UTC 24 |
| Finished | Aug 28 07:28:28 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137730687 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.4137730687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/14.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.2330099736 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 1398330401 ps |
| CPU time | 22.47 seconds |
| Started | Aug 28 07:28:11 PM UTC 24 |
| Finished | Aug 28 07:28:35 PM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330099736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2330099736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/14.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.182905110 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 64258791 ps |
| CPU time | 2.85 seconds |
| Started | Aug 28 07:28:02 PM UTC 24 |
| Finished | Aug 28 07:28:05 PM UTC 24 |
| Peak memory | 217068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182905110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.182905110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/14.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2237656762 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 6866385191 ps |
| CPU time | 37.5 seconds |
| Started | Aug 28 07:28:02 PM UTC 24 |
| Finished | Aug 28 07:28:40 PM UTC 24 |
| Peak memory | 217140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237656762 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2237656762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/14.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.4238515701 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 5096275955 ps |
| CPU time | 29.65 seconds |
| Started | Aug 28 07:28:04 PM UTC 24 |
| Finished | Aug 28 07:28:35 PM UTC 24 |
| Peak memory | 216868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238515701 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.4238515701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.1998477946 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 30406812 ps |
| CPU time | 3.49 seconds |
| Started | Aug 28 07:28:02 PM UTC 24 |
| Finished | Aug 28 07:28:06 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998477946 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.1998477946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/14.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.3268508294 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 11676497494 ps |
| CPU time | 222.54 seconds |
| Started | Aug 28 07:28:18 PM UTC 24 |
| Finished | Aug 28 07:32:04 PM UTC 24 |
| Peak memory | 223296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268508294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3268508294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/14.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.942677562 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 21804925088 ps |
| CPU time | 154.76 seconds |
| Started | Aug 28 07:28:22 PM UTC 24 |
| Finished | Aug 28 07:31:00 PM UTC 24 |
| Peak memory | 218940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942677562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.942677562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/14.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.4087719582 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 3316051966 ps |
| CPU time | 438.97 seconds |
| Started | Aug 28 07:28:20 PM UTC 24 |
| Finished | Aug 28 07:35:47 PM UTC 24 |
| Peak memory | 223672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087719582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.4087719582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.55500156 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 568920628 ps |
| CPU time | 273.82 seconds |
| Started | Aug 28 07:28:22 PM UTC 24 |
| Finished | Aug 28 07:33:01 PM UTC 24 |
| Peak memory | 233848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55500156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.55500156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.3636371125 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 712117747 ps |
| CPU time | 34.33 seconds |
| Started | Aug 28 07:28:14 PM UTC 24 |
| Finished | Aug 28 07:28:49 PM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636371125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3636371125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/14.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.2116825763 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2304984007 ps |
| CPU time | 84.64 seconds |
| Started | Aug 28 07:28:30 PM UTC 24 |
| Finished | Aug 28 07:29:57 PM UTC 24 |
| Peak memory | 219036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116825763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2116825763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/15.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.323188963 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 32168127611 ps |
| CPU time | 382.42 seconds |
| Started | Aug 28 07:28:30 PM UTC 24 |
| Finished | Aug 28 07:34:58 PM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323188963 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.323188963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2564740017 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 534374568 ps |
| CPU time | 7.91 seconds |
| Started | Aug 28 07:28:31 PM UTC 24 |
| Finished | Aug 28 07:28:40 PM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564740017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2564740017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.216338239 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 61180669 ps |
| CPU time | 7.67 seconds |
| Started | Aug 28 07:28:31 PM UTC 24 |
| Finished | Aug 28 07:28:40 PM UTC 24 |
| Peak memory | 216820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216338239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.216338239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/15.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random.1600507507 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 72999177 ps |
| CPU time | 3.75 seconds |
| Started | Aug 28 07:28:26 PM UTC 24 |
| Finished | Aug 28 07:28:31 PM UTC 24 |
| Peak memory | 216756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600507507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.1600507507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/15.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.865115935 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 10778587723 ps |
| CPU time | 82.1 seconds |
| Started | Aug 28 07:28:27 PM UTC 24 |
| Finished | Aug 28 07:29:51 PM UTC 24 |
| Peak memory | 217156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865115935 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.865115935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/15.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.847058610 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 20508290706 ps |
| CPU time | 178.33 seconds |
| Started | Aug 28 07:28:27 PM UTC 24 |
| Finished | Aug 28 07:31:29 PM UTC 24 |
| Peak memory | 218932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847058610 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.847058610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/15.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.3195083696 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 214981480 ps |
| CPU time | 27.79 seconds |
| Started | Aug 28 07:28:27 PM UTC 24 |
| Finished | Aug 28 07:28:56 PM UTC 24 |
| Peak memory | 217148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195083696 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3195083696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/15.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.2716077571 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1078158150 ps |
| CPU time | 30.63 seconds |
| Started | Aug 28 07:28:30 PM UTC 24 |
| Finished | Aug 28 07:29:02 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716077571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2716077571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/15.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.1315275731 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 330783519 ps |
| CPU time | 4.51 seconds |
| Started | Aug 28 07:28:24 PM UTC 24 |
| Finished | Aug 28 07:28:30 PM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315275731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1315275731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/15.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1468733213 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 5855674545 ps |
| CPU time | 36.93 seconds |
| Started | Aug 28 07:28:25 PM UTC 24 |
| Finished | Aug 28 07:29:03 PM UTC 24 |
| Peak memory | 217068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468733213 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1468733213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/15.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.555442835 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 4843768131 ps |
| CPU time | 42.5 seconds |
| Started | Aug 28 07:28:26 PM UTC 24 |
| Finished | Aug 28 07:29:10 PM UTC 24 |
| Peak memory | 216688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555442835 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.555442835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.1280200028 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 139084949 ps |
| CPU time | 3.37 seconds |
| Started | Aug 28 07:28:25 PM UTC 24 |
| Finished | Aug 28 07:28:29 PM UTC 24 |
| Peak memory | 216664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280200028 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1280200028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/15.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.3783601995 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 2631665379 ps |
| CPU time | 164.72 seconds |
| Started | Aug 28 07:28:32 PM UTC 24 |
| Finished | Aug 28 07:31:20 PM UTC 24 |
| Peak memory | 219204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783601995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3783601995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/15.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3801141163 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 253725678 ps |
| CPU time | 11.45 seconds |
| Started | Aug 28 07:28:36 PM UTC 24 |
| Finished | Aug 28 07:28:49 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801141163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3801141163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/15.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.1302471466 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 9821631613 ps |
| CPU time | 749.08 seconds |
| Started | Aug 28 07:28:35 PM UTC 24 |
| Finished | Aug 28 07:41:15 PM UTC 24 |
| Peak memory | 223304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302471466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.1302471466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2612053147 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 502722689 ps |
| CPU time | 185.74 seconds |
| Started | Aug 28 07:28:40 PM UTC 24 |
| Finished | Aug 28 07:31:50 PM UTC 24 |
| Peak memory | 222916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612053147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.2612053147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.3526159887 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 137487071 ps |
| CPU time | 12.78 seconds |
| Started | Aug 28 07:28:31 PM UTC 24 |
| Finished | Aug 28 07:28:45 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526159887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3526159887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/15.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.585367364 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 144691001 ps |
| CPU time | 20.01 seconds |
| Started | Aug 28 07:28:48 PM UTC 24 |
| Finished | Aug 28 07:29:09 PM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585367364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.585367364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/16.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.708384583 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 10274436400 ps |
| CPU time | 104.83 seconds |
| Started | Aug 28 07:28:49 PM UTC 24 |
| Finished | Aug 28 07:30:36 PM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708384583 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.708384583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1867208407 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 1067702527 ps |
| CPU time | 34.5 seconds |
| Started | Aug 28 07:28:57 PM UTC 24 |
| Finished | Aug 28 07:29:34 PM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867208407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1867208407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.2363852042 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 1589937965 ps |
| CPU time | 36.04 seconds |
| Started | Aug 28 07:28:50 PM UTC 24 |
| Finished | Aug 28 07:29:28 PM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363852042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2363852042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/16.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random.3377509983 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 156161663 ps |
| CPU time | 21.46 seconds |
| Started | Aug 28 07:28:45 PM UTC 24 |
| Finished | Aug 28 07:29:08 PM UTC 24 |
| Peak memory | 217084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377509983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.3377509983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/16.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.3190493126 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 39045131112 ps |
| CPU time | 220.74 seconds |
| Started | Aug 28 07:28:46 PM UTC 24 |
| Finished | Aug 28 07:32:31 PM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190493126 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3190493126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/16.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.3953409681 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 6047249999 ps |
| CPU time | 40.07 seconds |
| Started | Aug 28 07:28:48 PM UTC 24 |
| Finished | Aug 28 07:29:29 PM UTC 24 |
| Peak memory | 216820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953409681 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3953409681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/16.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.3812341063 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 176873097 ps |
| CPU time | 24.06 seconds |
| Started | Aug 28 07:28:46 PM UTC 24 |
| Finished | Aug 28 07:29:12 PM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812341063 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3812341063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/16.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.3842102568 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1715648763 ps |
| CPU time | 37.61 seconds |
| Started | Aug 28 07:28:50 PM UTC 24 |
| Finished | Aug 28 07:29:30 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842102568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3842102568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/16.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.1646387017 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 125847516 ps |
| CPU time | 4.18 seconds |
| Started | Aug 28 07:28:42 PM UTC 24 |
| Finished | Aug 28 07:28:47 PM UTC 24 |
| Peak memory | 216820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646387017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1646387017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/16.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2613742775 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 9113212702 ps |
| CPU time | 44.45 seconds |
| Started | Aug 28 07:28:42 PM UTC 24 |
| Finished | Aug 28 07:29:28 PM UTC 24 |
| Peak memory | 217204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613742775 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2613742775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/16.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.526742342 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 10891831827 ps |
| CPU time | 69.09 seconds |
| Started | Aug 28 07:28:43 PM UTC 24 |
| Finished | Aug 28 07:29:54 PM UTC 24 |
| Peak memory | 217136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526742342 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.526742342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.886757393 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 31953412 ps |
| CPU time | 3.41 seconds |
| Started | Aug 28 07:28:42 PM UTC 24 |
| Finished | Aug 28 07:28:46 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886757393 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.886757393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/16.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.980169209 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 2650545351 ps |
| CPU time | 174.37 seconds |
| Started | Aug 28 07:29:02 PM UTC 24 |
| Finished | Aug 28 07:32:01 PM UTC 24 |
| Peak memory | 220992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980169209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.980169209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/16.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.182989890 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1291000744 ps |
| CPU time | 42.25 seconds |
| Started | Aug 28 07:29:04 PM UTC 24 |
| Finished | Aug 28 07:29:48 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182989890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.182989890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/16.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3315857075 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 900980311 ps |
| CPU time | 546.46 seconds |
| Started | Aug 28 07:29:04 PM UTC 24 |
| Finished | Aug 28 07:38:20 PM UTC 24 |
| Peak memory | 222984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315857075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.3315857075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.3473505758 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 166913645 ps |
| CPU time | 37.51 seconds |
| Started | Aug 28 07:29:09 PM UTC 24 |
| Finished | Aug 28 07:29:48 PM UTC 24 |
| Peak memory | 219144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473505758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.3473505758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.4092614374 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 168846653 ps |
| CPU time | 18.1 seconds |
| Started | Aug 28 07:28:50 PM UTC 24 |
| Finished | Aug 28 07:29:10 PM UTC 24 |
| Peak memory | 217100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092614374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.4092614374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/16.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.20905596 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 166364330 ps |
| CPU time | 32.91 seconds |
| Started | Aug 28 07:29:25 PM UTC 24 |
| Finished | Aug 28 07:29:59 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20905596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.20905596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/17.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.2008877945 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 36037988735 ps |
| CPU time | 428.02 seconds |
| Started | Aug 28 07:29:26 PM UTC 24 |
| Finished | Aug 28 07:36:41 PM UTC 24 |
| Peak memory | 218956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008877945 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.2008877945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.2060233669 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 72948229 ps |
| CPU time | 15.75 seconds |
| Started | Aug 28 07:29:31 PM UTC 24 |
| Finished | Aug 28 07:29:48 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060233669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.2060233669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.1744257044 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 217000006 ps |
| CPU time | 9.72 seconds |
| Started | Aug 28 07:29:29 PM UTC 24 |
| Finished | Aug 28 07:29:40 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744257044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1744257044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/17.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random.1059938368 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 983447449 ps |
| CPU time | 32.99 seconds |
| Started | Aug 28 07:29:14 PM UTC 24 |
| Finished | Aug 28 07:29:48 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059938368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.1059938368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/17.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.4104223958 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 17806405080 ps |
| CPU time | 103.63 seconds |
| Started | Aug 28 07:29:17 PM UTC 24 |
| Finished | Aug 28 07:31:03 PM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104223958 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.4104223958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/17.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.371383877 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 63355001759 ps |
| CPU time | 324.66 seconds |
| Started | Aug 28 07:29:25 PM UTC 24 |
| Finished | Aug 28 07:34:55 PM UTC 24 |
| Peak memory | 219200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371383877 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.371383877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/17.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.165035450 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 114801457 ps |
| CPU time | 20.3 seconds |
| Started | Aug 28 07:29:16 PM UTC 24 |
| Finished | Aug 28 07:29:37 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165035450 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.165035450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/17.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.4082394721 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1908789047 ps |
| CPU time | 15.05 seconds |
| Started | Aug 28 07:29:28 PM UTC 24 |
| Finished | Aug 28 07:29:45 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082394721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.4082394721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/17.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.2043615060 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 62990749 ps |
| CPU time | 3.24 seconds |
| Started | Aug 28 07:29:10 PM UTC 24 |
| Finished | Aug 28 07:29:14 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043615060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2043615060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/17.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.843097799 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 5414323535 ps |
| CPU time | 58.03 seconds |
| Started | Aug 28 07:29:11 PM UTC 24 |
| Finished | Aug 28 07:30:11 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843097799 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.843097799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/17.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.1127829745 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 3257651788 ps |
| CPU time | 39.85 seconds |
| Started | Aug 28 07:29:13 PM UTC 24 |
| Finished | Aug 28 07:29:55 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127829745 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1127829745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3875235217 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 83123886 ps |
| CPU time | 3.53 seconds |
| Started | Aug 28 07:29:11 PM UTC 24 |
| Finished | Aug 28 07:29:16 PM UTC 24 |
| Peak memory | 216352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875235217 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3875235217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/17.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.2611085606 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 1618072600 ps |
| CPU time | 126.22 seconds |
| Started | Aug 28 07:29:33 PM UTC 24 |
| Finished | Aug 28 07:31:43 PM UTC 24 |
| Peak memory | 220924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611085606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2611085606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/17.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3012869906 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 20392064045 ps |
| CPU time | 301.48 seconds |
| Started | Aug 28 07:29:39 PM UTC 24 |
| Finished | Aug 28 07:34:46 PM UTC 24 |
| Peak memory | 223044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012869906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3012869906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/17.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.4237087807 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 530963857 ps |
| CPU time | 280.81 seconds |
| Started | Aug 28 07:29:34 PM UTC 24 |
| Finished | Aug 28 07:34:20 PM UTC 24 |
| Peak memory | 220936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237087807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.4237087807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.984861330 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 6984127135 ps |
| CPU time | 202.39 seconds |
| Started | Aug 28 07:29:41 PM UTC 24 |
| Finished | Aug 28 07:33:07 PM UTC 24 |
| Peak memory | 223248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984861330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.984861330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.1763360345 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 144140019 ps |
| CPU time | 23.96 seconds |
| Started | Aug 28 07:29:31 PM UTC 24 |
| Finished | Aug 28 07:29:56 PM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763360345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1763360345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/17.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.279078522 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 173643887 ps |
| CPU time | 6.87 seconds |
| Started | Aug 28 07:29:53 PM UTC 24 |
| Finished | Aug 28 07:30:01 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279078522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.279078522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/18.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.246378494 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 115752390933 ps |
| CPU time | 551.03 seconds |
| Started | Aug 28 07:29:54 PM UTC 24 |
| Finished | Aug 28 07:39:13 PM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246378494 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.246378494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.1854000777 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 132572763 ps |
| CPU time | 19.2 seconds |
| Started | Aug 28 07:29:57 PM UTC 24 |
| Finished | Aug 28 07:30:18 PM UTC 24 |
| Peak memory | 216736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854000777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.1854000777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.1740287691 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 1012986318 ps |
| CPU time | 32.12 seconds |
| Started | Aug 28 07:29:56 PM UTC 24 |
| Finished | Aug 28 07:30:30 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740287691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1740287691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/18.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random.3970025016 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 159513531 ps |
| CPU time | 30.35 seconds |
| Started | Aug 28 07:29:49 PM UTC 24 |
| Finished | Aug 28 07:30:21 PM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970025016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.3970025016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/18.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.2239446799 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 25721529132 ps |
| CPU time | 196.57 seconds |
| Started | Aug 28 07:29:50 PM UTC 24 |
| Finished | Aug 28 07:33:10 PM UTC 24 |
| Peak memory | 218876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239446799 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2239446799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/18.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.2150996302 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 13557518632 ps |
| CPU time | 151.31 seconds |
| Started | Aug 28 07:29:51 PM UTC 24 |
| Finished | Aug 28 07:32:25 PM UTC 24 |
| Peak memory | 218876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150996302 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2150996302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/18.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.122728508 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 194288657 ps |
| CPU time | 19.46 seconds |
| Started | Aug 28 07:29:49 PM UTC 24 |
| Finished | Aug 28 07:30:10 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122728508 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.122728508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/18.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.2467412027 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 6776404661 ps |
| CPU time | 53.53 seconds |
| Started | Aug 28 07:29:55 PM UTC 24 |
| Finished | Aug 28 07:30:50 PM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467412027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2467412027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/18.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.2074107579 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 28196374 ps |
| CPU time | 2.64 seconds |
| Started | Aug 28 07:29:46 PM UTC 24 |
| Finished | Aug 28 07:29:49 PM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074107579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2074107579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/18.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.3428963747 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 15184359770 ps |
| CPU time | 64.9 seconds |
| Started | Aug 28 07:29:49 PM UTC 24 |
| Finished | Aug 28 07:30:56 PM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428963747 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3428963747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/18.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.877910413 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 4299206172 ps |
| CPU time | 51.22 seconds |
| Started | Aug 28 07:29:49 PM UTC 24 |
| Finished | Aug 28 07:30:42 PM UTC 24 |
| Peak memory | 216348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877910413 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.877910413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1147108126 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 24262431 ps |
| CPU time | 2.22 seconds |
| Started | Aug 28 07:29:49 PM UTC 24 |
| Finished | Aug 28 07:29:53 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147108126 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1147108126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/18.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.336943774 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4988483408 ps |
| CPU time | 129.84 seconds |
| Started | Aug 28 07:30:01 PM UTC 24 |
| Finished | Aug 28 07:32:14 PM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336943774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.336943774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/18.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1245258008 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 3984565671 ps |
| CPU time | 86.96 seconds |
| Started | Aug 28 07:30:02 PM UTC 24 |
| Finished | Aug 28 07:31:32 PM UTC 24 |
| Peak memory | 216964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245258008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1245258008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/18.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.1528934069 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 37540546 ps |
| CPU time | 47.98 seconds |
| Started | Aug 28 07:30:02 PM UTC 24 |
| Finished | Aug 28 07:30:52 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528934069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.1528934069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.166909715 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 175028658 ps |
| CPU time | 8.2 seconds |
| Started | Aug 28 07:29:57 PM UTC 24 |
| Finished | Aug 28 07:30:07 PM UTC 24 |
| Peak memory | 216368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166909715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.166909715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/18.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.1634975747 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2056865932 ps |
| CPU time | 69.11 seconds |
| Started | Aug 28 07:30:38 PM UTC 24 |
| Finished | Aug 28 07:31:49 PM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634975747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1634975747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/19.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.363991472 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 57132701014 ps |
| CPU time | 400.56 seconds |
| Started | Aug 28 07:30:38 PM UTC 24 |
| Finished | Aug 28 07:37:24 PM UTC 24 |
| Peak memory | 218956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363991472 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.363991472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.3872741177 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1735150108 ps |
| CPU time | 36.85 seconds |
| Started | Aug 28 07:30:51 PM UTC 24 |
| Finished | Aug 28 07:31:29 PM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872741177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3872741177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.821326011 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 290127618 ps |
| CPU time | 30.09 seconds |
| Started | Aug 28 07:30:47 PM UTC 24 |
| Finished | Aug 28 07:31:18 PM UTC 24 |
| Peak memory | 216564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821326011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.821326011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/19.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random.374828591 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 7457429184 ps |
| CPU time | 40.86 seconds |
| Started | Aug 28 07:30:19 PM UTC 24 |
| Finished | Aug 28 07:31:01 PM UTC 24 |
| Peak memory | 218936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374828591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.374828591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/19.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.1224666853 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 53910185323 ps |
| CPU time | 400.18 seconds |
| Started | Aug 28 07:30:22 PM UTC 24 |
| Finished | Aug 28 07:37:08 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224666853 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1224666853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/19.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.2460129647 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 10291625496 ps |
| CPU time | 141.37 seconds |
| Started | Aug 28 07:30:30 PM UTC 24 |
| Finished | Aug 28 07:32:55 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460129647 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2460129647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/19.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.2655126532 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 313142836 ps |
| CPU time | 23.21 seconds |
| Started | Aug 28 07:30:20 PM UTC 24 |
| Finished | Aug 28 07:30:45 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655126532 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.2655126532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/19.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.1644084890 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 699285303 ps |
| CPU time | 20.11 seconds |
| Started | Aug 28 07:30:43 PM UTC 24 |
| Finished | Aug 28 07:31:04 PM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644084890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.1644084890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/19.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.2401292213 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 181989483 ps |
| CPU time | 5.85 seconds |
| Started | Aug 28 07:30:11 PM UTC 24 |
| Finished | Aug 28 07:30:19 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401292213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2401292213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/19.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.1520632466 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 7660400431 ps |
| CPU time | 42.38 seconds |
| Started | Aug 28 07:30:16 PM UTC 24 |
| Finished | Aug 28 07:31:01 PM UTC 24 |
| Peak memory | 216884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520632466 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1520632466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/19.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.101393814 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 14034134681 ps |
| CPU time | 52.18 seconds |
| Started | Aug 28 07:30:18 PM UTC 24 |
| Finished | Aug 28 07:31:12 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101393814 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.101393814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3148676214 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 43974552 ps |
| CPU time | 3.58 seconds |
| Started | Aug 28 07:30:12 PM UTC 24 |
| Finished | Aug 28 07:30:17 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148676214 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3148676214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/19.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.3215202253 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 6605223105 ps |
| CPU time | 205.47 seconds |
| Started | Aug 28 07:30:51 PM UTC 24 |
| Finished | Aug 28 07:34:20 PM UTC 24 |
| Peak memory | 221312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215202253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3215202253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/19.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.3924834274 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1231694816 ps |
| CPU time | 174.62 seconds |
| Started | Aug 28 07:30:57 PM UTC 24 |
| Finished | Aug 28 07:33:56 PM UTC 24 |
| Peak memory | 222980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924834274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3924834274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/19.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.4127178799 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 1623267750 ps |
| CPU time | 497.6 seconds |
| Started | Aug 28 07:30:53 PM UTC 24 |
| Finished | Aug 28 07:39:20 PM UTC 24 |
| Peak memory | 220936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127178799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.4127178799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.2009673403 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 4044719191 ps |
| CPU time | 228.19 seconds |
| Started | Aug 28 07:31:01 PM UTC 24 |
| Finished | Aug 28 07:34:54 PM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009673403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.2009673403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.4188112203 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 203006108 ps |
| CPU time | 21.71 seconds |
| Started | Aug 28 07:30:47 PM UTC 24 |
| Finished | Aug 28 07:31:10 PM UTC 24 |
| Peak memory | 219144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188112203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.4188112203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/19.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.1301776491 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 292160706 ps |
| CPU time | 58.61 seconds |
| Started | Aug 28 07:22:07 PM UTC 24 |
| Finished | Aug 28 07:23:08 PM UTC 24 |
| Peak memory | 218816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301776491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.1301776491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/2.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.1704298293 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 143885924 ps |
| CPU time | 3.8 seconds |
| Started | Aug 28 07:22:14 PM UTC 24 |
| Finished | Aug 28 07:22:18 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704298293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.1704298293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.607218103 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 132420517 ps |
| CPU time | 16.14 seconds |
| Started | Aug 28 07:22:10 PM UTC 24 |
| Finished | Aug 28 07:22:27 PM UTC 24 |
| Peak memory | 216792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607218103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.607218103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/2.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random.966978298 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 298484354 ps |
| CPU time | 8.95 seconds |
| Started | Aug 28 07:22:03 PM UTC 24 |
| Finished | Aug 28 07:22:13 PM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966978298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.966978298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/2.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.1189169470 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 39801952759 ps |
| CPU time | 133.52 seconds |
| Started | Aug 28 07:22:07 PM UTC 24 |
| Finished | Aug 28 07:24:23 PM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189169470 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1189169470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/2.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.150536201 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 90453337531 ps |
| CPU time | 363.76 seconds |
| Started | Aug 28 07:22:07 PM UTC 24 |
| Finished | Aug 28 07:28:17 PM UTC 24 |
| Peak memory | 218736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150536201 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.150536201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/2.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.2290256521 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 49584865 ps |
| CPU time | 12.75 seconds |
| Started | Aug 28 07:22:05 PM UTC 24 |
| Finished | Aug 28 07:22:19 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290256521 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.2290256521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/2.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.1305757407 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3441152466 ps |
| CPU time | 34.73 seconds |
| Started | Aug 28 07:22:08 PM UTC 24 |
| Finished | Aug 28 07:22:45 PM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305757407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1305757407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/2.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.2954671663 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 48583766 ps |
| CPU time | 3.76 seconds |
| Started | Aug 28 07:22:00 PM UTC 24 |
| Finished | Aug 28 07:22:05 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954671663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2954671663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/2.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.1355887659 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 6303696431 ps |
| CPU time | 51.05 seconds |
| Started | Aug 28 07:22:03 PM UTC 24 |
| Finished | Aug 28 07:22:56 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355887659 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1355887659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/2.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.1042823859 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3552011941 ps |
| CPU time | 36.11 seconds |
| Started | Aug 28 07:22:03 PM UTC 24 |
| Finished | Aug 28 07:22:41 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042823859 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1042823859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.524852601 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 53582909 ps |
| CPU time | 3.47 seconds |
| Started | Aug 28 07:22:02 PM UTC 24 |
| Finished | Aug 28 07:22:06 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524852601 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.524852601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/2.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.664275653 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 2301046450 ps |
| CPU time | 95.18 seconds |
| Started | Aug 28 07:22:16 PM UTC 24 |
| Finished | Aug 28 07:23:53 PM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664275653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.664275653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/2.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3385133783 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 586258240 ps |
| CPU time | 92.15 seconds |
| Started | Aug 28 07:22:16 PM UTC 24 |
| Finished | Aug 28 07:23:50 PM UTC 24 |
| Peak memory | 217100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385133783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3385133783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/2.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.1268731054 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 6561787677 ps |
| CPU time | 221.41 seconds |
| Started | Aug 28 07:22:18 PM UTC 24 |
| Finished | Aug 28 07:26:03 PM UTC 24 |
| Peak memory | 233648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268731054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.1268731054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.117986121 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1396870747 ps |
| CPU time | 53.6 seconds |
| Started | Aug 28 07:31:11 PM UTC 24 |
| Finished | Aug 28 07:32:06 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117986121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.117986121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/20.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3307139525 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 42974936600 ps |
| CPU time | 322.1 seconds |
| Started | Aug 28 07:31:13 PM UTC 24 |
| Finished | Aug 28 07:36:40 PM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307139525 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.3307139525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.3266532380 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 965894512 ps |
| CPU time | 31.16 seconds |
| Started | Aug 28 07:31:21 PM UTC 24 |
| Finished | Aug 28 07:31:54 PM UTC 24 |
| Peak memory | 217156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266532380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.3266532380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.3241430555 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 214101543 ps |
| CPU time | 11.02 seconds |
| Started | Aug 28 07:31:19 PM UTC 24 |
| Finished | Aug 28 07:31:31 PM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241430555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3241430555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/20.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random.848329066 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 207391617 ps |
| CPU time | 29.81 seconds |
| Started | Aug 28 07:31:05 PM UTC 24 |
| Finished | Aug 28 07:31:36 PM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848329066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.848329066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/20.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.1112766771 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 24112802674 ps |
| CPU time | 236.67 seconds |
| Started | Aug 28 07:31:06 PM UTC 24 |
| Finished | Aug 28 07:35:07 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112766771 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1112766771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/20.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3665054564 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 29846465689 ps |
| CPU time | 308.92 seconds |
| Started | Aug 28 07:31:08 PM UTC 24 |
| Finished | Aug 28 07:36:21 PM UTC 24 |
| Peak memory | 219268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665054564 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3665054564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/20.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.1425873070 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 836983596 ps |
| CPU time | 27.47 seconds |
| Started | Aug 28 07:31:05 PM UTC 24 |
| Finished | Aug 28 07:31:34 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425873070 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.1425873070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/20.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.2693917420 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 334966827 ps |
| CPU time | 9.97 seconds |
| Started | Aug 28 07:31:17 PM UTC 24 |
| Finished | Aug 28 07:31:28 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693917420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2693917420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/20.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.2909804030 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 175881534 ps |
| CPU time | 4.33 seconds |
| Started | Aug 28 07:31:02 PM UTC 24 |
| Finished | Aug 28 07:31:07 PM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909804030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2909804030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/20.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3213851193 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 5892217210 ps |
| CPU time | 46.13 seconds |
| Started | Aug 28 07:31:04 PM UTC 24 |
| Finished | Aug 28 07:31:52 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213851193 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3213851193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/20.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.1407948183 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 5361215702 ps |
| CPU time | 24.11 seconds |
| Started | Aug 28 07:31:04 PM UTC 24 |
| Finished | Aug 28 07:31:30 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407948183 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1407948183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1174948011 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 31625401 ps |
| CPU time | 3.22 seconds |
| Started | Aug 28 07:31:02 PM UTC 24 |
| Finished | Aug 28 07:31:06 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174948011 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1174948011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/20.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.3872550681 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 2162884493 ps |
| CPU time | 239.54 seconds |
| Started | Aug 28 07:31:28 PM UTC 24 |
| Finished | Aug 28 07:35:33 PM UTC 24 |
| Peak memory | 220924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872550681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3872550681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/20.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.3842265686 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 669980575 ps |
| CPU time | 114.49 seconds |
| Started | Aug 28 07:31:31 PM UTC 24 |
| Finished | Aug 28 07:33:29 PM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842265686 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3842265686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/20.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.985739670 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 162398680 ps |
| CPU time | 74.37 seconds |
| Started | Aug 28 07:31:30 PM UTC 24 |
| Finished | Aug 28 07:32:47 PM UTC 24 |
| Peak memory | 218828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985739670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.985739670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1632670080 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 95059114 ps |
| CPU time | 38.09 seconds |
| Started | Aug 28 07:31:31 PM UTC 24 |
| Finished | Aug 28 07:32:11 PM UTC 24 |
| Peak memory | 218804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632670080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.1632670080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.3052874640 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 428896297 ps |
| CPU time | 16.52 seconds |
| Started | Aug 28 07:31:21 PM UTC 24 |
| Finished | Aug 28 07:31:39 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052874640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3052874640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/20.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.935219094 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 239065598 ps |
| CPU time | 12.77 seconds |
| Started | Aug 28 07:31:41 PM UTC 24 |
| Finished | Aug 28 07:31:55 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935219094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.935219094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/21.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3202659366 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 6226559327 ps |
| CPU time | 71.3 seconds |
| Started | Aug 28 07:31:44 PM UTC 24 |
| Finished | Aug 28 07:32:57 PM UTC 24 |
| Peak memory | 217160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202659366 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.3202659366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.883069645 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 279391971 ps |
| CPU time | 11.27 seconds |
| Started | Aug 28 07:31:54 PM UTC 24 |
| Finished | Aug 28 07:32:07 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883069645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.883069645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.1643900050 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 42939422 ps |
| CPU time | 4.34 seconds |
| Started | Aug 28 07:31:51 PM UTC 24 |
| Finished | Aug 28 07:31:57 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643900050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1643900050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/21.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random.932951690 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 766585269 ps |
| CPU time | 20.58 seconds |
| Started | Aug 28 07:31:38 PM UTC 24 |
| Finished | Aug 28 07:32:00 PM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932951690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.932951690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/21.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.2059867507 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 61309403164 ps |
| CPU time | 352.08 seconds |
| Started | Aug 28 07:31:40 PM UTC 24 |
| Finished | Aug 28 07:37:38 PM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059867507 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2059867507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/21.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.3948609184 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 35387585902 ps |
| CPU time | 263.54 seconds |
| Started | Aug 28 07:31:40 PM UTC 24 |
| Finished | Aug 28 07:36:08 PM UTC 24 |
| Peak memory | 219268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948609184 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3948609184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/21.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.3434305932 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 188700537 ps |
| CPU time | 15.24 seconds |
| Started | Aug 28 07:31:39 PM UTC 24 |
| Finished | Aug 28 07:31:55 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434305932 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.3434305932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/21.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.4285074700 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 156673573 ps |
| CPU time | 16.97 seconds |
| Started | Aug 28 07:31:51 PM UTC 24 |
| Finished | Aug 28 07:32:09 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285074700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.4285074700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/21.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.434066001 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 32182130 ps |
| CPU time | 3.42 seconds |
| Started | Aug 28 07:31:32 PM UTC 24 |
| Finished | Aug 28 07:31:37 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434066001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.434066001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/21.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2452961693 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 5372708891 ps |
| CPU time | 38.1 seconds |
| Started | Aug 28 07:31:35 PM UTC 24 |
| Finished | Aug 28 07:32:15 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452961693 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2452961693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/21.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.3216476985 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2882591770 ps |
| CPU time | 27.06 seconds |
| Started | Aug 28 07:31:38 PM UTC 24 |
| Finished | Aug 28 07:32:06 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216476985 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3216476985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.1422437182 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 54252020 ps |
| CPU time | 3.06 seconds |
| Started | Aug 28 07:31:33 PM UTC 24 |
| Finished | Aug 28 07:31:38 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422437182 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.1422437182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/21.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.1095938101 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 2892361963 ps |
| CPU time | 99.12 seconds |
| Started | Aug 28 07:31:57 PM UTC 24 |
| Finished | Aug 28 07:33:38 PM UTC 24 |
| Peak memory | 219264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095938101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1095938101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/21.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.712729395 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 285567943 ps |
| CPU time | 34.98 seconds |
| Started | Aug 28 07:31:57 PM UTC 24 |
| Finished | Aug 28 07:32:33 PM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712729395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.712729395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/21.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.889055776 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 720329788 ps |
| CPU time | 343.24 seconds |
| Started | Aug 28 07:31:57 PM UTC 24 |
| Finished | Aug 28 07:37:46 PM UTC 24 |
| Peak memory | 221260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889055776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.889055776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1290154850 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 391408454 ps |
| CPU time | 127.83 seconds |
| Started | Aug 28 07:31:58 PM UTC 24 |
| Finished | Aug 28 07:34:09 PM UTC 24 |
| Peak memory | 222976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290154850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.1290154850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.4141353820 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 549454424 ps |
| CPU time | 29.23 seconds |
| Started | Aug 28 07:31:52 PM UTC 24 |
| Finished | Aug 28 07:32:23 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141353820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.4141353820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/21.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.2992512504 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 674959822 ps |
| CPU time | 25.9 seconds |
| Started | Aug 28 07:32:10 PM UTC 24 |
| Finished | Aug 28 07:32:38 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992512504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.2992512504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/22.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.1695855932 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 41965573226 ps |
| CPU time | 506.08 seconds |
| Started | Aug 28 07:32:12 PM UTC 24 |
| Finished | Aug 28 07:40:46 PM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695855932 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.1695855932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3187664905 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 234585928 ps |
| CPU time | 5.74 seconds |
| Started | Aug 28 07:32:24 PM UTC 24 |
| Finished | Aug 28 07:32:31 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187664905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.3187664905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.2742024465 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1158120927 ps |
| CPU time | 36.48 seconds |
| Started | Aug 28 07:32:15 PM UTC 24 |
| Finished | Aug 28 07:32:53 PM UTC 24 |
| Peak memory | 217084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742024465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2742024465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/22.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random.2886208824 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 422491782 ps |
| CPU time | 21.58 seconds |
| Started | Aug 28 07:32:07 PM UTC 24 |
| Finished | Aug 28 07:32:30 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886208824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.2886208824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/22.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.3265818671 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 39579034823 ps |
| CPU time | 453.3 seconds |
| Started | Aug 28 07:32:08 PM UTC 24 |
| Finished | Aug 28 07:39:48 PM UTC 24 |
| Peak memory | 216012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265818671 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3265818671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/22.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.349403270 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 4942436531 ps |
| CPU time | 39.69 seconds |
| Started | Aug 28 07:32:08 PM UTC 24 |
| Finished | Aug 28 07:32:49 PM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349403270 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.349403270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/22.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.3423022494 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 178650436 ps |
| CPU time | 26.07 seconds |
| Started | Aug 28 07:32:08 PM UTC 24 |
| Finished | Aug 28 07:32:36 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423022494 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.3423022494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/22.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.2019465888 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 772169186 ps |
| CPU time | 16.25 seconds |
| Started | Aug 28 07:32:14 PM UTC 24 |
| Finished | Aug 28 07:32:31 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019465888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2019465888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/22.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.4111597785 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 262146459 ps |
| CPU time | 4.84 seconds |
| Started | Aug 28 07:32:00 PM UTC 24 |
| Finished | Aug 28 07:32:06 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111597785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.4111597785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/22.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.2296854836 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 5744004445 ps |
| CPU time | 63.63 seconds |
| Started | Aug 28 07:32:05 PM UTC 24 |
| Finished | Aug 28 07:33:11 PM UTC 24 |
| Peak memory | 216884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296854836 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2296854836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/22.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.2753869703 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 7016896658 ps |
| CPU time | 30.12 seconds |
| Started | Aug 28 07:32:07 PM UTC 24 |
| Finished | Aug 28 07:32:38 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753869703 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2753869703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1159869797 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 29958951 ps |
| CPU time | 3.22 seconds |
| Started | Aug 28 07:32:01 PM UTC 24 |
| Finished | Aug 28 07:32:06 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159869797 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1159869797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/22.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.2290572755 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 1338359249 ps |
| CPU time | 173.46 seconds |
| Started | Aug 28 07:32:25 PM UTC 24 |
| Finished | Aug 28 07:35:23 PM UTC 24 |
| Peak memory | 218812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290572755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2290572755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/22.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3897128239 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 6958645447 ps |
| CPU time | 121.09 seconds |
| Started | Aug 28 07:32:31 PM UTC 24 |
| Finished | Aug 28 07:34:35 PM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897128239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3897128239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/22.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.4060736157 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 241652878 ps |
| CPU time | 82.13 seconds |
| Started | Aug 28 07:32:25 PM UTC 24 |
| Finished | Aug 28 07:33:50 PM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060736157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.4060736157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2576975926 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 32486828 ps |
| CPU time | 41.29 seconds |
| Started | Aug 28 07:32:32 PM UTC 24 |
| Finished | Aug 28 07:33:15 PM UTC 24 |
| Peak memory | 218816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576975926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.2576975926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.2181575783 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 529045973 ps |
| CPU time | 26.86 seconds |
| Started | Aug 28 07:32:16 PM UTC 24 |
| Finished | Aug 28 07:32:44 PM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181575783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2181575783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/22.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.698680119 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 424270095 ps |
| CPU time | 34.55 seconds |
| Started | Aug 28 07:32:39 PM UTC 24 |
| Finished | Aug 28 07:33:15 PM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698680119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.698680119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/23.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.2348094639 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 65085673343 ps |
| CPU time | 691.98 seconds |
| Started | Aug 28 07:32:45 PM UTC 24 |
| Finished | Aug 28 07:44:27 PM UTC 24 |
| Peak memory | 220936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348094639 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.2348094639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1858808567 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 63060550 ps |
| CPU time | 9.77 seconds |
| Started | Aug 28 07:32:54 PM UTC 24 |
| Finished | Aug 28 07:33:05 PM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858808567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1858808567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.1280781220 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 251684456 ps |
| CPU time | 5 seconds |
| Started | Aug 28 07:32:48 PM UTC 24 |
| Finished | Aug 28 07:32:54 PM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280781220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1280781220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/23.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random.1967510912 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1795918234 ps |
| CPU time | 31.09 seconds |
| Started | Aug 28 07:32:36 PM UTC 24 |
| Finished | Aug 28 07:33:09 PM UTC 24 |
| Peak memory | 217084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967510912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1967510912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/23.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.3009928529 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 11534304942 ps |
| CPU time | 131.43 seconds |
| Started | Aug 28 07:32:38 PM UTC 24 |
| Finished | Aug 28 07:34:52 PM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009928529 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3009928529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/23.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.2760581739 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 19182093759 ps |
| CPU time | 248.64 seconds |
| Started | Aug 28 07:32:39 PM UTC 24 |
| Finished | Aug 28 07:36:52 PM UTC 24 |
| Peak memory | 218876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760581739 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2760581739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/23.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.3594605767 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 48128235 ps |
| CPU time | 7.85 seconds |
| Started | Aug 28 07:32:38 PM UTC 24 |
| Finished | Aug 28 07:32:47 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594605767 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.3594605767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/23.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.3948973874 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 712925133 ps |
| CPU time | 15.27 seconds |
| Started | Aug 28 07:32:47 PM UTC 24 |
| Finished | Aug 28 07:33:04 PM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948973874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3948973874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/23.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.2660686245 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 64674594 ps |
| CPU time | 3.21 seconds |
| Started | Aug 28 07:32:32 PM UTC 24 |
| Finished | Aug 28 07:32:36 PM UTC 24 |
| Peak memory | 216616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660686245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2660686245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/23.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.126250125 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 18470530802 ps |
| CPU time | 54.38 seconds |
| Started | Aug 28 07:32:34 PM UTC 24 |
| Finished | Aug 28 07:33:30 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126250125 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.126250125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/23.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.1247771772 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 9392489677 ps |
| CPU time | 46.13 seconds |
| Started | Aug 28 07:32:35 PM UTC 24 |
| Finished | Aug 28 07:33:23 PM UTC 24 |
| Peak memory | 217072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247771772 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1247771772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.4167303950 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 47048359 ps |
| CPU time | 3.42 seconds |
| Started | Aug 28 07:32:32 PM UTC 24 |
| Finished | Aug 28 07:32:36 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167303950 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.4167303950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/23.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.2896373355 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 1109146313 ps |
| CPU time | 56.56 seconds |
| Started | Aug 28 07:32:56 PM UTC 24 |
| Finished | Aug 28 07:33:54 PM UTC 24 |
| Peak memory | 220612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896373355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2896373355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/23.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.3609984977 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 3083942460 ps |
| CPU time | 35.43 seconds |
| Started | Aug 28 07:32:56 PM UTC 24 |
| Finished | Aug 28 07:33:33 PM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609984977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3609984977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/23.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.406371264 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 235106379 ps |
| CPU time | 138.4 seconds |
| Started | Aug 28 07:32:56 PM UTC 24 |
| Finished | Aug 28 07:35:18 PM UTC 24 |
| Peak memory | 220648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406371264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.406371264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.622246330 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 7187891 ps |
| CPU time | 7.19 seconds |
| Started | Aug 28 07:32:58 PM UTC 24 |
| Finished | Aug 28 07:33:06 PM UTC 24 |
| Peak memory | 217076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622246330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.622246330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.1487086701 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 45371924 ps |
| CPU time | 2.86 seconds |
| Started | Aug 28 07:32:50 PM UTC 24 |
| Finished | Aug 28 07:32:55 PM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487086701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1487086701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/23.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.1166872293 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1840030820 ps |
| CPU time | 59.87 seconds |
| Started | Aug 28 07:33:09 PM UTC 24 |
| Finished | Aug 28 07:34:11 PM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166872293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1166872293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/24.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3901382901 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 91129444142 ps |
| CPU time | 676.68 seconds |
| Started | Aug 28 07:33:10 PM UTC 24 |
| Finished | Aug 28 07:44:37 PM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901382901 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.3901382901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.1593162610 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 107983490 ps |
| CPU time | 9.08 seconds |
| Started | Aug 28 07:33:16 PM UTC 24 |
| Finished | Aug 28 07:33:26 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593162610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.1593162610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.1756249459 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 1666980074 ps |
| CPU time | 36.28 seconds |
| Started | Aug 28 07:33:12 PM UTC 24 |
| Finished | Aug 28 07:33:50 PM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756249459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1756249459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/24.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random.3807200090 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 130819042 ps |
| CPU time | 22.58 seconds |
| Started | Aug 28 07:33:05 PM UTC 24 |
| Finished | Aug 28 07:33:30 PM UTC 24 |
| Peak memory | 217148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807200090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.3807200090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/24.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.705957680 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 8358727872 ps |
| CPU time | 43.57 seconds |
| Started | Aug 28 07:33:08 PM UTC 24 |
| Finished | Aug 28 07:33:53 PM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705957680 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.705957680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/24.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2434617320 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 40566292661 ps |
| CPU time | 389.02 seconds |
| Started | Aug 28 07:33:08 PM UTC 24 |
| Finished | Aug 28 07:39:43 PM UTC 24 |
| Peak memory | 218944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434617320 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2434617320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/24.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.2165395121 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 215141118 ps |
| CPU time | 33.88 seconds |
| Started | Aug 28 07:33:06 PM UTC 24 |
| Finished | Aug 28 07:33:42 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165395121 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.2165395121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/24.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.1941212913 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 715069872 ps |
| CPU time | 18.56 seconds |
| Started | Aug 28 07:33:11 PM UTC 24 |
| Finished | Aug 28 07:33:31 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941212913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1941212913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/24.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.2116798882 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 171056859 ps |
| CPU time | 4.94 seconds |
| Started | Aug 28 07:32:59 PM UTC 24 |
| Finished | Aug 28 07:33:05 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116798882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2116798882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/24.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3824269750 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 12089287438 ps |
| CPU time | 45.06 seconds |
| Started | Aug 28 07:33:02 PM UTC 24 |
| Finished | Aug 28 07:33:49 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824269750 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3824269750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/24.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.542531634 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 6642518262 ps |
| CPU time | 41.9 seconds |
| Started | Aug 28 07:33:05 PM UTC 24 |
| Finished | Aug 28 07:33:49 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542531634 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.542531634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1579293877 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 34294315 ps |
| CPU time | 3.21 seconds |
| Started | Aug 28 07:33:02 PM UTC 24 |
| Finished | Aug 28 07:33:06 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579293877 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1579293877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/24.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.570916164 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 475923716 ps |
| CPU time | 82.84 seconds |
| Started | Aug 28 07:33:21 PM UTC 24 |
| Finished | Aug 28 07:34:46 PM UTC 24 |
| Peak memory | 220868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570916164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.570916164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/24.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.1258401898 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 5786763142 ps |
| CPU time | 129.98 seconds |
| Started | Aug 28 07:33:25 PM UTC 24 |
| Finished | Aug 28 07:35:38 PM UTC 24 |
| Peak memory | 221252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258401898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1258401898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/24.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.3239234200 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 917240276 ps |
| CPU time | 154.33 seconds |
| Started | Aug 28 07:33:24 PM UTC 24 |
| Finished | Aug 28 07:36:01 PM UTC 24 |
| Peak memory | 220932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239234200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.3239234200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.4053317598 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 639125620 ps |
| CPU time | 218.88 seconds |
| Started | Aug 28 07:33:26 PM UTC 24 |
| Finished | Aug 28 07:37:10 PM UTC 24 |
| Peak memory | 223532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053317598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.4053317598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.53639490 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 13187085 ps |
| CPU time | 3.01 seconds |
| Started | Aug 28 07:33:16 PM UTC 24 |
| Finished | Aug 28 07:33:20 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53639490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.53639490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/24.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.3895272716 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 958178969 ps |
| CPU time | 25.59 seconds |
| Started | Aug 28 07:33:39 PM UTC 24 |
| Finished | Aug 28 07:34:06 PM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895272716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3895272716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/25.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.1461404356 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 3838891909 ps |
| CPU time | 37.68 seconds |
| Started | Aug 28 07:33:43 PM UTC 24 |
| Finished | Aug 28 07:34:22 PM UTC 24 |
| Peak memory | 217164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461404356 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.1461404356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.711146098 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 473809234 ps |
| CPU time | 15.22 seconds |
| Started | Aug 28 07:33:51 PM UTC 24 |
| Finished | Aug 28 07:34:07 PM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711146098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.711146098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.3463124942 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 843868523 ps |
| CPU time | 30.1 seconds |
| Started | Aug 28 07:33:49 PM UTC 24 |
| Finished | Aug 28 07:34:21 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463124942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3463124942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/25.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random.2009553171 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 101111103 ps |
| CPU time | 6.17 seconds |
| Started | Aug 28 07:33:34 PM UTC 24 |
| Finished | Aug 28 07:33:42 PM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009553171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.2009553171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/25.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.736829386 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 89512107688 ps |
| CPU time | 274.04 seconds |
| Started | Aug 28 07:33:37 PM UTC 24 |
| Finished | Aug 28 07:38:15 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736829386 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.736829386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/25.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1907437153 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 21508332160 ps |
| CPU time | 251.39 seconds |
| Started | Aug 28 07:33:38 PM UTC 24 |
| Finished | Aug 28 07:37:53 PM UTC 24 |
| Peak memory | 219200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907437153 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1907437153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/25.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.1398425694 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 643992154 ps |
| CPU time | 31.75 seconds |
| Started | Aug 28 07:33:36 PM UTC 24 |
| Finished | Aug 28 07:34:10 PM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398425694 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.1398425694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/25.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.2891919167 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 237453402 ps |
| CPU time | 24.69 seconds |
| Started | Aug 28 07:33:43 PM UTC 24 |
| Finished | Aug 28 07:34:09 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891919167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2891919167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/25.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.1519588846 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 250778917 ps |
| CPU time | 5.48 seconds |
| Started | Aug 28 07:33:30 PM UTC 24 |
| Finished | Aug 28 07:33:36 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519588846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1519588846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/25.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.1145547540 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 4444271834 ps |
| CPU time | 32.29 seconds |
| Started | Aug 28 07:33:31 PM UTC 24 |
| Finished | Aug 28 07:34:05 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145547540 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1145547540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/25.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.533964770 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 7831370966 ps |
| CPU time | 36.34 seconds |
| Started | Aug 28 07:33:32 PM UTC 24 |
| Finished | Aug 28 07:34:10 PM UTC 24 |
| Peak memory | 217136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533964770 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.533964770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2652509808 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 45866578 ps |
| CPU time | 3.2 seconds |
| Started | Aug 28 07:33:31 PM UTC 24 |
| Finished | Aug 28 07:33:35 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652509808 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2652509808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/25.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.4176730619 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 10838694071 ps |
| CPU time | 242.21 seconds |
| Started | Aug 28 07:33:52 PM UTC 24 |
| Finished | Aug 28 07:37:58 PM UTC 24 |
| Peak memory | 222968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176730619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.4176730619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/25.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.3734590112 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 4660712322 ps |
| CPU time | 145.88 seconds |
| Started | Aug 28 07:33:54 PM UTC 24 |
| Finished | Aug 28 07:36:23 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734590112 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3734590112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/25.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3729280737 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 3349034989 ps |
| CPU time | 452.24 seconds |
| Started | Aug 28 07:33:55 PM UTC 24 |
| Finished | Aug 28 07:41:35 PM UTC 24 |
| Peak memory | 233648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729280737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.3729280737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.4192030737 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 521932090 ps |
| CPU time | 21.95 seconds |
| Started | Aug 28 07:33:50 PM UTC 24 |
| Finished | Aug 28 07:34:14 PM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192030737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.4192030737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/25.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.2764726965 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 113098327 ps |
| CPU time | 10.65 seconds |
| Started | Aug 28 07:34:11 PM UTC 24 |
| Finished | Aug 28 07:34:23 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764726965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.2764726965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/26.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1258032505 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 69814381528 ps |
| CPU time | 585.38 seconds |
| Started | Aug 28 07:34:11 PM UTC 24 |
| Finished | Aug 28 07:44:05 PM UTC 24 |
| Peak memory | 219276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258032505 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.1258032505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.701630852 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 52766183 ps |
| CPU time | 5.45 seconds |
| Started | Aug 28 07:34:21 PM UTC 24 |
| Finished | Aug 28 07:34:28 PM UTC 24 |
| Peak memory | 217148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701630852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.701630852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.1866390143 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 371357920 ps |
| CPU time | 6.2 seconds |
| Started | Aug 28 07:34:14 PM UTC 24 |
| Finished | Aug 28 07:34:22 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866390143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1866390143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/26.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random.2155074616 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 537210946 ps |
| CPU time | 25.53 seconds |
| Started | Aug 28 07:34:08 PM UTC 24 |
| Finished | Aug 28 07:34:35 PM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155074616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.2155074616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/26.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.2992637829 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 33063463699 ps |
| CPU time | 112.05 seconds |
| Started | Aug 28 07:34:11 PM UTC 24 |
| Finished | Aug 28 07:36:06 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992637829 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.2992637829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/26.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.2850094401 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 33749748722 ps |
| CPU time | 231.81 seconds |
| Started | Aug 28 07:34:11 PM UTC 24 |
| Finished | Aug 28 07:38:07 PM UTC 24 |
| Peak memory | 217220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850094401 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2850094401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/26.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.158935313 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 105782230 ps |
| CPU time | 4.55 seconds |
| Started | Aug 28 07:34:09 PM UTC 24 |
| Finished | Aug 28 07:34:15 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158935313 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.158935313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/26.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.2699267174 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 1339520482 ps |
| CPU time | 42.3 seconds |
| Started | Aug 28 07:34:12 PM UTC 24 |
| Finished | Aug 28 07:34:56 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699267174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2699267174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/26.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.2226762419 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 145828472 ps |
| CPU time | 4.72 seconds |
| Started | Aug 28 07:33:57 PM UTC 24 |
| Finished | Aug 28 07:34:02 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226762419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2226762419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/26.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2985330475 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 7355478657 ps |
| CPU time | 30.04 seconds |
| Started | Aug 28 07:34:06 PM UTC 24 |
| Finished | Aug 28 07:34:37 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985330475 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2985330475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/26.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.1458472500 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 3534462624 ps |
| CPU time | 44.14 seconds |
| Started | Aug 28 07:34:07 PM UTC 24 |
| Finished | Aug 28 07:34:53 PM UTC 24 |
| Peak memory | 217200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458472500 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1458472500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1343697988 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 28998365 ps |
| CPU time | 3.15 seconds |
| Started | Aug 28 07:34:04 PM UTC 24 |
| Finished | Aug 28 07:34:08 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343697988 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1343697988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/26.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.491889857 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 5774759128 ps |
| CPU time | 143.55 seconds |
| Started | Aug 28 07:34:21 PM UTC 24 |
| Finished | Aug 28 07:36:48 PM UTC 24 |
| Peak memory | 220996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491889857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.491889857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/26.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1818643899 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 3446439967 ps |
| CPU time | 136.41 seconds |
| Started | Aug 28 07:34:24 PM UTC 24 |
| Finished | Aug 28 07:36:43 PM UTC 24 |
| Peak memory | 219268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818643899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1818643899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/26.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1641559146 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4094877842 ps |
| CPU time | 266.25 seconds |
| Started | Aug 28 07:34:22 PM UTC 24 |
| Finished | Aug 28 07:38:53 PM UTC 24 |
| Peak memory | 222984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641559146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.1641559146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.3961807860 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 80951616 ps |
| CPU time | 46.46 seconds |
| Started | Aug 28 07:34:24 PM UTC 24 |
| Finished | Aug 28 07:35:12 PM UTC 24 |
| Peak memory | 218816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961807860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.3961807860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.1202122325 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 54107893 ps |
| CPU time | 3.85 seconds |
| Started | Aug 28 07:34:16 PM UTC 24 |
| Finished | Aug 28 07:34:22 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202122325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1202122325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/26.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.3245280633 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 349112257 ps |
| CPU time | 44.72 seconds |
| Started | Aug 28 07:34:46 PM UTC 24 |
| Finished | Aug 28 07:35:32 PM UTC 24 |
| Peak memory | 219140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245280633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.3245280633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/27.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.1240958660 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 61042290863 ps |
| CPU time | 226.18 seconds |
| Started | Aug 28 07:34:47 PM UTC 24 |
| Finished | Aug 28 07:38:37 PM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240958660 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.1240958660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.1429674067 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 37983523 ps |
| CPU time | 5.49 seconds |
| Started | Aug 28 07:34:54 PM UTC 24 |
| Finished | Aug 28 07:35:00 PM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429674067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.1429674067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.877117353 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 488047199 ps |
| CPU time | 15.46 seconds |
| Started | Aug 28 07:34:49 PM UTC 24 |
| Finished | Aug 28 07:35:06 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877117353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.877117353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/27.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random.506061088 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 591161115 ps |
| CPU time | 33.36 seconds |
| Started | Aug 28 07:34:31 PM UTC 24 |
| Finished | Aug 28 07:35:07 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506061088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.506061088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/27.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.4216260372 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 57229917707 ps |
| CPU time | 143.02 seconds |
| Started | Aug 28 07:34:36 PM UTC 24 |
| Finished | Aug 28 07:37:02 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216260372 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.4216260372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/27.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.695781590 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 2020959128 ps |
| CPU time | 23.83 seconds |
| Started | Aug 28 07:34:38 PM UTC 24 |
| Finished | Aug 28 07:35:03 PM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695781590 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.695781590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/27.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.2715589147 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 95934592 ps |
| CPU time | 11.17 seconds |
| Started | Aug 28 07:34:35 PM UTC 24 |
| Finished | Aug 28 07:34:48 PM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715589147 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2715589147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/27.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.754772429 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 3199929481 ps |
| CPU time | 40.21 seconds |
| Started | Aug 28 07:34:47 PM UTC 24 |
| Finished | Aug 28 07:35:29 PM UTC 24 |
| Peak memory | 217020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754772429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.754772429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/27.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.2878244161 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 243403506 ps |
| CPU time | 5.05 seconds |
| Started | Aug 28 07:34:24 PM UTC 24 |
| Finished | Aug 28 07:34:30 PM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878244161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2878244161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/27.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1445329245 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 8100786390 ps |
| CPU time | 42.29 seconds |
| Started | Aug 28 07:34:29 PM UTC 24 |
| Finished | Aug 28 07:35:13 PM UTC 24 |
| Peak memory | 217204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445329245 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1445329245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/27.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3420131873 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 3345592151 ps |
| CPU time | 40.91 seconds |
| Started | Aug 28 07:34:30 PM UTC 24 |
| Finished | Aug 28 07:35:13 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420131873 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3420131873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.408416964 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 56493747 ps |
| CPU time | 3.5 seconds |
| Started | Aug 28 07:34:25 PM UTC 24 |
| Finished | Aug 28 07:34:29 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408416964 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.408416964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/27.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.791626393 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1875710849 ps |
| CPU time | 75.65 seconds |
| Started | Aug 28 07:34:55 PM UTC 24 |
| Finished | Aug 28 07:36:13 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791626393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.791626393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/27.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.1545564932 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 1586127057 ps |
| CPU time | 62.87 seconds |
| Started | Aug 28 07:34:57 PM UTC 24 |
| Finished | Aug 28 07:36:02 PM UTC 24 |
| Peak memory | 219140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545564932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.1545564932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/27.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.1889407999 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 8850716237 ps |
| CPU time | 261.34 seconds |
| Started | Aug 28 07:34:56 PM UTC 24 |
| Finished | Aug 28 07:39:23 PM UTC 24 |
| Peak memory | 222984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889407999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.1889407999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.4078192732 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 10624718832 ps |
| CPU time | 289.73 seconds |
| Started | Aug 28 07:34:59 PM UTC 24 |
| Finished | Aug 28 07:39:55 PM UTC 24 |
| Peak memory | 223368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078192732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.4078192732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.882779774 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1578023193 ps |
| CPU time | 16.76 seconds |
| Started | Aug 28 07:34:52 PM UTC 24 |
| Finished | Aug 28 07:35:10 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882779774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.882779774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/27.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.4182325456 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 290405162 ps |
| CPU time | 10.83 seconds |
| Started | Aug 28 07:35:11 PM UTC 24 |
| Finished | Aug 28 07:35:23 PM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182325456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.4182325456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/28.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2324638329 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 44568499247 ps |
| CPU time | 391.19 seconds |
| Started | Aug 28 07:35:13 PM UTC 24 |
| Finished | Aug 28 07:41:50 PM UTC 24 |
| Peak memory | 219084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324638329 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.2324638329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.657103134 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 94328256 ps |
| CPU time | 10.5 seconds |
| Started | Aug 28 07:35:24 PM UTC 24 |
| Finished | Aug 28 07:35:36 PM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657103134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.657103134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.1166150565 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 223459729 ps |
| CPU time | 25.49 seconds |
| Started | Aug 28 07:35:14 PM UTC 24 |
| Finished | Aug 28 07:35:41 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166150565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1166150565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/28.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random.377186087 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 2200335695 ps |
| CPU time | 46.96 seconds |
| Started | Aug 28 07:35:07 PM UTC 24 |
| Finished | Aug 28 07:35:56 PM UTC 24 |
| Peak memory | 216956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377186087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.377186087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/28.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.1634329037 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 64728156332 ps |
| CPU time | 364.64 seconds |
| Started | Aug 28 07:35:08 PM UTC 24 |
| Finished | Aug 28 07:41:19 PM UTC 24 |
| Peak memory | 219196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634329037 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1634329037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/28.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.1053521271 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1062603194 ps |
| CPU time | 15.85 seconds |
| Started | Aug 28 07:35:09 PM UTC 24 |
| Finished | Aug 28 07:35:26 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053521271 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.1053521271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/28.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.2712214504 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 501891109 ps |
| CPU time | 24.82 seconds |
| Started | Aug 28 07:35:08 PM UTC 24 |
| Finished | Aug 28 07:35:34 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712214504 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2712214504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/28.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.2259664205 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 878147608 ps |
| CPU time | 31.75 seconds |
| Started | Aug 28 07:35:14 PM UTC 24 |
| Finished | Aug 28 07:35:47 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259664205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2259664205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/28.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.3993072885 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 127179028 ps |
| CPU time | 2.94 seconds |
| Started | Aug 28 07:35:01 PM UTC 24 |
| Finished | Aug 28 07:35:05 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993072885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3993072885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/28.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.101217024 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 8781577600 ps |
| CPU time | 54.11 seconds |
| Started | Aug 28 07:35:04 PM UTC 24 |
| Finished | Aug 28 07:36:00 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101217024 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.101217024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/28.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.842230498 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 4825458301 ps |
| CPU time | 44.04 seconds |
| Started | Aug 28 07:35:06 PM UTC 24 |
| Finished | Aug 28 07:35:51 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842230498 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.842230498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.716275450 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 40906634 ps |
| CPU time | 3.19 seconds |
| Started | Aug 28 07:35:04 PM UTC 24 |
| Finished | Aug 28 07:35:08 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716275450 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.716275450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/28.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.1529834397 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 1295352551 ps |
| CPU time | 64.38 seconds |
| Started | Aug 28 07:35:24 PM UTC 24 |
| Finished | Aug 28 07:36:31 PM UTC 24 |
| Peak memory | 218812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529834397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1529834397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/28.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.2470457671 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 9890767726 ps |
| CPU time | 157.23 seconds |
| Started | Aug 28 07:35:30 PM UTC 24 |
| Finished | Aug 28 07:38:10 PM UTC 24 |
| Peak memory | 220996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470457671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2470457671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/28.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.347786740 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 173792138 ps |
| CPU time | 152.81 seconds |
| Started | Aug 28 07:35:28 PM UTC 24 |
| Finished | Aug 28 07:38:03 PM UTC 24 |
| Peak memory | 220936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347786740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.347786740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1725372820 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 10636875 ps |
| CPU time | 9.17 seconds |
| Started | Aug 28 07:35:33 PM UTC 24 |
| Finished | Aug 28 07:35:43 PM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725372820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.1725372820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.482028364 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1301786028 ps |
| CPU time | 20.05 seconds |
| Started | Aug 28 07:35:18 PM UTC 24 |
| Finished | Aug 28 07:35:40 PM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482028364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.482028364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/28.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.4192420097 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 206763845 ps |
| CPU time | 20.29 seconds |
| Started | Aug 28 07:35:42 PM UTC 24 |
| Finished | Aug 28 07:36:04 PM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192420097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.4192420097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/29.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2326700149 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 27452734227 ps |
| CPU time | 134.36 seconds |
| Started | Aug 28 07:35:44 PM UTC 24 |
| Finished | Aug 28 07:38:01 PM UTC 24 |
| Peak memory | 217160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326700149 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.2326700149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.2351051028 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 5765812047 ps |
| CPU time | 37.38 seconds |
| Started | Aug 28 07:35:56 PM UTC 24 |
| Finished | Aug 28 07:36:35 PM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351051028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.2351051028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.571098388 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 109597524 ps |
| CPU time | 17.21 seconds |
| Started | Aug 28 07:35:48 PM UTC 24 |
| Finished | Aug 28 07:36:06 PM UTC 24 |
| Peak memory | 217024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571098388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.571098388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/29.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random.1147207476 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 285743418 ps |
| CPU time | 22.67 seconds |
| Started | Aug 28 07:35:40 PM UTC 24 |
| Finished | Aug 28 07:36:04 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147207476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.1147207476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/29.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.3635384569 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 103441744302 ps |
| CPU time | 308.92 seconds |
| Started | Aug 28 07:35:41 PM UTC 24 |
| Finished | Aug 28 07:40:55 PM UTC 24 |
| Peak memory | 218876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635384569 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3635384569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/29.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1793354522 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 76038774356 ps |
| CPU time | 307.9 seconds |
| Started | Aug 28 07:35:41 PM UTC 24 |
| Finished | Aug 28 07:40:54 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793354522 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1793354522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/29.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.649969191 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 87898399 ps |
| CPU time | 14.51 seconds |
| Started | Aug 28 07:35:40 PM UTC 24 |
| Finished | Aug 28 07:35:55 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649969191 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.649969191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/29.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.1636152524 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 115058032 ps |
| CPU time | 10.24 seconds |
| Started | Aug 28 07:35:48 PM UTC 24 |
| Finished | Aug 28 07:35:59 PM UTC 24 |
| Peak memory | 217024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636152524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1636152524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/29.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.3684821960 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 135230100 ps |
| CPU time | 5.38 seconds |
| Started | Aug 28 07:35:34 PM UTC 24 |
| Finished | Aug 28 07:35:41 PM UTC 24 |
| Peak memory | 217140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684821960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3684821960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/29.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.2991365119 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 5005470065 ps |
| CPU time | 36.84 seconds |
| Started | Aug 28 07:35:35 PM UTC 24 |
| Finished | Aug 28 07:36:14 PM UTC 24 |
| Peak memory | 217140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991365119 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2991365119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/29.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.4189511881 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 2799346521 ps |
| CPU time | 33.51 seconds |
| Started | Aug 28 07:35:37 PM UTC 24 |
| Finished | Aug 28 07:36:12 PM UTC 24 |
| Peak memory | 216868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189511881 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.4189511881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.3191893073 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 84254344 ps |
| CPU time | 3.42 seconds |
| Started | Aug 28 07:35:34 PM UTC 24 |
| Finished | Aug 28 07:35:39 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191893073 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.3191893073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/29.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.3012414902 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 4067392062 ps |
| CPU time | 188.99 seconds |
| Started | Aug 28 07:35:56 PM UTC 24 |
| Finished | Aug 28 07:39:09 PM UTC 24 |
| Peak memory | 220924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012414902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3012414902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/29.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1523813654 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 1808810847 ps |
| CPU time | 210.89 seconds |
| Started | Aug 28 07:36:01 PM UTC 24 |
| Finished | Aug 28 07:39:36 PM UTC 24 |
| Peak memory | 219140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523813654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1523813654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/29.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.2974128316 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 1400713886 ps |
| CPU time | 264.31 seconds |
| Started | Aug 28 07:36:01 PM UTC 24 |
| Finished | Aug 28 07:40:30 PM UTC 24 |
| Peak memory | 221256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974128316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.2974128316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3524688765 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 6151068119 ps |
| CPU time | 290.4 seconds |
| Started | Aug 28 07:36:03 PM UTC 24 |
| Finished | Aug 28 07:40:59 PM UTC 24 |
| Peak memory | 233652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524688765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.3524688765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.3455275380 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 859085306 ps |
| CPU time | 30.34 seconds |
| Started | Aug 28 07:35:52 PM UTC 24 |
| Finished | Aug 28 07:36:24 PM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455275380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3455275380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/29.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.1566549949 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 5921704871 ps |
| CPU time | 60.76 seconds |
| Started | Aug 28 07:22:28 PM UTC 24 |
| Finished | Aug 28 07:23:31 PM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566549949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1566549949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/3.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.1165465453 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 78272087 ps |
| CPU time | 10.26 seconds |
| Started | Aug 28 07:22:35 PM UTC 24 |
| Finished | Aug 28 07:22:47 PM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165465453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.1165465453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.2646550738 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 308981470 ps |
| CPU time | 11.03 seconds |
| Started | Aug 28 07:22:34 PM UTC 24 |
| Finished | Aug 28 07:22:47 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646550738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2646550738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/3.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random.4213996358 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 61812608 ps |
| CPU time | 5.08 seconds |
| Started | Aug 28 07:22:27 PM UTC 24 |
| Finished | Aug 28 07:22:33 PM UTC 24 |
| Peak memory | 216756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213996358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.4213996358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/3.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.2951028373 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 61557659532 ps |
| CPU time | 352.72 seconds |
| Started | Aug 28 07:22:27 PM UTC 24 |
| Finished | Aug 28 07:28:26 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951028373 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2951028373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/3.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.541916461 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 33034443940 ps |
| CPU time | 195.41 seconds |
| Started | Aug 28 07:22:27 PM UTC 24 |
| Finished | Aug 28 07:25:46 PM UTC 24 |
| Peak memory | 216788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541916461 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.541916461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/3.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.3344870960 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 40502060 ps |
| CPU time | 5.06 seconds |
| Started | Aug 28 07:22:27 PM UTC 24 |
| Finished | Aug 28 07:22:33 PM UTC 24 |
| Peak memory | 217080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344870960 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.3344870960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/3.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.1071031767 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 32611871 ps |
| CPU time | 3.18 seconds |
| Started | Aug 28 07:22:31 PM UTC 24 |
| Finished | Aug 28 07:22:36 PM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071031767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1071031767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/3.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.1804554306 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 182934607 ps |
| CPU time | 5.95 seconds |
| Started | Aug 28 07:22:18 PM UTC 24 |
| Finished | Aug 28 07:22:25 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804554306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.1804554306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/3.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.4012968586 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 29919791501 ps |
| CPU time | 62.3 seconds |
| Started | Aug 28 07:22:21 PM UTC 24 |
| Finished | Aug 28 07:23:25 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012968586 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.4012968586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/3.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.2063595368 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 7013484582 ps |
| CPU time | 58.97 seconds |
| Started | Aug 28 07:22:21 PM UTC 24 |
| Finished | Aug 28 07:23:22 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063595368 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2063595368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.2233010871 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 35904357 ps |
| CPU time | 3.13 seconds |
| Started | Aug 28 07:22:21 PM UTC 24 |
| Finished | Aug 28 07:22:25 PM UTC 24 |
| Peak memory | 216800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233010871 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2233010871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/3.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.2329552684 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 4588679818 ps |
| CPU time | 176.98 seconds |
| Started | Aug 28 07:22:36 PM UTC 24 |
| Finished | Aug 28 07:25:36 PM UTC 24 |
| Peak memory | 218876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329552684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2329552684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/3.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3374832347 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 8042606664 ps |
| CPU time | 182.36 seconds |
| Started | Aug 28 07:22:42 PM UTC 24 |
| Finished | Aug 28 07:25:47 PM UTC 24 |
| Peak memory | 221004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374832347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3374832347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/3.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.262366740 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 278506120 ps |
| CPU time | 107.26 seconds |
| Started | Aug 28 07:22:37 PM UTC 24 |
| Finished | Aug 28 07:24:26 PM UTC 24 |
| Peak memory | 220936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262366740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.262366740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.3958342673 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 22664699136 ps |
| CPU time | 969.61 seconds |
| Started | Aug 28 07:22:46 PM UTC 24 |
| Finished | Aug 28 07:39:10 PM UTC 24 |
| Peak memory | 240432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958342673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.3958342673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.3304353591 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 328797526 ps |
| CPU time | 10.58 seconds |
| Started | Aug 28 07:22:35 PM UTC 24 |
| Finished | Aug 28 07:22:47 PM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304353591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3304353591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/3.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.354689174 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 1491209819 ps |
| CPU time | 63.83 seconds |
| Started | Aug 28 07:36:11 PM UTC 24 |
| Finished | Aug 28 07:37:17 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354689174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.354689174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/30.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.2094297716 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 7136438984 ps |
| CPU time | 84.95 seconds |
| Started | Aug 28 07:36:11 PM UTC 24 |
| Finished | Aug 28 07:37:38 PM UTC 24 |
| Peak memory | 217164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094297716 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.2094297716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3724814369 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 384042965 ps |
| CPU time | 19.55 seconds |
| Started | Aug 28 07:36:15 PM UTC 24 |
| Finished | Aug 28 07:36:36 PM UTC 24 |
| Peak memory | 216860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724814369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3724814369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.1612205315 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 337852720 ps |
| CPU time | 14.64 seconds |
| Started | Aug 28 07:36:13 PM UTC 24 |
| Finished | Aug 28 07:36:29 PM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612205315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1612205315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/30.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random.954406889 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 16423321 ps |
| CPU time | 3.17 seconds |
| Started | Aug 28 07:36:06 PM UTC 24 |
| Finished | Aug 28 07:36:11 PM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954406889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.954406889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/30.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.81860158 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 22351524844 ps |
| CPU time | 189.89 seconds |
| Started | Aug 28 07:36:09 PM UTC 24 |
| Finished | Aug 28 07:39:22 PM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81860158 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.81860158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/30.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.2507693713 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 30042532277 ps |
| CPU time | 343.69 seconds |
| Started | Aug 28 07:36:10 PM UTC 24 |
| Finished | Aug 28 07:41:59 PM UTC 24 |
| Peak memory | 218876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507693713 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.2507693713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/30.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.3491584867 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 29033934 ps |
| CPU time | 5.03 seconds |
| Started | Aug 28 07:36:07 PM UTC 24 |
| Finished | Aug 28 07:36:14 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491584867 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.3491584867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/30.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.919341712 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 329822294 ps |
| CPU time | 8.1 seconds |
| Started | Aug 28 07:36:12 PM UTC 24 |
| Finished | Aug 28 07:36:21 PM UTC 24 |
| Peak memory | 216956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919341712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.919341712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/30.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.3298923181 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 29506000 ps |
| CPU time | 2.94 seconds |
| Started | Aug 28 07:36:03 PM UTC 24 |
| Finished | Aug 28 07:36:07 PM UTC 24 |
| Peak memory | 217072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298923181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3298923181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/30.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.2161925520 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 5164743254 ps |
| CPU time | 41.41 seconds |
| Started | Aug 28 07:36:05 PM UTC 24 |
| Finished | Aug 28 07:36:48 PM UTC 24 |
| Peak memory | 216884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161925520 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2161925520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/30.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2785427034 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 5090148730 ps |
| CPU time | 73.75 seconds |
| Started | Aug 28 07:36:05 PM UTC 24 |
| Finished | Aug 28 07:37:21 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785427034 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2785427034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.1042415213 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 85072102 ps |
| CPU time | 3.82 seconds |
| Started | Aug 28 07:36:05 PM UTC 24 |
| Finished | Aug 28 07:36:10 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042415213 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.1042415213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/30.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.2894313638 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 347635146 ps |
| CPU time | 29.39 seconds |
| Started | Aug 28 07:36:15 PM UTC 24 |
| Finished | Aug 28 07:36:46 PM UTC 24 |
| Peak memory | 218716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894313638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2894313638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/30.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2401938617 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 19903046798 ps |
| CPU time | 299.81 seconds |
| Started | Aug 28 07:36:22 PM UTC 24 |
| Finished | Aug 28 07:41:27 PM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401938617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2401938617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/30.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.1350398196 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 5750447352 ps |
| CPU time | 322.99 seconds |
| Started | Aug 28 07:36:22 PM UTC 24 |
| Finished | Aug 28 07:41:51 PM UTC 24 |
| Peak memory | 223304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350398196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.1350398196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.102894378 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 7368493163 ps |
| CPU time | 213.35 seconds |
| Started | Aug 28 07:36:24 PM UTC 24 |
| Finished | Aug 28 07:40:02 PM UTC 24 |
| Peak memory | 223052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102894378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.102894378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.309199113 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 188963092 ps |
| CPU time | 27.33 seconds |
| Started | Aug 28 07:36:13 PM UTC 24 |
| Finished | Aug 28 07:36:42 PM UTC 24 |
| Peak memory | 218800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309199113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.309199113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/30.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.3175988938 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 1129959974 ps |
| CPU time | 24.4 seconds |
| Started | Aug 28 07:36:42 PM UTC 24 |
| Finished | Aug 28 07:37:07 PM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175988938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3175988938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/31.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2902247635 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 131076269345 ps |
| CPU time | 635.7 seconds |
| Started | Aug 28 07:36:43 PM UTC 24 |
| Finished | Aug 28 07:47:28 PM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902247635 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.2902247635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.2768019141 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 44293573 ps |
| CPU time | 4.97 seconds |
| Started | Aug 28 07:36:49 PM UTC 24 |
| Finished | Aug 28 07:36:55 PM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768019141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2768019141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.573016538 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1957693879 ps |
| CPU time | 40.1 seconds |
| Started | Aug 28 07:36:44 PM UTC 24 |
| Finished | Aug 28 07:37:26 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573016538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.573016538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/31.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random.2055082900 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 798384847 ps |
| CPU time | 30.71 seconds |
| Started | Aug 28 07:36:36 PM UTC 24 |
| Finished | Aug 28 07:37:08 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055082900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.2055082900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/31.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.2806950138 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 34792867649 ps |
| CPU time | 98.57 seconds |
| Started | Aug 28 07:36:37 PM UTC 24 |
| Finished | Aug 28 07:38:18 PM UTC 24 |
| Peak memory | 217212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806950138 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2806950138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/31.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.4227186005 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 16168495842 ps |
| CPU time | 100.15 seconds |
| Started | Aug 28 07:36:40 PM UTC 24 |
| Finished | Aug 28 07:38:23 PM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227186005 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.4227186005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/31.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.3567314385 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 22539392 ps |
| CPU time | 4.38 seconds |
| Started | Aug 28 07:36:36 PM UTC 24 |
| Finished | Aug 28 07:36:42 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567314385 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3567314385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/31.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.2440985380 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 238817008 ps |
| CPU time | 17.62 seconds |
| Started | Aug 28 07:36:43 PM UTC 24 |
| Finished | Aug 28 07:37:02 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440985380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.2440985380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/31.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.2853245892 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 39979855 ps |
| CPU time | 2.97 seconds |
| Started | Aug 28 07:36:25 PM UTC 24 |
| Finished | Aug 28 07:36:29 PM UTC 24 |
| Peak memory | 216944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853245892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2853245892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/31.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.3953340401 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 5975393086 ps |
| CPU time | 42.26 seconds |
| Started | Aug 28 07:36:31 PM UTC 24 |
| Finished | Aug 28 07:37:15 PM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953340401 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3953340401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/31.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.3603365818 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 3138606073 ps |
| CPU time | 45.63 seconds |
| Started | Aug 28 07:36:32 PM UTC 24 |
| Finished | Aug 28 07:37:20 PM UTC 24 |
| Peak memory | 217136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603365818 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3603365818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.703052403 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 49557388 ps |
| CPU time | 3.21 seconds |
| Started | Aug 28 07:36:31 PM UTC 24 |
| Finished | Aug 28 07:36:35 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703052403 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.703052403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/31.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.2433968330 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 4908491899 ps |
| CPU time | 185.04 seconds |
| Started | Aug 28 07:36:49 PM UTC 24 |
| Finished | Aug 28 07:39:58 PM UTC 24 |
| Peak memory | 220988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433968330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2433968330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/31.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3638025440 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 684832724 ps |
| CPU time | 50.29 seconds |
| Started | Aug 28 07:36:56 PM UTC 24 |
| Finished | Aug 28 07:37:48 PM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638025440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3638025440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/31.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1525979914 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 163745185 ps |
| CPU time | 62.31 seconds |
| Started | Aug 28 07:36:53 PM UTC 24 |
| Finished | Aug 28 07:37:57 PM UTC 24 |
| Peak memory | 219140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525979914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.1525979914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.210021556 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 4243065153 ps |
| CPU time | 254.95 seconds |
| Started | Aug 28 07:37:04 PM UTC 24 |
| Finished | Aug 28 07:41:23 PM UTC 24 |
| Peak memory | 223672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210021556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.210021556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.3896274487 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 71148519 ps |
| CPU time | 15.59 seconds |
| Started | Aug 28 07:36:46 PM UTC 24 |
| Finished | Aug 28 07:37:03 PM UTC 24 |
| Peak memory | 216776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896274487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3896274487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/31.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.1024195742 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 479734874 ps |
| CPU time | 49.95 seconds |
| Started | Aug 28 07:37:16 PM UTC 24 |
| Finished | Aug 28 07:38:08 PM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024195742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.1024195742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/32.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3913820966 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 42022408672 ps |
| CPU time | 419.87 seconds |
| Started | Aug 28 07:37:18 PM UTC 24 |
| Finished | Aug 28 07:44:24 PM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913820966 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.3913820966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2435465647 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 481577101 ps |
| CPU time | 5.09 seconds |
| Started | Aug 28 07:37:27 PM UTC 24 |
| Finished | Aug 28 07:37:33 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435465647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2435465647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.1952282408 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 465528997 ps |
| CPU time | 25.08 seconds |
| Started | Aug 28 07:37:21 PM UTC 24 |
| Finished | Aug 28 07:37:48 PM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952282408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1952282408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/32.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random.1895918126 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2268786798 ps |
| CPU time | 23.8 seconds |
| Started | Aug 28 07:37:10 PM UTC 24 |
| Finished | Aug 28 07:37:35 PM UTC 24 |
| Peak memory | 216640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895918126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.1895918126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/32.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.517362045 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 9864114234 ps |
| CPU time | 89.74 seconds |
| Started | Aug 28 07:37:12 PM UTC 24 |
| Finished | Aug 28 07:38:44 PM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517362045 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.517362045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/32.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.521179502 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 24285020404 ps |
| CPU time | 121.12 seconds |
| Started | Aug 28 07:37:12 PM UTC 24 |
| Finished | Aug 28 07:39:15 PM UTC 24 |
| Peak memory | 216820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521179502 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.521179502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/32.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.1246730085 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 177923514 ps |
| CPU time | 24.84 seconds |
| Started | Aug 28 07:37:10 PM UTC 24 |
| Finished | Aug 28 07:37:36 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246730085 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1246730085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/32.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.17696669 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 972001496 ps |
| CPU time | 8.58 seconds |
| Started | Aug 28 07:37:20 PM UTC 24 |
| Finished | Aug 28 07:37:30 PM UTC 24 |
| Peak memory | 217148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17696669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.17696669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/32.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.2290380282 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 615062503 ps |
| CPU time | 5.61 seconds |
| Started | Aug 28 07:37:04 PM UTC 24 |
| Finished | Aug 28 07:37:10 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290380282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2290380282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/32.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.160697143 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 12592146137 ps |
| CPU time | 46.42 seconds |
| Started | Aug 28 07:37:08 PM UTC 24 |
| Finished | Aug 28 07:37:56 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160697143 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.160697143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/32.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.10933599 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 3024624460 ps |
| CPU time | 37.76 seconds |
| Started | Aug 28 07:37:10 PM UTC 24 |
| Finished | Aug 28 07:37:49 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10933599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.10933599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.3455398041 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 30345962 ps |
| CPU time | 3.17 seconds |
| Started | Aug 28 07:37:05 PM UTC 24 |
| Finished | Aug 28 07:37:09 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455398041 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.3455398041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/32.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.831525250 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 248567673 ps |
| CPU time | 28.84 seconds |
| Started | Aug 28 07:37:31 PM UTC 24 |
| Finished | Aug 28 07:38:01 PM UTC 24 |
| Peak memory | 219204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831525250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.831525250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/32.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1031207010 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 14224333804 ps |
| CPU time | 105.2 seconds |
| Started | Aug 28 07:37:36 PM UTC 24 |
| Finished | Aug 28 07:39:24 PM UTC 24 |
| Peak memory | 218944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031207010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1031207010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/32.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3464949207 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 4229833134 ps |
| CPU time | 584.44 seconds |
| Started | Aug 28 07:37:34 PM UTC 24 |
| Finished | Aug 28 07:47:28 PM UTC 24 |
| Peak memory | 223052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464949207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.3464949207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.2567555627 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 2509186717 ps |
| CPU time | 186.55 seconds |
| Started | Aug 28 07:37:37 PM UTC 24 |
| Finished | Aug 28 07:40:48 PM UTC 24 |
| Peak memory | 222980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567555627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.2567555627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.180065465 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1305933600 ps |
| CPU time | 20.58 seconds |
| Started | Aug 28 07:37:26 PM UTC 24 |
| Finished | Aug 28 07:37:48 PM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180065465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.180065465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/32.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.3266146038 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 1949323875 ps |
| CPU time | 42.76 seconds |
| Started | Aug 28 07:37:49 PM UTC 24 |
| Finished | Aug 28 07:38:34 PM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266146038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3266146038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/33.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1896362985 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 15838852272 ps |
| CPU time | 140.69 seconds |
| Started | Aug 28 07:37:49 PM UTC 24 |
| Finished | Aug 28 07:40:13 PM UTC 24 |
| Peak memory | 219212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896362985 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.1896362985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.1284904282 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 828937527 ps |
| CPU time | 32.58 seconds |
| Started | Aug 28 07:37:58 PM UTC 24 |
| Finished | Aug 28 07:38:32 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284904282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.1284904282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.1296979069 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 953913792 ps |
| CPU time | 21.62 seconds |
| Started | Aug 28 07:37:54 PM UTC 24 |
| Finished | Aug 28 07:38:17 PM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296979069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1296979069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/33.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random.4198381626 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 1119636401 ps |
| CPU time | 34.62 seconds |
| Started | Aug 28 07:37:47 PM UTC 24 |
| Finished | Aug 28 07:38:23 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198381626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.4198381626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/33.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.120422385 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 42091588668 ps |
| CPU time | 133.08 seconds |
| Started | Aug 28 07:37:48 PM UTC 24 |
| Finished | Aug 28 07:40:04 PM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120422385 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.120422385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/33.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.2818235679 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 18017525854 ps |
| CPU time | 171.67 seconds |
| Started | Aug 28 07:37:49 PM UTC 24 |
| Finished | Aug 28 07:40:44 PM UTC 24 |
| Peak memory | 218428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818235679 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2818235679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/33.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.4235665730 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 156398850 ps |
| CPU time | 30 seconds |
| Started | Aug 28 07:37:47 PM UTC 24 |
| Finished | Aug 28 07:38:19 PM UTC 24 |
| Peak memory | 217024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235665730 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.4235665730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/33.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.2502349999 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 5802700432 ps |
| CPU time | 51.1 seconds |
| Started | Aug 28 07:37:50 PM UTC 24 |
| Finished | Aug 28 07:38:44 PM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502349999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2502349999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/33.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.728861221 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 302091890 ps |
| CPU time | 5.74 seconds |
| Started | Aug 28 07:37:40 PM UTC 24 |
| Finished | Aug 28 07:37:47 PM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728861221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.728861221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/33.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.1833791956 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 5541527556 ps |
| CPU time | 41.77 seconds |
| Started | Aug 28 07:37:40 PM UTC 24 |
| Finished | Aug 28 07:38:23 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833791956 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1833791956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/33.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.3329970574 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 10927874066 ps |
| CPU time | 56.78 seconds |
| Started | Aug 28 07:37:45 PM UTC 24 |
| Finished | Aug 28 07:38:44 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329970574 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3329970574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.272430232 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 47163870 ps |
| CPU time | 4.08 seconds |
| Started | Aug 28 07:37:40 PM UTC 24 |
| Finished | Aug 28 07:37:45 PM UTC 24 |
| Peak memory | 217064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272430232 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.272430232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/33.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.232502295 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 1519247999 ps |
| CPU time | 86.33 seconds |
| Started | Aug 28 07:37:59 PM UTC 24 |
| Finished | Aug 28 07:39:29 PM UTC 24 |
| Peak memory | 219140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232502295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.232502295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/33.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.1034254513 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 31043522855 ps |
| CPU time | 273.35 seconds |
| Started | Aug 28 07:38:02 PM UTC 24 |
| Finished | Aug 28 07:42:40 PM UTC 24 |
| Peak memory | 221316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034254513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1034254513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/33.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.559355956 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 207863452 ps |
| CPU time | 104.92 seconds |
| Started | Aug 28 07:38:02 PM UTC 24 |
| Finished | Aug 28 07:39:51 PM UTC 24 |
| Peak memory | 221256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559355956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.559355956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.3890940962 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 86634394 ps |
| CPU time | 29.89 seconds |
| Started | Aug 28 07:38:05 PM UTC 24 |
| Finished | Aug 28 07:38:36 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890940962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.3890940962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.3322037257 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 541705256 ps |
| CPU time | 20.14 seconds |
| Started | Aug 28 07:37:58 PM UTC 24 |
| Finished | Aug 28 07:38:19 PM UTC 24 |
| Peak memory | 217916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322037257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3322037257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/33.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.1267585040 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 584663206 ps |
| CPU time | 59.4 seconds |
| Started | Aug 28 07:38:19 PM UTC 24 |
| Finished | Aug 28 07:39:20 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267585040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1267585040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/34.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3627396159 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 106135720354 ps |
| CPU time | 454.14 seconds |
| Started | Aug 28 07:38:19 PM UTC 24 |
| Finished | Aug 28 07:46:00 PM UTC 24 |
| Peak memory | 219212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627396159 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.3627396159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.3918246558 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 14057653 ps |
| CPU time | 2.23 seconds |
| Started | Aug 28 07:38:24 PM UTC 24 |
| Finished | Aug 28 07:38:28 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918246558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.3918246558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.3490088710 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 6566658931 ps |
| CPU time | 43.55 seconds |
| Started | Aug 28 07:38:22 PM UTC 24 |
| Finished | Aug 28 07:39:07 PM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490088710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3490088710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/34.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random.4284539559 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 388279380 ps |
| CPU time | 19.7 seconds |
| Started | Aug 28 07:38:14 PM UTC 24 |
| Finished | Aug 28 07:38:35 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284539559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.4284539559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/34.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.1475247440 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 9427864185 ps |
| CPU time | 65.44 seconds |
| Started | Aug 28 07:38:17 PM UTC 24 |
| Finished | Aug 28 07:39:24 PM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475247440 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1475247440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/34.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1027759194 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 9174250158 ps |
| CPU time | 90.54 seconds |
| Started | Aug 28 07:38:18 PM UTC 24 |
| Finished | Aug 28 07:39:51 PM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027759194 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1027759194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/34.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.3732950449 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 113953847 ps |
| CPU time | 16.75 seconds |
| Started | Aug 28 07:38:16 PM UTC 24 |
| Finished | Aug 28 07:38:34 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732950449 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3732950449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/34.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.936876898 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 4439258406 ps |
| CPU time | 41.45 seconds |
| Started | Aug 28 07:38:20 PM UTC 24 |
| Finished | Aug 28 07:39:03 PM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936876898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.936876898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/34.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.199090105 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 510319261 ps |
| CPU time | 5.22 seconds |
| Started | Aug 28 07:38:08 PM UTC 24 |
| Finished | Aug 28 07:38:14 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199090105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.199090105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/34.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.2658911248 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 7627277422 ps |
| CPU time | 48.87 seconds |
| Started | Aug 28 07:38:10 PM UTC 24 |
| Finished | Aug 28 07:39:01 PM UTC 24 |
| Peak memory | 216884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658911248 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2658911248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/34.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.3987439569 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 4295815049 ps |
| CPU time | 25.23 seconds |
| Started | Aug 28 07:38:11 PM UTC 24 |
| Finished | Aug 28 07:38:38 PM UTC 24 |
| Peak memory | 217200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987439569 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3987439569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.1568299320 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 38564537 ps |
| CPU time | 3.35 seconds |
| Started | Aug 28 07:38:09 PM UTC 24 |
| Finished | Aug 28 07:38:13 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568299320 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.1568299320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/34.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.806204037 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 1328149922 ps |
| CPU time | 53.93 seconds |
| Started | Aug 28 07:38:24 PM UTC 24 |
| Finished | Aug 28 07:39:20 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806204037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.806204037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/34.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1613232077 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3268770112 ps |
| CPU time | 124.35 seconds |
| Started | Aug 28 07:38:31 PM UTC 24 |
| Finished | Aug 28 07:40:38 PM UTC 24 |
| Peak memory | 220996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613232077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1613232077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/34.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.740544864 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 5023245223 ps |
| CPU time | 351.89 seconds |
| Started | Aug 28 07:38:29 PM UTC 24 |
| Finished | Aug 28 07:44:27 PM UTC 24 |
| Peak memory | 221260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740544864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.740544864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.2948160140 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 4452611251 ps |
| CPU time | 521.57 seconds |
| Started | Aug 28 07:38:33 PM UTC 24 |
| Finished | Aug 28 07:47:22 PM UTC 24 |
| Peak memory | 239732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948160140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.2948160140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.432185516 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 69602111 ps |
| CPU time | 4.17 seconds |
| Started | Aug 28 07:38:24 PM UTC 24 |
| Finished | Aug 28 07:38:30 PM UTC 24 |
| Peak memory | 216736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432185516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.432185516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/34.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.4033022651 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 543472509 ps |
| CPU time | 31.64 seconds |
| Started | Aug 28 07:38:45 PM UTC 24 |
| Finished | Aug 28 07:39:18 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033022651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.4033022651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/35.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2246248237 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 97940459558 ps |
| CPU time | 741.97 seconds |
| Started | Aug 28 07:38:45 PM UTC 24 |
| Finished | Aug 28 07:51:18 PM UTC 24 |
| Peak memory | 221168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246248237 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.2246248237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1339490603 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 1242900632 ps |
| CPU time | 28.84 seconds |
| Started | Aug 28 07:38:54 PM UTC 24 |
| Finished | Aug 28 07:39:25 PM UTC 24 |
| Peak memory | 217156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339490603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1339490603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.1135574235 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 29682874 ps |
| CPU time | 2.4 seconds |
| Started | Aug 28 07:38:49 PM UTC 24 |
| Finished | Aug 28 07:38:53 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135574235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1135574235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/35.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random.2699579098 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 270934783 ps |
| CPU time | 9.24 seconds |
| Started | Aug 28 07:38:38 PM UTC 24 |
| Finished | Aug 28 07:38:48 PM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699579098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.2699579098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/35.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.74740273 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 33790080448 ps |
| CPU time | 154.73 seconds |
| Started | Aug 28 07:38:41 PM UTC 24 |
| Finished | Aug 28 07:41:19 PM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74740273 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.74740273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/35.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.222495409 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 29848226267 ps |
| CPU time | 282.85 seconds |
| Started | Aug 28 07:38:42 PM UTC 24 |
| Finished | Aug 28 07:43:30 PM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222495409 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.222495409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/35.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.1203627497 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 107550141 ps |
| CPU time | 17.49 seconds |
| Started | Aug 28 07:38:39 PM UTC 24 |
| Finished | Aug 28 07:38:58 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203627497 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1203627497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/35.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.1476619707 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 379123670 ps |
| CPU time | 18.35 seconds |
| Started | Aug 28 07:38:45 PM UTC 24 |
| Finished | Aug 28 07:39:05 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476619707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1476619707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/35.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.1814647461 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 100106411 ps |
| CPU time | 4.61 seconds |
| Started | Aug 28 07:38:35 PM UTC 24 |
| Finished | Aug 28 07:38:41 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814647461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1814647461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/35.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1453374002 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 9645092528 ps |
| CPU time | 67.23 seconds |
| Started | Aug 28 07:38:36 PM UTC 24 |
| Finished | Aug 28 07:39:46 PM UTC 24 |
| Peak memory | 216884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453374002 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1453374002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/35.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.4286799328 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 5876045425 ps |
| CPU time | 40.2 seconds |
| Started | Aug 28 07:38:38 PM UTC 24 |
| Finished | Aug 28 07:39:20 PM UTC 24 |
| Peak memory | 216580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286799328 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.4286799328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1809191748 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 40330929 ps |
| CPU time | 3.43 seconds |
| Started | Aug 28 07:38:35 PM UTC 24 |
| Finished | Aug 28 07:38:40 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809191748 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1809191748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/35.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.1121419344 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 1460407836 ps |
| CPU time | 152.67 seconds |
| Started | Aug 28 07:38:54 PM UTC 24 |
| Finished | Aug 28 07:41:31 PM UTC 24 |
| Peak memory | 219136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121419344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1121419344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/35.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.205775964 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 934867499 ps |
| CPU time | 89.85 seconds |
| Started | Aug 28 07:38:59 PM UTC 24 |
| Finished | Aug 28 07:40:31 PM UTC 24 |
| Peak memory | 218812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205775964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.205775964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/35.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1230538353 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 888963686 ps |
| CPU time | 330.6 seconds |
| Started | Aug 28 07:38:57 PM UTC 24 |
| Finished | Aug 28 07:44:34 PM UTC 24 |
| Peak memory | 222920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230538353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.1230538353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.450367636 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 6776059322 ps |
| CPU time | 396.58 seconds |
| Started | Aug 28 07:39:02 PM UTC 24 |
| Finished | Aug 28 07:45:45 PM UTC 24 |
| Peak memory | 222988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450367636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.450367636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.4082634834 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 495295710 ps |
| CPU time | 23.34 seconds |
| Started | Aug 28 07:38:54 PM UTC 24 |
| Finished | Aug 28 07:39:19 PM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082634834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.4082634834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/35.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.630320302 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 5189013298 ps |
| CPU time | 44.23 seconds |
| Started | Aug 28 07:39:16 PM UTC 24 |
| Finished | Aug 28 07:40:03 PM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630320302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.630320302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/36.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.138231150 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 207186872429 ps |
| CPU time | 938.56 seconds |
| Started | Aug 28 07:39:19 PM UTC 24 |
| Finished | Aug 28 07:55:10 PM UTC 24 |
| Peak memory | 221004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138231150 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.138231150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.1524757010 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 58594801 ps |
| CPU time | 9.15 seconds |
| Started | Aug 28 07:39:22 PM UTC 24 |
| Finished | Aug 28 07:39:33 PM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524757010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1524757010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.2101575698 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 605975413 ps |
| CPU time | 20.32 seconds |
| Started | Aug 28 07:39:22 PM UTC 24 |
| Finished | Aug 28 07:39:44 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101575698 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2101575698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/36.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random.2940095171 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 858820079 ps |
| CPU time | 30.48 seconds |
| Started | Aug 28 07:39:11 PM UTC 24 |
| Finished | Aug 28 07:39:43 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940095171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.2940095171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/36.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.2120137383 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 13110245670 ps |
| CPU time | 85.1 seconds |
| Started | Aug 28 07:39:12 PM UTC 24 |
| Finished | Aug 28 07:40:39 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120137383 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2120137383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/36.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2751315839 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 28956795523 ps |
| CPU time | 324.06 seconds |
| Started | Aug 28 07:39:14 PM UTC 24 |
| Finished | Aug 28 07:44:44 PM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751315839 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2751315839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/36.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.2723822566 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 178014211 ps |
| CPU time | 12.93 seconds |
| Started | Aug 28 07:39:11 PM UTC 24 |
| Finished | Aug 28 07:39:25 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723822566 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2723822566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/36.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.709777919 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 1336711208 ps |
| CPU time | 32.35 seconds |
| Started | Aug 28 07:39:20 PM UTC 24 |
| Finished | Aug 28 07:39:54 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709777919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.709777919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/36.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.2297131450 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 27771255 ps |
| CPU time | 3.11 seconds |
| Started | Aug 28 07:39:04 PM UTC 24 |
| Finished | Aug 28 07:39:08 PM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297131450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2297131450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/36.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2716652446 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 6119284696 ps |
| CPU time | 48.05 seconds |
| Started | Aug 28 07:39:08 PM UTC 24 |
| Finished | Aug 28 07:39:58 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716652446 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2716652446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/36.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.233794992 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 6918127913 ps |
| CPU time | 41.72 seconds |
| Started | Aug 28 07:39:11 PM UTC 24 |
| Finished | Aug 28 07:39:54 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233794992 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.233794992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1892364021 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 40993576 ps |
| CPU time | 3.21 seconds |
| Started | Aug 28 07:39:05 PM UTC 24 |
| Finished | Aug 28 07:39:10 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892364021 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1892364021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/36.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.681300591 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 473961169 ps |
| CPU time | 65.57 seconds |
| Started | Aug 28 07:39:22 PM UTC 24 |
| Finished | Aug 28 07:40:30 PM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681300591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.681300591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/36.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1832480386 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 2015731678 ps |
| CPU time | 48.73 seconds |
| Started | Aug 28 07:39:25 PM UTC 24 |
| Finished | Aug 28 07:40:16 PM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832480386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1832480386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/36.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1594036369 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 516883409 ps |
| CPU time | 339.76 seconds |
| Started | Aug 28 07:39:23 PM UTC 24 |
| Finished | Aug 28 07:45:09 PM UTC 24 |
| Peak memory | 221192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594036369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.1594036369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.1268362630 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 542641317 ps |
| CPU time | 159.45 seconds |
| Started | Aug 28 07:39:25 PM UTC 24 |
| Finished | Aug 28 07:42:08 PM UTC 24 |
| Peak memory | 222980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268362630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.1268362630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.3601654612 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 2722854158 ps |
| CPU time | 33.18 seconds |
| Started | Aug 28 07:39:22 PM UTC 24 |
| Finished | Aug 28 07:39:57 PM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601654612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.3601654612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/36.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.950546927 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 201077825 ps |
| CPU time | 34.77 seconds |
| Started | Aug 28 07:39:44 PM UTC 24 |
| Finished | Aug 28 07:40:20 PM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950546927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.950546927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/37.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.4267107296 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 31700948206 ps |
| CPU time | 319.58 seconds |
| Started | Aug 28 07:39:44 PM UTC 24 |
| Finished | Aug 28 07:45:08 PM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267107296 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.4267107296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.536776852 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 1021460734 ps |
| CPU time | 21.79 seconds |
| Started | Aug 28 07:39:49 PM UTC 24 |
| Finished | Aug 28 07:40:12 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536776852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.536776852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.2036399460 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 1054549715 ps |
| CPU time | 33.88 seconds |
| Started | Aug 28 07:39:46 PM UTC 24 |
| Finished | Aug 28 07:40:22 PM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036399460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2036399460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/37.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random.600482397 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 945841671 ps |
| CPU time | 23.13 seconds |
| Started | Aug 28 07:39:32 PM UTC 24 |
| Finished | Aug 28 07:39:56 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600482397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.600482397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/37.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.2841474807 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 13061565482 ps |
| CPU time | 69.59 seconds |
| Started | Aug 28 07:39:35 PM UTC 24 |
| Finished | Aug 28 07:40:47 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841474807 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2841474807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/37.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.4183058745 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 50955256356 ps |
| CPU time | 232.9 seconds |
| Started | Aug 28 07:39:36 PM UTC 24 |
| Finished | Aug 28 07:43:34 PM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183058745 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.4183058745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/37.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.1178673006 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 368107737 ps |
| CPU time | 12.33 seconds |
| Started | Aug 28 07:39:32 PM UTC 24 |
| Finished | Aug 28 07:39:45 PM UTC 24 |
| Peak memory | 217084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178673006 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.1178673006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/37.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.3955033621 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 113294033 ps |
| CPU time | 12.48 seconds |
| Started | Aug 28 07:39:45 PM UTC 24 |
| Finished | Aug 28 07:39:59 PM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955033621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3955033621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/37.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.1234504262 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 25718712 ps |
| CPU time | 3.29 seconds |
| Started | Aug 28 07:39:25 PM UTC 24 |
| Finished | Aug 28 07:39:30 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234504262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1234504262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/37.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3797232345 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 37001031483 ps |
| CPU time | 101.53 seconds |
| Started | Aug 28 07:39:27 PM UTC 24 |
| Finished | Aug 28 07:41:11 PM UTC 24 |
| Peak memory | 217204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797232345 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3797232345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/37.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.55900557 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 19483316567 ps |
| CPU time | 52.6 seconds |
| Started | Aug 28 07:39:30 PM UTC 24 |
| Finished | Aug 28 07:40:24 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55900557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.55900557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.1024217579 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 31373861 ps |
| CPU time | 3.37 seconds |
| Started | Aug 28 07:39:25 PM UTC 24 |
| Finished | Aug 28 07:39:30 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024217579 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.1024217579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/37.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.2008604967 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 10170390790 ps |
| CPU time | 359.29 seconds |
| Started | Aug 28 07:39:52 PM UTC 24 |
| Finished | Aug 28 07:45:58 PM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008604967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2008604967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/37.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1573662987 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 7013546049 ps |
| CPU time | 155.83 seconds |
| Started | Aug 28 07:39:55 PM UTC 24 |
| Finished | Aug 28 07:42:34 PM UTC 24 |
| Peak memory | 219204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573662987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1573662987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/37.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3614851818 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 348659452 ps |
| CPU time | 201.44 seconds |
| Started | Aug 28 07:39:52 PM UTC 24 |
| Finished | Aug 28 07:43:18 PM UTC 24 |
| Peak memory | 220936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614851818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.3614851818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3244635939 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 10930427495 ps |
| CPU time | 259.28 seconds |
| Started | Aug 28 07:39:55 PM UTC 24 |
| Finished | Aug 28 07:44:19 PM UTC 24 |
| Peak memory | 223672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244635939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.3244635939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.3926999842 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 462553103 ps |
| CPU time | 23.84 seconds |
| Started | Aug 28 07:39:46 PM UTC 24 |
| Finished | Aug 28 07:40:12 PM UTC 24 |
| Peak memory | 217100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926999842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3926999842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/37.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.1005048627 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 1085552034 ps |
| CPU time | 54.73 seconds |
| Started | Aug 28 07:40:03 PM UTC 24 |
| Finished | Aug 28 07:41:00 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005048627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1005048627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/38.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1672538863 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 68646046098 ps |
| CPU time | 429.32 seconds |
| Started | Aug 28 07:40:05 PM UTC 24 |
| Finished | Aug 28 07:47:20 PM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672538863 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.1672538863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.1980892154 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 132963771 ps |
| CPU time | 7.3 seconds |
| Started | Aug 28 07:40:15 PM UTC 24 |
| Finished | Aug 28 07:40:23 PM UTC 24 |
| Peak memory | 217156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980892154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.1980892154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.2744139593 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 228338916 ps |
| CPU time | 29.89 seconds |
| Started | Aug 28 07:40:13 PM UTC 24 |
| Finished | Aug 28 07:40:45 PM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744139593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2744139593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/38.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random.791906477 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 2679053651 ps |
| CPU time | 35.33 seconds |
| Started | Aug 28 07:40:00 PM UTC 24 |
| Finished | Aug 28 07:40:37 PM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791906477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.791906477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/38.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.4162412573 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 35046564471 ps |
| CPU time | 263.84 seconds |
| Started | Aug 28 07:40:01 PM UTC 24 |
| Finished | Aug 28 07:44:30 PM UTC 24 |
| Peak memory | 217216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162412573 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.4162412573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/38.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.3049660644 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 2345529825 ps |
| CPU time | 34.5 seconds |
| Started | Aug 28 07:40:03 PM UTC 24 |
| Finished | Aug 28 07:40:39 PM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049660644 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3049660644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/38.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.201505882 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 170769645 ps |
| CPU time | 24.83 seconds |
| Started | Aug 28 07:40:00 PM UTC 24 |
| Finished | Aug 28 07:40:27 PM UTC 24 |
| Peak memory | 217084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201505882 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.201505882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/38.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.4059259836 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 167028391 ps |
| CPU time | 17.32 seconds |
| Started | Aug 28 07:40:05 PM UTC 24 |
| Finished | Aug 28 07:40:24 PM UTC 24 |
| Peak memory | 216960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059259836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.4059259836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/38.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.518497515 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 417264584 ps |
| CPU time | 5.66 seconds |
| Started | Aug 28 07:39:57 PM UTC 24 |
| Finished | Aug 28 07:40:03 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518497515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.518497515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/38.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3573302463 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 8164038974 ps |
| CPU time | 47.5 seconds |
| Started | Aug 28 07:39:58 PM UTC 24 |
| Finished | Aug 28 07:40:48 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573302463 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3573302463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/38.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1603262858 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 4579173404 ps |
| CPU time | 37.38 seconds |
| Started | Aug 28 07:40:00 PM UTC 24 |
| Finished | Aug 28 07:40:39 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603262858 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1603262858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2868512726 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 31389835 ps |
| CPU time | 2.83 seconds |
| Started | Aug 28 07:39:57 PM UTC 24 |
| Finished | Aug 28 07:40:01 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868512726 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2868512726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/38.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.3309345972 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 1113636031 ps |
| CPU time | 100.99 seconds |
| Started | Aug 28 07:40:17 PM UTC 24 |
| Finished | Aug 28 07:42:01 PM UTC 24 |
| Peak memory | 220860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309345972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3309345972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/38.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3124360649 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 838913674 ps |
| CPU time | 98.34 seconds |
| Started | Aug 28 07:40:23 PM UTC 24 |
| Finished | Aug 28 07:42:03 PM UTC 24 |
| Peak memory | 221252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124360649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3124360649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/38.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.3668370172 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 4799461463 ps |
| CPU time | 314.07 seconds |
| Started | Aug 28 07:40:21 PM UTC 24 |
| Finished | Aug 28 07:45:41 PM UTC 24 |
| Peak memory | 220936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668370172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.3668370172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3719549676 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 8067446086 ps |
| CPU time | 272.48 seconds |
| Started | Aug 28 07:40:24 PM UTC 24 |
| Finished | Aug 28 07:45:02 PM UTC 24 |
| Peak memory | 233588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719549676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.3719549676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.2855326251 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 367758077 ps |
| CPU time | 24.42 seconds |
| Started | Aug 28 07:40:13 PM UTC 24 |
| Finished | Aug 28 07:40:39 PM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855326251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.2855326251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/38.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.2188482094 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 535439703 ps |
| CPU time | 51.22 seconds |
| Started | Aug 28 07:40:39 PM UTC 24 |
| Finished | Aug 28 07:41:32 PM UTC 24 |
| Peak memory | 219204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188482094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2188482094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/39.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3506746580 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 8129805856 ps |
| CPU time | 43.79 seconds |
| Started | Aug 28 07:40:39 PM UTC 24 |
| Finished | Aug 28 07:41:24 PM UTC 24 |
| Peak memory | 216904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506746580 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.3506746580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.3351621405 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 120161451 ps |
| CPU time | 3.17 seconds |
| Started | Aug 28 07:40:41 PM UTC 24 |
| Finished | Aug 28 07:40:45 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351621405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.3351621405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.1412695029 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 349041907 ps |
| CPU time | 13.45 seconds |
| Started | Aug 28 07:40:41 PM UTC 24 |
| Finished | Aug 28 07:40:56 PM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412695029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1412695029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/39.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random.299349867 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 75027037 ps |
| CPU time | 3.88 seconds |
| Started | Aug 28 07:40:33 PM UTC 24 |
| Finished | Aug 28 07:40:38 PM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299349867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.299349867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/39.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.2886318380 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 92893615598 ps |
| CPU time | 193.96 seconds |
| Started | Aug 28 07:40:33 PM UTC 24 |
| Finished | Aug 28 07:43:50 PM UTC 24 |
| Peak memory | 217148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886318380 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2886318380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/39.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1661427951 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 23619042459 ps |
| CPU time | 121.1 seconds |
| Started | Aug 28 07:40:34 PM UTC 24 |
| Finished | Aug 28 07:42:38 PM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661427951 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1661427951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/39.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.2388582978 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 129926772 ps |
| CPU time | 7.18 seconds |
| Started | Aug 28 07:40:33 PM UTC 24 |
| Finished | Aug 28 07:40:41 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388582978 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.2388582978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/39.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.1266585311 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 339261995 ps |
| CPU time | 26.93 seconds |
| Started | Aug 28 07:40:39 PM UTC 24 |
| Finished | Aug 28 07:41:07 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266585311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1266585311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/39.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.1144520421 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 214614839 ps |
| CPU time | 5.35 seconds |
| Started | Aug 28 07:40:24 PM UTC 24 |
| Finished | Aug 28 07:40:31 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144520421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1144520421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/39.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.2838345464 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 8411620974 ps |
| CPU time | 49.4 seconds |
| Started | Aug 28 07:40:28 PM UTC 24 |
| Finished | Aug 28 07:41:19 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838345464 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2838345464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/39.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1077845295 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 4618896148 ps |
| CPU time | 31.74 seconds |
| Started | Aug 28 07:40:32 PM UTC 24 |
| Finished | Aug 28 07:41:06 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077845295 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1077845295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2016859942 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 32090250 ps |
| CPU time | 3.4 seconds |
| Started | Aug 28 07:40:26 PM UTC 24 |
| Finished | Aug 28 07:40:30 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016859942 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2016859942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/39.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.997902988 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 12381612313 ps |
| CPU time | 288.43 seconds |
| Started | Aug 28 07:40:46 PM UTC 24 |
| Finished | Aug 28 07:45:39 PM UTC 24 |
| Peak memory | 223040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997902988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.997902988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/39.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.449099593 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 4049878694 ps |
| CPU time | 185.87 seconds |
| Started | Aug 28 07:40:42 PM UTC 24 |
| Finished | Aug 28 07:43:52 PM UTC 24 |
| Peak memory | 223052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449099593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.449099593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3832878795 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 1644432734 ps |
| CPU time | 290.96 seconds |
| Started | Aug 28 07:40:46 PM UTC 24 |
| Finished | Aug 28 07:45:42 PM UTC 24 |
| Peak memory | 233468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832878795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.3832878795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.2127937334 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 556486097 ps |
| CPU time | 21.6 seconds |
| Started | Aug 28 07:40:41 PM UTC 24 |
| Finished | Aug 28 07:41:04 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127937334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2127937334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/39.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.2899615384 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 963897884 ps |
| CPU time | 29.01 seconds |
| Started | Aug 28 07:23:04 PM UTC 24 |
| Finished | Aug 28 07:23:35 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899615384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.2899615384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/4.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.2899294271 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 129523722496 ps |
| CPU time | 395.52 seconds |
| Started | Aug 28 07:23:07 PM UTC 24 |
| Finished | Aug 28 07:29:49 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899294271 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.2899294271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3190405387 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 643282779 ps |
| CPU time | 29.66 seconds |
| Started | Aug 28 07:23:11 PM UTC 24 |
| Finished | Aug 28 07:23:42 PM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190405387 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3190405387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.909790728 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1361511306 ps |
| CPU time | 28.1 seconds |
| Started | Aug 28 07:23:08 PM UTC 24 |
| Finished | Aug 28 07:23:38 PM UTC 24 |
| Peak memory | 216756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909790728 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.909790728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/4.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random.1989666460 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 149313285 ps |
| CPU time | 14.27 seconds |
| Started | Aug 28 07:22:51 PM UTC 24 |
| Finished | Aug 28 07:23:07 PM UTC 24 |
| Peak memory | 217080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989666460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.1989666460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/4.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.3377330970 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 40051533132 ps |
| CPU time | 131.86 seconds |
| Started | Aug 28 07:22:53 PM UTC 24 |
| Finished | Aug 28 07:25:08 PM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377330970 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3377330970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/4.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.4211452810 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 27537574034 ps |
| CPU time | 204.46 seconds |
| Started | Aug 28 07:22:56 PM UTC 24 |
| Finished | Aug 28 07:26:25 PM UTC 24 |
| Peak memory | 219068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211452810 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.4211452810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/4.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.1066873016 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 141233223 ps |
| CPU time | 27.61 seconds |
| Started | Aug 28 07:22:53 PM UTC 24 |
| Finished | Aug 28 07:23:22 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066873016 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1066873016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/4.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.685901833 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 125709485 ps |
| CPU time | 9.14 seconds |
| Started | Aug 28 07:23:08 PM UTC 24 |
| Finished | Aug 28 07:23:19 PM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685901833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.685901833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/4.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.1509650799 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 202484532 ps |
| CPU time | 4.81 seconds |
| Started | Aug 28 07:22:47 PM UTC 24 |
| Finished | Aug 28 07:22:53 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509650799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1509650799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/4.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.4188483269 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 8630732707 ps |
| CPU time | 60.95 seconds |
| Started | Aug 28 07:22:48 PM UTC 24 |
| Finished | Aug 28 07:23:51 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188483269 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.4188483269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/4.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2667605256 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 5567701357 ps |
| CPU time | 47.71 seconds |
| Started | Aug 28 07:22:50 PM UTC 24 |
| Finished | Aug 28 07:23:40 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667605256 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2667605256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.1178856277 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 67110447 ps |
| CPU time | 3.07 seconds |
| Started | Aug 28 07:22:48 PM UTC 24 |
| Finished | Aug 28 07:22:52 PM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178856277 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.1178856277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/4.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.3382696450 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3779266233 ps |
| CPU time | 140.81 seconds |
| Started | Aug 28 07:23:14 PM UTC 24 |
| Finished | Aug 28 07:25:38 PM UTC 24 |
| Peak memory | 221248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382696450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3382696450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/4.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.833828952 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 352044479 ps |
| CPU time | 13.73 seconds |
| Started | Aug 28 07:23:21 PM UTC 24 |
| Finished | Aug 28 07:23:36 PM UTC 24 |
| Peak memory | 217084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833828952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.833828952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/4.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.663769653 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 13067702859 ps |
| CPU time | 594.65 seconds |
| Started | Aug 28 07:23:20 PM UTC 24 |
| Finished | Aug 28 07:33:24 PM UTC 24 |
| Peak memory | 235768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663769653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.663769653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.1197204721 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 11971465 ps |
| CPU time | 2.63 seconds |
| Started | Aug 28 07:23:09 PM UTC 24 |
| Finished | Aug 28 07:23:13 PM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197204721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1197204721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/4.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.3072581884 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 4759984693 ps |
| CPU time | 68.89 seconds |
| Started | Aug 28 07:40:56 PM UTC 24 |
| Finished | Aug 28 07:42:08 PM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072581884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3072581884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/40.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1939953939 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 11161184281 ps |
| CPU time | 147.79 seconds |
| Started | Aug 28 07:40:56 PM UTC 24 |
| Finished | Aug 28 07:43:28 PM UTC 24 |
| Peak memory | 219208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939953939 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.1939953939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.2948557475 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 1325191656 ps |
| CPU time | 35.92 seconds |
| Started | Aug 28 07:41:05 PM UTC 24 |
| Finished | Aug 28 07:41:42 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948557475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.2948557475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.2391696338 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 247440916 ps |
| CPU time | 18.17 seconds |
| Started | Aug 28 07:41:00 PM UTC 24 |
| Finished | Aug 28 07:41:20 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391696338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2391696338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/40.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random.2706171926 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 140647387 ps |
| CPU time | 24.35 seconds |
| Started | Aug 28 07:40:49 PM UTC 24 |
| Finished | Aug 28 07:41:15 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706171926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.2706171926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/40.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.817217058 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 27730038114 ps |
| CPU time | 58.67 seconds |
| Started | Aug 28 07:40:53 PM UTC 24 |
| Finished | Aug 28 07:41:54 PM UTC 24 |
| Peak memory | 216784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817217058 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.817217058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/40.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2453868137 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 12146450833 ps |
| CPU time | 86.8 seconds |
| Started | Aug 28 07:40:55 PM UTC 24 |
| Finished | Aug 28 07:42:23 PM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453868137 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2453868137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/40.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.3947751401 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 146560899 ps |
| CPU time | 13.43 seconds |
| Started | Aug 28 07:40:53 PM UTC 24 |
| Finished | Aug 28 07:41:08 PM UTC 24 |
| Peak memory | 216948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947751401 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.3947751401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/40.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.1331426304 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 281833293 ps |
| CPU time | 6.9 seconds |
| Started | Aug 28 07:40:56 PM UTC 24 |
| Finished | Aug 28 07:41:05 PM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331426304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1331426304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/40.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.3641134060 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 214249864 ps |
| CPU time | 5.2 seconds |
| Started | Aug 28 07:40:46 PM UTC 24 |
| Finished | Aug 28 07:40:52 PM UTC 24 |
| Peak memory | 217072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641134060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3641134060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/40.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.625123277 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 5710298375 ps |
| CPU time | 46.09 seconds |
| Started | Aug 28 07:40:48 PM UTC 24 |
| Finished | Aug 28 07:41:35 PM UTC 24 |
| Peak memory | 216944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625123277 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.625123277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/40.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.4069715359 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 2365961471 ps |
| CPU time | 29.66 seconds |
| Started | Aug 28 07:40:49 PM UTC 24 |
| Finished | Aug 28 07:41:20 PM UTC 24 |
| Peak memory | 217200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069715359 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.4069715359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.2126977775 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 29404231 ps |
| CPU time | 3.25 seconds |
| Started | Aug 28 07:40:47 PM UTC 24 |
| Finished | Aug 28 07:40:52 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126977775 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.2126977775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/40.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.835157651 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 2062016438 ps |
| CPU time | 129.4 seconds |
| Started | Aug 28 07:41:06 PM UTC 24 |
| Finished | Aug 28 07:43:18 PM UTC 24 |
| Peak memory | 219204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835157651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.835157651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/40.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2607180792 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 2513482223 ps |
| CPU time | 228.19 seconds |
| Started | Aug 28 07:41:08 PM UTC 24 |
| Finished | Aug 28 07:45:01 PM UTC 24 |
| Peak memory | 223668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607180792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2607180792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/40.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1761747744 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 2541775447 ps |
| CPU time | 710.03 seconds |
| Started | Aug 28 07:41:08 PM UTC 24 |
| Finished | Aug 28 07:53:08 PM UTC 24 |
| Peak memory | 220996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761747744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.1761747744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.2071603784 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 3077587871 ps |
| CPU time | 479.9 seconds |
| Started | Aug 28 07:41:10 PM UTC 24 |
| Finished | Aug 28 07:49:17 PM UTC 24 |
| Peak memory | 240172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071603784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.2071603784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.2668964306 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 1441985879 ps |
| CPU time | 41.57 seconds |
| Started | Aug 28 07:41:01 PM UTC 24 |
| Finished | Aug 28 07:41:45 PM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668964306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2668964306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/40.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.796119529 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 4362707062 ps |
| CPU time | 66.88 seconds |
| Started | Aug 28 07:41:21 PM UTC 24 |
| Finished | Aug 28 07:42:30 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796119529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.796119529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/41.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3716599345 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 101210405229 ps |
| CPU time | 900.49 seconds |
| Started | Aug 28 07:41:25 PM UTC 24 |
| Finished | Aug 28 07:56:38 PM UTC 24 |
| Peak memory | 219276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716599345 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.3716599345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.2581009623 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 120121539 ps |
| CPU time | 21.69 seconds |
| Started | Aug 28 07:41:32 PM UTC 24 |
| Finished | Aug 28 07:41:55 PM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581009623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.2581009623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.4066423835 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 58062833 ps |
| CPU time | 8.27 seconds |
| Started | Aug 28 07:41:26 PM UTC 24 |
| Finished | Aug 28 07:41:36 PM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066423835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.4066423835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/41.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random.3824510699 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 306459784 ps |
| CPU time | 15.03 seconds |
| Started | Aug 28 07:41:20 PM UTC 24 |
| Finished | Aug 28 07:41:36 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824510699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.3824510699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/41.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.1305729233 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 5684689583 ps |
| CPU time | 58.46 seconds |
| Started | Aug 28 07:41:21 PM UTC 24 |
| Finished | Aug 28 07:42:21 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305729233 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1305729233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/41.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2944575132 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 141553862489 ps |
| CPU time | 539.81 seconds |
| Started | Aug 28 07:41:21 PM UTC 24 |
| Finished | Aug 28 07:50:29 PM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944575132 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2944575132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/41.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.444620497 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 1031287715 ps |
| CPU time | 31.83 seconds |
| Started | Aug 28 07:41:21 PM UTC 24 |
| Finished | Aug 28 07:41:55 PM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444620497 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.444620497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/41.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.1347713104 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 622915778 ps |
| CPU time | 22.24 seconds |
| Started | Aug 28 07:41:25 PM UTC 24 |
| Finished | Aug 28 07:41:48 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347713104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1347713104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/41.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.1689425872 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 29489581 ps |
| CPU time | 3.41 seconds |
| Started | Aug 28 07:41:12 PM UTC 24 |
| Finished | Aug 28 07:41:16 PM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689425872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1689425872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/41.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.1040804921 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 12177131928 ps |
| CPU time | 48.54 seconds |
| Started | Aug 28 07:41:18 PM UTC 24 |
| Finished | Aug 28 07:42:08 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040804921 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1040804921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/41.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.1685526293 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 5037462820 ps |
| CPU time | 28.46 seconds |
| Started | Aug 28 07:41:18 PM UTC 24 |
| Finished | Aug 28 07:41:48 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685526293 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1685526293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.3672337812 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 45005540 ps |
| CPU time | 3.52 seconds |
| Started | Aug 28 07:41:18 PM UTC 24 |
| Finished | Aug 28 07:41:23 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672337812 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.3672337812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/41.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.2361395921 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 1696266181 ps |
| CPU time | 149.58 seconds |
| Started | Aug 28 07:41:32 PM UTC 24 |
| Finished | Aug 28 07:44:05 PM UTC 24 |
| Peak memory | 222908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361395921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2361395921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/41.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3968972485 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 562737600 ps |
| CPU time | 31.66 seconds |
| Started | Aug 28 07:41:37 PM UTC 24 |
| Finished | Aug 28 07:42:10 PM UTC 24 |
| Peak memory | 218536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968972485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3968972485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/41.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3207971150 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 272843350 ps |
| CPU time | 147.28 seconds |
| Started | Aug 28 07:41:37 PM UTC 24 |
| Finished | Aug 28 07:44:08 PM UTC 24 |
| Peak memory | 220952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207971150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.3207971150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1011939996 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 359182419 ps |
| CPU time | 138.75 seconds |
| Started | Aug 28 07:41:37 PM UTC 24 |
| Finished | Aug 28 07:43:59 PM UTC 24 |
| Peak memory | 222980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011939996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.1011939996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.2613061907 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 610961133 ps |
| CPU time | 34.74 seconds |
| Started | Aug 28 07:41:29 PM UTC 24 |
| Finished | Aug 28 07:42:05 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613061907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2613061907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/41.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.3951968009 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1454177134 ps |
| CPU time | 61.09 seconds |
| Started | Aug 28 07:41:53 PM UTC 24 |
| Finished | Aug 28 07:42:55 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951968009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3951968009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/42.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2271192110 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 149111255392 ps |
| CPU time | 610.84 seconds |
| Started | Aug 28 07:41:55 PM UTC 24 |
| Finished | Aug 28 07:52:14 PM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271192110 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.2271192110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.4077050242 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 632015452 ps |
| CPU time | 22.79 seconds |
| Started | Aug 28 07:42:01 PM UTC 24 |
| Finished | Aug 28 07:42:25 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077050242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.4077050242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.321438404 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 500267564 ps |
| CPU time | 13.52 seconds |
| Started | Aug 28 07:41:57 PM UTC 24 |
| Finished | Aug 28 07:42:11 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321438404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.321438404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/42.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random.426984143 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 2016589743 ps |
| CPU time | 44.72 seconds |
| Started | Aug 28 07:41:50 PM UTC 24 |
| Finished | Aug 28 07:42:37 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426984143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.426984143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/42.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.2509216230 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 12496484126 ps |
| CPU time | 23.79 seconds |
| Started | Aug 28 07:41:50 PM UTC 24 |
| Finished | Aug 28 07:42:16 PM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509216230 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2509216230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/42.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2434530283 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 24740385434 ps |
| CPU time | 145.2 seconds |
| Started | Aug 28 07:41:53 PM UTC 24 |
| Finished | Aug 28 07:44:20 PM UTC 24 |
| Peak memory | 217216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434530283 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2434530283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/42.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.3673578870 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 324599747 ps |
| CPU time | 27.54 seconds |
| Started | Aug 28 07:41:50 PM UTC 24 |
| Finished | Aug 28 07:42:19 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673578870 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.3673578870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/42.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.1832790331 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 1615436660 ps |
| CPU time | 45.28 seconds |
| Started | Aug 28 07:41:55 PM UTC 24 |
| Finished | Aug 28 07:42:42 PM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832790331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1832790331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/42.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.1044288924 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 60721395 ps |
| CPU time | 3.34 seconds |
| Started | Aug 28 07:41:37 PM UTC 24 |
| Finished | Aug 28 07:41:42 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044288924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1044288924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/42.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1540610120 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3629423105 ps |
| CPU time | 27.91 seconds |
| Started | Aug 28 07:41:44 PM UTC 24 |
| Finished | Aug 28 07:42:14 PM UTC 24 |
| Peak memory | 217140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540610120 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1540610120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/42.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1749783595 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 9260579440 ps |
| CPU time | 39.35 seconds |
| Started | Aug 28 07:41:46 PM UTC 24 |
| Finished | Aug 28 07:42:27 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749783595 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1749783595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3170907786 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 36644528 ps |
| CPU time | 3.73 seconds |
| Started | Aug 28 07:41:43 PM UTC 24 |
| Finished | Aug 28 07:41:48 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170907786 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3170907786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/42.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.1571328520 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 4768371713 ps |
| CPU time | 206.52 seconds |
| Started | Aug 28 07:42:05 PM UTC 24 |
| Finished | Aug 28 07:45:36 PM UTC 24 |
| Peak memory | 223036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571328520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1571328520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/42.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3832862443 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 15952437171 ps |
| CPU time | 242.73 seconds |
| Started | Aug 28 07:42:07 PM UTC 24 |
| Finished | Aug 28 07:46:14 PM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832862443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3832862443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/42.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1229650223 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 3799933318 ps |
| CPU time | 738.14 seconds |
| Started | Aug 28 07:42:07 PM UTC 24 |
| Finished | Aug 28 07:54:37 PM UTC 24 |
| Peak memory | 233916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229650223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.1229650223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3591065000 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 9795781936 ps |
| CPU time | 293.8 seconds |
| Started | Aug 28 07:42:10 PM UTC 24 |
| Finished | Aug 28 07:47:09 PM UTC 24 |
| Peak memory | 233976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591065000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.3591065000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.4110629137 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 270058372 ps |
| CPU time | 23.26 seconds |
| Started | Aug 28 07:42:00 PM UTC 24 |
| Finished | Aug 28 07:42:25 PM UTC 24 |
| Peak memory | 217096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110629137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.4110629137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/42.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.2121370736 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 1296866884 ps |
| CPU time | 69.51 seconds |
| Started | Aug 28 07:42:21 PM UTC 24 |
| Finished | Aug 28 07:43:33 PM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121370736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.2121370736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/43.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1667587165 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 42779375417 ps |
| CPU time | 514.89 seconds |
| Started | Aug 28 07:42:23 PM UTC 24 |
| Finished | Aug 28 07:51:05 PM UTC 24 |
| Peak memory | 219276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667587165 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.1667587165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.302220815 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 119995301 ps |
| CPU time | 5.74 seconds |
| Started | Aug 28 07:42:29 PM UTC 24 |
| Finished | Aug 28 07:42:36 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302220815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.302220815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.640932646 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 297364953 ps |
| CPU time | 23.17 seconds |
| Started | Aug 28 07:42:27 PM UTC 24 |
| Finished | Aug 28 07:42:52 PM UTC 24 |
| Peak memory | 216820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640932646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.640932646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/43.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random.1236768413 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 105565338 ps |
| CPU time | 19.65 seconds |
| Started | Aug 28 07:42:16 PM UTC 24 |
| Finished | Aug 28 07:42:37 PM UTC 24 |
| Peak memory | 217080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236768413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1236768413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/43.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.2217297153 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 29711084621 ps |
| CPU time | 99.37 seconds |
| Started | Aug 28 07:42:17 PM UTC 24 |
| Finished | Aug 28 07:43:59 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217297153 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2217297153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/43.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.4018375553 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 20102926303 ps |
| CPU time | 164.31 seconds |
| Started | Aug 28 07:42:18 PM UTC 24 |
| Finished | Aug 28 07:45:05 PM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018375553 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.4018375553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/43.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.506767978 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 86408634 ps |
| CPU time | 18.2 seconds |
| Started | Aug 28 07:42:16 PM UTC 24 |
| Finished | Aug 28 07:42:35 PM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506767978 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.506767978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/43.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.1441369533 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 1630370851 ps |
| CPU time | 34.78 seconds |
| Started | Aug 28 07:42:25 PM UTC 24 |
| Finished | Aug 28 07:43:01 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441369533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1441369533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/43.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.159985761 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 310958120 ps |
| CPU time | 4.73 seconds |
| Started | Aug 28 07:42:10 PM UTC 24 |
| Finished | Aug 28 07:42:16 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159985761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.159985761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/43.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2589729270 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 6346928783 ps |
| CPU time | 47.07 seconds |
| Started | Aug 28 07:42:11 PM UTC 24 |
| Finished | Aug 28 07:43:00 PM UTC 24 |
| Peak memory | 217140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589729270 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2589729270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/43.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.4280380738 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 14027833704 ps |
| CPU time | 40.52 seconds |
| Started | Aug 28 07:42:13 PM UTC 24 |
| Finished | Aug 28 07:42:55 PM UTC 24 |
| Peak memory | 217136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280380738 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.4280380738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.636470651 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 54820291 ps |
| CPU time | 2.91 seconds |
| Started | Aug 28 07:42:10 PM UTC 24 |
| Finished | Aug 28 07:42:14 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636470651 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.636470651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/43.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.2312983001 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 1204022659 ps |
| CPU time | 156.2 seconds |
| Started | Aug 28 07:42:31 PM UTC 24 |
| Finished | Aug 28 07:45:11 PM UTC 24 |
| Peak memory | 221184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312983001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2312983001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/43.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1124504761 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 4258808435 ps |
| CPU time | 144.74 seconds |
| Started | Aug 28 07:42:37 PM UTC 24 |
| Finished | Aug 28 07:45:05 PM UTC 24 |
| Peak memory | 220996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124504761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1124504761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/43.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1161443396 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 100315152 ps |
| CPU time | 57.75 seconds |
| Started | Aug 28 07:42:35 PM UTC 24 |
| Finished | Aug 28 07:43:35 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161443396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.1161443396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.445685129 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 2284571787 ps |
| CPU time | 293.71 seconds |
| Started | Aug 28 07:42:37 PM UTC 24 |
| Finished | Aug 28 07:47:36 PM UTC 24 |
| Peak memory | 233660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445685129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.445685129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.3454383280 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 147525882 ps |
| CPU time | 26.99 seconds |
| Started | Aug 28 07:42:27 PM UTC 24 |
| Finished | Aug 28 07:42:55 PM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454383280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3454383280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/43.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.3973103278 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 2315590775 ps |
| CPU time | 56.88 seconds |
| Started | Aug 28 07:42:53 PM UTC 24 |
| Finished | Aug 28 07:43:52 PM UTC 24 |
| Peak memory | 219204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973103278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.3973103278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/44.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.4204074160 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 35164383237 ps |
| CPU time | 166.92 seconds |
| Started | Aug 28 07:42:56 PM UTC 24 |
| Finished | Aug 28 07:45:46 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204074160 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.4204074160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.618718539 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 111740326 ps |
| CPU time | 19.19 seconds |
| Started | Aug 28 07:43:03 PM UTC 24 |
| Finished | Aug 28 07:43:23 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618718539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.618718539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.2977011608 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 75372491 ps |
| CPU time | 4.2 seconds |
| Started | Aug 28 07:42:57 PM UTC 24 |
| Finished | Aug 28 07:43:03 PM UTC 24 |
| Peak memory | 217084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977011608 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2977011608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/44.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.1706383293 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 178355062 ps |
| CPU time | 28.71 seconds |
| Started | Aug 28 07:42:44 PM UTC 24 |
| Finished | Aug 28 07:43:14 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706383293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.1706383293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/44.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.1308365656 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 32540373894 ps |
| CPU time | 238.92 seconds |
| Started | Aug 28 07:42:46 PM UTC 24 |
| Finished | Aug 28 07:46:49 PM UTC 24 |
| Peak memory | 217212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308365656 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1308365656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/44.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1756661411 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 8472556732 ps |
| CPU time | 127.98 seconds |
| Started | Aug 28 07:42:52 PM UTC 24 |
| Finished | Aug 28 07:45:03 PM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756661411 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1756661411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/44.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.1925206779 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 92948171 ps |
| CPU time | 5.91 seconds |
| Started | Aug 28 07:42:44 PM UTC 24 |
| Finished | Aug 28 07:42:51 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925206779 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1925206779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/44.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.4134745874 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 1761390762 ps |
| CPU time | 22.46 seconds |
| Started | Aug 28 07:42:56 PM UTC 24 |
| Finished | Aug 28 07:43:20 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134745874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.4134745874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/44.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.518280382 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 153448326 ps |
| CPU time | 5.12 seconds |
| Started | Aug 28 07:42:38 PM UTC 24 |
| Finished | Aug 28 07:42:45 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518280382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.518280382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/44.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1938262535 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 24521222648 ps |
| CPU time | 64.67 seconds |
| Started | Aug 28 07:42:40 PM UTC 24 |
| Finished | Aug 28 07:43:47 PM UTC 24 |
| Peak memory | 217012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938262535 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1938262535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/44.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.173696991 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 21349608818 ps |
| CPU time | 53 seconds |
| Started | Aug 28 07:42:41 PM UTC 24 |
| Finished | Aug 28 07:43:36 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173696991 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.173696991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.1621862811 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 96520830 ps |
| CPU time | 3.75 seconds |
| Started | Aug 28 07:42:39 PM UTC 24 |
| Finished | Aug 28 07:42:43 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621862811 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.1621862811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/44.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.1194285375 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 7742652519 ps |
| CPU time | 201.61 seconds |
| Started | Aug 28 07:43:03 PM UTC 24 |
| Finished | Aug 28 07:46:28 PM UTC 24 |
| Peak memory | 220924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194285375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1194285375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/44.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1474877953 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 1670173497 ps |
| CPU time | 50.9 seconds |
| Started | Aug 28 07:43:16 PM UTC 24 |
| Finished | Aug 28 07:44:08 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474877953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1474877953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/44.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2486393168 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 806133879 ps |
| CPU time | 260.21 seconds |
| Started | Aug 28 07:43:18 PM UTC 24 |
| Finished | Aug 28 07:47:43 PM UTC 24 |
| Peak memory | 223284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486393168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.2486393168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.26156235 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 265716401 ps |
| CPU time | 14.75 seconds |
| Started | Aug 28 07:43:01 PM UTC 24 |
| Finished | Aug 28 07:43:17 PM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26156235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.26156235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/44.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.4199648469 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 279465296 ps |
| CPU time | 23.72 seconds |
| Started | Aug 28 07:43:33 PM UTC 24 |
| Finished | Aug 28 07:43:58 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199648469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.4199648469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/45.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1221917952 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 75385369789 ps |
| CPU time | 833.15 seconds |
| Started | Aug 28 07:43:33 PM UTC 24 |
| Finished | Aug 28 07:57:37 PM UTC 24 |
| Peak memory | 221000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221917952 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.1221917952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1680443660 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 175225719 ps |
| CPU time | 11.48 seconds |
| Started | Aug 28 07:43:37 PM UTC 24 |
| Finished | Aug 28 07:43:50 PM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680443660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.1680443660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.1695223199 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 168710954 ps |
| CPU time | 23.5 seconds |
| Started | Aug 28 07:43:37 PM UTC 24 |
| Finished | Aug 28 07:44:02 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695223199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1695223199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/45.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.393712224 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 188341843 ps |
| CPU time | 23.23 seconds |
| Started | Aug 28 07:43:26 PM UTC 24 |
| Finished | Aug 28 07:43:52 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393712224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.393712224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/45.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.2014989251 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 21674205266 ps |
| CPU time | 168 seconds |
| Started | Aug 28 07:43:28 PM UTC 24 |
| Finished | Aug 28 07:46:19 PM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014989251 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2014989251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/45.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1827608855 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 4560107340 ps |
| CPU time | 39.18 seconds |
| Started | Aug 28 07:43:30 PM UTC 24 |
| Finished | Aug 28 07:44:11 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827608855 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1827608855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/45.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.374100865 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 18990038 ps |
| CPU time | 2.4 seconds |
| Started | Aug 28 07:43:26 PM UTC 24 |
| Finished | Aug 28 07:43:31 PM UTC 24 |
| Peak memory | 217016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374100865 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.374100865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/45.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.4152056080 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 1510001113 ps |
| CPU time | 40.76 seconds |
| Started | Aug 28 07:43:34 PM UTC 24 |
| Finished | Aug 28 07:44:17 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152056080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.4152056080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/45.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.3206079168 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 206655780 ps |
| CPU time | 3.92 seconds |
| Started | Aug 28 07:43:20 PM UTC 24 |
| Finished | Aug 28 07:43:25 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206079168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3206079168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/45.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2816116278 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 4039115443 ps |
| CPU time | 35.42 seconds |
| Started | Aug 28 07:43:22 PM UTC 24 |
| Finished | Aug 28 07:43:58 PM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816116278 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2816116278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/45.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.996545316 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 2962722166 ps |
| CPU time | 38.04 seconds |
| Started | Aug 28 07:43:26 PM UTC 24 |
| Finished | Aug 28 07:44:06 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996545316 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.996545316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3459588074 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 69158010 ps |
| CPU time | 3.51 seconds |
| Started | Aug 28 07:43:20 PM UTC 24 |
| Finished | Aug 28 07:43:25 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459588074 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.3459588074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/45.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.1493056779 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 5309859497 ps |
| CPU time | 224.4 seconds |
| Started | Aug 28 07:43:48 PM UTC 24 |
| Finished | Aug 28 07:47:37 PM UTC 24 |
| Peak memory | 222976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493056779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1493056779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/45.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.493991425 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 3074149027 ps |
| CPU time | 124.67 seconds |
| Started | Aug 28 07:43:54 PM UTC 24 |
| Finished | Aug 28 07:46:01 PM UTC 24 |
| Peak memory | 218876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493991425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.493991425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/45.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.966679519 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 642304258 ps |
| CPU time | 236.05 seconds |
| Started | Aug 28 07:43:54 PM UTC 24 |
| Finished | Aug 28 07:47:54 PM UTC 24 |
| Peak memory | 220932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966679519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.966679519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3704267100 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 510995379 ps |
| CPU time | 169.27 seconds |
| Started | Aug 28 07:43:54 PM UTC 24 |
| Finished | Aug 28 07:46:47 PM UTC 24 |
| Peak memory | 222912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704267100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.3704267100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.3673650850 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 1180550661 ps |
| CPU time | 22.3 seconds |
| Started | Aug 28 07:43:37 PM UTC 24 |
| Finished | Aug 28 07:44:01 PM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673650850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3673650850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/45.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.2709133042 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 564590977 ps |
| CPU time | 20.67 seconds |
| Started | Aug 28 07:44:05 PM UTC 24 |
| Finished | Aug 28 07:44:27 PM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709133042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2709133042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/46.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.694002689 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 16888631971 ps |
| CPU time | 103.53 seconds |
| Started | Aug 28 07:44:05 PM UTC 24 |
| Finished | Aug 28 07:45:51 PM UTC 24 |
| Peak memory | 216904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694002689 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.694002689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2820548605 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 140827634 ps |
| CPU time | 5.62 seconds |
| Started | Aug 28 07:44:12 PM UTC 24 |
| Finished | Aug 28 07:44:19 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820548605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2820548605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.4001834353 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 386455431 ps |
| CPU time | 27.75 seconds |
| Started | Aug 28 07:44:12 PM UTC 24 |
| Finished | Aug 28 07:44:41 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001834353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.4001834353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/46.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.2059240077 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 968299831 ps |
| CPU time | 28.7 seconds |
| Started | Aug 28 07:44:05 PM UTC 24 |
| Finished | Aug 28 07:44:35 PM UTC 24 |
| Peak memory | 217080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059240077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2059240077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/46.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.1482243949 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 38666295964 ps |
| CPU time | 287.97 seconds |
| Started | Aug 28 07:44:05 PM UTC 24 |
| Finished | Aug 28 07:48:58 PM UTC 24 |
| Peak memory | 219072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482243949 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1482243949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/46.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.4057418681 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 10399452281 ps |
| CPU time | 88.64 seconds |
| Started | Aug 28 07:44:05 PM UTC 24 |
| Finished | Aug 28 07:45:36 PM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057418681 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.4057418681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/46.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.271855207 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 93986109 ps |
| CPU time | 11.89 seconds |
| Started | Aug 28 07:44:05 PM UTC 24 |
| Finished | Aug 28 07:44:18 PM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271855207 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.271855207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/46.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.1799056975 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 973784164 ps |
| CPU time | 28.79 seconds |
| Started | Aug 28 07:44:05 PM UTC 24 |
| Finished | Aug 28 07:44:35 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799056975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1799056975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/46.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.2285581894 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 158510444 ps |
| CPU time | 4.51 seconds |
| Started | Aug 28 07:43:57 PM UTC 24 |
| Finished | Aug 28 07:44:02 PM UTC 24 |
| Peak memory | 217032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285581894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2285581894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/46.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.4227817807 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 25208406050 ps |
| CPU time | 55.37 seconds |
| Started | Aug 28 07:44:00 PM UTC 24 |
| Finished | Aug 28 07:44:57 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227817807 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.4227817807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/46.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1836688996 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 5657530936 ps |
| CPU time | 42.76 seconds |
| Started | Aug 28 07:44:00 PM UTC 24 |
| Finished | Aug 28 07:44:44 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836688996 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1836688996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.2087905289 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 50276062 ps |
| CPU time | 3.26 seconds |
| Started | Aug 28 07:43:57 PM UTC 24 |
| Finished | Aug 28 07:44:01 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087905289 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.2087905289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/46.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.465511358 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 274401901 ps |
| CPU time | 34.22 seconds |
| Started | Aug 28 07:44:12 PM UTC 24 |
| Finished | Aug 28 07:44:48 PM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465511358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.465511358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/46.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.234401945 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 425922603 ps |
| CPU time | 57.27 seconds |
| Started | Aug 28 07:44:12 PM UTC 24 |
| Finished | Aug 28 07:45:11 PM UTC 24 |
| Peak memory | 217156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234401945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.234401945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/46.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.4199348635 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 108019495 ps |
| CPU time | 41.78 seconds |
| Started | Aug 28 07:44:12 PM UTC 24 |
| Finished | Aug 28 07:44:56 PM UTC 24 |
| Peak memory | 219204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199348635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.4199348635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2514347348 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 310333823 ps |
| CPU time | 115.87 seconds |
| Started | Aug 28 07:44:18 PM UTC 24 |
| Finished | Aug 28 07:46:17 PM UTC 24 |
| Peak memory | 223300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514347348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.2514347348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.2145649309 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 4554362998 ps |
| CPU time | 46.07 seconds |
| Started | Aug 28 07:44:12 PM UTC 24 |
| Finished | Aug 28 07:45:00 PM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145649309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2145649309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/46.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.2768830131 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 295367951 ps |
| CPU time | 16.73 seconds |
| Started | Aug 28 07:44:31 PM UTC 24 |
| Finished | Aug 28 07:44:49 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768830131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.2768830131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/47.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.122817620 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 29153462437 ps |
| CPU time | 277.13 seconds |
| Started | Aug 28 07:44:31 PM UTC 24 |
| Finished | Aug 28 07:49:13 PM UTC 24 |
| Peak memory | 219208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122817620 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.122817620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2704549203 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 1162446134 ps |
| CPU time | 11.74 seconds |
| Started | Aug 28 07:44:37 PM UTC 24 |
| Finished | Aug 28 07:44:50 PM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704549203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2704549203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1584925037 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 348839550 ps |
| CPU time | 6.01 seconds |
| Started | Aug 28 07:44:33 PM UTC 24 |
| Finished | Aug 28 07:44:40 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584925037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1584925037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/47.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.3121954403 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 328876288 ps |
| CPU time | 35.48 seconds |
| Started | Aug 28 07:44:26 PM UTC 24 |
| Finished | Aug 28 07:45:03 PM UTC 24 |
| Peak memory | 216472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121954403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.3121954403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/47.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.3616499094 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 16218190891 ps |
| CPU time | 131.18 seconds |
| Started | Aug 28 07:44:31 PM UTC 24 |
| Finished | Aug 28 07:46:45 PM UTC 24 |
| Peak memory | 216568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616499094 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3616499094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/47.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1391821749 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 35316629997 ps |
| CPU time | 303.01 seconds |
| Started | Aug 28 07:44:31 PM UTC 24 |
| Finished | Aug 28 07:49:39 PM UTC 24 |
| Peak memory | 216656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391821749 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1391821749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/47.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.3891635036 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 15028544 ps |
| CPU time | 3.38 seconds |
| Started | Aug 28 07:44:26 PM UTC 24 |
| Finished | Aug 28 07:44:30 PM UTC 24 |
| Peak memory | 217080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891635036 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.3891635036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/47.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.3683891490 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 2527988286 ps |
| CPU time | 22.51 seconds |
| Started | Aug 28 07:44:31 PM UTC 24 |
| Finished | Aug 28 07:44:55 PM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683891490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3683891490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/47.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.956290342 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 620003965 ps |
| CPU time | 5.9 seconds |
| Started | Aug 28 07:44:20 PM UTC 24 |
| Finished | Aug 28 07:44:27 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956290342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.956290342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/47.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1037368182 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 13248994348 ps |
| CPU time | 42.24 seconds |
| Started | Aug 28 07:44:23 PM UTC 24 |
| Finished | Aug 28 07:45:07 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037368182 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1037368182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/47.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.1229772830 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 2866642878 ps |
| CPU time | 32.71 seconds |
| Started | Aug 28 07:44:23 PM UTC 24 |
| Finished | Aug 28 07:44:57 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229772830 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1229772830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2264492236 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 101654564 ps |
| CPU time | 3.14 seconds |
| Started | Aug 28 07:44:20 PM UTC 24 |
| Finished | Aug 28 07:44:24 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264492236 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.2264492236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/47.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.2451362963 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 3873403305 ps |
| CPU time | 160.02 seconds |
| Started | Aug 28 07:44:37 PM UTC 24 |
| Finished | Aug 28 07:47:20 PM UTC 24 |
| Peak memory | 220988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451362963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2451362963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/47.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.4186584159 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 14986571992 ps |
| CPU time | 268.33 seconds |
| Started | Aug 28 07:44:43 PM UTC 24 |
| Finished | Aug 28 07:49:16 PM UTC 24 |
| Peak memory | 223668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186584159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.4186584159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/47.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3652796619 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 10782919976 ps |
| CPU time | 224.29 seconds |
| Started | Aug 28 07:44:39 PM UTC 24 |
| Finished | Aug 28 07:48:27 PM UTC 24 |
| Peak memory | 221004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652796619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.3652796619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1959040031 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 837766201 ps |
| CPU time | 228.53 seconds |
| Started | Aug 28 07:44:44 PM UTC 24 |
| Finished | Aug 28 07:48:38 PM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959040031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.1959040031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.862610961 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 126678011 ps |
| CPU time | 23.1 seconds |
| Started | Aug 28 07:44:37 PM UTC 24 |
| Finished | Aug 28 07:45:01 PM UTC 24 |
| Peak memory | 218892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862610961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.862610961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/47.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.1989517818 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 90327590 ps |
| CPU time | 4.21 seconds |
| Started | Aug 28 07:44:58 PM UTC 24 |
| Finished | Aug 28 07:45:04 PM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989517818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.1989517818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/48.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3337997288 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 69011362793 ps |
| CPU time | 613.04 seconds |
| Started | Aug 28 07:44:58 PM UTC 24 |
| Finished | Aug 28 07:55:20 PM UTC 24 |
| Peak memory | 219276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337997288 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.3337997288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.2281458476 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 808270631 ps |
| CPU time | 21.27 seconds |
| Started | Aug 28 07:45:09 PM UTC 24 |
| Finished | Aug 28 07:45:32 PM UTC 24 |
| Peak memory | 216040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281458476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.2281458476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.2100146988 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 300254370 ps |
| CPU time | 20.08 seconds |
| Started | Aug 28 07:45:03 PM UTC 24 |
| Finished | Aug 28 07:45:24 PM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100146988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2100146988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/48.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.2401682663 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 144407163 ps |
| CPU time | 14.3 seconds |
| Started | Aug 28 07:44:53 PM UTC 24 |
| Finished | Aug 28 07:45:09 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401682663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.2401682663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/48.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.3647194616 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 51215932157 ps |
| CPU time | 212.02 seconds |
| Started | Aug 28 07:44:56 PM UTC 24 |
| Finished | Aug 28 07:48:32 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647194616 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3647194616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/48.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3586170847 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 20279773894 ps |
| CPU time | 172.75 seconds |
| Started | Aug 28 07:44:58 PM UTC 24 |
| Finished | Aug 28 07:47:54 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586170847 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3586170847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/48.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.3838152940 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 82756575 ps |
| CPU time | 4.31 seconds |
| Started | Aug 28 07:44:54 PM UTC 24 |
| Finished | Aug 28 07:44:59 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838152940 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.3838152940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/48.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.651258682 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 277528484 ps |
| CPU time | 8.74 seconds |
| Started | Aug 28 07:45:03 PM UTC 24 |
| Finished | Aug 28 07:45:13 PM UTC 24 |
| Peak memory | 217084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651258682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.651258682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/48.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.2236387920 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 438151145 ps |
| CPU time | 5.67 seconds |
| Started | Aug 28 07:44:46 PM UTC 24 |
| Finished | Aug 28 07:44:53 PM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236387920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2236387920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/48.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3065045392 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 3743348208 ps |
| CPU time | 35.69 seconds |
| Started | Aug 28 07:44:49 PM UTC 24 |
| Finished | Aug 28 07:45:26 PM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065045392 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3065045392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/48.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.398529621 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 10401851691 ps |
| CPU time | 49.7 seconds |
| Started | Aug 28 07:44:53 PM UTC 24 |
| Finished | Aug 28 07:45:45 PM UTC 24 |
| Peak memory | 217200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398529621 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.398529621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2776686923 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 49756677 ps |
| CPU time | 3.32 seconds |
| Started | Aug 28 07:44:46 PM UTC 24 |
| Finished | Aug 28 07:44:51 PM UTC 24 |
| Peak memory | 217068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776686923 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2776686923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/48.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.2310052113 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 2077378116 ps |
| CPU time | 54.85 seconds |
| Started | Aug 28 07:45:09 PM UTC 24 |
| Finished | Aug 28 07:46:06 PM UTC 24 |
| Peak memory | 218796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310052113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2310052113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/48.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1816779841 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 1047494350 ps |
| CPU time | 104.37 seconds |
| Started | Aug 28 07:45:09 PM UTC 24 |
| Finished | Aug 28 07:46:56 PM UTC 24 |
| Peak memory | 219140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816779841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1816779841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/48.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2288371984 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 10789195598 ps |
| CPU time | 653.44 seconds |
| Started | Aug 28 07:45:09 PM UTC 24 |
| Finished | Aug 28 07:56:12 PM UTC 24 |
| Peak memory | 222600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288371984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.2288371984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.4020489211 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 128635118 ps |
| CPU time | 23.15 seconds |
| Started | Aug 28 07:45:10 PM UTC 24 |
| Finished | Aug 28 07:45:34 PM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020489211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.4020489211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.3109707482 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 598798316 ps |
| CPU time | 15.19 seconds |
| Started | Aug 28 07:45:03 PM UTC 24 |
| Finished | Aug 28 07:45:19 PM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109707482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3109707482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/48.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.980487804 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 317928373 ps |
| CPU time | 12.9 seconds |
| Started | Aug 28 07:45:13 PM UTC 24 |
| Finished | Aug 28 07:45:28 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980487804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.980487804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/49.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3352242580 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 128109278174 ps |
| CPU time | 825.29 seconds |
| Started | Aug 28 07:45:16 PM UTC 24 |
| Finished | Aug 28 07:59:13 PM UTC 24 |
| Peak memory | 219276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352242580 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.3352242580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.87249520 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1613248733 ps |
| CPU time | 20.69 seconds |
| Started | Aug 28 07:45:25 PM UTC 24 |
| Finished | Aug 28 07:45:47 PM UTC 24 |
| Peak memory | 217084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87249520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.87249520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.3245426418 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 99933787 ps |
| CPU time | 13.98 seconds |
| Started | Aug 28 07:45:17 PM UTC 24 |
| Finished | Aug 28 07:45:32 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245426418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3245426418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/49.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.3230056766 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 189021408 ps |
| CPU time | 10.17 seconds |
| Started | Aug 28 07:45:13 PM UTC 24 |
| Finished | Aug 28 07:45:25 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230056766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.3230056766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/49.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.784939252 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 145497879358 ps |
| CPU time | 222.89 seconds |
| Started | Aug 28 07:45:13 PM UTC 24 |
| Finished | Aug 28 07:49:00 PM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784939252 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.784939252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/49.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2415117141 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 18306282269 ps |
| CPU time | 85.73 seconds |
| Started | Aug 28 07:45:13 PM UTC 24 |
| Finished | Aug 28 07:46:41 PM UTC 24 |
| Peak memory | 216964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415117141 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2415117141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/49.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.1652357048 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 65732463 ps |
| CPU time | 8.78 seconds |
| Started | Aug 28 07:45:13 PM UTC 24 |
| Finished | Aug 28 07:45:23 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652357048 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.1652357048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/49.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.3327425908 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 5847831855 ps |
| CPU time | 40.66 seconds |
| Started | Aug 28 07:45:16 PM UTC 24 |
| Finished | Aug 28 07:45:59 PM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327425908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3327425908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/49.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.75337222 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 33405614 ps |
| CPU time | 2.79 seconds |
| Started | Aug 28 07:45:10 PM UTC 24 |
| Finished | Aug 28 07:45:13 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75337222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.75337222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/49.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.162130022 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 5676575717 ps |
| CPU time | 50.35 seconds |
| Started | Aug 28 07:45:10 PM UTC 24 |
| Finished | Aug 28 07:46:02 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162130022 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.162130022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/49.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.332196097 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3736186339 ps |
| CPU time | 38.59 seconds |
| Started | Aug 28 07:45:10 PM UTC 24 |
| Finished | Aug 28 07:45:50 PM UTC 24 |
| Peak memory | 216752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332196097 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.332196097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2726138604 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 106066937 ps |
| CPU time | 3.82 seconds |
| Started | Aug 28 07:45:10 PM UTC 24 |
| Finished | Aug 28 07:45:15 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726138604 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.2726138604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/49.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.2049122392 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 5721617808 ps |
| CPU time | 240.83 seconds |
| Started | Aug 28 07:45:28 PM UTC 24 |
| Finished | Aug 28 07:49:32 PM UTC 24 |
| Peak memory | 220988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049122392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2049122392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/49.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.581278120 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 14756872696 ps |
| CPU time | 238.86 seconds |
| Started | Aug 28 07:45:31 PM UTC 24 |
| Finished | Aug 28 07:49:34 PM UTC 24 |
| Peak memory | 218940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581278120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.581278120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/49.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3596024156 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 4852526635 ps |
| CPU time | 614.57 seconds |
| Started | Aug 28 07:45:28 PM UTC 24 |
| Finished | Aug 28 07:55:52 PM UTC 24 |
| Peak memory | 233656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596024156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.3596024156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.950758268 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 1296036715 ps |
| CPU time | 128.23 seconds |
| Started | Aug 28 07:45:31 PM UTC 24 |
| Finished | Aug 28 07:47:42 PM UTC 24 |
| Peak memory | 220944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950758268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.950758268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.1154012011 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 845498635 ps |
| CPU time | 33.93 seconds |
| Started | Aug 28 07:45:21 PM UTC 24 |
| Finished | Aug 28 07:45:57 PM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154012011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1154012011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/49.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.4238971847 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 310100759 ps |
| CPU time | 39.95 seconds |
| Started | Aug 28 07:23:31 PM UTC 24 |
| Finished | Aug 28 07:24:12 PM UTC 24 |
| Peak memory | 219140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238971847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.4238971847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/5.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2101728214 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 57165910891 ps |
| CPU time | 445.17 seconds |
| Started | Aug 28 07:23:31 PM UTC 24 |
| Finished | Aug 28 07:31:03 PM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101728214 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.2101728214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.863857335 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 639478165 ps |
| CPU time | 21.97 seconds |
| Started | Aug 28 07:23:37 PM UTC 24 |
| Finished | Aug 28 07:24:00 PM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863857335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.863857335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.3076563244 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1201626222 ps |
| CPU time | 28.14 seconds |
| Started | Aug 28 07:23:33 PM UTC 24 |
| Finished | Aug 28 07:24:02 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076563244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3076563244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/5.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random.3257857709 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 769343284 ps |
| CPU time | 31.28 seconds |
| Started | Aug 28 07:23:30 PM UTC 24 |
| Finished | Aug 28 07:24:03 PM UTC 24 |
| Peak memory | 217148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257857709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.3257857709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/5.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.4140143489 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 196452709076 ps |
| CPU time | 348.96 seconds |
| Started | Aug 28 07:23:30 PM UTC 24 |
| Finished | Aug 28 07:29:24 PM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140143489 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.4140143489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/5.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.3202560459 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 6688297517 ps |
| CPU time | 60.99 seconds |
| Started | Aug 28 07:23:30 PM UTC 24 |
| Finished | Aug 28 07:24:33 PM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202560459 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3202560459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/5.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.3041234986 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 31192420 ps |
| CPU time | 4.89 seconds |
| Started | Aug 28 07:23:30 PM UTC 24 |
| Finished | Aug 28 07:23:36 PM UTC 24 |
| Peak memory | 217148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041234986 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3041234986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/5.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.328710016 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 643456960 ps |
| CPU time | 20.38 seconds |
| Started | Aug 28 07:23:32 PM UTC 24 |
| Finished | Aug 28 07:23:54 PM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328710016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.328710016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/5.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.80415647 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 133358567 ps |
| CPU time | 4.28 seconds |
| Started | Aug 28 07:23:23 PM UTC 24 |
| Finished | Aug 28 07:23:28 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80415647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.80415647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/5.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.3201632718 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 15703080544 ps |
| CPU time | 60.66 seconds |
| Started | Aug 28 07:23:26 PM UTC 24 |
| Finished | Aug 28 07:24:29 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201632718 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3201632718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/5.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1444476248 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 3130776506 ps |
| CPU time | 30.9 seconds |
| Started | Aug 28 07:23:26 PM UTC 24 |
| Finished | Aug 28 07:23:59 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444476248 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1444476248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.1825689380 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 112673753 ps |
| CPU time | 3 seconds |
| Started | Aug 28 07:23:24 PM UTC 24 |
| Finished | Aug 28 07:23:28 PM UTC 24 |
| Peak memory | 216800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825689380 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.1825689380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/5.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3257495642 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 168777682 ps |
| CPU time | 103.16 seconds |
| Started | Aug 28 07:23:39 PM UTC 24 |
| Finished | Aug 28 07:25:24 PM UTC 24 |
| Peak memory | 220932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257495642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.3257495642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.2587609444 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 3151465387 ps |
| CPU time | 271.73 seconds |
| Started | Aug 28 07:23:44 PM UTC 24 |
| Finished | Aug 28 07:28:20 PM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587609444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.2587609444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.1069281854 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 228444091 ps |
| CPU time | 25.21 seconds |
| Started | Aug 28 07:23:36 PM UTC 24 |
| Finished | Aug 28 07:24:02 PM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069281854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1069281854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/5.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.2815887846 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 321345990 ps |
| CPU time | 35.94 seconds |
| Started | Aug 28 07:23:56 PM UTC 24 |
| Finished | Aug 28 07:24:33 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815887846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2815887846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/6.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.134008800 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 6969087001 ps |
| CPU time | 54.59 seconds |
| Started | Aug 28 07:23:58 PM UTC 24 |
| Finished | Aug 28 07:24:54 PM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134008800 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.134008800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.896071790 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 145301672 ps |
| CPU time | 22.89 seconds |
| Started | Aug 28 07:24:03 PM UTC 24 |
| Finished | Aug 28 07:24:28 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896071790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.896071790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.1588845318 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 1754693073 ps |
| CPU time | 19.5 seconds |
| Started | Aug 28 07:24:01 PM UTC 24 |
| Finished | Aug 28 07:24:22 PM UTC 24 |
| Peak memory | 217020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588845318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1588845318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/6.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random.4213079717 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1369760864 ps |
| CPU time | 13.89 seconds |
| Started | Aug 28 07:23:51 PM UTC 24 |
| Finished | Aug 28 07:24:06 PM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213079717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.4213079717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/6.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.1927961986 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 127196112029 ps |
| CPU time | 378.83 seconds |
| Started | Aug 28 07:23:51 PM UTC 24 |
| Finished | Aug 28 07:30:16 PM UTC 24 |
| Peak memory | 218944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927961986 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1927961986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/6.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3369110801 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 32750795383 ps |
| CPU time | 265.92 seconds |
| Started | Aug 28 07:23:54 PM UTC 24 |
| Finished | Aug 28 07:28:25 PM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369110801 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3369110801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/6.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.3593746404 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 223052370 ps |
| CPU time | 17.49 seconds |
| Started | Aug 28 07:23:51 PM UTC 24 |
| Finished | Aug 28 07:24:10 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593746404 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3593746404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/6.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.3323810947 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 147913780 ps |
| CPU time | 13.12 seconds |
| Started | Aug 28 07:24:00 PM UTC 24 |
| Finished | Aug 28 07:24:14 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323810947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3323810947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/6.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.3999801058 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 110442646 ps |
| CPU time | 4.99 seconds |
| Started | Aug 28 07:23:44 PM UTC 24 |
| Finished | Aug 28 07:23:50 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999801058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3999801058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/6.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.1648463115 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 6772565818 ps |
| CPU time | 52.08 seconds |
| Started | Aug 28 07:23:51 PM UTC 24 |
| Finished | Aug 28 07:24:45 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648463115 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1648463115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/6.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.839821015 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 13758179346 ps |
| CPU time | 42.92 seconds |
| Started | Aug 28 07:23:51 PM UTC 24 |
| Finished | Aug 28 07:24:36 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839821015 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.839821015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2307055412 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 100602824 ps |
| CPU time | 3.55 seconds |
| Started | Aug 28 07:23:46 PM UTC 24 |
| Finished | Aug 28 07:23:51 PM UTC 24 |
| Peak memory | 216800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307055412 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2307055412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/6.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.945014287 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 2344707010 ps |
| CPU time | 84.41 seconds |
| Started | Aug 28 07:24:03 PM UTC 24 |
| Finished | Aug 28 07:25:30 PM UTC 24 |
| Peak memory | 218940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945014287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.945014287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/6.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.3155738719 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1274381399 ps |
| CPU time | 101.77 seconds |
| Started | Aug 28 07:24:07 PM UTC 24 |
| Finished | Aug 28 07:25:51 PM UTC 24 |
| Peak memory | 218824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155738719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3155738719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/6.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.3011655585 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 309912347 ps |
| CPU time | 75.05 seconds |
| Started | Aug 28 07:24:11 PM UTC 24 |
| Finished | Aug 28 07:25:28 PM UTC 24 |
| Peak memory | 221192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011655585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.3011655585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.686689470 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1261388883 ps |
| CPU time | 40.43 seconds |
| Started | Aug 28 07:24:03 PM UTC 24 |
| Finished | Aug 28 07:24:45 PM UTC 24 |
| Peak memory | 218876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686689470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.686689470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/6.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.1765999280 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1295686435 ps |
| CPU time | 40.71 seconds |
| Started | Aug 28 07:24:30 PM UTC 24 |
| Finished | Aug 28 07:25:12 PM UTC 24 |
| Peak memory | 218816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765999280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1765999280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/7.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.1420411142 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 27405907867 ps |
| CPU time | 318.31 seconds |
| Started | Aug 28 07:24:36 PM UTC 24 |
| Finished | Aug 28 07:30:01 PM UTC 24 |
| Peak memory | 219212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420411142 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.1420411142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.4046582007 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 245592685 ps |
| CPU time | 14.26 seconds |
| Started | Aug 28 07:24:39 PM UTC 24 |
| Finished | Aug 28 07:24:54 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046582007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.4046582007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.2576565468 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 801927212 ps |
| CPU time | 30.81 seconds |
| Started | Aug 28 07:24:36 PM UTC 24 |
| Finished | Aug 28 07:25:09 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576565468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2576565468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/7.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random.2303421691 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 901369002 ps |
| CPU time | 36.73 seconds |
| Started | Aug 28 07:24:22 PM UTC 24 |
| Finished | Aug 28 07:25:01 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303421691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.2303421691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/7.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.763465424 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 27667380383 ps |
| CPU time | 210.11 seconds |
| Started | Aug 28 07:24:27 PM UTC 24 |
| Finished | Aug 28 07:28:01 PM UTC 24 |
| Peak memory | 219004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763465424 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.763465424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/7.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.510690866 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 22696735334 ps |
| CPU time | 193.95 seconds |
| Started | Aug 28 07:24:30 PM UTC 24 |
| Finished | Aug 28 07:27:47 PM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510690866 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.510690866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/7.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.2159747391 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 464516005 ps |
| CPU time | 30.48 seconds |
| Started | Aug 28 07:24:24 PM UTC 24 |
| Finished | Aug 28 07:24:56 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159747391 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.2159747391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/7.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.3310172982 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 313073839 ps |
| CPU time | 18.14 seconds |
| Started | Aug 28 07:24:36 PM UTC 24 |
| Finished | Aug 28 07:24:56 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310172982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3310172982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/7.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.654689892 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 88612314 ps |
| CPU time | 3.32 seconds |
| Started | Aug 28 07:24:13 PM UTC 24 |
| Finished | Aug 28 07:24:17 PM UTC 24 |
| Peak memory | 216752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654689892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.654689892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/7.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2915683011 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 8378183903 ps |
| CPU time | 48.06 seconds |
| Started | Aug 28 07:24:18 PM UTC 24 |
| Finished | Aug 28 07:25:08 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915683011 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2915683011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/7.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.2856443541 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 9791209595 ps |
| CPU time | 47.18 seconds |
| Started | Aug 28 07:24:20 PM UTC 24 |
| Finished | Aug 28 07:25:09 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856443541 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2856443541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.306549883 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 86348759 ps |
| CPU time | 3.31 seconds |
| Started | Aug 28 07:24:15 PM UTC 24 |
| Finished | Aug 28 07:24:19 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306549883 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.306549883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/7.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.2931392439 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1785377366 ps |
| CPU time | 68.17 seconds |
| Started | Aug 28 07:24:39 PM UTC 24 |
| Finished | Aug 28 07:25:49 PM UTC 24 |
| Peak memory | 218812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931392439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2931392439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/7.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1602042717 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 3449223214 ps |
| CPU time | 83.83 seconds |
| Started | Aug 28 07:24:46 PM UTC 24 |
| Finished | Aug 28 07:26:12 PM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602042717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1602042717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/7.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.4247247817 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 479032719 ps |
| CPU time | 180.13 seconds |
| Started | Aug 28 07:24:46 PM UTC 24 |
| Finished | Aug 28 07:27:50 PM UTC 24 |
| Peak memory | 220868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247247817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.4247247817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3089472504 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 718647828 ps |
| CPU time | 141.86 seconds |
| Started | Aug 28 07:24:50 PM UTC 24 |
| Finished | Aug 28 07:27:15 PM UTC 24 |
| Peak memory | 222980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089472504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.3089472504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.4257523616 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 253678831 ps |
| CPU time | 10.86 seconds |
| Started | Aug 28 07:24:36 PM UTC 24 |
| Finished | Aug 28 07:24:49 PM UTC 24 |
| Peak memory | 217156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257523616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.4257523616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/7.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.4293672510 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 468888176 ps |
| CPU time | 28.71 seconds |
| Started | Aug 28 07:25:08 PM UTC 24 |
| Finished | Aug 28 07:25:38 PM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293672510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.4293672510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/8.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.263302884 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 170167606806 ps |
| CPU time | 586.02 seconds |
| Started | Aug 28 07:25:09 PM UTC 24 |
| Finished | Aug 28 07:35:03 PM UTC 24 |
| Peak memory | 219140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263302884 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.263302884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.297546642 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 439675106 ps |
| CPU time | 24.46 seconds |
| Started | Aug 28 07:25:13 PM UTC 24 |
| Finished | Aug 28 07:25:39 PM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297546642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.297546642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.2870496885 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 267719893 ps |
| CPU time | 11.25 seconds |
| Started | Aug 28 07:25:10 PM UTC 24 |
| Finished | Aug 28 07:25:23 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870496885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2870496885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/8.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random.2752568188 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 283194127 ps |
| CPU time | 8.57 seconds |
| Started | Aug 28 07:24:57 PM UTC 24 |
| Finished | Aug 28 07:25:07 PM UTC 24 |
| Peak memory | 217084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752568188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.2752568188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/8.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.2499845058 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 30774331544 ps |
| CPU time | 220.8 seconds |
| Started | Aug 28 07:25:01 PM UTC 24 |
| Finished | Aug 28 07:28:46 PM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499845058 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2499845058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/8.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.1015142339 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 125012731855 ps |
| CPU time | 357.4 seconds |
| Started | Aug 28 07:25:02 PM UTC 24 |
| Finished | Aug 28 07:31:04 PM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015142339 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1015142339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/8.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.2123173022 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 271953360 ps |
| CPU time | 26.7 seconds |
| Started | Aug 28 07:25:01 PM UTC 24 |
| Finished | Aug 28 07:25:29 PM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123173022 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.2123173022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/8.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.106063713 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1208018158 ps |
| CPU time | 37.09 seconds |
| Started | Aug 28 07:25:09 PM UTC 24 |
| Finished | Aug 28 07:25:48 PM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106063713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.106063713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/8.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.575476066 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 108019063 ps |
| CPU time | 3.5 seconds |
| Started | Aug 28 07:24:55 PM UTC 24 |
| Finished | Aug 28 07:25:00 PM UTC 24 |
| Peak memory | 216752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575476066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.575476066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/8.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.1833734303 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 5141344083 ps |
| CPU time | 43.28 seconds |
| Started | Aug 28 07:24:57 PM UTC 24 |
| Finished | Aug 28 07:25:42 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833734303 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1833734303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/8.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2244010345 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 2815026910 ps |
| CPU time | 33.1 seconds |
| Started | Aug 28 07:24:57 PM UTC 24 |
| Finished | Aug 28 07:25:32 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244010345 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2244010345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.948526420 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 32719415 ps |
| CPU time | 3.18 seconds |
| Started | Aug 28 07:24:55 PM UTC 24 |
| Finished | Aug 28 07:24:59 PM UTC 24 |
| Peak memory | 216804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948526420 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.948526420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/8.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.349930591 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1033066823 ps |
| CPU time | 162.64 seconds |
| Started | Aug 28 07:25:21 PM UTC 24 |
| Finished | Aug 28 07:28:08 PM UTC 24 |
| Peak memory | 220868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349930591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.349930591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/8.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.3742292884 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 3134660942 ps |
| CPU time | 113.03 seconds |
| Started | Aug 28 07:25:26 PM UTC 24 |
| Finished | Aug 28 07:27:21 PM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742292884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3742292884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/8.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.1454544728 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 13550216790 ps |
| CPU time | 724.52 seconds |
| Started | Aug 28 07:25:23 PM UTC 24 |
| Finished | Aug 28 07:37:39 PM UTC 24 |
| Peak memory | 233596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454544728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.1454544728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2797927877 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1572456829 ps |
| CPU time | 312.27 seconds |
| Started | Aug 28 07:25:27 PM UTC 24 |
| Finished | Aug 28 07:30:45 PM UTC 24 |
| Peak memory | 233524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797927877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.2797927877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.1637401304 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 957569816 ps |
| CPU time | 30.4 seconds |
| Started | Aug 28 07:25:10 PM UTC 24 |
| Finished | Aug 28 07:25:42 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637401304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1637401304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/8.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.1117840498 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 767642684 ps |
| CPU time | 22.16 seconds |
| Started | Aug 28 07:25:39 PM UTC 24 |
| Finished | Aug 28 07:26:02 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117840498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1117840498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/9.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.130386984 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 44006784 ps |
| CPU time | 3.36 seconds |
| Started | Aug 28 07:25:46 PM UTC 24 |
| Finished | Aug 28 07:25:50 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130386984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.130386984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.2812033695 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1031101704 ps |
| CPU time | 17.93 seconds |
| Started | Aug 28 07:25:43 PM UTC 24 |
| Finished | Aug 28 07:26:02 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812033695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2812033695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/9.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random.4076228129 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 509085210 ps |
| CPU time | 19.62 seconds |
| Started | Aug 28 07:25:36 PM UTC 24 |
| Finished | Aug 28 07:25:57 PM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076228129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.4076228129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/9.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.4037388436 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 11741535232 ps |
| CPU time | 85.64 seconds |
| Started | Aug 28 07:25:37 PM UTC 24 |
| Finished | Aug 28 07:27:05 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037388436 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.4037388436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/9.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.3060352066 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 28175839568 ps |
| CPU time | 139.56 seconds |
| Started | Aug 28 07:25:38 PM UTC 24 |
| Finished | Aug 28 07:28:00 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060352066 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3060352066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/9.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.4086288785 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 63503188 ps |
| CPU time | 7.42 seconds |
| Started | Aug 28 07:25:36 PM UTC 24 |
| Finished | Aug 28 07:25:45 PM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086288785 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.4086288785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/9.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.1785293255 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1458779062 ps |
| CPU time | 34.9 seconds |
| Started | Aug 28 07:25:40 PM UTC 24 |
| Finished | Aug 28 07:26:16 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785293255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1785293255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/9.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.2153411551 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 237628173 ps |
| CPU time | 5.53 seconds |
| Started | Aug 28 07:25:29 PM UTC 24 |
| Finished | Aug 28 07:25:36 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153411551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2153411551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/9.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.4292463952 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 5746690138 ps |
| CPU time | 38.92 seconds |
| Started | Aug 28 07:25:31 PM UTC 24 |
| Finished | Aug 28 07:26:12 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292463952 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.4292463952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/9.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.3241518774 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 7600007951 ps |
| CPU time | 46.38 seconds |
| Started | Aug 28 07:25:33 PM UTC 24 |
| Finished | Aug 28 07:26:21 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241518774 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3241518774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.2344691860 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 34764212 ps |
| CPU time | 3.59 seconds |
| Started | Aug 28 07:25:30 PM UTC 24 |
| Finished | Aug 28 07:25:35 PM UTC 24 |
| Peak memory | 216800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344691860 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2344691860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/9.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.4011256282 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 488971037 ps |
| CPU time | 76.23 seconds |
| Started | Aug 28 07:25:47 PM UTC 24 |
| Finished | Aug 28 07:27:06 PM UTC 24 |
| Peak memory | 219136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011256282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.4011256282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/9.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.2888458545 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 6181869726 ps |
| CPU time | 138.44 seconds |
| Started | Aug 28 07:25:48 PM UTC 24 |
| Finished | Aug 28 07:28:10 PM UTC 24 |
| Peak memory | 218956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888458545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2888458545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/9.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.740649166 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 976646428 ps |
| CPU time | 199.56 seconds |
| Started | Aug 28 07:25:49 PM UTC 24 |
| Finished | Aug 28 07:29:13 PM UTC 24 |
| Peak memory | 222924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740649166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.740649166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.2013602040 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 46048747 ps |
| CPU time | 9.66 seconds |
| Started | Aug 28 07:25:43 PM UTC 24 |
| Finished | Aug 28 07:25:54 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013602040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2013602040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/9.xbar_unmapped_addr/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |