Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1752	1			T14	4		T50	3		T20	4
all_values[1]	1858	1			T14	2		T50	2		T20	3
all_values[2]	1733	1			T14	6		T47	1		T50	2
all_values[3]	1772	1			T14	2		T50	1		T20	2
all_values[4]	1801	1			T14	2		T47	2		T50	1
all_values[5]	1765	1			T14	2		T47	2		T50	3
all_values[6]	1765	1			T14	4		T47	1		T50	4
all_values[7]	1752	1			T14	2		T47	3		T20	4
all_values[8]	1828	1			T14	6		T47	2		T50	3
all_values[9]	1883	1			T14	1		T47	1		T50	4
all_values[10]	1786	1			T47	1		T50	1		T20	2
all_values[11]	1781	1			T14	4		T47	3		T50	4
all_values[12]	1773	1			T14	6		T47	2		T50	1
all_values[13]	1706	1			T14	3		T47	1		T50	3
all_values[14]	1795	1			T14	2		T47	1		T50	3
all_values[15]	1797	1			T14	2		T47	1		T20	5
all_values[16]	1820	1			T14	5		T47	1		T50	2
all_values[17]	1850	1			T14	2		T50	3		T20	1
all_values[18]	1799	1			T14	2		T47	1		T50	2
all_values[19]	1755	1			T14	1		T50	2		T20	2
all_values[20]	1780	1			T14	4		T47	1		T20	1
all_values[21]	1764	1			T14	2		T47	2		T50	5
all_values[22]	1801	1			T14	1		T47	2		T50	1
all_values[23]	1807	1			T14	2		T47	3		T50	3
all_values[24]	1703	1			T14	3		T47	1		T50	2
all_values[25]	1782	1			T14	4		T47	3		T50	3
all_values[26]	1793	1			T14	2		T47	3		T50	3
all_values[27]	1758	1			T14	7		T47	2		T20	3
all_values[28]	1810	1			T14	8		T47	2		T50	1
all_values[29]	1786	1			T14	4		T47	2		T20	7
all_values[30]	1782	1			T47	1		T50	2		T20	4
all_values[31]	1879	1			T14	3		T50	4		T20	1
all_values[32]	1765	1			T14	2		T47	1		T50	2
all_values[33]	1688	1			T14	2		T47	3		T50	1
all_values[34]	1864	1			T14	2		T47	2		T50	3
all_values[35]	1819	1			T14	2		T47	1		T50	5
all_values[36]	1854	1			T14	4		T47	2		T50	6
all_values[37]	1792	1			T14	2		T47	1		T50	1
all_values[38]	1716	1			T14	4		T47	3		T50	1
all_values[39]	1749	1			T14	1		T47	1		T50	2
all_values[40]	1802	1			T14	3		T50	2		T20	3
all_values[41]	1789	1			T14	3		T50	3		T20	4
all_values[42]	1727	1			T14	1		T50	1		T20	4
all_values[43]	1744	1			T14	3		T47	1		T50	4
all_values[44]	1793	1			T14	5		T50	3		T20	3
all_values[45]	1781	1			T14	1		T47	3		T50	2
all_values[46]	1805	1			T14	3		T47	3		T50	1
all_values[47]	1790	1			T14	2		T47	5		T50	3
all_values[48]	1764	1			T14	3		T50	5		T20	3
all_values[49]	1781	1			T14	3		T50	1		T20	1
all_values[50]	1754	1			T47	6		T50	5		T20	7
all_values[51]	1792	1			T14	1		T47	1		T20	1
all_values[52]	1848	1			T47	1		T50	1		T20	3
all_values[53]	1743	1			T14	5		T50	3		T20	3
all_values[54]	1740	1			T14	3		T47	2		T50	2
all_values[55]	1731	1			T14	3		T50	2		T20	4
all_values[56]	1797	1			T14	2		T50	3		T20	1
all_values[57]	1756	1			T14	5		T50	2		T20	1
all_values[58]	1801	1			T14	4		T47	2		T50	3
all_values[59]	1855	1			T14	3		T47	2		T50	2
all_values[60]	1774	1			T14	7		T47	1		T50	2
all_values[61]	1836	1			T14	3		T47	1		T50	4
all_values[62]	1840	1			T14	5		T47	2		T50	2
all_values[63]	1776	1			T14	3		T47	3		T50	5