Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.02	99.26	88.92	98.80		95.88	99.26	100.00

Total test records in report: 900

T768	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2703706130	Sep 01 06:03:58 AM UTC 24	Sep 01 06:04:47 AM UTC 24	5957613963 ps
T769	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.2370601399	Sep 01 06:04:30 AM UTC 24	Sep 01 06:04:49 AM UTC 24	526890696 ps
T770	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.3798194719	Sep 01 06:00:16 AM UTC 24	Sep 01 06:04:49 AM UTC 24	103079268690 ps
T771	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.679900263	Sep 01 06:03:57 AM UTC 24	Sep 01 06:04:51 AM UTC 24	13542298390 ps
T286	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.2278101592	Sep 01 06:04:28 AM UTC 24	Sep 01 06:04:51 AM UTC 24	2239344826 ps
T772	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3400832407	Sep 01 06:03:45 AM UTC 24	Sep 01 06:04:52 AM UTC 24	186920565 ps
T773	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2350120616	Sep 01 06:04:49 AM UTC 24	Sep 01 06:04:52 AM UTC 24	24378391 ps
T774	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.839617934	Sep 01 05:58:21 AM UTC 24	Sep 01 06:04:53 AM UTC 24	8786316625 ps
T775	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.3797108315	Sep 01 06:04:49 AM UTC 24	Sep 01 06:04:54 AM UTC 24	185199763 ps
T776	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.330245492	Sep 01 06:04:40 AM UTC 24	Sep 01 06:04:55 AM UTC 24	362678766 ps
T777	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.22675610	Sep 01 06:04:42 AM UTC 24	Sep 01 06:04:56 AM UTC 24	519322205 ps
T778	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.1955279967	Sep 01 06:04:32 AM UTC 24	Sep 01 06:04:57 AM UTC 24	677460176 ps
T779	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.3796251065	Sep 01 06:04:40 AM UTC 24	Sep 01 06:04:58 AM UTC 24	604034470 ps
T780	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.2586832801	Sep 01 06:04:52 AM UTC 24	Sep 01 06:05:01 AM UTC 24	68489795 ps
T781	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.2197037710	Sep 01 06:04:40 AM UTC 24	Sep 01 06:05:01 AM UTC 24	373197361 ps
T782	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.1597487478	Sep 01 05:56:43 AM UTC 24	Sep 01 06:05:02 AM UTC 24	46932607652 ps
T783	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.4230467856	Sep 01 06:04:52 AM UTC 24	Sep 01 06:05:02 AM UTC 24	78329732 ps
T784	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.2339292163	Sep 01 06:04:58 AM UTC 24	Sep 01 06:05:05 AM UTC 24	92265730 ps
T785	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.939370765	Sep 01 06:04:28 AM UTC 24	Sep 01 06:05:06 AM UTC 24	3618230967 ps
T786	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.2951582730	Sep 01 06:04:25 AM UTC 24	Sep 01 06:05:09 AM UTC 24	5130738854 ps
T787	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.370577951	Sep 01 06:05:07 AM UTC 24	Sep 01 06:05:11 AM UTC 24	27322022 ps
T788	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.3814861109	Sep 01 06:05:07 AM UTC 24	Sep 01 06:05:12 AM UTC 24	118662820 ps
T789	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3763817264	Sep 01 06:04:58 AM UTC 24	Sep 01 06:05:13 AM UTC 24	355986931 ps
T790	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.162298252	Sep 01 05:58:33 AM UTC 24	Sep 01 06:05:14 AM UTC 24	34456563230 ps
T791	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.1648058530	Sep 01 06:01:49 AM UTC 24	Sep 01 06:05:14 AM UTC 24	8938093234 ps
T792	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.1954263988	Sep 01 06:04:58 AM UTC 24	Sep 01 06:05:21 AM UTC 24	782340135 ps
T793	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.359454664	Sep 01 06:05:14 AM UTC 24	Sep 01 06:05:25 AM UTC 24	264744457 ps
T794	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2440945756	Sep 01 06:04:21 AM UTC 24	Sep 01 06:05:26 AM UTC 24	70789437 ps
T795	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1872311657	Sep 01 06:05:00 AM UTC 24	Sep 01 06:05:26 AM UTC 24	1954628702 ps
T796	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.3234364356	Sep 01 06:05:16 AM UTC 24	Sep 01 06:05:27 AM UTC 24	122414159 ps
T797	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.2096098031	Sep 01 06:04:10 AM UTC 24	Sep 01 06:05:29 AM UTC 24	34718720843 ps
T798	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.554219236	Sep 01 06:04:45 AM UTC 24	Sep 01 06:05:29 AM UTC 24	857622831 ps
T799	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.2516711145	Sep 01 06:03:06 AM UTC 24	Sep 01 06:05:32 AM UTC 24	14862814295 ps
T800	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.1319307207	Sep 01 06:05:29 AM UTC 24	Sep 01 06:05:33 AM UTC 24	24100235 ps
T801	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1089746141	Sep 01 06:02:28 AM UTC 24	Sep 01 06:05:36 AM UTC 24	30588198475 ps
T802	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.4176635129	Sep 01 06:04:50 AM UTC 24	Sep 01 06:05:45 AM UTC 24	5546588758 ps
T803	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.4068869044	Sep 01 06:02:26 AM UTC 24	Sep 01 06:05:50 AM UTC 24	43319681850 ps
T804	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.3484665087	Sep 01 06:05:46 AM UTC 24	Sep 01 06:05:50 AM UTC 24	27506050 ps
T805	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1596018910	Sep 01 06:05:16 AM UTC 24	Sep 01 06:07:56 AM UTC 24	16510584009 ps
T806	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.2774722216	Sep 01 06:04:56 AM UTC 24	Sep 01 06:05:54 AM UTC 24	1578264398 ps
T807	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.2017650467	Sep 01 06:05:29 AM UTC 24	Sep 01 06:05:55 AM UTC 24	257490265 ps
T808	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1718726232	Sep 01 06:05:51 AM UTC 24	Sep 01 06:05:55 AM UTC 24	41692984 ps
T809	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.448173525	Sep 01 06:04:32 AM UTC 24	Sep 01 06:05:57 AM UTC 24	5590838117 ps
T810	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1263863951	Sep 01 06:04:21 AM UTC 24	Sep 01 06:05:57 AM UTC 24	909164241 ps
T811	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2288707314	Sep 01 06:00:46 AM UTC 24	Sep 01 06:05:57 AM UTC 24	35469903446 ps
T226	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.2700172798	Sep 01 06:00:55 AM UTC 24	Sep 01 06:05:59 AM UTC 24	69934981206 ps
T812	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.633454833	Sep 01 06:05:31 AM UTC 24	Sep 01 06:05:59 AM UTC 24	2289117087 ps
T813	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1536495107	Sep 01 06:02:09 AM UTC 24	Sep 01 06:06:01 AM UTC 24	54995990462 ps
T814	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3369320175	Sep 01 06:05:03 AM UTC 24	Sep 01 06:06:02 AM UTC 24	1759045991 ps
T815	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.657144750	Sep 01 06:05:12 AM UTC 24	Sep 01 06:06:04 AM UTC 24	3037682601 ps
T816	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1450039830	Sep 01 06:06:01 AM UTC 24	Sep 01 06:06:06 AM UTC 24	336189757 ps
T817	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.2750403984	Sep 01 05:58:54 AM UTC 24	Sep 01 06:06:06 AM UTC 24	4258138341 ps
T818	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.42840040	Sep 01 06:04:50 AM UTC 24	Sep 01 06:06:06 AM UTC 24	11240027253 ps
T71	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.3632573374	Sep 01 06:05:21 AM UTC 24	Sep 01 06:06:09 AM UTC 24	3890795031 ps
T819	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.3090664592	Sep 01 06:06:04 AM UTC 24	Sep 01 06:06:11 AM UTC 24	121819538 ps
T820	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.139415220	Sep 01 06:02:47 AM UTC 24	Sep 01 06:06:13 AM UTC 24	601250051 ps
T821	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3357558981	Sep 01 06:06:11 AM UTC 24	Sep 01 06:06:13 AM UTC 24	7757892 ps
T822	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.1764538289	Sep 01 06:05:59 AM UTC 24	Sep 01 06:06:16 AM UTC 24	144448285 ps
T823	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2202867444	Sep 01 06:06:12 AM UTC 24	Sep 01 06:06:17 AM UTC 24	34828986 ps
T824	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.2828241387	Sep 01 06:06:11 AM UTC 24	Sep 01 06:06:18 AM UTC 24	690729981 ps
T825	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3963232506	Sep 01 06:06:04 AM UTC 24	Sep 01 06:06:19 AM UTC 24	273669920 ps
T826	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1890940412	Sep 01 06:05:10 AM UTC 24	Sep 01 06:06:20 AM UTC 24	11344178688 ps
T827	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.910680853	Sep 01 06:06:01 AM UTC 24	Sep 01 06:06:21 AM UTC 24	1041725113 ps
T828	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.1559717711	Sep 01 06:05:16 AM UTC 24	Sep 01 06:06:22 AM UTC 24	16157100190 ps
T829	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.2232781318	Sep 01 06:04:10 AM UTC 24	Sep 01 06:06:24 AM UTC 24	25760002385 ps
T830	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.3120501594	Sep 01 06:05:31 AM UTC 24	Sep 01 06:06:28 AM UTC 24	358363811 ps
T252	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2485121077	Sep 01 06:04:56 AM UTC 24	Sep 01 06:06:28 AM UTC 24	8708999758 ps
T831	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.4130547429	Sep 01 06:06:09 AM UTC 24	Sep 01 06:06:28 AM UTC 24	770757638 ps
T832	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.4065993241	Sep 01 06:05:55 AM UTC 24	Sep 01 06:06:33 AM UTC 24	821756189 ps
T833	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.3641813425	Sep 01 06:06:17 AM UTC 24	Sep 01 06:06:34 AM UTC 24	137884293 ps
T834	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.2901543798	Sep 01 06:05:55 AM UTC 24	Sep 01 06:06:36 AM UTC 24	361183553 ps
T835	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1124265902	Sep 01 06:05:53 AM UTC 24	Sep 01 06:06:37 AM UTC 24	16032483482 ps
T836	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.1066223191	Sep 01 06:06:19 AM UTC 24	Sep 01 06:06:40 AM UTC 24	141978610 ps
T837	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.1548167124	Sep 01 06:06:26 AM UTC 24	Sep 01 06:06:41 AM UTC 24	683084180 ps
T838	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.860717283	Sep 01 06:03:45 AM UTC 24	Sep 01 06:06:41 AM UTC 24	6115359885 ps
T839	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.2017036281	Sep 01 06:06:39 AM UTC 24	Sep 01 06:06:43 AM UTC 24	28233529 ps
T41	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.216377032	Sep 01 06:03:50 AM UTC 24	Sep 01 06:06:44 AM UTC 24	1635674892 ps
T840	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.2658172390	Sep 01 06:06:30 AM UTC 24	Sep 01 06:06:45 AM UTC 24	437307744 ps
T841	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2468193682	Sep 01 06:06:15 AM UTC 24	Sep 01 06:06:46 AM UTC 24	3826719762 ps
T842	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.445433184	Sep 01 06:06:42 AM UTC 24	Sep 01 06:06:46 AM UTC 24	42838172 ps
T843	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.877857265	Sep 01 06:06:30 AM UTC 24	Sep 01 06:06:50 AM UTC 24	183902472 ps
T844	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.4083055477	Sep 01 06:06:23 AM UTC 24	Sep 01 06:06:52 AM UTC 24	2668722886 ps
T137	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3643628200	Sep 01 05:57:13 AM UTC 24	Sep 01 06:06:52 AM UTC 24	130331121910 ps
T845	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2761828046	Sep 01 06:05:54 AM UTC 24	Sep 01 06:06:53 AM UTC 24	14142656578 ps
T846	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.1650718976	Sep 01 06:05:03 AM UTC 24	Sep 01 06:06:54 AM UTC 24	3763175831 ps
T847	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1028106602	Sep 01 06:06:09 AM UTC 24	Sep 01 06:06:57 AM UTC 24	186781158 ps
T848	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.1255990569	Sep 01 06:06:23 AM UTC 24	Sep 01 06:06:58 AM UTC 24	961036834 ps
T210	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.448506490	Sep 01 06:05:26 AM UTC 24	Sep 01 06:06:59 AM UTC 24	9100589314 ps
T849	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.1142864731	Sep 01 06:05:37 AM UTC 24	Sep 01 06:06:59 AM UTC 24	369704611 ps
T850	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1960248965	Sep 01 06:01:54 AM UTC 24	Sep 01 06:06:59 AM UTC 24	1990501318 ps
T851	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.4186189500	Sep 01 06:06:53 AM UTC 24	Sep 01 06:07:00 AM UTC 24	73324195 ps
T852	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3053991789	Sep 01 06:01:27 AM UTC 24	Sep 01 06:07:03 AM UTC 24	62125423546 ps
T853	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1823568875	Sep 01 06:05:04 AM UTC 24	Sep 01 06:07:03 AM UTC 24	622501230 ps
T854	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2071160450	Sep 01 06:06:55 AM UTC 24	Sep 01 06:07:06 AM UTC 24	71882889 ps
T855	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.3440145106	Sep 01 06:06:48 AM UTC 24	Sep 01 06:07:06 AM UTC 24	82801085 ps
T856	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2338654749	Sep 01 06:06:14 AM UTC 24	Sep 01 06:07:09 AM UTC 24	8477740101 ps
T857	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.900265062	Sep 01 05:54:56 AM UTC 24	Sep 01 06:07:11 AM UTC 24	75723777453 ps
T858	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.860884782	Sep 01 06:06:53 AM UTC 24	Sep 01 06:07:13 AM UTC 24	153894193 ps
T859	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.3101802816	Sep 01 06:06:46 AM UTC 24	Sep 01 06:07:14 AM UTC 24	197699502 ps
T860	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2967498821	Sep 01 06:06:46 AM UTC 24	Sep 01 06:07:16 AM UTC 24	2606284975 ps
T861	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.3127447722	Sep 01 06:06:35 AM UTC 24	Sep 01 06:07:17 AM UTC 24	916624660 ps
T138	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3226166739	Sep 01 06:06:23 AM UTC 24	Sep 01 06:07:17 AM UTC 24	4951457056 ps
T862	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.3681533077	Sep 01 06:06:55 AM UTC 24	Sep 01 06:07:20 AM UTC 24	128729506 ps
T863	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2536458337	Sep 01 06:04:54 AM UTC 24	Sep 01 06:07:24 AM UTC 24	14638843720 ps
T288	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2766756230	Sep 01 06:01:50 AM UTC 24	Sep 01 06:07:25 AM UTC 24	4110634669 ps
T864	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.4077718013	Sep 01 06:04:42 AM UTC 24	Sep 01 06:07:25 AM UTC 24	2334917590 ps
T865	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.4293253807	Sep 01 06:00:34 AM UTC 24	Sep 01 06:07:27 AM UTC 24	837598454 ps
T866	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.4119346189	Sep 01 06:04:54 AM UTC 24	Sep 01 06:07:29 AM UTC 24	36345269998 ps
T867	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1406022440	Sep 01 06:06:42 AM UTC 24	Sep 01 06:07:31 AM UTC 24	5837277030 ps
T868	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.624824976	Sep 01 06:06:42 AM UTC 24	Sep 01 06:07:32 AM UTC 24	4122295408 ps
T869	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2807021317	Sep 01 06:05:34 AM UTC 24	Sep 01 06:07:36 AM UTC 24	4052495184 ps
T870	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.237253039	Sep 01 06:06:30 AM UTC 24	Sep 01 06:07:36 AM UTC 24	488877470 ps
T871	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1474272274	Sep 01 06:05:59 AM UTC 24	Sep 01 06:07:42 AM UTC 24	13157687589 ps
T872	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.3936956610	Sep 01 06:02:39 AM UTC 24	Sep 01 06:08:00 AM UTC 24	15678416262 ps
T873	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2939416382	Sep 01 06:02:20 AM UTC 24	Sep 01 06:08:01 AM UTC 24	1873981316 ps
T143	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.248186750	Sep 01 06:05:57 AM UTC 24	Sep 01 06:08:11 AM UTC 24	23475705353 ps
T874	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.602595918	Sep 01 06:06:38 AM UTC 24	Sep 01 06:08:13 AM UTC 24	241807553 ps
T875	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.1403254223	Sep 01 06:07:02 AM UTC 24	Sep 01 06:08:30 AM UTC 24	811779706 ps
T876	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.116070866	Sep 01 06:01:21 AM UTC 24	Sep 01 06:08:30 AM UTC 24	126135626908 ps
T877	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.246944278	Sep 01 06:06:05 AM UTC 24	Sep 01 06:08:30 AM UTC 24	1740055419 ps
T878	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.1985799006	Sep 01 06:03:27 AM UTC 24	Sep 01 06:08:32 AM UTC 24	79961185295 ps
T879	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3523485357	Sep 01 06:06:20 AM UTC 24	Sep 01 06:08:34 AM UTC 24	22630323150 ps
T880	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3953619704	Sep 01 06:05:59 AM UTC 24	Sep 01 06:08:34 AM UTC 24	24869798594 ps
T881	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.68653581	Sep 01 06:03:06 AM UTC 24	Sep 01 06:08:39 AM UTC 24	45703579559 ps
T882	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.4064302895	Sep 01 06:06:59 AM UTC 24	Sep 01 06:08:41 AM UTC 24	131543046 ps
T883	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2786293358	Sep 01 06:06:35 AM UTC 24	Sep 01 06:08:47 AM UTC 24	121988200 ps
T160	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.21364958	Sep 01 06:04:45 AM UTC 24	Sep 01 06:08:57 AM UTC 24	2961272287 ps
T884	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.39440216	Sep 01 05:56:05 AM UTC 24	Sep 01 06:09:05 AM UTC 24	154850869084 ps
T46	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2614786726	Sep 01 06:01:02 AM UTC 24	Sep 01 06:09:17 AM UTC 24	10014182323 ps
T885	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.1087050387	Sep 01 06:06:19 AM UTC 24	Sep 01 06:09:19 AM UTC 24	18964188262 ps
T886	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.2515723297	Sep 01 06:04:18 AM UTC 24	Sep 01 06:09:26 AM UTC 24	32984563346 ps
T274	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2054593420	Sep 01 06:05:03 AM UTC 24	Sep 01 06:09:42 AM UTC 24	1804253201 ps
T887	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3870370647	Sep 01 06:02:56 AM UTC 24	Sep 01 06:09:58 AM UTC 24	4869667003 ps
T888	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.2455125171	Sep 01 06:06:48 AM UTC 24	Sep 01 06:09:59 AM UTC 24	28502364211 ps
T227	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.3644670515	Sep 01 06:00:06 AM UTC 24	Sep 01 06:10:17 AM UTC 24	2578313426 ps
T134	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3501057858	Sep 01 06:02:30 AM UTC 24	Sep 01 06:10:31 AM UTC 24	84648998236 ps
T889	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1001861363	Sep 01 06:05:32 AM UTC 24	Sep 01 06:10:32 AM UTC 24	6172716667 ps
T135	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.1493903621	Sep 01 06:06:59 AM UTC 24	Sep 01 06:10:46 AM UTC 24	5999478972 ps
T890	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.4178944039	Sep 01 06:04:45 AM UTC 24	Sep 01 06:10:55 AM UTC 24	2442665514 ps
T891	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1719121041	Sep 01 06:04:21 AM UTC 24	Sep 01 06:11:08 AM UTC 24	2060280073 ps
T892	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.1033485438	Sep 01 05:50:10 AM UTC 24	Sep 01 06:11:35 AM UTC 24	142859972874 ps
T893	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3215944958	Sep 01 06:04:13 AM UTC 24	Sep 01 06:12:11 AM UTC 24	52175658371 ps
T894	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1330906884	Sep 01 06:03:31 AM UTC 24	Sep 01 06:12:25 AM UTC 24	77620888610 ps
T895	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3076222790	Sep 01 06:03:06 AM UTC 24	Sep 01 06:12:26 AM UTC 24	51787692189 ps
T896	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1964787075	Sep 01 06:07:02 AM UTC 24	Sep 01 06:13:15 AM UTC 24	2673243935 ps
T132	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1206183613	Sep 01 06:03:10 AM UTC 24	Sep 01 06:13:37 AM UTC 24	5568371171 ps
T897	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3425190433	Sep 01 06:04:34 AM UTC 24	Sep 01 06:13:38 AM UTC 24	86614077101 ps
T898	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3716530647	Sep 01 06:06:51 AM UTC 24	Sep 01 06:14:07 AM UTC 24	83374226151 ps
T899	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3876538525	Sep 01 06:02:09 AM UTC 24	Sep 01 06:14:17 AM UTC 24	126086110292 ps
T900	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1988639953	Sep 01 06:00:23 AM UTC 24	Sep 01 06:18:42 AM UTC 24	117899799395 ps

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random.1903406885
Short name	T7
Test name
Test status
Simulation time	2682907240 ps
CPU time	50.17 seconds
Started	Sep 01 05:35:06 AM UTC 24
Finished	Sep 01 05:35:58 AM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903406885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.1903406885
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/0.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.4059687695
Short name	T294
Test name
Test status
Simulation time	299815044801 ps
CPU time	667.44 seconds
Started	Sep 01 05:42:48 AM UTC 24
Finished	Sep 01 05:54:04 AM UTC 24
Peak memory	220500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059687695 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.4059687695
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/7.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.3725483634
Short name	T77
Test name
Test status
Simulation time	1880616406 ps
CPU time	78.11 seconds
Started	Sep 01 05:37:57 AM UTC 24
Finished	Sep 01 05:39:17 AM UTC 24
Peak memory	218820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725483634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.3725483634
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/2.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.1571696813
Short name	T80
Test name
Test status
Simulation time	2101967521 ps
CPU time	92.28 seconds
Started	Sep 01 05:41:05 AM UTC 24
Finished	Sep 01 05:42:39 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571696813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1571696813
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/5.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3409123482
Short name	T47
Test name
Test status
Simulation time	2992638877 ps
CPU time	51.1 seconds
Started	Sep 01 05:36:18 AM UTC 24
Finished	Sep 01 05:37:11 AM UTC 24
Peak memory	219204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409123482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3409123482
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/0.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.728166910
Short name	T6
Test name
Test status
Simulation time	5289646793 ps
CPU time	251 seconds
Started	Sep 01 05:39:24 AM UTC 24
Finished	Sep 01 05:43:39 AM UTC 24
Peak memory	220928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728166910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.728166910
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/3.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2122694403
Short name	T122
Test name
Test status
Simulation time	84369028617 ps
CPU time	726.01 seconds
Started	Sep 01 05:44:35 AM UTC 24
Finished	Sep 01 05:56:50 AM UTC 24
Peak memory	220500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122694403 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.2122694403
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/10.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.437642652
Short name	T79
Test name
Test status
Simulation time	40002461020 ps
CPU time	376.1 seconds
Started	Sep 01 05:35:45 AM UTC 24
Finished	Sep 01 05:42:06 AM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437642652 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.437642652
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/0.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.3957184803
Short name	T14
Test name
Test status
Simulation time	731457904 ps
CPU time	29.43 seconds
Started	Sep 01 05:35:48 AM UTC 24
Finished	Sep 01 05:36:18 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957184803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.3957184803
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/0.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.2203871228
Short name	T184
Test name
Test status
Simulation time	6481352490 ps
CPU time	56.67 seconds
Started	Sep 01 05:36:22 AM UTC 24
Finished	Sep 01 05:37:20 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203871228 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2203871228
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/1.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.1975413493
Short name	T54
Test name
Test status
Simulation time	5158409820 ps
CPU time	83.62 seconds
Started	Sep 01 05:39:02 AM UTC 24
Finished	Sep 01 05:40:28 AM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975413493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1975413493
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/3.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.919771714
Short name	T104
Test name
Test status
Simulation time	2001957589 ps
CPU time	68.24 seconds
Started	Sep 01 05:45:12 AM UTC 24
Finished	Sep 01 05:46:22 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919771714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.919771714
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/11.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.461076943
Short name	T36
Test name
Test status
Simulation time	180954990 ps
CPU time	103.03 seconds
Started	Sep 01 05:36:18 AM UTC 24
Finished	Sep 01 05:38:04 AM UTC 24
Peak memory	221196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461076943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.461076943
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/0.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2544477076
Short name	T30
Test name
Test status
Simulation time	603355850 ps
CPU time	163.54 seconds
Started	Sep 01 05:44:53 AM UTC 24
Finished	Sep 01 05:47:39 AM UTC 24
Peak memory	222988 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544477076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.2544477076
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/10.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.2925416159
Short name	T27
Test name
Test status
Simulation time	13541359555 ps
CPU time	432.65 seconds
Started	Sep 01 05:40:29 AM UTC 24
Finished	Sep 01 05:47:47 AM UTC 24
Peak memory	233656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925416159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.2925416159
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/4.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.617232713
Short name	T55
Test name
Test status
Simulation time	8019404677 ps
CPU time	228.6 seconds
Started	Sep 01 05:38:16 AM UTC 24
Finished	Sep 01 05:42:08 AM UTC 24
Peak memory	223300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617232713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.617232713
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/2.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2191974022
Short name	T52
Test name
Test status
Simulation time	7620905785 ps
CPU time	75.51 seconds
Started	Sep 01 05:36:44 AM UTC 24
Finished	Sep 01 05:38:01 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191974022 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2191974022
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/1.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2782514797
Short name	T282
Test name
Test status
Simulation time	6602504843 ps
CPU time	240.84 seconds
Started	Sep 01 05:51:56 AM UTC 24
Finished	Sep 01 05:56:00 AM UTC 24
Peak memory	223416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782514797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.2782514797
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/22.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.3200519032
Short name	T619
Test name
Test status
Simulation time	539626310 ps
CPU time	308.47 seconds
Started	Sep 01 05:54:29 AM UTC 24
Finished	Sep 01 05:59:42 AM UTC 24
Peak memory	220936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200519032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.3200519032
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/26.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.313028473
Short name	T128
Test name
Test status
Simulation time	19102746106 ps
CPU time	315.78 seconds
Started	Sep 01 05:55:44 AM UTC 24
Finished	Sep 01 06:01:05 AM UTC 24
Peak memory	223040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313028473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.313028473
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/28.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2961071019
Short name	T43
Test name
Test status
Simulation time	4810115839 ps
CPU time	303.17 seconds
Started	Sep 01 05:47:24 AM UTC 24
Finished	Sep 01 05:52:32 AM UTC 24
Peak memory	223352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961071019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.2961071019
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/14.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2614786726
Short name	T46
Test name
Test status
Simulation time	10014182323 ps
CPU time	487.29 seconds
Started	Sep 01 06:01:02 AM UTC 24
Finished	Sep 01 06:09:17 AM UTC 24
Peak memory	224876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614786726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.2614786726
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/37.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.216377032
Short name	T41
Test name
Test status
Simulation time	1635674892 ps
CPU time	170.45 seconds
Started	Sep 01 06:03:50 AM UTC 24
Finished	Sep 01 06:06:44 AM UTC 24
Peak memory	222980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216377032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.216377032
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/42.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.4178851966
Short name	T9
Test name
Test status
Simulation time	64754407 ps
CPU time	3.37 seconds
Started	Sep 01 05:35:42 AM UTC 24
Finished	Sep 01 05:35:47 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178851966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.4178851966
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/0.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.578035148
Short name	T15
Test name
Test status
Simulation time	548561057 ps
CPU time	17.99 seconds
Started	Sep 01 05:36:02 AM UTC 24
Finished	Sep 01 05:36:21 AM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578035148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.578035148
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/0.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.3790247555
Short name	T10
Test name
Test status
Simulation time	245017173 ps
CPU time	8.1 seconds
Started	Sep 01 05:35:52 AM UTC 24
Finished	Sep 01 05:36:01 AM UTC 24
Peak memory	216884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790247555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3790247555
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/0.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.2556353326
Short name	T12
Test name
Test status
Simulation time	12504147105 ps
CPU time	61.84 seconds
Started	Sep 01 05:35:13 AM UTC 24
Finished	Sep 01 05:36:17 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556353326 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2556353326
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/0.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.655284217
Short name	T73
Test name
Test status
Simulation time	26986189603 ps
CPU time	164.3 seconds
Started	Sep 01 05:35:40 AM UTC 24
Finished	Sep 01 05:38:27 AM UTC 24
Peak memory	217152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655284217 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.655284217
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/0.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.1700665525
Short name	T8
Test name
Test status
Simulation time	599552633 ps
CPU time	30.7 seconds
Started	Sep 01 05:35:13 AM UTC 24
Finished	Sep 01 05:35:45 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700665525 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.1700665525
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/0.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.91889497
Short name	T2
Test name
Test status
Simulation time	143795897 ps
CPU time	5.91 seconds
Started	Sep 01 05:34:56 AM UTC 24
Finished	Sep 01 05:35:03 AM UTC 24
Peak memory	217072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91889497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.91889497
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/0.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.3612722859
Short name	T11
Test name
Test status
Simulation time	8821999253 ps
CPU time	67.84 seconds
Started	Sep 01 05:35:03 AM UTC 24
Finished	Sep 01 05:36:12 AM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612722859 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3612722859
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/0.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.3764202163
Short name	T3
Test name
Test status
Simulation time	3786677209 ps
CPU time	34.36 seconds
Started	Sep 01 05:35:04 AM UTC 24
Finished	Sep 01 05:35:39 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764202163 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3764202163
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/0.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.2497942245
Short name	T1
Test name
Test status
Simulation time	27598243 ps
CPU time	3.15 seconds
Started	Sep 01 05:34:58 AM UTC 24
Finished	Sep 01 05:35:02 AM UTC 24
Peak memory	216872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497942245 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.2497942245
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/0.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.3934740144
Short name	T48
Test name
Test status
Simulation time	21453486876 ps
CPU time	157.49 seconds
Started	Sep 01 05:36:13 AM UTC 24
Finished	Sep 01 05:38:53 AM UTC 24
Peak memory	223172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934740144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3934740144
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/0.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.2763473128
Short name	T35
Test name
Test status
Simulation time	5709416674 ps
CPU time	197.8 seconds
Started	Sep 01 05:36:17 AM UTC 24
Finished	Sep 01 05:39:38 AM UTC 24
Peak memory	223048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763473128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.2763473128
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/0.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.1722652670
Short name	T13
Test name
Test status
Simulation time	114139577 ps
CPU time	17.18 seconds
Started	Sep 01 05:35:59 AM UTC 24
Finished	Sep 01 05:36:17 AM UTC 24
Peak memory	219200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722652670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1722652670
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/0.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.2534726589
Short name	T18
Test name
Test status
Simulation time	373860425 ps
CPU time	14.14 seconds
Started	Sep 01 05:36:45 AM UTC 24
Finished	Sep 01 05:37:01 AM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534726589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2534726589
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/1.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1351696556
Short name	T83
Test name
Test status
Simulation time	175761219567 ps
CPU time	403.17 seconds
Started	Sep 01 05:36:47 AM UTC 24
Finished	Sep 01 05:43:36 AM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351696556 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.1351696556
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/1.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1829713520
Short name	T26
Test name
Test status
Simulation time	176354890 ps
CPU time	6.75 seconds
Started	Sep 01 05:37:03 AM UTC 24
Finished	Sep 01 05:37:11 AM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829713520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1829713520
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/1.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.1283447812
Short name	T19
Test name
Test status
Simulation time	945498783 ps
CPU time	23.11 seconds
Started	Sep 01 05:36:56 AM UTC 24
Finished	Sep 01 05:37:20 AM UTC 24
Peak memory	217084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283447812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1283447812
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/1.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random.3011528028
Short name	T16
Test name
Test status
Simulation time	191438810 ps
CPU time	17.18 seconds
Started	Sep 01 05:36:25 AM UTC 24
Finished	Sep 01 05:36:43 AM UTC 24
Peak memory	217100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011528028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.3011528028
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/1.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.4167769255
Short name	T336
Test name
Test status
Simulation time	42182518425 ps
CPU time	444.54 seconds
Started	Sep 01 05:36:39 AM UTC 24
Finished	Sep 01 05:44:10 AM UTC 24
Peak memory	219208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167769255 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.4167769255
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/1.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.858541147
Short name	T17
Test name
Test status
Simulation time	120646006 ps
CPU time	17.58 seconds
Started	Sep 01 05:36:26 AM UTC 24
Finished	Sep 01 05:36:45 AM UTC 24
Peak memory	217084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858541147 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.858541147
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/1.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.886886256
Short name	T50
Test name
Test status
Simulation time	1121558465 ps
CPU time	39.03 seconds
Started	Sep 01 05:36:47 AM UTC 24
Finished	Sep 01 05:37:28 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886886256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.886886256
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/1.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.1671212274
Short name	T24
Test name
Test status
Simulation time	32113803 ps
CPU time	3.39 seconds
Started	Sep 01 05:36:19 AM UTC 24
Finished	Sep 01 05:36:24 AM UTC 24
Peak memory	216744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671212274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1671212274
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/1.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1379573751
Short name	T49
Test name
Test status
Simulation time	11011539451 ps
CPU time	58.05 seconds
Started	Sep 01 05:36:23 AM UTC 24
Finished	Sep 01 05:37:23 AM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379573751 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1379573751
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/1.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.2100043409
Short name	T25
Test name
Test status
Simulation time	40681579 ps
CPU time	3.63 seconds
Started	Sep 01 05:36:20 AM UTC 24
Finished	Sep 01 05:36:25 AM UTC 24
Peak memory	216744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100043409 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.2100043409
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/1.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.2322228540
Short name	T34
Test name
Test status
Simulation time	4804013759 ps
CPU time	131 seconds
Started	Sep 01 05:37:12 AM UTC 24
Finished	Sep 01 05:39:25 AM UTC 24
Peak memory	220928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322228540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2322228540
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/1.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.3958674986
Short name	T111
Test name
Test status
Simulation time	19027734169 ps
CPU time	284.43 seconds
Started	Sep 01 05:37:21 AM UTC 24
Finished	Sep 01 05:42:10 AM UTC 24
Peak memory	223292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958674986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.3958674986
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/1.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.1784692523
Short name	T314
Test name
Test status
Simulation time	3690637539 ps
CPU time	690.71 seconds
Started	Sep 01 05:37:12 AM UTC 24
Finished	Sep 01 05:48:52 AM UTC 24
Peak memory	239804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784692523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.1784692523
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/1.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.1491328806
Short name	T88
Test name
Test status
Simulation time	3434331578 ps
CPU time	184.31 seconds
Started	Sep 01 05:37:21 AM UTC 24
Finished	Sep 01 05:40:29 AM UTC 24
Peak memory	223308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491328806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.1491328806
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/1.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.1498533906
Short name	T39
Test name
Test status
Simulation time	2586148552 ps
CPU time	38.76 seconds
Started	Sep 01 05:37:02 AM UTC 24
Finished	Sep 01 05:37:42 AM UTC 24
Peak memory	218944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498533906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1498533906
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/1.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.3902068582
Short name	T174
Test name
Test status
Simulation time	973006242 ps
CPU time	46.4 seconds
Started	Sep 01 05:44:32 AM UTC 24
Finished	Sep 01 05:45:20 AM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902068582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3902068582
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/10.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.228774537
Short name	T169
Test name
Test status
Simulation time	861592149 ps
CPU time	23.78 seconds
Started	Sep 01 05:44:45 AM UTC 24
Finished	Sep 01 05:45:10 AM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228774537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.228774537
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/10.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.1130700786
Short name	T345
Test name
Test status
Simulation time	136585665 ps
CPU time	3.93 seconds
Started	Sep 01 05:44:38 AM UTC 24
Finished	Sep 01 05:44:43 AM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130700786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1130700786
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/10.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random.3409644165
Short name	T347
Test name
Test status
Simulation time	352602738 ps
CPU time	22.09 seconds
Started	Sep 01 05:44:24 AM UTC 24
Finished	Sep 01 05:44:48 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409644165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.3409644165
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/10.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.3844276121
Short name	T166
Test name
Test status
Simulation time	71848086102 ps
CPU time	326.59 seconds
Started	Sep 01 05:44:31 AM UTC 24
Finished	Sep 01 05:50:02 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844276121 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3844276121
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/10.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.2098968780
Short name	T147
Test name
Test status
Simulation time	16422511563 ps
CPU time	205.83 seconds
Started	Sep 01 05:44:32 AM UTC 24
Finished	Sep 01 05:48:01 AM UTC 24
Peak memory	217160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098968780 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.2098968780
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/10.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.464382670
Short name	T348
Test name
Test status
Simulation time	377474178 ps
CPU time	24.35 seconds
Started	Sep 01 05:44:24 AM UTC 24
Finished	Sep 01 05:44:50 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464382670 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.464382670
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/10.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.1055563174
Short name	T346
Test name
Test status
Simulation time	37824349 ps
CPU time	4.51 seconds
Started	Sep 01 05:44:38 AM UTC 24
Finished	Sep 01 05:44:44 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055563174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1055563174
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/10.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.948433085
Short name	T342
Test name
Test status
Simulation time	293153585 ps
CPU time	5.76 seconds
Started	Sep 01 05:44:17 AM UTC 24
Finished	Sep 01 05:44:24 AM UTC 24
Peak memory	216752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948433085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.948433085
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/10.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.2083713060
Short name	T59
Test name
Test status
Simulation time	12226603734 ps
CPU time	59.12 seconds
Started	Sep 01 05:44:23 AM UTC 24
Finished	Sep 01 05:45:24 AM UTC 24
Peak memory	216884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083713060 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2083713060
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/10.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3076717556
Short name	T349
Test name
Test status
Simulation time	7086111370 ps
CPU time	25.81 seconds
Started	Sep 01 05:44:23 AM UTC 24
Finished	Sep 01 05:44:50 AM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076717556 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3076717556
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/10.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1367326086
Short name	T340
Test name
Test status
Simulation time	116133484 ps
CPU time	2.41 seconds
Started	Sep 01 05:44:19 AM UTC 24
Finished	Sep 01 05:44:22 AM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367326086 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.1367326086
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/10.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.3204650488
Short name	T356
Test name
Test status
Simulation time	2221000418 ps
CPU time	47.8 seconds
Started	Sep 01 05:44:49 AM UTC 24
Finished	Sep 01 05:45:38 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204650488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3204650488
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/10.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.1170622072
Short name	T370
Test name
Test status
Simulation time	3556905414 ps
CPU time	125.53 seconds
Started	Sep 01 05:44:51 AM UTC 24
Finished	Sep 01 05:46:59 AM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170622072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1170622072
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/10.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.357404217
Short name	T148
Test name
Test status
Simulation time	3182421895 ps
CPU time	210.97 seconds
Started	Sep 01 05:44:51 AM UTC 24
Finished	Sep 01 05:48:25 AM UTC 24
Peak memory	220992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357404217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.357404217
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/10.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.1060491689
Short name	T101
Test name
Test status
Simulation time	1407421429 ps
CPU time	22.47 seconds
Started	Sep 01 05:44:45 AM UTC 24
Finished	Sep 01 05:45:08 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060491689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1060491689
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/10.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.2393711350
Short name	T309
Test name
Test status
Simulation time	51120946265 ps
CPU time	653.77 seconds
Started	Sep 01 05:45:12 AM UTC 24
Finished	Sep 01 05:56:14 AM UTC 24
Peak memory	220564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393711350 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.2393711350
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/11.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.85665804
Short name	T351
Test name
Test status
Simulation time	55019042 ps
CPU time	3.26 seconds
Started	Sep 01 05:45:25 AM UTC 24
Finished	Sep 01 05:45:30 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85665804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.85665804
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/11.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.1546912879
Short name	T353
Test name
Test status
Simulation time	290547252 ps
CPU time	9.74 seconds
Started	Sep 01 05:45:21 AM UTC 24
Finished	Sep 01 05:45:32 AM UTC 24
Peak memory	217084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546912879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1546912879
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/11.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random.4002306136
Short name	T86
Test name
Test status
Simulation time	272664764 ps
CPU time	14.72 seconds
Started	Sep 01 05:45:07 AM UTC 24
Finished	Sep 01 05:45:23 AM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002306136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.4002306136
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/11.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.9297105
Short name	T61
Test name
Test status
Simulation time	29626279925 ps
CPU time	76.41 seconds
Started	Sep 01 05:45:10 AM UTC 24
Finished	Sep 01 05:46:29 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9297105 -assert nopostproc +UVM_TESTNAME=xbar_base_t est +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.9297105
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/11.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.1223690733
Short name	T360
Test name
Test status
Simulation time	3936313020 ps
CPU time	46.7 seconds
Started	Sep 01 05:45:10 AM UTC 24
Finished	Sep 01 05:45:59 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223690733 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1223690733
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/11.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.4130212731
Short name	T173
Test name
Test status
Simulation time	28247217 ps
CPU time	5.04 seconds
Started	Sep 01 05:45:09 AM UTC 24
Finished	Sep 01 05:45:15 AM UTC 24
Peak memory	217080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130212731 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.4130212731
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/11.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.753825201
Short name	T204
Test name
Test status
Simulation time	7226420924 ps
CPU time	47.99 seconds
Started	Sep 01 05:45:16 AM UTC 24
Finished	Sep 01 05:46:05 AM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753825201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.753825201
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/11.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.1656143616
Short name	T170
Test name
Test status
Simulation time	490656096 ps
CPU time	5.71 seconds
Started	Sep 01 05:45:03 AM UTC 24
Finished	Sep 01 05:45:10 AM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656143616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1656143616
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/11.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.789890854
Short name	T355
Test name
Test status
Simulation time	7362156945 ps
CPU time	29.33 seconds
Started	Sep 01 05:45:06 AM UTC 24
Finished	Sep 01 05:45:36 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789890854 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.789890854
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/11.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.363191888
Short name	T102
Test name
Test status
Simulation time	12920451433 ps
CPU time	51.09 seconds
Started	Sep 01 05:45:06 AM UTC 24
Finished	Sep 01 05:45:58 AM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363191888 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.363191888
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/11.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.3230119819
Short name	T172
Test name
Test status
Simulation time	121288275 ps
CPU time	3.7 seconds
Started	Sep 01 05:45:06 AM UTC 24
Finished	Sep 01 05:45:10 AM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230119819 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.3230119819
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/11.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.1001222934
Short name	T258
Test name
Test status
Simulation time	26016149094 ps
CPU time	134.86 seconds
Started	Sep 01 05:45:28 AM UTC 24
Finished	Sep 01 05:47:46 AM UTC 24
Peak memory	218880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001222934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1001222934
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/11.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.112476833
Short name	T202
Test name
Test status
Simulation time	2595957759 ps
CPU time	29.59 seconds
Started	Sep 01 05:45:32 AM UTC 24
Finished	Sep 01 05:46:03 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112476833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.112476833
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/11.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.739506919
Short name	T414
Test name
Test status
Simulation time	3709058982 ps
CPU time	207.05 seconds
Started	Sep 01 05:45:31 AM UTC 24
Finished	Sep 01 05:49:01 AM UTC 24
Peak memory	220924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739506919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.739506919
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/11.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1017457626
Short name	T37
Test name
Test status
Simulation time	2762828747 ps
CPU time	537.53 seconds
Started	Sep 01 05:45:33 AM UTC 24
Finished	Sep 01 05:54:38 AM UTC 24
Peak memory	233916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017457626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.1017457626
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/11.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.2301174260
Short name	T354
Test name
Test status
Simulation time	104586503 ps
CPU time	7.76 seconds
Started	Sep 01 05:45:24 AM UTC 24
Finished	Sep 01 05:45:33 AM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301174260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2301174260
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/11.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.1367438787
Short name	T105
Test name
Test status
Simulation time	1438912249 ps
CPU time	63.35 seconds
Started	Sep 01 05:45:46 AM UTC 24
Finished	Sep 01 05:46:51 AM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367438787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1367438787
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/12.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2691420891
Short name	T299
Test name
Test status
Simulation time	49960108196 ps
CPU time	513.78 seconds
Started	Sep 01 05:45:52 AM UTC 24
Finished	Sep 01 05:54:32 AM UTC 24
Peak memory	219208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691420891 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.2691420891
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/12.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.1776020147
Short name	T203
Test name
Test status
Simulation time	45875894 ps
CPU time	5.85 seconds
Started	Sep 01 05:45:58 AM UTC 24
Finished	Sep 01 05:46:05 AM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776020147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.1776020147
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/12.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.1731107562
Short name	T362
Test name
Test status
Simulation time	3645701681 ps
CPU time	43.08 seconds
Started	Sep 01 05:45:54 AM UTC 24
Finished	Sep 01 05:46:39 AM UTC 24
Peak memory	216888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731107562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1731107562
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/12.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random.1263780904
Short name	T207
Test name
Test status
Simulation time	492371514 ps
CPU time	31.18 seconds
Started	Sep 01 05:45:39 AM UTC 24
Finished	Sep 01 05:46:12 AM UTC 24
Peak memory	217156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263780904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.1263780904
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/12.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.2319105772
Short name	T371
Test name
Test status
Simulation time	62340193624 ps
CPU time	86.27 seconds
Started	Sep 01 05:45:40 AM UTC 24
Finished	Sep 01 05:47:08 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319105772 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2319105772
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/12.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.775305171
Short name	T402
Test name
Test status
Simulation time	11174707132 ps
CPU time	170.2 seconds
Started	Sep 01 05:45:40 AM UTC 24
Finished	Sep 01 05:48:34 AM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775305171 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.775305171
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/12.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.3978562547
Short name	T359
Test name
Test status
Simulation time	149204499 ps
CPU time	10.57 seconds
Started	Sep 01 05:45:39 AM UTC 24
Finished	Sep 01 05:45:51 AM UTC 24
Peak memory	216752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978562547 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.3978562547
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/12.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.211247722
Short name	T208
Test name
Test status
Simulation time	447847149 ps
CPU time	16.68 seconds
Started	Sep 01 05:45:54 AM UTC 24
Finished	Sep 01 05:46:12 AM UTC 24
Peak memory	217084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211247722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.211247722
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/12.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.2880706846
Short name	T358
Test name
Test status
Simulation time	147316317 ps
CPU time	4.78 seconds
Started	Sep 01 05:45:33 AM UTC 24
Finished	Sep 01 05:45:39 AM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880706846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2880706846
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/12.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.690220418
Short name	T140
Test name
Test status
Simulation time	5006378376 ps
CPU time	52.41 seconds
Started	Sep 01 05:45:34 AM UTC 24
Finished	Sep 01 05:46:28 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690220418 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.690220418
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/12.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1285065773
Short name	T243
Test name
Test status
Simulation time	4806761591 ps
CPU time	51.08 seconds
Started	Sep 01 05:45:37 AM UTC 24
Finished	Sep 01 05:46:30 AM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285065773 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1285065773
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/12.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.3665817438
Short name	T357
Test name
Test status
Simulation time	109329628 ps
CPU time	3.45 seconds
Started	Sep 01 05:45:34 AM UTC 24
Finished	Sep 01 05:45:39 AM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665817438 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.3665817438
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/12.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.2327741095
Short name	T259
Test name
Test status
Simulation time	4850402347 ps
CPU time	114.79 seconds
Started	Sep 01 05:45:59 AM UTC 24
Finished	Sep 01 05:47:57 AM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327741095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2327741095
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/12.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.876176625
Short name	T293
Test name
Test status
Simulation time	2813984490 ps
CPU time	83.68 seconds
Started	Sep 01 05:46:01 AM UTC 24
Finished	Sep 01 05:47:26 AM UTC 24
Peak memory	218944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876176625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.876176625
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/12.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1606753644
Short name	T311
Test name
Test status
Simulation time	127893211 ps
CPU time	81.25 seconds
Started	Sep 01 05:46:00 AM UTC 24
Finished	Sep 01 05:47:23 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606753644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.1606753644
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/12.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.2384503987
Short name	T315
Test name
Test status
Simulation time	548120877 ps
CPU time	103.44 seconds
Started	Sep 01 05:46:03 AM UTC 24
Finished	Sep 01 05:47:48 AM UTC 24
Peak memory	223176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384503987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.2384503987
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/12.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.1778737669
Short name	T361
Test name
Test status
Simulation time	110981974 ps
CPU time	3.66 seconds
Started	Sep 01 05:45:55 AM UTC 24
Finished	Sep 01 05:46:00 AM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778737669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1778737669
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/12.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.715282758
Short name	T209
Test name
Test status
Simulation time	19453237 ps
CPU time	4.5 seconds
Started	Sep 01 05:46:22 AM UTC 24
Finished	Sep 01 05:46:28 AM UTC 24
Peak memory	217084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715282758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.715282758
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/13.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.1022779517
Short name	T125
Test name
Test status
Simulation time	92901389658 ps
CPU time	709.11 seconds
Started	Sep 01 05:46:22 AM UTC 24
Finished	Sep 01 05:58:20 AM UTC 24
Peak memory	222548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022779517 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.1022779517
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/13.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.3390739165
Short name	T365
Test name
Test status
Simulation time	542302109 ps
CPU time	19.32 seconds
Started	Sep 01 05:46:31 AM UTC 24
Finished	Sep 01 05:46:52 AM UTC 24
Peak memory	216904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390739165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.3390739165
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/13.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.1680307506
Short name	T368
Test name
Test status
Simulation time	971655928 ps
CPU time	22.76 seconds
Started	Sep 01 05:46:30 AM UTC 24
Finished	Sep 01 05:46:54 AM UTC 24
Peak memory	217152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680307506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1680307506
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/13.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random.1763230870
Short name	T367
Test name
Test status
Simulation time	1727534860 ps
CPU time	40.69 seconds
Started	Sep 01 05:46:11 AM UTC 24
Finished	Sep 01 05:46:54 AM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763230870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.1763230870
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/13.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.464180142
Short name	T287
Test name
Test status
Simulation time	29462138849 ps
CPU time	213.7 seconds
Started	Sep 01 05:46:13 AM UTC 24
Finished	Sep 01 05:49:50 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464180142 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.464180142
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/13.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.382768538
Short name	T289
Test name
Test status
Simulation time	5797123125 ps
CPU time	64.31 seconds
Started	Sep 01 05:46:16 AM UTC 24
Finished	Sep 01 05:47:22 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382768538 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.382768538
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/13.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.553795215
Short name	T244
Test name
Test status
Simulation time	128977726 ps
CPU time	17.29 seconds
Started	Sep 01 05:46:13 AM UTC 24
Finished	Sep 01 05:46:31 AM UTC 24
Peak memory	217080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553795215 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.553795215
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/13.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.1494572999
Short name	T366
Test name
Test status
Simulation time	254213675 ps
CPU time	22.35 seconds
Started	Sep 01 05:46:28 AM UTC 24
Finished	Sep 01 05:46:52 AM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494572999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1494572999
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/13.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.637983141
Short name	T205
Test name
Test status
Simulation time	76234185 ps
CPU time	3.84 seconds
Started	Sep 01 05:46:04 AM UTC 24
Finished	Sep 01 05:46:09 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637983141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.637983141
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/13.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.1157095393
Short name	T246
Test name
Test status
Simulation time	5328270673 ps
CPU time	31.33 seconds
Started	Sep 01 05:46:06 AM UTC 24
Finished	Sep 01 05:46:39 AM UTC 24
Peak memory	217204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157095393 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.1157095393
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/13.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.1169957096
Short name	T272
Test name
Test status
Simulation time	9599285383 ps
CPU time	37.03 seconds
Started	Sep 01 05:46:09 AM UTC 24
Finished	Sep 01 05:46:48 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169957096 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1169957096
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/13.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.2965585739
Short name	T206
Test name
Test status
Simulation time	33229949 ps
CPU time	3.57 seconds
Started	Sep 01 05:46:06 AM UTC 24
Finished	Sep 01 05:46:11 AM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965585739 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.2965585739
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/13.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.2250606699
Short name	T405
Test name
Test status
Simulation time	8058310472 ps
CPU time	129.35 seconds
Started	Sep 01 05:46:31 AM UTC 24
Finished	Sep 01 05:48:43 AM UTC 24
Peak memory	220992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250606699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2250606699
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/13.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2962009098
Short name	T388
Test name
Test status
Simulation time	5681338179 ps
CPU time	78.15 seconds
Started	Sep 01 05:46:38 AM UTC 24
Finished	Sep 01 05:47:58 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962009098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2962009098
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/13.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.668664790
Short name	T123
Test name
Test status
Simulation time	10369716248 ps
CPU time	630.48 seconds
Started	Sep 01 05:46:32 AM UTC 24
Finished	Sep 01 05:57:11 AM UTC 24
Peak memory	223356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668664790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.668664790
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/13.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.2086226102
Short name	T534
Test name
Test status
Simulation time	22176502295 ps
CPU time	506.78 seconds
Started	Sep 01 05:46:40 AM UTC 24
Finished	Sep 01 05:55:13 AM UTC 24
Peak memory	223152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086226102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.2086226102
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/13.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.2520491610
Short name	T245
Test name
Test status
Simulation time	149486488 ps
CPU time	7.78 seconds
Started	Sep 01 05:46:30 AM UTC 24
Finished	Sep 01 05:46:39 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520491610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2520491610
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/13.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.1070443004
Short name	T386
Test name
Test status
Simulation time	1206087534 ps
CPU time	61.57 seconds
Started	Sep 01 05:46:54 AM UTC 24
Finished	Sep 01 05:47:57 AM UTC 24
Peak memory	218820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070443004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.1070443004
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/14.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1140048589
Short name	T308
Test name
Test status
Simulation time	60396324451 ps
CPU time	473.41 seconds
Started	Sep 01 05:46:55 AM UTC 24
Finished	Sep 01 05:54:54 AM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140048589 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.1140048589
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/14.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2753267584
Short name	T380
Test name
Test status
Simulation time	780638989 ps
CPU time	30.47 seconds
Started	Sep 01 05:47:00 AM UTC 24
Finished	Sep 01 05:47:32 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753267584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2753267584
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/14.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.4199708892
Short name	T375
Test name
Test status
Simulation time	245673382 ps
CPU time	23.66 seconds
Started	Sep 01 05:47:00 AM UTC 24
Finished	Sep 01 05:47:25 AM UTC 24
Peak memory	216760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199708892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.4199708892
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/14.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random.569260235
Short name	T373
Test name
Test status
Simulation time	768076113 ps
CPU time	33.37 seconds
Started	Sep 01 05:46:48 AM UTC 24
Finished	Sep 01 05:47:23 AM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569260235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.569260235
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/14.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.3373568435
Short name	T387
Test name
Test status
Simulation time	20215122365 ps
CPU time	64.24 seconds
Started	Sep 01 05:46:52 AM UTC 24
Finished	Sep 01 05:47:58 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373568435 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3373568435
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/14.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2417700571
Short name	T443
Test name
Test status
Simulation time	52153845928 ps
CPU time	198.58 seconds
Started	Sep 01 05:46:52 AM UTC 24
Finished	Sep 01 05:50:14 AM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417700571 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2417700571
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/14.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.4227461171
Short name	T374
Test name
Test status
Simulation time	485917117 ps
CPU time	32.07 seconds
Started	Sep 01 05:46:51 AM UTC 24
Finished	Sep 01 05:47:25 AM UTC 24
Peak memory	218800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227461171 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.4227461171
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/14.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.2236134750
Short name	T369
Test name
Test status
Simulation time	29405170 ps
CPU time	2.97 seconds
Started	Sep 01 05:46:55 AM UTC 24
Finished	Sep 01 05:46:59 AM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236134750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2236134750
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/14.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.1791845694
Short name	T363
Test name
Test status
Simulation time	91212498 ps
CPU time	3.51 seconds
Started	Sep 01 05:46:40 AM UTC 24
Finished	Sep 01 05:46:44 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791845694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1791845694
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/14.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3485966436
Short name	T376
Test name
Test status
Simulation time	6815097923 ps
CPU time	40.94 seconds
Started	Sep 01 05:46:45 AM UTC 24
Finished	Sep 01 05:47:27 AM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485966436 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3485966436
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/14.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2673896695
Short name	T383
Test name
Test status
Simulation time	4101042659 ps
CPU time	50.61 seconds
Started	Sep 01 05:46:46 AM UTC 24
Finished	Sep 01 05:47:38 AM UTC 24
Peak memory	217008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673896695 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2673896695
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/14.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.1961789600
Short name	T364
Test name
Test status
Simulation time	115070312 ps
CPU time	3.83 seconds
Started	Sep 01 05:46:40 AM UTC 24
Finished	Sep 01 05:46:44 AM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961789600 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.1961789600
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/14.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.2049214074
Short name	T109
Test name
Test status
Simulation time	8708423071 ps
CPU time	191.06 seconds
Started	Sep 01 05:47:09 AM UTC 24
Finished	Sep 01 05:50:24 AM UTC 24
Peak memory	220992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049214074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2049214074
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/14.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.3087314354
Short name	T297
Test name
Test status
Simulation time	12817420708 ps
CPU time	223.01 seconds
Started	Sep 01 05:47:23 AM UTC 24
Finished	Sep 01 05:51:09 AM UTC 24
Peak memory	223288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087314354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3087314354
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/14.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.2713208612
Short name	T445
Test name
Test status
Simulation time	1124766289 ps
CPU time	178.16 seconds
Started	Sep 01 05:47:17 AM UTC 24
Finished	Sep 01 05:50:18 AM UTC 24
Peak memory	221196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713208612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.2713208612
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/14.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.3641965453
Short name	T372
Test name
Test status
Simulation time	71659589 ps
CPU time	14.08 seconds
Started	Sep 01 05:47:00 AM UTC 24
Finished	Sep 01 05:47:15 AM UTC 24
Peak memory	218816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641965453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3641965453
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/14.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.1117394277
Short name	T403
Test name
Test status
Simulation time	538315609 ps
CPU time	64.03 seconds
Started	Sep 01 05:47:33 AM UTC 24
Finished	Sep 01 05:48:39 AM UTC 24
Peak memory	218820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117394277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.1117394277
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/15.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1192939190
Short name	T310
Test name
Test status
Simulation time	18633453098 ps
CPU time	68.16 seconds
Started	Sep 01 05:47:35 AM UTC 24
Finished	Sep 01 05:48:45 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192939190 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.1192939190
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/15.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.1435273077
Short name	T390
Test name
Test status
Simulation time	194522747 ps
CPU time	19.09 seconds
Started	Sep 01 05:47:42 AM UTC 24
Finished	Sep 01 05:48:02 AM UTC 24
Peak memory	216904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435273077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.1435273077
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/15.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.247096465
Short name	T385
Test name
Test status
Simulation time	102193189 ps
CPU time	5.87 seconds
Started	Sep 01 05:47:38 AM UTC 24
Finished	Sep 01 05:47:45 AM UTC 24
Peak memory	217148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247096465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.247096465
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/15.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random.557559858
Short name	T384
Test name
Test status
Simulation time	241064630 ps
CPU time	11.08 seconds
Started	Sep 01 05:47:28 AM UTC 24
Finished	Sep 01 05:47:41 AM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557559858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.557559858
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/15.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.4185115513
Short name	T432
Test name
Test status
Simulation time	70501458590 ps
CPU time	137.54 seconds
Started	Sep 01 05:47:30 AM UTC 24
Finished	Sep 01 05:49:49 AM UTC 24
Peak memory	217028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185115513 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.4185115513
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/15.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.728197194
Short name	T408
Test name
Test status
Simulation time	9302835757 ps
CPU time	74.57 seconds
Started	Sep 01 05:47:31 AM UTC 24
Finished	Sep 01 05:48:47 AM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728197194 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.728197194
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/15.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.3270950808
Short name	T382
Test name
Test status
Simulation time	66060859 ps
CPU time	4.58 seconds
Started	Sep 01 05:47:30 AM UTC 24
Finished	Sep 01 05:47:35 AM UTC 24
Peak memory	216752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270950808 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3270950808
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/15.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.927124065
Short name	T394
Test name
Test status
Simulation time	1068218468 ps
CPU time	36.09 seconds
Started	Sep 01 05:47:36 AM UTC 24
Finished	Sep 01 05:48:14 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927124065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.927124065
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/15.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.3126124346
Short name	T377
Test name
Test status
Simulation time	48764724 ps
CPU time	3.38 seconds
Started	Sep 01 05:47:24 AM UTC 24
Finished	Sep 01 05:47:29 AM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126124346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3126124346
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/15.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3198714609
Short name	T395
Test name
Test status
Simulation time	12068078189 ps
CPU time	46.25 seconds
Started	Sep 01 05:47:26 AM UTC 24
Finished	Sep 01 05:48:14 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198714609 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3198714609
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/15.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.1508635545
Short name	T393
Test name
Test status
Simulation time	3691410069 ps
CPU time	43.67 seconds
Started	Sep 01 05:47:27 AM UTC 24
Finished	Sep 01 05:48:13 AM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508635545 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1508635545
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/15.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.1869022639
Short name	T379
Test name
Test status
Simulation time	51500388 ps
CPU time	2.85 seconds
Started	Sep 01 05:47:26 AM UTC 24
Finished	Sep 01 05:47:30 AM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869022639 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1869022639
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/15.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.1762990875
Short name	T475
Test name
Test status
Simulation time	28810793113 ps
CPU time	248.88 seconds
Started	Sep 01 05:47:46 AM UTC 24
Finished	Sep 01 05:51:59 AM UTC 24
Peak memory	220992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762990875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1762990875
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/15.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.679326873
Short name	T400
Test name
Test status
Simulation time	3496229807 ps
CPU time	39.3 seconds
Started	Sep 01 05:47:49 AM UTC 24
Finished	Sep 01 05:48:30 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679326873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.679326873
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/15.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3716792131
Short name	T401
Test name
Test status
Simulation time	172579838 ps
CPU time	43.79 seconds
Started	Sep 01 05:47:46 AM UTC 24
Finished	Sep 01 05:48:32 AM UTC 24
Peak memory	219144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716792131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.3716792131
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/15.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.3115593449
Short name	T44
Test name
Test status
Simulation time	156402357 ps
CPU time	70.5 seconds
Started	Sep 01 05:47:50 AM UTC 24
Finished	Sep 01 05:49:03 AM UTC 24
Peak memory	220868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115593449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.3115593449
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/15.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.277160782
Short name	T392
Test name
Test status
Simulation time	412099849 ps
CPU time	22.05 seconds
Started	Sep 01 05:47:41 AM UTC 24
Finished	Sep 01 05:48:04 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277160782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.277160782
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/15.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.4067996758
Short name	T300
Test name
Test status
Simulation time	869227252 ps
CPU time	36.56 seconds
Started	Sep 01 05:48:04 AM UTC 24
Finished	Sep 01 05:48:42 AM UTC 24
Peak memory	216968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067996758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.4067996758
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/16.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.1409557563
Short name	T129
Test name
Test status
Simulation time	186789179825 ps
CPU time	815.47 seconds
Started	Sep 01 05:48:04 AM UTC 24
Finished	Sep 01 06:01:49 AM UTC 24
Peak memory	222612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409557563 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.1409557563
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/16.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.3764956070
Short name	T409
Test name
Test status
Simulation time	1530407555 ps
CPU time	35.19 seconds
Started	Sep 01 05:48:14 AM UTC 24
Finished	Sep 01 05:48:51 AM UTC 24
Peak memory	217160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764956070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.3764956070
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/16.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.2560737571
Short name	T398
Test name
Test status
Simulation time	240625039 ps
CPU time	21.34 seconds
Started	Sep 01 05:48:05 AM UTC 24
Finished	Sep 01 05:48:28 AM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560737571 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2560737571
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/16.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random.2836576277
Short name	T187
Test name
Test status
Simulation time	1393158157 ps
CPU time	17.71 seconds
Started	Sep 01 05:48:00 AM UTC 24
Finished	Sep 01 05:48:19 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836576277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.2836576277
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/16.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.3460363322
Short name	T255
Test name
Test status
Simulation time	59063646326 ps
CPU time	135.09 seconds
Started	Sep 01 05:48:02 AM UTC 24
Finished	Sep 01 05:50:20 AM UTC 24
Peak memory	217160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460363322 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3460363322
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/16.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.279503513
Short name	T439
Test name
Test status
Simulation time	8581903189 ps
CPU time	119.55 seconds
Started	Sep 01 05:48:02 AM UTC 24
Finished	Sep 01 05:50:04 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279503513 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.279503513
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/16.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.3463072575
Short name	T396
Test name
Test status
Simulation time	76168152 ps
CPU time	11.65 seconds
Started	Sep 01 05:48:02 AM UTC 24
Finished	Sep 01 05:48:15 AM UTC 24
Peak memory	216752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463072575 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3463072575
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/16.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.3265701938
Short name	T399
Test name
Test status
Simulation time	660538678 ps
CPU time	22.87 seconds
Started	Sep 01 05:48:04 AM UTC 24
Finished	Sep 01 05:48:28 AM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265701938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3265701938
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/16.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.2054206881
Short name	T391
Test name
Test status
Simulation time	176543510 ps
CPU time	4.24 seconds
Started	Sep 01 05:47:57 AM UTC 24
Finished	Sep 01 05:48:03 AM UTC 24
Peak memory	217072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054206881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2054206881
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/16.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3920306581
Short name	T416
Test name
Test status
Simulation time	9301350038 ps
CPU time	64.35 seconds
Started	Sep 01 05:47:59 AM UTC 24
Finished	Sep 01 05:49:05 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920306581 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3920306581
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/16.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2090092502
Short name	T397
Test name
Test status
Simulation time	3116438265 ps
CPU time	23.85 seconds
Started	Sep 01 05:47:59 AM UTC 24
Finished	Sep 01 05:48:24 AM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090092502 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2090092502
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/16.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.547507767
Short name	T389
Test name
Test status
Simulation time	25133859 ps
CPU time	3.09 seconds
Started	Sep 01 05:47:57 AM UTC 24
Finished	Sep 01 05:48:01 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547507767 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.547507767
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/16.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.3930793192
Short name	T28
Test name
Test status
Simulation time	13522202485 ps
CPU time	131.19 seconds
Started	Sep 01 05:48:14 AM UTC 24
Finished	Sep 01 05:50:28 AM UTC 24
Peak memory	218876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930793192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3930793192
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/16.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1464413334
Short name	T430
Test name
Test status
Simulation time	7008106554 ps
CPU time	84.82 seconds
Started	Sep 01 05:48:16 AM UTC 24
Finished	Sep 01 05:49:43 AM UTC 24
Peak memory	216904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464413334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1464413334
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/16.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.4185042283
Short name	T29
Test name
Test status
Simulation time	248353755 ps
CPU time	197.04 seconds
Started	Sep 01 05:48:16 AM UTC 24
Finished	Sep 01 05:51:36 AM UTC 24
Peak memory	220936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185042283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.4185042283
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/16.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.1219499078
Short name	T429
Test name
Test status
Simulation time	261923302 ps
CPU time	79.86 seconds
Started	Sep 01 05:48:20 AM UTC 24
Finished	Sep 01 05:49:42 AM UTC 24
Peak memory	222984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219499078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.1219499078
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/16.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.3512626417
Short name	T266
Test name
Test status
Simulation time	577054336 ps
CPU time	35.96 seconds
Started	Sep 01 05:48:13 AM UTC 24
Finished	Sep 01 05:48:51 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512626417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3512626417
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/16.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.1688826203
Short name	T404
Test name
Test status
Simulation time	1656653279 ps
CPU time	11.63 seconds
Started	Sep 01 05:48:30 AM UTC 24
Finished	Sep 01 05:48:42 AM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688826203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.1688826203
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/17.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.772033462
Short name	T710
Test name
Test status
Simulation time	120219775654 ps
CPU time	858.5 seconds
Started	Sep 01 05:48:31 AM UTC 24
Finished	Sep 01 06:03:00 AM UTC 24
Peak memory	222616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772033462 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.772033462
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/17.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.4238667195
Short name	T412
Test name
Test status
Simulation time	403689849 ps
CPU time	14.25 seconds
Started	Sep 01 05:48:42 AM UTC 24
Finished	Sep 01 05:48:58 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238667195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.4238667195
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/17.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.1920377330
Short name	T417
Test name
Test status
Simulation time	1005211835 ps
CPU time	32.52 seconds
Started	Sep 01 05:48:35 AM UTC 24
Finished	Sep 01 05:49:09 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920377330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1920377330
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/17.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random.1640101276
Short name	T415
Test name
Test status
Simulation time	200579698 ps
CPU time	36.06 seconds
Started	Sep 01 05:48:27 AM UTC 24
Finished	Sep 01 05:49:05 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640101276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.1640101276
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/17.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.4031004399
Short name	T64
Test name
Test status
Simulation time	15396103061 ps
CPU time	127.7 seconds
Started	Sep 01 05:48:28 AM UTC 24
Finished	Sep 01 05:50:39 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031004399 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.4031004399
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/17.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3245978720
Short name	T221
Test name
Test status
Simulation time	28877920177 ps
CPU time	322.1 seconds
Started	Sep 01 05:48:30 AM UTC 24
Finished	Sep 01 05:53:56 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245978720 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3245978720
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/17.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.1135891492
Short name	T406
Test name
Test status
Simulation time	375171942 ps
CPU time	14.87 seconds
Started	Sep 01 05:48:28 AM UTC 24
Finished	Sep 01 05:48:45 AM UTC 24
Peak memory	216752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135891492 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.1135891492
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/17.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.4165532054
Short name	T418
Test name
Test status
Simulation time	1109845872 ps
CPU time	37.89 seconds
Started	Sep 01 05:48:33 AM UTC 24
Finished	Sep 01 05:49:13 AM UTC 24
Peak memory	217156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165532054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.4165532054
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/17.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.925381649
Short name	T119
Test name
Test status
Simulation time	1014980920 ps
CPU time	7.4 seconds
Started	Sep 01 05:48:20 AM UTC 24
Finished	Sep 01 05:48:29 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925381649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.925381649
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/17.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2911581930
Short name	T442
Test name
Test status
Simulation time	43697993645 ps
CPU time	106.38 seconds
Started	Sep 01 05:48:25 AM UTC 24
Finished	Sep 01 05:50:13 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911581930 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2911581930
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/17.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3257628164
Short name	T419
Test name
Test status
Simulation time	7885112329 ps
CPU time	45.03 seconds
Started	Sep 01 05:48:27 AM UTC 24
Finished	Sep 01 05:49:14 AM UTC 24
Peak memory	217200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257628164 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3257628164
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/17.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3936688782
Short name	T62
Test name
Test status
Simulation time	60815336 ps
CPU time	3.33 seconds
Started	Sep 01 05:48:22 AM UTC 24
Finished	Sep 01 05:48:27 AM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936688782 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3936688782
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/17.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.3291505222
Short name	T45
Test name
Test status
Simulation time	7914152395 ps
CPU time	149.03 seconds
Started	Sep 01 05:48:44 AM UTC 24
Finished	Sep 01 05:51:16 AM UTC 24
Peak memory	220992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291505222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3291505222
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/17.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3835010189
Short name	T550
Test name
Test status
Simulation time	74215915153 ps
CPU time	418.02 seconds
Started	Sep 01 05:48:46 AM UTC 24
Finished	Sep 01 05:55:50 AM UTC 24
Peak memory	223416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835010189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3835010189
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/17.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.453539547
Short name	T126
Test name
Test status
Simulation time	12220360060 ps
CPU time	614.51 seconds
Started	Sep 01 05:48:44 AM UTC 24
Finished	Sep 01 05:59:07 AM UTC 24
Peak memory	233588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453539547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.453539547
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/17.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.1987370268
Short name	T313
Test name
Test status
Simulation time	94321616 ps
CPU time	58.52 seconds
Started	Sep 01 05:48:46 AM UTC 24
Finished	Sep 01 05:49:47 AM UTC 24
Peak memory	218820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987370268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.1987370268
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/17.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.2459092014
Short name	T407
Test name
Test status
Simulation time	130099808 ps
CPU time	6 seconds
Started	Sep 01 05:48:39 AM UTC 24
Finished	Sep 01 05:48:46 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459092014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2459092014
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/17.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.1719618955
Short name	T431
Test name
Test status
Simulation time	384904723 ps
CPU time	43.5 seconds
Started	Sep 01 05:49:01 AM UTC 24
Finished	Sep 01 05:49:46 AM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719618955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1719618955
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/18.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.2835150355
Short name	T304
Test name
Test status
Simulation time	57094237825 ps
CPU time	553.96 seconds
Started	Sep 01 05:49:02 AM UTC 24
Finished	Sep 01 05:58:23 AM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835150355 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.2835150355
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/18.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3237995755
Short name	T426
Test name
Test status
Simulation time	151277111 ps
CPU time	23.84 seconds
Started	Sep 01 05:49:10 AM UTC 24
Finished	Sep 01 05:49:35 AM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237995755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3237995755
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/18.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.2398905236
Short name	T422
Test name
Test status
Simulation time	633287270 ps
CPU time	15.81 seconds
Started	Sep 01 05:49:06 AM UTC 24
Finished	Sep 01 05:49:23 AM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398905236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2398905236
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/18.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random.993266973
Short name	T107
Test name
Test status
Simulation time	678725127 ps
CPU time	23.12 seconds
Started	Sep 01 05:48:53 AM UTC 24
Finished	Sep 01 05:49:18 AM UTC 24
Peak memory	223340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993266973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.993266973
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/18.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.620503074
Short name	T428
Test name
Test status
Simulation time	5526773957 ps
CPU time	41.42 seconds
Started	Sep 01 05:48:55 AM UTC 24
Finished	Sep 01 05:49:37 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620503074 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.620503074
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/18.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.1651531886
Short name	T486
Test name
Test status
Simulation time	33540799438 ps
CPU time	198.5 seconds
Started	Sep 01 05:48:59 AM UTC 24
Finished	Sep 01 05:52:21 AM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651531886 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1651531886
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/18.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.1929766229
Short name	T413
Test name
Test status
Simulation time	18762597 ps
CPU time	4.31 seconds
Started	Sep 01 05:48:55 AM UTC 24
Finished	Sep 01 05:49:00 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929766229 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.1929766229
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/18.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.2240613247
Short name	T420
Test name
Test status
Simulation time	206643232 ps
CPU time	12.91 seconds
Started	Sep 01 05:49:04 AM UTC 24
Finished	Sep 01 05:49:18 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240613247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2240613247
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/18.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.4265657416
Short name	T411
Test name
Test status
Simulation time	175281320 ps
CPU time	5.19 seconds
Started	Sep 01 05:48:47 AM UTC 24
Finished	Sep 01 05:48:54 AM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265657416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.4265657416
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/18.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.4021252503
Short name	T427
Test name
Test status
Simulation time	8282027950 ps
CPU time	43.38 seconds
Started	Sep 01 05:48:52 AM UTC 24
Finished	Sep 01 05:49:37 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021252503 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.4021252503
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/18.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.347086934
Short name	T421
Test name
Test status
Simulation time	5174491779 ps
CPU time	28.04 seconds
Started	Sep 01 05:48:52 AM UTC 24
Finished	Sep 01 05:49:21 AM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347086934 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.347086934
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/18.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.2612013328
Short name	T410
Test name
Test status
Simulation time	32836957 ps
CPU time	3.71 seconds
Started	Sep 01 05:48:49 AM UTC 24
Finished	Sep 01 05:48:54 AM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612013328 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.2612013328
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/18.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.2275044530
Short name	T457
Test name
Test status
Simulation time	4904922778 ps
CPU time	115.04 seconds
Started	Sep 01 05:49:12 AM UTC 24
Finished	Sep 01 05:51:10 AM UTC 24
Peak memory	219144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275044530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2275044530
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/18.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.2638123155
Short name	T476
Test name
Test status
Simulation time	5475715948 ps
CPU time	163.59 seconds
Started	Sep 01 05:49:15 AM UTC 24
Finished	Sep 01 05:52:01 AM UTC 24
Peak memory	219268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638123155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2638123155
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/18.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.4084879793
Short name	T434
Test name
Test status
Simulation time	99311382 ps
CPU time	41.35 seconds
Started	Sep 01 05:49:15 AM UTC 24
Finished	Sep 01 05:49:58 AM UTC 24
Peak memory	219144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084879793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.4084879793
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/18.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.3956850001
Short name	T576
Test name
Test status
Simulation time	11424965432 ps
CPU time	470.02 seconds
Started	Sep 01 05:49:19 AM UTC 24
Finished	Sep 01 05:57:16 AM UTC 24
Peak memory	238012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956850001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.3956850001
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/18.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.374708388
Short name	T425
Test name
Test status
Simulation time	193647725 ps
CPU time	21.82 seconds
Started	Sep 01 05:49:06 AM UTC 24
Finished	Sep 01 05:49:29 AM UTC 24
Peak memory	219200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374708388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.374708388
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/18.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.1449216253
Short name	T108
Test name
Test status
Simulation time	1449685518 ps
CPU time	34.34 seconds
Started	Sep 01 05:49:37 AM UTC 24
Finished	Sep 01 05:50:12 AM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449216253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1449216253
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/19.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2717078897
Short name	T595
Test name
Test status
Simulation time	97273532815 ps
CPU time	542.76 seconds
Started	Sep 01 05:49:38 AM UTC 24
Finished	Sep 01 05:58:47 AM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717078897 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.2717078897
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/19.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.1456185797
Short name	T441
Test name
Test status
Simulation time	2534523330 ps
CPU time	21.57 seconds
Started	Sep 01 05:49:47 AM UTC 24
Finished	Sep 01 05:50:09 AM UTC 24
Peak memory	217224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456185797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.1456185797
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/19.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.4116747656
Short name	T433
Test name
Test status
Simulation time	159004607 ps
CPU time	8.31 seconds
Started	Sep 01 05:49:43 AM UTC 24
Finished	Sep 01 05:49:53 AM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116747656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.4116747656
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/19.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random.1651743264
Short name	T177
Test name
Test status
Simulation time	96539673 ps
CPU time	6.31 seconds
Started	Sep 01 05:49:28 AM UTC 24
Finished	Sep 01 05:49:35 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651743264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.1651743264
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/19.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.3169825901
Short name	T527
Test name
Test status
Simulation time	54525121533 ps
CPU time	320.47 seconds
Started	Sep 01 05:49:32 AM UTC 24
Finished	Sep 01 05:54:57 AM UTC 24
Peak memory	216904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169825901 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3169825901
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/19.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.1212449839
Short name	T544
Test name
Test status
Simulation time	122122585462 ps
CPU time	355.1 seconds
Started	Sep 01 05:49:37 AM UTC 24
Finished	Sep 01 05:55:37 AM UTC 24
Peak memory	217160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212449839 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1212449839
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/19.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.1228821465
Short name	T254
Test name
Test status
Simulation time	165999067 ps
CPU time	17.13 seconds
Started	Sep 01 05:49:30 AM UTC 24
Finished	Sep 01 05:49:49 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228821465 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1228821465
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/19.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.3664130913
Short name	T436
Test name
Test status
Simulation time	297932813 ps
CPU time	20.02 seconds
Started	Sep 01 05:49:38 AM UTC 24
Finished	Sep 01 05:49:59 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664130913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3664130913
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/19.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.3509831316
Short name	T423
Test name
Test status
Simulation time	159665318 ps
CPU time	4.02 seconds
Started	Sep 01 05:49:19 AM UTC 24
Finished	Sep 01 05:49:24 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509831316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3509831316
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/19.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3911383484
Short name	T446
Test name
Test status
Simulation time	13304715541 ps
CPU time	53.5 seconds
Started	Sep 01 05:49:24 AM UTC 24
Finished	Sep 01 05:50:19 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911383484 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3911383484
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/19.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.3189137919
Short name	T444
Test name
Test status
Simulation time	9806773113 ps
CPU time	53.57 seconds
Started	Sep 01 05:49:25 AM UTC 24
Finished	Sep 01 05:50:20 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189137919 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3189137919
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/19.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.715605911
Short name	T424
Test name
Test status
Simulation time	29400197 ps
CPU time	3.29 seconds
Started	Sep 01 05:49:22 AM UTC 24
Finished	Sep 01 05:49:27 AM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715605911 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.715605911
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/19.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.5707507
Short name	T298
Test name
Test status
Simulation time	5466265611 ps
CPU time	194.1 seconds
Started	Sep 01 05:49:48 AM UTC 24
Finished	Sep 01 05:53:05 AM UTC 24
Peak memory	220924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5707507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T EST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.5707507
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/19.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.3789502268
Short name	T216
Test name
Test status
Simulation time	10397789050 ps
CPU time	224.4 seconds
Started	Sep 01 05:49:50 AM UTC 24
Finished	Sep 01 05:53:38 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789502268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3789502268
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/19.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2286260925
Short name	T156
Test name
Test status
Simulation time	8727934342 ps
CPU time	470 seconds
Started	Sep 01 05:49:49 AM UTC 24
Finished	Sep 01 05:57:46 AM UTC 24
Peak memory	223416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286260925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.2286260925
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/19.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1645514182
Short name	T450
Test name
Test status
Simulation time	165850244 ps
CPU time	38.78 seconds
Started	Sep 01 05:49:52 AM UTC 24
Finished	Sep 01 05:50:32 AM UTC 24
Peak memory	219148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645514182 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.1645514182
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/19.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.4101311381
Short name	T167
Test name
Test status
Simulation time	484439429 ps
CPU time	23.23 seconds
Started	Sep 01 05:49:44 AM UTC 24
Finished	Sep 01 05:50:09 AM UTC 24
Peak memory	217148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101311381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.4101311381
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/19.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.2582124030
Short name	T118
Test name
Test status
Simulation time	38099521472 ps
CPU time	229.64 seconds
Started	Sep 01 05:38:02 AM UTC 24
Finished	Sep 01 05:41:55 AM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582124030 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.2582124030
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/2.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.2066555732
Short name	T23
Test name
Test status
Simulation time	225902632 ps
CPU time	21.93 seconds
Started	Sep 01 05:38:15 AM UTC 24
Finished	Sep 01 05:38:38 AM UTC 24
Peak memory	216844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066555732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.2066555732
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/2.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.1195697132
Short name	T74
Test name
Test status
Simulation time	98866428 ps
CPU time	3.72 seconds
Started	Sep 01 05:38:05 AM UTC 24
Finished	Sep 01 05:38:09 AM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195697132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1195697132
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/2.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random.2609085434
Short name	T4
Test name
Test status
Simulation time	422590581 ps
CPU time	23.27 seconds
Started	Sep 01 05:37:32 AM UTC 24
Finished	Sep 01 05:37:57 AM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609085434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.2609085434
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/2.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.3956853735
Short name	T97
Test name
Test status
Simulation time	30517810279 ps
CPU time	116.38 seconds
Started	Sep 01 05:37:48 AM UTC 24
Finished	Sep 01 05:39:47 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956853735 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3956853735
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/2.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.1675829096
Short name	T180
Test name
Test status
Simulation time	6889162315 ps
CPU time	97.3 seconds
Started	Sep 01 05:37:54 AM UTC 24
Finished	Sep 01 05:39:34 AM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675829096 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1675829096
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/2.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.4006843389
Short name	T21
Test name
Test status
Simulation time	78343782 ps
CPU time	9.4 seconds
Started	Sep 01 05:37:43 AM UTC 24
Finished	Sep 01 05:37:54 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006843389 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.4006843389
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/2.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.2478656686
Short name	T22
Test name
Test status
Simulation time	1183817035 ps
CPU time	21.6 seconds
Started	Sep 01 05:38:03 AM UTC 24
Finished	Sep 01 05:38:26 AM UTC 24
Peak memory	217152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478656686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2478656686
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/2.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.1416373731
Short name	T51
Test name
Test status
Simulation time	209213207 ps
CPU time	6 seconds
Started	Sep 01 05:37:23 AM UTC 24
Finished	Sep 01 05:37:30 AM UTC 24
Peak memory	217064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416373731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1416373731
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/2.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.1310302487
Short name	T53
Test name
Test status
Simulation time	15027334783 ps
CPU time	32.42 seconds
Started	Sep 01 05:37:29 AM UTC 24
Finished	Sep 01 05:38:02 AM UTC 24
Peak memory	216884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310302487 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1310302487
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/2.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.4083014313
Short name	T75
Test name
Test status
Simulation time	4967091624 ps
CPU time	42.67 seconds
Started	Sep 01 05:37:30 AM UTC 24
Finished	Sep 01 05:38:14 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083014313 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.4083014313
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/2.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3716463720
Short name	T253
Test name
Test status
Simulation time	47207108 ps
CPU time	3.21 seconds
Started	Sep 01 05:37:24 AM UTC 24
Finished	Sep 01 05:37:29 AM UTC 24
Peak memory	216744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716463720 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3716463720
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/2.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.1034368201
Short name	T264
Test name
Test status
Simulation time	6865825994 ps
CPU time	185.79 seconds
Started	Sep 01 05:38:20 AM UTC 24
Finished	Sep 01 05:41:29 AM UTC 24
Peak memory	222972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034368201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1034368201
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/2.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1042276087
Short name	T183
Test name
Test status
Simulation time	262518034 ps
CPU time	83.77 seconds
Started	Sep 01 05:38:19 AM UTC 24
Finished	Sep 01 05:39:45 AM UTC 24
Peak memory	221192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042276087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.1042276087
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/2.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.2960067850
Short name	T269
Test name
Test status
Simulation time	28297493 ps
CPU time	29.71 seconds
Started	Sep 01 05:38:27 AM UTC 24
Finished	Sep 01 05:38:58 AM UTC 24
Peak memory	216904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960067850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.2960067850
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/2.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.3426385179
Short name	T72
Test name
Test status
Simulation time	99937464 ps
CPU time	7.41 seconds
Started	Sep 01 05:38:10 AM UTC 24
Finished	Sep 01 05:38:18 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426385179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3426385179
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/2.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.1681528905
Short name	T303
Test name
Test status
Simulation time	5474680657 ps
CPU time	59.34 seconds
Started	Sep 01 05:50:07 AM UTC 24
Finished	Sep 01 05:51:08 AM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681528905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.1681528905
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/20.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.1033485438
Short name	T892
Test name
Test status
Simulation time	142859972874 ps
CPU time	1269.95 seconds
Started	Sep 01 05:50:10 AM UTC 24
Finished	Sep 01 06:11:35 AM UTC 24
Peak memory	220824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033485438 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.1033485438
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/20.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.527912601
Short name	T451
Test name
Test status
Simulation time	506005409 ps
CPU time	20.42 seconds
Started	Sep 01 05:50:16 AM UTC 24
Finished	Sep 01 05:50:38 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527912601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.527912601
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/20.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.421547568
Short name	T453
Test name
Test status
Simulation time	1842104647 ps
CPU time	37.94 seconds
Started	Sep 01 05:50:13 AM UTC 24
Finished	Sep 01 05:50:53 AM UTC 24
Peak memory	216760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421547568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.421547568
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/20.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random.1191893993
Short name	T175
Test name
Test status
Simulation time	1015940070 ps
CPU time	26.92 seconds
Started	Sep 01 05:50:02 AM UTC 24
Finished	Sep 01 05:50:31 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191893993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.1191893993
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/20.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.4031608238
Short name	T447
Test name
Test status
Simulation time	2061720863 ps
CPU time	14.81 seconds
Started	Sep 01 05:50:04 AM UTC 24
Finished	Sep 01 05:50:20 AM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031608238 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.4031608238
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/20.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3644489254
Short name	T539
Test name
Test status
Simulation time	43684174960 ps
CPU time	310.97 seconds
Started	Sep 01 05:50:05 AM UTC 24
Finished	Sep 01 05:55:21 AM UTC 24
Peak memory	218888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644489254 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3644489254
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/20.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.3415261476
Short name	T440
Test name
Test status
Simulation time	12182083 ps
CPU time	3.08 seconds
Started	Sep 01 05:50:03 AM UTC 24
Finished	Sep 01 05:50:07 AM UTC 24
Peak memory	217076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415261476 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.3415261476
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/20.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.1460487283
Short name	T448
Test name
Test status
Simulation time	379808401 ps
CPU time	12.59 seconds
Started	Sep 01 05:50:10 AM UTC 24
Finished	Sep 01 05:50:24 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460487283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1460487283
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/20.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.4070586724
Short name	T435
Test name
Test status
Simulation time	34260211 ps
CPU time	2.99 seconds
Started	Sep 01 05:49:54 AM UTC 24
Finished	Sep 01 05:49:58 AM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070586724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.4070586724
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/20.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.328845126
Short name	T292
Test name
Test status
Simulation time	17274961985 ps
CPU time	33.16 seconds
Started	Sep 01 05:50:00 AM UTC 24
Finished	Sep 01 05:50:35 AM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328845126 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.328845126
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/20.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.1210133809
Short name	T452
Test name
Test status
Simulation time	6125612561 ps
CPU time	41.8 seconds
Started	Sep 01 05:50:00 AM UTC 24
Finished	Sep 01 05:50:44 AM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210133809 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1210133809
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/20.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2353764889
Short name	T438
Test name
Test status
Simulation time	27996557 ps
CPU time	3.42 seconds
Started	Sep 01 05:49:58 AM UTC 24
Finished	Sep 01 05:50:03 AM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353764889 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2353764889
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/20.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.2423499652
Short name	T467
Test name
Test status
Simulation time	1593592250 ps
CPU time	69.15 seconds
Started	Sep 01 05:50:19 AM UTC 24
Finished	Sep 01 05:51:30 AM UTC 24
Peak memory	218812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423499652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2423499652
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/20.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.965230085
Short name	T474
Test name
Test status
Simulation time	571752776 ps
CPU time	95.9 seconds
Started	Sep 01 05:50:21 AM UTC 24
Finished	Sep 01 05:51:59 AM UTC 24
Peak memory	219148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965230085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.965230085
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/20.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.3207797124
Short name	T139
Test name
Test status
Simulation time	5396018446 ps
CPU time	334.97 seconds
Started	Sep 01 05:50:19 AM UTC 24
Finished	Sep 01 05:55:59 AM UTC 24
Peak memory	223048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207797124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.3207797124
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/20.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.2236883368
Short name	T217
Test name
Test status
Simulation time	589247998 ps
CPU time	195.44 seconds
Started	Sep 01 05:50:21 AM UTC 24
Finished	Sep 01 05:53:40 AM UTC 24
Peak memory	222920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236883368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.2236883368
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/20.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.2261147653
Short name	T455
Test name
Test status
Simulation time	1211698831 ps
CPU time	43.17 seconds
Started	Sep 01 05:50:15 AM UTC 24
Finished	Sep 01 05:51:00 AM UTC 24
Peak memory	218880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261147653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.2261147653
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/20.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.853539866
Short name	T473
Test name
Test status
Simulation time	4014217410 ps
CPU time	80.16 seconds
Started	Sep 01 05:50:36 AM UTC 24
Finished	Sep 01 05:51:58 AM UTC 24
Peak memory	219268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853539866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.853539866
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/21.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2770335199
Short name	T711
Test name
Test status
Simulation time	106102770488 ps
CPU time	731.59 seconds
Started	Sep 01 05:50:39 AM UTC 24
Finished	Sep 01 06:03:00 AM UTC 24
Peak memory	222872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770335199 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.2770335199
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/21.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.919007022
Short name	T459
Test name
Test status
Simulation time	698074549 ps
CPU time	16.85 seconds
Started	Sep 01 05:50:56 AM UTC 24
Finished	Sep 01 05:51:14 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919007022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.919007022
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/21.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.463530533
Short name	T456
Test name
Test status
Simulation time	102348129 ps
CPU time	14.19 seconds
Started	Sep 01 05:50:44 AM UTC 24
Finished	Sep 01 05:51:00 AM UTC 24
Peak memory	217084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463530533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.463530533
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/21.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random.1225660442
Short name	T463
Test name
Test status
Simulation time	974126196 ps
CPU time	50.31 seconds
Started	Sep 01 05:50:29 AM UTC 24
Finished	Sep 01 05:51:21 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225660442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.1225660442
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/21.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.561685526
Short name	T543
Test name
Test status
Simulation time	59722921391 ps
CPU time	298.48 seconds
Started	Sep 01 05:50:32 AM UTC 24
Finished	Sep 01 05:55:34 AM UTC 24
Peak memory	219208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561685526 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.561685526
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/21.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1753359598
Short name	T492
Test name
Test status
Simulation time	37588315362 ps
CPU time	128.07 seconds
Started	Sep 01 05:50:33 AM UTC 24
Finished	Sep 01 05:52:44 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753359598 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1753359598
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/21.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.2168145018
Short name	T454
Test name
Test status
Simulation time	158557083 ps
CPU time	22.16 seconds
Started	Sep 01 05:50:32 AM UTC 24
Finished	Sep 01 05:50:55 AM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168145018 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.2168145018
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/21.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.64799673
Short name	T458
Test name
Test status
Simulation time	1264349452 ps
CPU time	29.45 seconds
Started	Sep 01 05:50:40 AM UTC 24
Finished	Sep 01 05:51:11 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64799673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.64799673
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/21.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.536815507
Short name	T63
Test name
Test status
Simulation time	254113256 ps
CPU time	5.19 seconds
Started	Sep 01 05:50:21 AM UTC 24
Finished	Sep 01 05:50:27 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536815507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.536815507
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/21.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.758910951
Short name	T462
Test name
Test status
Simulation time	5076266312 ps
CPU time	50.09 seconds
Started	Sep 01 05:50:25 AM UTC 24
Finished	Sep 01 05:51:17 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758910951 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.758910951
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/21.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2738814923
Short name	T465
Test name
Test status
Simulation time	9549007904 ps
CPU time	56.27 seconds
Started	Sep 01 05:50:28 AM UTC 24
Finished	Sep 01 05:51:26 AM UTC 24
Peak memory	216868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738814923 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2738814923
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/21.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.1793498599
Short name	T449
Test name
Test status
Simulation time	30799778 ps
CPU time	3.86 seconds
Started	Sep 01 05:50:25 AM UTC 24
Finished	Sep 01 05:50:30 AM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793498599 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.1793498599
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/21.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.702887260
Short name	T469
Test name
Test status
Simulation time	704327478 ps
CPU time	36 seconds
Started	Sep 01 05:51:01 AM UTC 24
Finished	Sep 01 05:51:39 AM UTC 24
Peak memory	218812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702887260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.702887260
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/21.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.56077264
Short name	T295
Test name
Test status
Simulation time	2327630783 ps
CPU time	70.23 seconds
Started	Sep 01 05:51:10 AM UTC 24
Finished	Sep 01 05:52:22 AM UTC 24
Peak memory	217156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56077264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.56077264
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/21.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.274795608
Short name	T555
Test name
Test status
Simulation time	515507388 ps
CPU time	303.11 seconds
Started	Sep 01 05:51:01 AM UTC 24
Finished	Sep 01 05:56:10 AM UTC 24
Peak memory	220860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274795608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.274795608
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/21.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.3052991452
Short name	T525
Test name
Test status
Simulation time	3771474617 ps
CPU time	215.44 seconds
Started	Sep 01 05:51:11 AM UTC 24
Finished	Sep 01 05:54:50 AM UTC 24
Peak memory	221324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052991452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.3052991452
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/21.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.2806100792
Short name	T466
Test name
Test status
Simulation time	1426781190 ps
CPU time	33.29 seconds
Started	Sep 01 05:50:54 AM UTC 24
Finished	Sep 01 05:51:28 AM UTC 24
Peak memory	216964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806100792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2806100792
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/21.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.1643395896
Short name	T468
Test name
Test status
Simulation time	85475718 ps
CPU time	9.21 seconds
Started	Sep 01 05:51:25 AM UTC 24
Finished	Sep 01 05:51:35 AM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643395896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1643395896
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/22.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2655212807
Short name	T224
Test name
Test status
Simulation time	75894137424 ps
CPU time	766.27 seconds
Started	Sep 01 05:51:27 AM UTC 24
Finished	Sep 01 06:04:22 AM UTC 24
Peak memory	222872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655212807 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.2655212807
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/22.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.402488850
Short name	T471
Test name
Test status
Simulation time	580597030 ps
CPU time	16.27 seconds
Started	Sep 01 05:51:37 AM UTC 24
Finished	Sep 01 05:51:55 AM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402488850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.402488850
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/22.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.2927964655
Short name	T470
Test name
Test status
Simulation time	81681533 ps
CPU time	9.35 seconds
Started	Sep 01 05:51:32 AM UTC 24
Finished	Sep 01 05:51:42 AM UTC 24
Peak memory	217080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927964655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2927964655
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/22.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random.2275749983
Short name	T481
Test name
Test status
Simulation time	1937747011 ps
CPU time	47.67 seconds
Started	Sep 01 05:51:17 AM UTC 24
Finished	Sep 01 05:52:07 AM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275749983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.2275749983
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/22.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.1821375228
Short name	T643
Test name
Test status
Simulation time	201117928848 ps
CPU time	544.77 seconds
Started	Sep 01 05:51:18 AM UTC 24
Finished	Sep 01 06:00:30 AM UTC 24
Peak memory	218880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821375228 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1821375228
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/22.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.323589658
Short name	T283
Test name
Test status
Simulation time	24866870960 ps
CPU time	281.53 seconds
Started	Sep 01 05:51:23 AM UTC 24
Finished	Sep 01 05:56:09 AM UTC 24
Peak memory	219204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323589658 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.323589658
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/22.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.1195737917
Short name	T464
Test name
Test status
Simulation time	33204112 ps
CPU time	4.96 seconds
Started	Sep 01 05:51:18 AM UTC 24
Finished	Sep 01 05:51:24 AM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195737917 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.1195737917
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/22.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.662588396
Short name	T472
Test name
Test status
Simulation time	2159341609 ps
CPU time	24.85 seconds
Started	Sep 01 05:51:29 AM UTC 24
Finished	Sep 01 05:51:56 AM UTC 24
Peak memory	216892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662588396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.662588396
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/22.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.683680579
Short name	T460
Test name
Test status
Simulation time	39120878 ps
CPU time	3.31 seconds
Started	Sep 01 05:51:11 AM UTC 24
Finished	Sep 01 05:51:15 AM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683680579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.683680579
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/22.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.140267349
Short name	T479
Test name
Test status
Simulation time	10031039365 ps
CPU time	48.55 seconds
Started	Sep 01 05:51:15 AM UTC 24
Finished	Sep 01 05:52:05 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140267349 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.140267349
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/22.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.3538610358
Short name	T482
Test name
Test status
Simulation time	8530678737 ps
CPU time	52.64 seconds
Started	Sep 01 05:51:17 AM UTC 24
Finished	Sep 01 05:52:12 AM UTC 24
Peak memory	217008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538610358 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3538610358
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/22.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.896402860
Short name	T461
Test name
Test status
Simulation time	33547097 ps
CPU time	3.56 seconds
Started	Sep 01 05:51:12 AM UTC 24
Finished	Sep 01 05:51:17 AM UTC 24
Peak memory	217132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896402860 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.896402860
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/22.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.596481595
Short name	T218
Test name
Test status
Simulation time	1485222622 ps
CPU time	120.72 seconds
Started	Sep 01 05:51:40 AM UTC 24
Finished	Sep 01 05:53:43 AM UTC 24
Peak memory	218816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596481595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.596481595
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/22.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.802117175
Short name	T496
Test name
Test status
Simulation time	6090861968 ps
CPU time	75.59 seconds
Started	Sep 01 05:51:44 AM UTC 24
Finished	Sep 01 05:53:01 AM UTC 24
Peak memory	218944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802117175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.802117175
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/22.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1902697691
Short name	T480
Test name
Test status
Simulation time	10131444 ps
CPU time	21.79 seconds
Started	Sep 01 05:51:42 AM UTC 24
Finished	Sep 01 05:52:05 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902697691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.1902697691
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/22.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.3907064143
Short name	T256
Test name
Test status
Simulation time	1422365792 ps
CPU time	35.33 seconds
Started	Sep 01 05:51:37 AM UTC 24
Finished	Sep 01 05:52:14 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907064143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3907064143
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/22.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.261606594
Short name	T488
Test name
Test status
Simulation time	411924996 ps
CPU time	27.54 seconds
Started	Sep 01 05:52:07 AM UTC 24
Finished	Sep 01 05:52:36 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261606594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.261606594
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/23.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.179114667
Short name	T136
Test name
Test status
Simulation time	84040719719 ps
CPU time	501.4 seconds
Started	Sep 01 05:52:08 AM UTC 24
Finished	Sep 01 06:00:37 AM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179114667 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.179114667
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/23.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.3541166492
Short name	T495
Test name
Test status
Simulation time	769312314 ps
CPU time	32.47 seconds
Started	Sep 01 05:52:19 AM UTC 24
Finished	Sep 01 05:52:53 AM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541166492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.3541166492
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/23.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.1258779856
Short name	T494
Test name
Test status
Simulation time	1180669197 ps
CPU time	35.3 seconds
Started	Sep 01 05:52:14 AM UTC 24
Finished	Sep 01 05:52:50 AM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258779856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1258779856
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/23.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random.393672333
Short name	T485
Test name
Test status
Simulation time	464751773 ps
CPU time	14.62 seconds
Started	Sep 01 05:52:02 AM UTC 24
Finished	Sep 01 05:52:18 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393672333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.393672333
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/23.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.1842026938
Short name	T120
Test name
Test status
Simulation time	32651527023 ps
CPU time	83.19 seconds
Started	Sep 01 05:52:06 AM UTC 24
Finished	Sep 01 05:53:31 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842026938 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.1842026938
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/23.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.725057681
Short name	T500
Test name
Test status
Simulation time	4517722811 ps
CPU time	68.43 seconds
Started	Sep 01 05:52:06 AM UTC 24
Finished	Sep 01 05:53:16 AM UTC 24
Peak memory	216892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725057681 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.725057681
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/23.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.1798400206
Short name	T483
Test name
Test status
Simulation time	31003310 ps
CPU time	7.02 seconds
Started	Sep 01 05:52:04 AM UTC 24
Finished	Sep 01 05:52:12 AM UTC 24
Peak memory	216752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798400206 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.1798400206
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/23.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.1290652123
Short name	T484
Test name
Test status
Simulation time	133232600 ps
CPU time	4.31 seconds
Started	Sep 01 05:52:12 AM UTC 24
Finished	Sep 01 05:52:18 AM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290652123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1290652123
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/23.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.1050837566
Short name	T478
Test name
Test status
Simulation time	163009598 ps
CPU time	6 seconds
Started	Sep 01 05:51:57 AM UTC 24
Finished	Sep 01 05:52:04 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050837566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1050837566
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/23.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.2296396517
Short name	T493
Test name
Test status
Simulation time	4276721347 ps
CPU time	46.93 seconds
Started	Sep 01 05:52:00 AM UTC 24
Finished	Sep 01 05:52:48 AM UTC 24
Peak memory	217204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296396517 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2296396517
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/23.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.1422359053
Short name	T490
Test name
Test status
Simulation time	6797893800 ps
CPU time	38.44 seconds
Started	Sep 01 05:52:00 AM UTC 24
Finished	Sep 01 05:52:40 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422359053 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1422359053
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/23.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.824278863
Short name	T477
Test name
Test status
Simulation time	47962881 ps
CPU time	3.56 seconds
Started	Sep 01 05:51:58 AM UTC 24
Finished	Sep 01 05:52:03 AM UTC 24
Peak memory	217068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824278863 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.824278863
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/23.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.1767738835
Short name	T200
Test name
Test status
Simulation time	549163171 ps
CPU time	60.37 seconds
Started	Sep 01 05:52:19 AM UTC 24
Finished	Sep 01 05:53:21 AM UTC 24
Peak memory	218880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767738835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1767738835
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/23.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.3727036985
Short name	T546
Test name
Test status
Simulation time	14261098315 ps
CPU time	193.93 seconds
Started	Sep 01 05:52:23 AM UTC 24
Finished	Sep 01 05:55:40 AM UTC 24
Peak memory	219208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727036985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3727036985
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/23.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3179789368
Short name	T685
Test name
Test status
Simulation time	3169644587 ps
CPU time	579.45 seconds
Started	Sep 01 05:52:21 AM UTC 24
Finished	Sep 01 06:02:09 AM UTC 24
Peak memory	237692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179789368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.3179789368
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/23.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.406771259
Short name	T507
Test name
Test status
Simulation time	914005154 ps
CPU time	98.89 seconds
Started	Sep 01 05:52:23 AM UTC 24
Finished	Sep 01 05:54:04 AM UTC 24
Peak memory	221124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406771259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.406771259
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/23.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.1471042739
Short name	T487
Test name
Test status
Simulation time	35428348 ps
CPU time	6.28 seconds
Started	Sep 01 05:52:15 AM UTC 24
Finished	Sep 01 05:52:22 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471042739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1471042739
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/23.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.354280051
Short name	T499
Test name
Test status
Simulation time	661998872 ps
CPU time	18.15 seconds
Started	Sep 01 05:52:51 AM UTC 24
Finished	Sep 01 05:53:11 AM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354280051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.354280051
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/24.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1628361560
Short name	T223
Test name
Test status
Simulation time	10513981619 ps
CPU time	61.53 seconds
Started	Sep 01 05:52:54 AM UTC 24
Finished	Sep 01 05:53:57 AM UTC 24
Peak memory	217156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628361560 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.1628361560
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/24.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.1259998646
Short name	T503
Test name
Test status
Simulation time	138078851 ps
CPU time	14.04 seconds
Started	Sep 01 05:53:11 AM UTC 24
Finished	Sep 01 05:53:26 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259998646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.1259998646
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/24.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.1877507371
Short name	T498
Test name
Test status
Simulation time	18147325 ps
CPU time	2.65 seconds
Started	Sep 01 05:53:06 AM UTC 24
Finished	Sep 01 05:53:10 AM UTC 24
Peak memory	217076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877507371 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1877507371
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/24.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random.405317872
Short name	T214
Test name
Test status
Simulation time	3066957512 ps
CPU time	54.21 seconds
Started	Sep 01 05:52:42 AM UTC 24
Finished	Sep 01 05:53:38 AM UTC 24
Peak memory	217220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405317872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.405317872
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/24.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.3803998847
Short name	T215
Test name
Test status
Simulation time	23447404805 ps
CPU time	146.84 seconds
Started	Sep 01 05:52:45 AM UTC 24
Finished	Sep 01 05:55:15 AM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803998847 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3803998847
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/24.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.1507477632
Short name	T564
Test name
Test status
Simulation time	16609070241 ps
CPU time	228.26 seconds
Started	Sep 01 05:52:49 AM UTC 24
Finished	Sep 01 05:56:41 AM UTC 24
Peak memory	216904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507477632 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1507477632
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/24.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.1884966127
Short name	T213
Test name
Test status
Simulation time	238267149 ps
CPU time	24.28 seconds
Started	Sep 01 05:52:44 AM UTC 24
Finished	Sep 01 05:53:09 AM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884966127 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1884966127
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/24.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.4170614327
Short name	T497
Test name
Test status
Simulation time	41500027 ps
CPU time	5.13 seconds
Started	Sep 01 05:53:02 AM UTC 24
Finished	Sep 01 05:53:08 AM UTC 24
Peak memory	217028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170614327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.4170614327
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/24.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.870868853
Short name	T489
Test name
Test status
Simulation time	25522675 ps
CPU time	3.18 seconds
Started	Sep 01 05:52:33 AM UTC 24
Finished	Sep 01 05:52:38 AM UTC 24
Peak memory	217132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870868853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.870868853
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/24.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.505519000
Short name	T501
Test name
Test status
Simulation time	4097308176 ps
CPU time	43.03 seconds
Started	Sep 01 05:52:39 AM UTC 24
Finished	Sep 01 05:53:23 AM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505519000 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.505519000
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/24.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.3351385780
Short name	T219
Test name
Test status
Simulation time	5070456840 ps
CPU time	63.5 seconds
Started	Sep 01 05:52:41 AM UTC 24
Finished	Sep 01 05:53:47 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351385780 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3351385780
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/24.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.50076624
Short name	T491
Test name
Test status
Simulation time	49872181 ps
CPU time	3.21 seconds
Started	Sep 01 05:52:37 AM UTC 24
Finished	Sep 01 05:52:41 AM UTC 24
Peak memory	216744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50076624 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.50076624
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/24.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.3050798758
Short name	T197
Test name
Test status
Simulation time	3387609365 ps
CPU time	170.55 seconds
Started	Sep 01 05:53:11 AM UTC 24
Finished	Sep 01 05:56:05 AM UTC 24
Peak memory	220996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050798758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3050798758
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/24.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.1379106218
Short name	T547
Test name
Test status
Simulation time	4303968444 ps
CPU time	143.7 seconds
Started	Sep 01 05:53:17 AM UTC 24
Finished	Sep 01 05:55:44 AM UTC 24
Peak memory	219208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379106218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1379106218
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/24.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.3101697385
Short name	T196
Test name
Test status
Simulation time	219967229 ps
CPU time	45.82 seconds
Started	Sep 01 05:53:12 AM UTC 24
Finished	Sep 01 05:54:00 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101697385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.3101697385
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/24.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.3410817529
Short name	T531
Test name
Test status
Simulation time	191876566 ps
CPU time	99.48 seconds
Started	Sep 01 05:53:23 AM UTC 24
Finished	Sep 01 05:55:04 AM UTC 24
Peak memory	222980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410817529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.3410817529
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/24.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.982437672
Short name	T502
Test name
Test status
Simulation time	84066376 ps
CPU time	12.95 seconds
Started	Sep 01 05:53:09 AM UTC 24
Finished	Sep 01 05:53:24 AM UTC 24
Peak memory	218876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982437672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.982437672
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/24.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.3508610037
Short name	T516
Test name
Test status
Simulation time	1216529033 ps
CPU time	40.41 seconds
Started	Sep 01 05:53:40 AM UTC 24
Finished	Sep 01 05:54:22 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508610037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3508610037
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/25.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.70472532
Short name	T69
Test name
Test status
Simulation time	81929203929 ps
CPU time	552.05 seconds
Started	Sep 01 05:53:41 AM UTC 24
Finished	Sep 01 06:03:00 AM UTC 24
Peak memory	220496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70472532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.70472532
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/25.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3177035483
Short name	T511
Test name
Test status
Simulation time	314340304 ps
CPU time	10.81 seconds
Started	Sep 01 05:53:57 AM UTC 24
Finished	Sep 01 05:54:09 AM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177035483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3177035483
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/25.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.959191109
Short name	T509
Test name
Test status
Simulation time	1128832283 ps
CPU time	16.72 seconds
Started	Sep 01 05:53:48 AM UTC 24
Finished	Sep 01 05:54:05 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959191109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.959191109
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/25.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random.1500286243
Short name	T508
Test name
Test status
Simulation time	506124109 ps
CPU time	33.64 seconds
Started	Sep 01 05:53:30 AM UTC 24
Finished	Sep 01 05:54:05 AM UTC 24
Peak memory	216568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500286243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.1500286243
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/25.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.306904506
Short name	T220
Test name
Test status
Simulation time	1825440955 ps
CPU time	13.07 seconds
Started	Sep 01 05:53:36 AM UTC 24
Finished	Sep 01 05:53:50 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306904506 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.306904506
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/25.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1280469432
Short name	T510
Test name
Test status
Simulation time	3458432896 ps
CPU time	25.93 seconds
Started	Sep 01 05:53:40 AM UTC 24
Finished	Sep 01 05:54:07 AM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280469432 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1280469432
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/25.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.2175407854
Short name	T222
Test name
Test status
Simulation time	416022379 ps
CPU time	23.48 seconds
Started	Sep 01 05:53:32 AM UTC 24
Finished	Sep 01 05:53:57 AM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175407854 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2175407854
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/25.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.3225260616
Short name	T240
Test name
Test status
Simulation time	239595919 ps
CPU time	21.33 seconds
Started	Sep 01 05:53:44 AM UTC 24
Finished	Sep 01 05:54:07 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225260616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3225260616
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/25.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.3819342054
Short name	T504
Test name
Test status
Simulation time	27197435 ps
CPU time	3.47 seconds
Started	Sep 01 05:53:24 AM UTC 24
Finished	Sep 01 05:53:28 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819342054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.3819342054
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/25.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.93213952
Short name	T522
Test name
Test status
Simulation time	7549167959 ps
CPU time	69.3 seconds
Started	Sep 01 05:53:27 AM UTC 24
Finished	Sep 01 05:54:39 AM UTC 24
Peak memory	217076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93213952 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.93213952
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/25.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.126323245
Short name	T513
Test name
Test status
Simulation time	4264962494 ps
CPU time	41.42 seconds
Started	Sep 01 05:53:30 AM UTC 24
Finished	Sep 01 05:54:13 AM UTC 24
Peak memory	216548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126323245 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.126323245
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/25.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.3706644582
Short name	T505
Test name
Test status
Simulation time	28204358 ps
CPU time	2.36 seconds
Started	Sep 01 05:53:25 AM UTC 24
Finished	Sep 01 05:53:29 AM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706644582 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.3706644582
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/25.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.373942671
Short name	T127
Test name
Test status
Simulation time	11279484220 ps
CPU time	318.67 seconds
Started	Sep 01 05:53:57 AM UTC 24
Finished	Sep 01 05:59:21 AM UTC 24
Peak memory	220928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373942671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.373942671
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/25.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1886684216
Short name	T552
Test name
Test status
Simulation time	3750808741 ps
CPU time	111.29 seconds
Started	Sep 01 05:54:01 AM UTC 24
Finished	Sep 01 05:55:55 AM UTC 24
Peak memory	220996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886684216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1886684216
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/25.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.2243899321
Short name	T241
Test name
Test status
Simulation time	569795980 ps
CPU time	240.81 seconds
Started	Sep 01 05:53:59 AM UTC 24
Finished	Sep 01 05:58:03 AM UTC 24
Peak memory	222984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243899321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.2243899321
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/25.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.1342563138
Short name	T520
Test name
Test status
Simulation time	92584805 ps
CPU time	29.59 seconds
Started	Sep 01 05:54:02 AM UTC 24
Finished	Sep 01 05:54:33 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342563138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.1342563138
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/25.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.668494766
Short name	T506
Test name
Test status
Simulation time	203446689 ps
CPU time	9.58 seconds
Started	Sep 01 05:53:51 AM UTC 24
Finished	Sep 01 05:54:01 AM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668494766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.668494766
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/25.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.2243300474
Short name	T536
Test name
Test status
Simulation time	1742989664 ps
CPU time	61.67 seconds
Started	Sep 01 05:54:11 AM UTC 24
Finished	Sep 01 05:55:16 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243300474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.2243300474
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/26.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1197560827
Short name	T133
Test name
Test status
Simulation time	27938149043 ps
CPU time	344.91 seconds
Started	Sep 01 05:54:11 AM UTC 24
Finished	Sep 01 06:00:01 AM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197560827 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.1197560827
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/26.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3148357156
Short name	T526
Test name
Test status
Simulation time	717389786 ps
CPU time	31.83 seconds
Started	Sep 01 05:54:22 AM UTC 24
Finished	Sep 01 05:54:56 AM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148357156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3148357156
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/26.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.3722530839
Short name	T515
Test name
Test status
Simulation time	21275317 ps
CPU time	2.23 seconds
Started	Sep 01 05:54:18 AM UTC 24
Finished	Sep 01 05:54:21 AM UTC 24
Peak memory	217140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722530839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3722530839
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/26.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random.1782805823
Short name	T518
Test name
Test status
Simulation time	513672485 ps
CPU time	19.22 seconds
Started	Sep 01 05:54:07 AM UTC 24
Finished	Sep 01 05:54:28 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782805823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.1782805823
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/26.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.2958434576
Short name	T548
Test name
Test status
Simulation time	21302096221 ps
CPU time	93.59 seconds
Started	Sep 01 05:54:08 AM UTC 24
Finished	Sep 01 05:55:44 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958434576 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.2958434576
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/26.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.3891576922
Short name	T556
Test name
Test status
Simulation time	7834440385 ps
CPU time	120.44 seconds
Started	Sep 01 05:54:10 AM UTC 24
Finished	Sep 01 05:56:13 AM UTC 24
Peak memory	218888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891576922 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3891576922
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/26.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.1001200640
Short name	T514
Test name
Test status
Simulation time	84177728 ps
CPU time	7.9 seconds
Started	Sep 01 05:54:08 AM UTC 24
Finished	Sep 01 05:54:17 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001200640 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.1001200640
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/26.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.2719347683
Short name	T517
Test name
Test status
Simulation time	1033230144 ps
CPU time	11.62 seconds
Started	Sep 01 05:54:14 AM UTC 24
Finished	Sep 01 05:54:27 AM UTC 24
Peak memory	217152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719347683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2719347683
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/26.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.1348998565
Short name	T65
Test name
Test status
Simulation time	143438186 ps
CPU time	4.97 seconds
Started	Sep 01 05:54:02 AM UTC 24
Finished	Sep 01 05:54:08 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348998565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1348998565
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/26.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3883163009
Short name	T540
Test name
Test status
Simulation time	39113546085 ps
CPU time	77.23 seconds
Started	Sep 01 05:54:06 AM UTC 24
Finished	Sep 01 05:55:25 AM UTC 24
Peak memory	216884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883163009 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3883163009
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/26.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.1129015916
Short name	T528
Test name
Test status
Simulation time	9227239024 ps
CPU time	50.53 seconds
Started	Sep 01 05:54:06 AM UTC 24
Finished	Sep 01 05:54:58 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129015916 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1129015916
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/26.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.3065240763
Short name	T512
Test name
Test status
Simulation time	108891360 ps
CPU time	2.76 seconds
Started	Sep 01 05:54:06 AM UTC 24
Finished	Sep 01 05:54:09 AM UTC 24
Peak memory	217064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065240763 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.3065240763
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/26.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.1215116573
Short name	T198
Test name
Test status
Simulation time	2797191008 ps
CPU time	211.37 seconds
Started	Sep 01 05:54:28 AM UTC 24
Finished	Sep 01 05:58:03 AM UTC 24
Peak memory	223364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215116573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1215116573
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/26.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.4239043125
Short name	T230
Test name
Test status
Simulation time	1580506512 ps
CPU time	140.56 seconds
Started	Sep 01 05:54:32 AM UTC 24
Finished	Sep 01 05:56:56 AM UTC 24
Peak memory	220932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239043125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.4239043125
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/26.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.916718772
Short name	T603
Test name
Test status
Simulation time	1889598855 ps
CPU time	260.59 seconds
Started	Sep 01 05:54:34 AM UTC 24
Finished	Sep 01 05:58:59 AM UTC 24
Peak memory	233844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916718772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.916718772
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/26.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.1138154300
Short name	T519
Test name
Test status
Simulation time	163971729 ps
CPU time	7.66 seconds
Started	Sep 01 05:54:22 AM UTC 24
Finished	Sep 01 05:54:31 AM UTC 24
Peak memory	217084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138154300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1138154300
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/26.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.3565296550
Short name	T545
Test name
Test status
Simulation time	2645700303 ps
CPU time	42.96 seconds
Started	Sep 01 05:54:55 AM UTC 24
Finished	Sep 01 05:55:40 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565296550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.3565296550
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/27.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.900265062
Short name	T857
Test name
Test status
Simulation time	75723777453 ps
CPU time	727.03 seconds
Started	Sep 01 05:54:56 AM UTC 24
Finished	Sep 01 06:07:11 AM UTC 24
Peak memory	222612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900265062 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.900265062
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/27.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3487888765
Short name	T532
Test name
Test status
Simulation time	64050739 ps
CPU time	8.42 seconds
Started	Sep 01 05:55:01 AM UTC 24
Finished	Sep 01 05:55:11 AM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487888765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3487888765
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/27.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.206628873
Short name	T530
Test name
Test status
Simulation time	53922935 ps
CPU time	3.78 seconds
Started	Sep 01 05:54:59 AM UTC 24
Finished	Sep 01 05:55:04 AM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206628873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.206628873
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/27.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random.3421030694
Short name	T529
Test name
Test status
Simulation time	116389890 ps
CPU time	17.9 seconds
Started	Sep 01 05:54:41 AM UTC 24
Finished	Sep 01 05:55:00 AM UTC 24
Peak memory	217028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421030694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.3421030694
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/27.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.1664574630
Short name	T609
Test name
Test status
Simulation time	89576473314 ps
CPU time	256.8 seconds
Started	Sep 01 05:54:51 AM UTC 24
Finished	Sep 01 05:59:11 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664574630 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1664574630
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/27.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3624135605
Short name	T66
Test name
Test status
Simulation time	23216896307 ps
CPU time	300.46 seconds
Started	Sep 01 05:54:52 AM UTC 24
Finished	Sep 01 05:59:57 AM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624135605 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3624135605
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/27.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.2904911932
Short name	T535
Test name
Test status
Simulation time	209274072 ps
CPU time	31.07 seconds
Started	Sep 01 05:54:41 AM UTC 24
Finished	Sep 01 05:55:13 AM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904911932 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2904911932
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/27.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.2514126023
Short name	T533
Test name
Test status
Simulation time	371207703 ps
CPU time	12.81 seconds
Started	Sep 01 05:54:57 AM UTC 24
Finished	Sep 01 05:55:11 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514126023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2514126023
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/27.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.932025196
Short name	T523
Test name
Test status
Simulation time	662183512 ps
CPU time	3.83 seconds
Started	Sep 01 05:54:34 AM UTC 24
Finished	Sep 01 05:54:39 AM UTC 24
Peak memory	217068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932025196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.932025196
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/27.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.3994107053
Short name	T549
Test name
Test status
Simulation time	8943234351 ps
CPU time	67.18 seconds
Started	Sep 01 05:54:40 AM UTC 24
Finished	Sep 01 05:55:49 AM UTC 24
Peak memory	217140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994107053 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3994107053
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/27.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.2348892165
Short name	T542
Test name
Test status
Simulation time	17509819119 ps
CPU time	45.32 seconds
Started	Sep 01 05:54:41 AM UTC 24
Finished	Sep 01 05:55:27 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348892165 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2348892165
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/27.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1712849092
Short name	T524
Test name
Test status
Simulation time	22778573 ps
CPU time	2.48 seconds
Started	Sep 01 05:54:36 AM UTC 24
Finished	Sep 01 05:54:40 AM UTC 24
Peak memory	217064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712849092 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.1712849092
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/27.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.3230947749
Short name	T124
Test name
Test status
Simulation time	7195917928 ps
CPU time	147.85 seconds
Started	Sep 01 05:55:04 AM UTC 24
Finished	Sep 01 05:57:35 AM UTC 24
Peak memory	221316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230947749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3230947749
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/27.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.1388509606
Short name	T234
Test name
Test status
Simulation time	2540795075 ps
CPU time	108.83 seconds
Started	Sep 01 05:55:11 AM UTC 24
Finished	Sep 01 05:57:03 AM UTC 24
Peak memory	219144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388509606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.1388509606
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/27.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3632284527
Short name	T31
Test name
Test status
Simulation time	567676450 ps
CPU time	333.72 seconds
Started	Sep 01 05:55:06 AM UTC 24
Finished	Sep 01 06:00:45 AM UTC 24
Peak memory	223244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632284527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.3632284527
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/27.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.498222983
Short name	T233
Test name
Test status
Simulation time	381847832 ps
CPU time	107.34 seconds
Started	Sep 01 05:55:13 AM UTC 24
Finished	Sep 01 05:57:02 AM UTC 24
Peak memory	220928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498222983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.498222983
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/27.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.891535482
Short name	T541
Test name
Test status
Simulation time	531910333 ps
CPU time	26.48 seconds
Started	Sep 01 05:54:59 AM UTC 24
Finished	Sep 01 05:55:27 AM UTC 24
Peak memory	216960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891535482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.891535482
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/27.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.3262726293
Short name	T121
Test name
Test status
Simulation time	963686627 ps
CPU time	38.32 seconds
Started	Sep 01 05:55:29 AM UTC 24
Finished	Sep 01 05:56:09 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262726293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3262726293
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/28.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.1083081161
Short name	T225
Test name
Test status
Simulation time	98357496043 ps
CPU time	535.2 seconds
Started	Sep 01 05:55:29 AM UTC 24
Finished	Sep 01 06:04:31 AM UTC 24
Peak memory	219264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083081161 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.1083081161
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/28.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.3611316934
Short name	T562
Test name
Test status
Simulation time	2146964221 ps
CPU time	38.55 seconds
Started	Sep 01 05:55:42 AM UTC 24
Finished	Sep 01 05:56:22 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611316934 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.3611316934
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/28.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.2976920000
Short name	T554
Test name
Test status
Simulation time	763522620 ps
CPU time	29.93 seconds
Started	Sep 01 05:55:38 AM UTC 24
Finished	Sep 01 05:56:09 AM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976920000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2976920000
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/28.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random.1064368500
Short name	T284
Test name
Test status
Simulation time	1371796540 ps
CPU time	47.59 seconds
Started	Sep 01 05:55:20 AM UTC 24
Finished	Sep 01 05:56:09 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064368500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.1064368500
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/28.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.591335005
Short name	T588
Test name
Test status
Simulation time	56470677596 ps
CPU time	184.3 seconds
Started	Sep 01 05:55:21 AM UTC 24
Finished	Sep 01 05:58:29 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591335005 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.591335005
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/28.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2199202634
Short name	T692
Test name
Test status
Simulation time	115759274018 ps
CPU time	407.07 seconds
Started	Sep 01 05:55:26 AM UTC 24
Finished	Sep 01 06:02:18 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199202634 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2199202634
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/28.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.3002652633
Short name	T551
Test name
Test status
Simulation time	257907872 ps
CPU time	30.71 seconds
Started	Sep 01 05:55:20 AM UTC 24
Finished	Sep 01 05:55:52 AM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002652633 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3002652633
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/28.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.2527094474
Short name	T278
Test name
Test status
Simulation time	2722799932 ps
CPU time	22.34 seconds
Started	Sep 01 05:55:35 AM UTC 24
Finished	Sep 01 05:55:59 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527094474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2527094474
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/28.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.1028246816
Short name	T537
Test name
Test status
Simulation time	50590653 ps
CPU time	3.42 seconds
Started	Sep 01 05:55:15 AM UTC 24
Finished	Sep 01 05:55:19 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028246816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1028246816
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/28.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.334653712
Short name	T566
Test name
Test status
Simulation time	38921652586 ps
CPU time	84.22 seconds
Started	Sep 01 05:55:16 AM UTC 24
Finished	Sep 01 05:56:42 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334653712 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.334653712
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/28.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.3182915950
Short name	T281
Test name
Test status
Simulation time	6755384989 ps
CPU time	41.46 seconds
Started	Sep 01 05:55:18 AM UTC 24
Finished	Sep 01 05:56:00 AM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182915950 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3182915950
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/28.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1345130979
Short name	T538
Test name
Test status
Simulation time	140107503 ps
CPU time	3.69 seconds
Started	Sep 01 05:55:15 AM UTC 24
Finished	Sep 01 05:55:19 AM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345130979 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1345130979
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/28.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.1122211116
Short name	T579
Test name
Test status
Simulation time	751543734 ps
CPU time	95.35 seconds
Started	Sep 01 05:55:50 AM UTC 24
Finished	Sep 01 05:57:28 AM UTC 24
Peak memory	220868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122211116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1122211116
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/28.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.433866968
Short name	T610
Test name
Test status
Simulation time	228078550 ps
CPU time	204.41 seconds
Started	Sep 01 05:55:46 AM UTC 24
Finished	Sep 01 05:59:14 AM UTC 24
Peak memory	220868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433866968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.433866968
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/28.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.908836720
Short name	T629
Test name
Test status
Simulation time	1165628490 ps
CPU time	243.98 seconds
Started	Sep 01 05:55:51 AM UTC 24
Finished	Sep 01 05:59:59 AM UTC 24
Peak memory	233652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908836720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.908836720
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/28.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.356542283
Short name	T553
Test name
Test status
Simulation time	60611643 ps
CPU time	14.86 seconds
Started	Sep 01 05:55:41 AM UTC 24
Finished	Sep 01 05:55:57 AM UTC 24
Peak memory	217152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356542283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.356542283
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/28.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.3320006835
Short name	T575
Test name
Test status
Simulation time	2394255450 ps
CPU time	68.73 seconds
Started	Sep 01 05:56:03 AM UTC 24
Finished	Sep 01 05:57:14 AM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320006835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.3320006835
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/29.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.39440216
Short name	T884
Test name
Test status
Simulation time	154850869084 ps
CPU time	770.37 seconds
Started	Sep 01 05:56:05 AM UTC 24
Finished	Sep 01 06:09:05 AM UTC 24
Peak memory	222548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39440216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.39440216
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/29.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.212780202
Short name	T565
Test name
Test status
Simulation time	575579879 ps
CPU time	28.4 seconds
Started	Sep 01 05:56:12 AM UTC 24
Finished	Sep 01 05:56:41 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212780202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.212780202
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/29.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.112149577
Short name	T567
Test name
Test status
Simulation time	1222291416 ps
CPU time	32.11 seconds
Started	Sep 01 05:56:12 AM UTC 24
Finished	Sep 01 05:56:45 AM UTC 24
Peak memory	217156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112149577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.112149577
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/29.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random.564619671
Short name	T557
Test name
Test status
Simulation time	297722131 ps
CPU time	10.56 seconds
Started	Sep 01 05:56:01 AM UTC 24
Finished	Sep 01 05:56:13 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564619671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.564619671
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/29.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.1175780299
Short name	T679
Test name
Test status
Simulation time	39840550484 ps
CPU time	346.41 seconds
Started	Sep 01 05:56:02 AM UTC 24
Finished	Sep 01 06:01:53 AM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175780299 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1175780299
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/29.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1404205793
Short name	T268
Test name
Test status
Simulation time	55278120660 ps
CPU time	361.52 seconds
Started	Sep 01 05:56:02 AM UTC 24
Finished	Sep 01 06:02:08 AM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404205793 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1404205793
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/29.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.1102995454
Short name	T558
Test name
Test status
Simulation time	59447158 ps
CPU time	12.09 seconds
Started	Sep 01 05:56:01 AM UTC 24
Finished	Sep 01 05:56:15 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102995454 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.1102995454
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/29.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.3392282509
Short name	T563
Test name
Test status
Simulation time	603699699 ps
CPU time	16.71 seconds
Started	Sep 01 05:56:06 AM UTC 24
Finished	Sep 01 05:56:24 AM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392282509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3392282509
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/29.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.982481443
Short name	T279
Test name
Test status
Simulation time	195235688 ps
CPU time	4.73 seconds
Started	Sep 01 05:55:54 AM UTC 24
Finished	Sep 01 05:56:00 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982481443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.982481443
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/29.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.871009271
Short name	T569
Test name
Test status
Simulation time	9303438130 ps
CPU time	47.06 seconds
Started	Sep 01 05:55:58 AM UTC 24
Finished	Sep 01 05:56:47 AM UTC 24
Peak memory	217200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871009271 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.871009271
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/29.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.3606103192
Short name	T573
Test name
Test status
Simulation time	3921578454 ps
CPU time	67.94 seconds
Started	Sep 01 05:56:01 AM UTC 24
Finished	Sep 01 05:57:11 AM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606103192 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3606103192
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/29.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.4073313297
Short name	T280
Test name
Test status
Simulation time	32854829 ps
CPU time	2.99 seconds
Started	Sep 01 05:55:56 AM UTC 24
Finished	Sep 01 05:56:00 AM UTC 24
Peak memory	217064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073313297 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.4073313297
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/29.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.4162234841
Short name	T153
Test name
Test status
Simulation time	2294496313 ps
CPU time	86.26 seconds
Started	Sep 01 05:56:12 AM UTC 24
Finished	Sep 01 05:57:40 AM UTC 24
Peak memory	221060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162234841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.4162234841
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/29.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1345923864
Short name	T570
Test name
Test status
Simulation time	406658867 ps
CPU time	32.89 seconds
Started	Sep 01 05:56:14 AM UTC 24
Finished	Sep 01 05:56:49 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345923864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1345923864
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/29.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.2855987847
Short name	T598
Test name
Test status
Simulation time	448174237 ps
CPU time	157.71 seconds
Started	Sep 01 05:56:12 AM UTC 24
Finished	Sep 01 05:58:52 AM UTC 24
Peak memory	220932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855987847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.2855987847
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/29.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.680438658
Short name	T151
Test name
Test status
Simulation time	168176841 ps
CPU time	79.18 seconds
Started	Sep 01 05:56:14 AM UTC 24
Finished	Sep 01 05:57:35 AM UTC 24
Peak memory	219136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680438658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.680438658
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/29.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.1475642145
Short name	T559
Test name
Test status
Simulation time	154862443 ps
CPU time	6.73 seconds
Started	Sep 01 05:56:12 AM UTC 24
Finished	Sep 01 05:56:19 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475642145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.1475642145
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/29.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.219673994
Short name	T78
Test name
Test status
Simulation time	3465426991 ps
CPU time	44.65 seconds
Started	Sep 01 05:39:10 AM UTC 24
Finished	Sep 01 05:39:56 AM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219673994 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.219673994
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/3.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.2043300413
Short name	T42
Test name
Test status
Simulation time	930350036 ps
CPU time	29.63 seconds
Started	Sep 01 05:39:23 AM UTC 24
Finished	Sep 01 05:39:54 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043300413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.2043300413
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/3.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.3407294290
Short name	T318
Test name
Test status
Simulation time	3475359824 ps
CPU time	38.73 seconds
Started	Sep 01 05:39:19 AM UTC 24
Finished	Sep 01 05:39:59 AM UTC 24
Peak memory	217144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407294290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3407294290
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/3.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random.1299888515
Short name	T33
Test name
Test status
Simulation time	4659178766 ps
CPU time	41.86 seconds
Started	Sep 01 05:38:39 AM UTC 24
Finished	Sep 01 05:39:22 AM UTC 24
Peak memory	218944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299888515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.1299888515
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/3.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.3887118812
Short name	T162
Test name
Test status
Simulation time	9699655678 ps
CPU time	51.56 seconds
Started	Sep 01 05:38:54 AM UTC 24
Finished	Sep 01 05:39:47 AM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887118812 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3887118812
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/3.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.3351585048
Short name	T98
Test name
Test status
Simulation time	13973597694 ps
CPU time	152.14 seconds
Started	Sep 01 05:38:59 AM UTC 24
Finished	Sep 01 05:41:34 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351585048 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3351585048
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/3.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.2225296849
Short name	T270
Test name
Test status
Simulation time	99789381 ps
CPU time	14.37 seconds
Started	Sep 01 05:38:46 AM UTC 24
Finished	Sep 01 05:39:01 AM UTC 24
Peak memory	216888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225296849 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2225296849
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/3.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.957476697
Short name	T161
Test name
Test status
Simulation time	605600977 ps
CPU time	20.89 seconds
Started	Sep 01 05:39:15 AM UTC 24
Finished	Sep 01 05:39:37 AM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957476697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.957476697
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/3.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.1725175750
Short name	T76
Test name
Test status
Simulation time	118252818 ps
CPU time	3.6 seconds
Started	Sep 01 05:38:28 AM UTC 24
Finished	Sep 01 05:38:33 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725175750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.1725175750
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/3.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3978106758
Short name	T179
Test name
Test status
Simulation time	7994407711 ps
CPU time	58.07 seconds
Started	Sep 01 05:38:34 AM UTC 24
Finished	Sep 01 05:39:33 AM UTC 24
Peak memory	216948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978106758 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3978106758
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/3.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.4248225409
Short name	T237
Test name
Test status
Simulation time	10309066697 ps
CPU time	33.46 seconds
Started	Sep 01 05:38:39 AM UTC 24
Finished	Sep 01 05:39:13 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248225409 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.4248225409
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/3.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1543701196
Short name	T165
Test name
Test status
Simulation time	35524353 ps
CPU time	3.04 seconds
Started	Sep 01 05:38:34 AM UTC 24
Finished	Sep 01 05:38:38 AM UTC 24
Peak memory	216744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543701196 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1543701196
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/3.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3362970486
Short name	T195
Test name
Test status
Simulation time	10668718833 ps
CPU time	151.16 seconds
Started	Sep 01 05:39:29 AM UTC 24
Finished	Sep 01 05:42:03 AM UTC 24
Peak memory	218944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362970486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3362970486
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/3.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.2026970081
Short name	T186
Test name
Test status
Simulation time	825635592 ps
CPU time	284.48 seconds
Started	Sep 01 05:39:26 AM UTC 24
Finished	Sep 01 05:44:15 AM UTC 24
Peak memory	222920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026970081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.2026970081
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/3.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1605548371
Short name	T113
Test name
Test status
Simulation time	406984411 ps
CPU time	158.42 seconds
Started	Sep 01 05:39:35 AM UTC 24
Finished	Sep 01 05:42:16 AM UTC 24
Peak memory	221196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605548371 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.1605548371
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/3.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.2007348837
Short name	T178
Test name
Test status
Simulation time	28371673 ps
CPU time	5.05 seconds
Started	Sep 01 05:39:22 AM UTC 24
Finished	Sep 01 05:39:28 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007348837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2007348837
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/3.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.2128651062
Short name	T229
Test name
Test status
Simulation time	723350933 ps
CPU time	9.27 seconds
Started	Sep 01 05:56:42 AM UTC 24
Finished	Sep 01 05:56:53 AM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128651062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.2128651062
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/30.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.1597487478
Short name	T782
Test name
Test status
Simulation time	46932607652 ps
CPU time	491.81 seconds
Started	Sep 01 05:56:43 AM UTC 24
Finished	Sep 01 06:05:02 AM UTC 24
Peak memory	221320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597487478 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.1597487478
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/30.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3748724490
Short name	T571
Test name
Test status
Simulation time	603375423 ps
CPU time	16.38 seconds
Started	Sep 01 05:56:50 AM UTC 24
Finished	Sep 01 05:57:07 AM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748724490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3748724490
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/30.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.367829256
Short name	T577
Test name
Test status
Simulation time	833656935 ps
CPU time	28.91 seconds
Started	Sep 01 05:56:47 AM UTC 24
Finished	Sep 01 05:57:17 AM UTC 24
Peak memory	217160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367829256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.367829256
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/30.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random.3320166039
Short name	T568
Test name
Test status
Simulation time	208022496 ps
CPU time	22.81 seconds
Started	Sep 01 05:56:22 AM UTC 24
Finished	Sep 01 05:56:46 AM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320166039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.3320166039
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/30.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.2547289775
Short name	T267
Test name
Test status
Simulation time	60236512829 ps
CPU time	359.98 seconds
Started	Sep 01 05:56:25 AM UTC 24
Finished	Sep 01 06:02:29 AM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547289775 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2547289775
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/30.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1884650412
Short name	T596
Test name
Test status
Simulation time	8853108898 ps
CPU time	125.78 seconds
Started	Sep 01 05:56:42 AM UTC 24
Finished	Sep 01 05:58:50 AM UTC 24
Peak memory	217224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884650412 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1884650412
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/30.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.578556258
Short name	T228
Test name
Test status
Simulation time	172998040 ps
CPU time	26.35 seconds
Started	Sep 01 05:56:23 AM UTC 24
Finished	Sep 01 05:56:51 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578556258 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.578556258
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/30.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.2627242767
Short name	T231
Test name
Test status
Simulation time	407329986 ps
CPU time	13.08 seconds
Started	Sep 01 05:56:46 AM UTC 24
Finished	Sep 01 05:57:00 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627242767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2627242767
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/30.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.3498011782
Short name	T561
Test name
Test status
Simulation time	37750665 ps
CPU time	3.46 seconds
Started	Sep 01 05:56:16 AM UTC 24
Finished	Sep 01 05:56:21 AM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498011782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3498011782
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/30.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.3073541870
Short name	T290
Test name
Test status
Simulation time	18476407355 ps
CPU time	57.46 seconds
Started	Sep 01 05:56:21 AM UTC 24
Finished	Sep 01 05:57:20 AM UTC 24
Peak memory	217140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073541870 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3073541870
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/30.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.1554976851
Short name	T232
Test name
Test status
Simulation time	5402611465 ps
CPU time	38.03 seconds
Started	Sep 01 05:56:21 AM UTC 24
Finished	Sep 01 05:57:00 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554976851 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1554976851
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/30.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.3993434857
Short name	T560
Test name
Test status
Simulation time	23427973 ps
CPU time	2.74 seconds
Started	Sep 01 05:56:16 AM UTC 24
Finished	Sep 01 05:56:20 AM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993434857 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.3993434857
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/30.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.6820552
Short name	T578
Test name
Test status
Simulation time	579216685 ps
CPU time	28.21 seconds
Started	Sep 01 05:56:51 AM UTC 24
Finished	Sep 01 05:57:20 AM UTC 24
Peak memory	216760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6820552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T EST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.6820552
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/30.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3919013335
Short name	T636
Test name
Test status
Simulation time	7716272717 ps
CPU time	195.75 seconds
Started	Sep 01 05:56:54 AM UTC 24
Finished	Sep 01 06:00:13 AM UTC 24
Peak memory	221320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919013335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3919013335
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/30.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.476272851
Short name	T645
Test name
Test status
Simulation time	433708710 ps
CPU time	216.38 seconds
Started	Sep 01 05:56:53 AM UTC 24
Finished	Sep 01 06:00:33 AM UTC 24
Peak memory	220928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476272851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.476272851
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/30.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.385116009
Short name	T655
Test name
Test status
Simulation time	9731656990 ps
CPU time	234.4 seconds
Started	Sep 01 05:56:58 AM UTC 24
Finished	Sep 01 06:00:56 AM UTC 24
Peak memory	223404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385116009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.385116009
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/30.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.3367022283
Short name	T572
Test name
Test status
Simulation time	409879927 ps
CPU time	21.39 seconds
Started	Sep 01 05:56:48 AM UTC 24
Finished	Sep 01 05:57:11 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367022283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.3367022283
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/30.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.207890170
Short name	T594
Test name
Test status
Simulation time	2213907902 ps
CPU time	82.05 seconds
Started	Sep 01 05:57:13 AM UTC 24
Finished	Sep 01 05:58:37 AM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207890170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.207890170
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/31.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3643628200
Short name	T137
Test name
Test status
Simulation time	130331121910 ps
CPU time	572.25 seconds
Started	Sep 01 05:57:13 AM UTC 24
Finished	Sep 01 06:06:52 AM UTC 24
Peak memory	220564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643628200 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.3643628200
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/31.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.2666617088
Short name	T580
Test name
Test status
Simulation time	186776984 ps
CPU time	9.57 seconds
Started	Sep 01 05:57:18 AM UTC 24
Finished	Sep 01 05:57:29 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666617088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2666617088
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/31.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.3841514601
Short name	T159
Test name
Test status
Simulation time	2237152057 ps
CPU time	41.18 seconds
Started	Sep 01 05:57:16 AM UTC 24
Finished	Sep 01 05:57:58 AM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841514601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3841514601
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/31.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random.2331157134
Short name	T574
Test name
Test status
Simulation time	189743237 ps
CPU time	7.07 seconds
Started	Sep 01 05:57:05 AM UTC 24
Finished	Sep 01 05:57:13 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331157134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.2331157134
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/31.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.3156825264
Short name	T593
Test name
Test status
Simulation time	20668312517 ps
CPU time	85.74 seconds
Started	Sep 01 05:57:09 AM UTC 24
Finished	Sep 01 05:58:37 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156825264 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3156825264
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/31.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.3226425039
Short name	T131
Test name
Test status
Simulation time	67758359593 ps
CPU time	300.35 seconds
Started	Sep 01 05:57:13 AM UTC 24
Finished	Sep 01 06:02:18 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226425039 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3226425039
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/31.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.2393453180
Short name	T582
Test name
Test status
Simulation time	221447837 ps
CPU time	21.25 seconds
Started	Sep 01 05:57:08 AM UTC 24
Finished	Sep 01 05:57:31 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393453180 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.2393453180
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/31.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.3819137097
Short name	T154
Test name
Test status
Simulation time	885023245 ps
CPU time	26.54 seconds
Started	Sep 01 05:57:14 AM UTC 24
Finished	Sep 01 05:57:42 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819137097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3819137097
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/31.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.1388726573
Short name	T235
Test name
Test status
Simulation time	63440573 ps
CPU time	2.48 seconds
Started	Sep 01 05:57:01 AM UTC 24
Finished	Sep 01 05:57:04 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388726573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1388726573
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/31.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.660451344
Short name	T285
Test name
Test status
Simulation time	46118705405 ps
CPU time	76.49 seconds
Started	Sep 01 05:57:04 AM UTC 24
Finished	Sep 01 05:58:22 AM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660451344 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.660451344
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/31.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.3570092896
Short name	T155
Test name
Test status
Simulation time	3337823580 ps
CPU time	39.02 seconds
Started	Sep 01 05:57:04 AM UTC 24
Finished	Sep 01 05:57:45 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570092896 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3570092896
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/31.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1395185232
Short name	T236
Test name
Test status
Simulation time	49673294 ps
CPU time	3.42 seconds
Started	Sep 01 05:57:02 AM UTC 24
Finished	Sep 01 05:57:07 AM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395185232 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1395185232
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/31.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.1411374329
Short name	T130
Test name
Test status
Simulation time	35516269542 ps
CPU time	266.94 seconds
Started	Sep 01 05:57:21 AM UTC 24
Finished	Sep 01 06:01:52 AM UTC 24
Peak memory	222976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411374329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1411374329
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/31.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.1846586185
Short name	T628
Test name
Test status
Simulation time	5198253911 ps
CPU time	146.64 seconds
Started	Sep 01 05:57:28 AM UTC 24
Finished	Sep 01 05:59:58 AM UTC 24
Peak memory	223044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846586185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1846586185
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/31.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1322472973
Short name	T38
Test name
Test status
Simulation time	6010826710 ps
CPU time	430.79 seconds
Started	Sep 01 05:57:22 AM UTC 24
Finished	Sep 01 06:04:39 AM UTC 24
Peak memory	223408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322472973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.1322472973
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/31.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.2181552565
Short name	T671
Test name
Test status
Simulation time	5178085578 ps
CPU time	231.9 seconds
Started	Sep 01 05:57:31 AM UTC 24
Finished	Sep 01 06:01:26 AM UTC 24
Peak memory	223420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181552565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.2181552565
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/31.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.1334250627
Short name	T581
Test name
Test status
Simulation time	633438660 ps
CPU time	11.56 seconds
Started	Sep 01 05:57:17 AM UTC 24
Finished	Sep 01 05:57:30 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334250627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1334250627
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/31.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.1853994570
Short name	T158
Test name
Test status
Simulation time	69389290 ps
CPU time	5.36 seconds
Started	Sep 01 05:57:46 AM UTC 24
Finished	Sep 01 05:57:52 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853994570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.1853994570
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/32.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.4220083496
Short name	T625
Test name
Test status
Simulation time	22263049572 ps
CPU time	125.28 seconds
Started	Sep 01 05:57:47 AM UTC 24
Finished	Sep 01 05:59:55 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220083496 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.4220083496
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/32.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.4137950949
Short name	T586
Test name
Test status
Simulation time	894721220 ps
CPU time	20.48 seconds
Started	Sep 01 05:58:04 AM UTC 24
Finished	Sep 01 05:58:26 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137950949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.4137950949
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/32.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.589143864
Short name	T590
Test name
Test status
Simulation time	2054931143 ps
CPU time	36.88 seconds
Started	Sep 01 05:57:54 AM UTC 24
Finished	Sep 01 05:58:32 AM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589143864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.589143864
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/32.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random.1210972725
Short name	T584
Test name
Test status
Simulation time	748230921 ps
CPU time	35.69 seconds
Started	Sep 01 05:57:37 AM UTC 24
Finished	Sep 01 05:58:14 AM UTC 24
Peak memory	216968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210972725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.1210972725
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/32.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.3758804450
Short name	T632
Test name
Test status
Simulation time	35748689590 ps
CPU time	143.66 seconds
Started	Sep 01 05:57:41 AM UTC 24
Finished	Sep 01 06:00:07 AM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758804450 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3758804450
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/32.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.2988922806
Short name	T617
Test name
Test status
Simulation time	10225854896 ps
CPU time	109.91 seconds
Started	Sep 01 05:57:43 AM UTC 24
Finished	Sep 01 05:59:36 AM UTC 24
Peak memory	216904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988922806 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2988922806
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/32.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.2115402138
Short name	T157
Test name
Test status
Simulation time	73899629 ps
CPU time	12.13 seconds
Started	Sep 01 05:57:38 AM UTC 24
Finished	Sep 01 05:57:51 AM UTC 24
Peak memory	216752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115402138 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.2115402138
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/32.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.806270912
Short name	T585
Test name
Test status
Simulation time	420496950 ps
CPU time	23.15 seconds
Started	Sep 01 05:57:52 AM UTC 24
Finished	Sep 01 05:58:17 AM UTC 24
Peak memory	216760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806270912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.806270912
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/32.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.3333482204
Short name	T583
Test name
Test status
Simulation time	36455258 ps
CPU time	3.18 seconds
Started	Sep 01 05:57:31 AM UTC 24
Finished	Sep 01 05:57:35 AM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333482204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3333482204
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/32.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1155920234
Short name	T587
Test name
Test status
Simulation time	23314186918 ps
CPU time	49.6 seconds
Started	Sep 01 05:57:37 AM UTC 24
Finished	Sep 01 05:58:28 AM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155920234 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1155920234
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/32.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.3915206517
Short name	T592
Test name
Test status
Simulation time	5828269307 ps
CPU time	54.63 seconds
Started	Sep 01 05:57:37 AM UTC 24
Finished	Sep 01 05:58:33 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915206517 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3915206517
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/32.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.897732295
Short name	T152
Test name
Test status
Simulation time	26754678 ps
CPU time	3.43 seconds
Started	Sep 01 05:57:32 AM UTC 24
Finished	Sep 01 05:57:37 AM UTC 24
Peak memory	217068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897732295 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.897732295
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/32.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.2553338891
Short name	T608
Test name
Test status
Simulation time	1382643196 ps
CPU time	64.17 seconds
Started	Sep 01 05:58:04 AM UTC 24
Finished	Sep 01 05:59:10 AM UTC 24
Peak memory	218876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553338891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2553338891
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/32.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.860028681
Short name	T637
Test name
Test status
Simulation time	6085087162 ps
CPU time	112.91 seconds
Started	Sep 01 05:58:18 AM UTC 24
Finished	Sep 01 06:00:14 AM UTC 24
Peak memory	218888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860028681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.860028681
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/32.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.4175390956
Short name	T712
Test name
Test status
Simulation time	1511230422 ps
CPU time	282.46 seconds
Started	Sep 01 05:58:15 AM UTC 24
Finished	Sep 01 06:03:02 AM UTC 24
Peak memory	222920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175390956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.4175390956
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/32.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.839617934
Short name	T774
Test name
Test status
Simulation time	8786316625 ps
CPU time	387.32 seconds
Started	Sep 01 05:58:21 AM UTC 24
Finished	Sep 01 06:04:53 AM UTC 24
Peak memory	237748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839617934 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.839617934
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/32.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.526128503
Short name	T257
Test name
Test status
Simulation time	1421027767 ps
CPU time	32.66 seconds
Started	Sep 01 05:57:59 AM UTC 24
Finished	Sep 01 05:58:33 AM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526128503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.526128503
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/32.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.1367534988
Short name	T176
Test name
Test status
Simulation time	687075071 ps
CPU time	25.21 seconds
Started	Sep 01 05:58:35 AM UTC 24
Finished	Sep 01 05:59:01 AM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367534988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.1367534988
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/33.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2242057993
Short name	T766
Test name
Test status
Simulation time	36636375119 ps
CPU time	364.02 seconds
Started	Sep 01 05:58:35 AM UTC 24
Finished	Sep 01 06:04:44 AM UTC 24
Peak memory	219272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242057993 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.2242057993
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/33.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.3605056332
Short name	T601
Test name
Test status
Simulation time	107894579 ps
CPU time	5.42 seconds
Started	Sep 01 05:58:51 AM UTC 24
Finished	Sep 01 05:58:58 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605056332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3605056332
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/33.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.97641329
Short name	T600
Test name
Test status
Simulation time	393289439 ps
CPU time	17.29 seconds
Started	Sep 01 05:58:38 AM UTC 24
Finished	Sep 01 05:58:57 AM UTC 24
Peak memory	216956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97641329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.97641329
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/33.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random.2956575657
Short name	T611
Test name
Test status
Simulation time	1185220074 ps
CPU time	47.19 seconds
Started	Sep 01 05:58:29 AM UTC 24
Finished	Sep 01 05:59:18 AM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956575657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2956575657
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/33.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.1298724996
Short name	T651
Test name
Test status
Simulation time	48465432947 ps
CPU time	125.34 seconds
Started	Sep 01 05:58:33 AM UTC 24
Finished	Sep 01 06:00:41 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298724996 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.1298724996
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/33.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.162298252
Short name	T790
Test name
Test status
Simulation time	34456563230 ps
CPU time	394.99 seconds
Started	Sep 01 05:58:33 AM UTC 24
Finished	Sep 01 06:05:14 AM UTC 24
Peak memory	217156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162298252 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.162298252
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/33.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.2259132302
Short name	T597
Test name
Test status
Simulation time	181493789 ps
CPU time	19.8 seconds
Started	Sep 01 05:58:31 AM UTC 24
Finished	Sep 01 05:58:52 AM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259132302 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2259132302
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/33.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.3015115135
Short name	T613
Test name
Test status
Simulation time	4878301665 ps
CPU time	38.71 seconds
Started	Sep 01 05:58:38 AM UTC 24
Finished	Sep 01 05:59:18 AM UTC 24
Peak memory	216888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015115135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3015115135
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/33.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.249875736
Short name	T591
Test name
Test status
Simulation time	201284715 ps
CPU time	6.7 seconds
Started	Sep 01 05:58:24 AM UTC 24
Finished	Sep 01 05:58:32 AM UTC 24
Peak memory	217068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249875736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.249875736
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/33.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2533997592
Short name	T607
Test name
Test status
Simulation time	21122238082 ps
CPU time	41.55 seconds
Started	Sep 01 05:58:27 AM UTC 24
Finished	Sep 01 05:59:10 AM UTC 24
Peak memory	217140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533997592 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2533997592
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/33.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.984416002
Short name	T606
Test name
Test status
Simulation time	4760243978 ps
CPU time	34.86 seconds
Started	Sep 01 05:58:29 AM UTC 24
Finished	Sep 01 05:59:06 AM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984416002 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.984416002
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/33.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.4096741356
Short name	T589
Test name
Test status
Simulation time	30131034 ps
CPU time	3.22 seconds
Started	Sep 01 05:58:24 AM UTC 24
Finished	Sep 01 05:58:29 AM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096741356 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.4096741356
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/33.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.1656736346
Short name	T696
Test name
Test status
Simulation time	9981861530 ps
CPU time	208.38 seconds
Started	Sep 01 05:58:54 AM UTC 24
Finished	Sep 01 06:02:26 AM UTC 24
Peak memory	218880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656736346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1656736346
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/33.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.1536312885
Short name	T665
Test name
Test status
Simulation time	3806524035 ps
CPU time	141.03 seconds
Started	Sep 01 05:58:55 AM UTC 24
Finished	Sep 01 06:01:19 AM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536312885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1536312885
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/33.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.2750403984
Short name	T817
Test name
Test status
Simulation time	4258138341 ps
CPU time	425.6 seconds
Started	Sep 01 05:58:54 AM UTC 24
Finished	Sep 01 06:06:06 AM UTC 24
Peak memory	223372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750403984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.2750403984
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/33.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.4198638718
Short name	T662
Test name
Test status
Simulation time	7808266173 ps
CPU time	130.78 seconds
Started	Sep 01 05:58:58 AM UTC 24
Finished	Sep 01 06:01:11 AM UTC 24
Peak memory	221196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198638718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.4198638718
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/33.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.1891789284
Short name	T599
Test name
Test status
Simulation time	91377506 ps
CPU time	4.73 seconds
Started	Sep 01 05:58:49 AM UTC 24
Finished	Sep 01 05:58:55 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891789284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.1891789284
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/33.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.1358151853
Short name	T614
Test name
Test status
Simulation time	373910335 ps
CPU time	12.75 seconds
Started	Sep 01 05:59:11 AM UTC 24
Finished	Sep 01 05:59:25 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358151853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1358151853
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/34.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1567576667
Short name	T701
Test name
Test status
Simulation time	76425587475 ps
CPU time	200.61 seconds
Started	Sep 01 05:59:13 AM UTC 24
Finished	Sep 01 06:02:36 AM UTC 24
Peak memory	219208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567576667 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.1567576667
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/34.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1815865920
Short name	T626
Test name
Test status
Simulation time	1567798101 ps
CPU time	33.85 seconds
Started	Sep 01 05:59:20 AM UTC 24
Finished	Sep 01 05:59:56 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815865920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.1815865920
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/34.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.224553419
Short name	T624
Test name
Test status
Simulation time	683787117 ps
CPU time	28.27 seconds
Started	Sep 01 05:59:20 AM UTC 24
Finished	Sep 01 05:59:50 AM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224553419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.224553419
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/34.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random.437919559
Short name	T612
Test name
Test status
Simulation time	45881090 ps
CPU time	10.08 seconds
Started	Sep 01 05:59:07 AM UTC 24
Finished	Sep 01 05:59:18 AM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437919559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.437919559
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/34.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.669207990
Short name	T621
Test name
Test status
Simulation time	3316102671 ps
CPU time	33.49 seconds
Started	Sep 01 05:59:09 AM UTC 24
Finished	Sep 01 05:59:44 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669207990 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.669207990
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/34.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.723208047
Short name	T727
Test name
Test status
Simulation time	32677715063 ps
CPU time	249.78 seconds
Started	Sep 01 05:59:11 AM UTC 24
Finished	Sep 01 06:03:25 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723208047 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.723208047
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/34.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.3052708361
Short name	T618
Test name
Test status
Simulation time	249354581 ps
CPU time	27.51 seconds
Started	Sep 01 05:59:07 AM UTC 24
Finished	Sep 01 05:59:36 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052708361 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3052708361
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/34.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.3713625611
Short name	T615
Test name
Test status
Simulation time	173891696 ps
CPU time	13.52 seconds
Started	Sep 01 05:59:15 AM UTC 24
Finished	Sep 01 05:59:30 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713625611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3713625611
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/34.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.4052362147
Short name	T605
Test name
Test status
Simulation time	244395001 ps
CPU time	5.04 seconds
Started	Sep 01 05:58:59 AM UTC 24
Finished	Sep 01 05:59:05 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052362147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.4052362147
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/34.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.3889148741
Short name	T630
Test name
Test status
Simulation time	5033994638 ps
CPU time	60.28 seconds
Started	Sep 01 05:59:02 AM UTC 24
Finished	Sep 01 06:00:05 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889148741 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3889148741
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/34.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.3776690725
Short name	T616
Test name
Test status
Simulation time	3568194468 ps
CPU time	28.07 seconds
Started	Sep 01 05:59:06 AM UTC 24
Finished	Sep 01 05:59:35 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776690725 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3776690725
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/34.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.2099562565
Short name	T604
Test name
Test status
Simulation time	31734656 ps
CPU time	3.37 seconds
Started	Sep 01 05:59:00 AM UTC 24
Finished	Sep 01 05:59:05 AM UTC 24
Peak memory	217064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099562565 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.2099562565
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/34.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.1000542436
Short name	T690
Test name
Test status
Simulation time	1305470958 ps
CPU time	169.06 seconds
Started	Sep 01 05:59:22 AM UTC 24
Finished	Sep 01 06:02:14 AM UTC 24
Peak memory	219140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000542436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1000542436
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/34.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.2893786380
Short name	T634
Test name
Test status
Simulation time	1007876319 ps
CPU time	40.92 seconds
Started	Sep 01 05:59:27 AM UTC 24
Finished	Sep 01 06:00:09 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893786380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2893786380
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/34.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.897294709
Short name	T647
Test name
Test status
Simulation time	172729922 ps
CPU time	70.31 seconds
Started	Sep 01 05:59:22 AM UTC 24
Finished	Sep 01 06:00:34 AM UTC 24
Peak memory	221188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897294709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.897294709
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/34.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.254794595
Short name	T714
Test name
Test status
Simulation time	4385669309 ps
CPU time	207.23 seconds
Started	Sep 01 05:59:31 AM UTC 24
Finished	Sep 01 06:03:02 AM UTC 24
Peak memory	222980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254794595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.254794595
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/34.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.827515760
Short name	T623
Test name
Test status
Simulation time	178007130 ps
CPU time	23.41 seconds
Started	Sep 01 05:59:20 AM UTC 24
Finished	Sep 01 05:59:45 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827515760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.827515760
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/34.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.949564501
Short name	T199
Test name
Test status
Simulation time	331719113 ps
CPU time	39.02 seconds
Started	Sep 01 05:59:51 AM UTC 24
Finished	Sep 01 06:00:32 AM UTC 24
Peak memory	219140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949564501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.949564501
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/35.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1858305084
Short name	T682
Test name
Test status
Simulation time	18853978691 ps
CPU time	125.99 seconds
Started	Sep 01 05:59:55 AM UTC 24
Finished	Sep 01 06:02:04 AM UTC 24
Peak memory	217220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858305084 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.1858305084
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/35.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.258832700
Short name	T635
Test name
Test status
Simulation time	75692954 ps
CPU time	8.2 seconds
Started	Sep 01 06:00:00 AM UTC 24
Finished	Sep 01 06:00:09 AM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258832700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.258832700
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/35.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.2556033049
Short name	T631
Test name
Test status
Simulation time	343531248 ps
CPU time	6.12 seconds
Started	Sep 01 06:00:00 AM UTC 24
Finished	Sep 01 06:00:07 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556033049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2556033049
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/35.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random.355585141
Short name	T149
Test name
Test status
Simulation time	953442968 ps
CPU time	40.76 seconds
Started	Sep 01 05:59:44 AM UTC 24
Finished	Sep 01 06:00:26 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355585141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.355585141
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/35.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.328318735
Short name	T670
Test name
Test status
Simulation time	16306280969 ps
CPU time	95.3 seconds
Started	Sep 01 05:59:48 AM UTC 24
Finished	Sep 01 06:01:25 AM UTC 24
Peak memory	217028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328318735 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.328318735
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/35.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2728201046
Short name	T640
Test name
Test status
Simulation time	4037829896 ps
CPU time	31.35 seconds
Started	Sep 01 05:59:48 AM UTC 24
Finished	Sep 01 06:00:20 AM UTC 24
Peak memory	217156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728201046 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2728201046
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/35.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.3090286011
Short name	T627
Test name
Test status
Simulation time	167257740 ps
CPU time	8.95 seconds
Started	Sep 01 05:59:48 AM UTC 24
Finished	Sep 01 05:59:58 AM UTC 24
Peak memory	217080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090286011 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.3090286011
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/35.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.891773240
Short name	T633
Test name
Test status
Simulation time	281467232 ps
CPU time	9.56 seconds
Started	Sep 01 05:59:57 AM UTC 24
Finished	Sep 01 06:00:08 AM UTC 24
Peak memory	216760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891773240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.891773240
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/35.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.3367202352
Short name	T622
Test name
Test status
Simulation time	1036549849 ps
CPU time	6.82 seconds
Started	Sep 01 05:59:36 AM UTC 24
Finished	Sep 01 05:59:44 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367202352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3367202352
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/35.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3371680248
Short name	T646
Test name
Test status
Simulation time	5717760153 ps
CPU time	54.03 seconds
Started	Sep 01 05:59:38 AM UTC 24
Finished	Sep 01 06:00:34 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371680248 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3371680248
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/35.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1461954188
Short name	T648
Test name
Test status
Simulation time	3765841502 ps
CPU time	48.86 seconds
Started	Sep 01 05:59:44 AM UTC 24
Finished	Sep 01 06:00:35 AM UTC 24
Peak memory	217200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461954188 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1461954188
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/35.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.823408221
Short name	T620
Test name
Test status
Simulation time	117679731 ps
CPU time	4.18 seconds
Started	Sep 01 05:59:38 AM UTC 24
Finished	Sep 01 05:59:43 AM UTC 24
Peak memory	217004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823408221 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.823408221
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/35.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.1066909664
Short name	T661
Test name
Test status
Simulation time	1876554667 ps
CPU time	63.83 seconds
Started	Sep 01 06:00:02 AM UTC 24
Finished	Sep 01 06:01:10 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066909664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1066909664
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/35.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2397930868
Short name	T708
Test name
Test status
Simulation time	1475077781 ps
CPU time	168.73 seconds
Started	Sep 01 06:00:06 AM UTC 24
Finished	Sep 01 06:02:58 AM UTC 24
Peak memory	220932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397930868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2397930868
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/35.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.3644670515
Short name	T227
Test name
Test status
Simulation time	2578313426 ps
CPU time	602.75 seconds
Started	Sep 01 06:00:06 AM UTC 24
Finished	Sep 01 06:10:17 AM UTC 24
Peak memory	224600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644670515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.3644670515
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/35.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.2746090517
Short name	T765
Test name
Test status
Simulation time	4261854706 ps
CPU time	267.39 seconds
Started	Sep 01 06:00:09 AM UTC 24
Finished	Sep 01 06:04:42 AM UTC 24
Peak memory	223048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746090517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.2746090517
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/35.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.2248244960
Short name	T641
Test name
Test status
Simulation time	346335687 ps
CPU time	17.72 seconds
Started	Sep 01 06:00:00 AM UTC 24
Finished	Sep 01 06:00:22 AM UTC 24
Peak memory	217028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248244960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2248244960
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/35.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.592426279
Short name	T656
Test name
Test status
Simulation time	520266768 ps
CPU time	36.76 seconds
Started	Sep 01 06:00:21 AM UTC 24
Finished	Sep 01 06:00:59 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592426279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.592426279
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/36.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1988639953
Short name	T900
Test name
Test status
Simulation time	117899799395 ps
CPU time	1084.35 seconds
Started	Sep 01 06:00:23 AM UTC 24
Finished	Sep 01 06:18:42 AM UTC 24
Peak memory	222612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988639953 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.1988639953
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/36.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.1124713684
Short name	T657
Test name
Test status
Simulation time	956496234 ps
CPU time	26.33 seconds
Started	Sep 01 06:00:32 AM UTC 24
Finished	Sep 01 06:00:59 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124713684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1124713684
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/36.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.3426985824
Short name	T649
Test name
Test status
Simulation time	151810798 ps
CPU time	8.45 seconds
Started	Sep 01 06:00:29 AM UTC 24
Finished	Sep 01 06:00:39 AM UTC 24
Peak memory	216752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426985824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.3426985824
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/36.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random.3642394983
Short name	T642
Test name
Test status
Simulation time	164791882 ps
CPU time	13.92 seconds
Started	Sep 01 06:00:15 AM UTC 24
Finished	Sep 01 06:00:30 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642394983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.3642394983
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/36.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.3798194719
Short name	T770
Test name
Test status
Simulation time	103079268690 ps
CPU time	268.95 seconds
Started	Sep 01 06:00:16 AM UTC 24
Finished	Sep 01 06:04:49 AM UTC 24
Peak memory	217220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798194719 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3798194719
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/36.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2699036621
Short name	T762
Test name
Test status
Simulation time	29572183800 ps
CPU time	256.5 seconds
Started	Sep 01 06:00:18 AM UTC 24
Finished	Sep 01 06:04:38 AM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699036621 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2699036621
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/36.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.3983878887
Short name	T654
Test name
Test status
Simulation time	772865431 ps
CPU time	36.77 seconds
Started	Sep 01 06:00:15 AM UTC 24
Finished	Sep 01 06:00:53 AM UTC 24
Peak memory	219132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983878887 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.3983878887
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/36.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.992866315
Short name	T644
Test name
Test status
Simulation time	24509658 ps
CPU time	2.87 seconds
Started	Sep 01 06:00:28 AM UTC 24
Finished	Sep 01 06:00:32 AM UTC 24
Peak memory	216756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992866315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.992866315
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/36.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.69561907
Short name	T639
Test name
Test status
Simulation time	124106148 ps
CPU time	5.54 seconds
Started	Sep 01 06:00:09 AM UTC 24
Finished	Sep 01 06:00:17 AM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69561907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.69561907
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/36.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.1236575554
Short name	T659
Test name
Test status
Simulation time	39327780288 ps
CPU time	46.96 seconds
Started	Sep 01 06:00:12 AM UTC 24
Finished	Sep 01 06:01:01 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236575554 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1236575554
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/36.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.4281589569
Short name	T653
Test name
Test status
Simulation time	10100051011 ps
CPU time	35.6 seconds
Started	Sep 01 06:00:12 AM UTC 24
Finished	Sep 01 06:00:49 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281589569 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.4281589569
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/36.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.3245538634
Short name	T638
Test name
Test status
Simulation time	151618139 ps
CPU time	3.62 seconds
Started	Sep 01 06:00:09 AM UTC 24
Finished	Sep 01 06:00:15 AM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245538634 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.3245538634
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/36.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.2053118334
Short name	T150
Test name
Test status
Simulation time	8468041601 ps
CPU time	136.58 seconds
Started	Sep 01 06:00:34 AM UTC 24
Finished	Sep 01 06:02:53 AM UTC 24
Peak memory	218880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053118334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2053118334
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/36.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.616136718
Short name	T668
Test name
Test status
Simulation time	1345270325 ps
CPU time	44.76 seconds
Started	Sep 01 06:00:36 AM UTC 24
Finished	Sep 01 06:01:23 AM UTC 24
Peak memory	216776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616136718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.616136718
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/36.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.4293253807
Short name	T865
Test name
Test status
Simulation time	837598454 ps
CPU time	408.12 seconds
Started	Sep 01 06:00:34 AM UTC 24
Finished	Sep 01 06:07:27 AM UTC 24
Peak memory	222920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293253807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.4293253807
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/36.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.1793534541
Short name	T718
Test name
Test status
Simulation time	261353458 ps
CPU time	145.98 seconds
Started	Sep 01 06:00:36 AM UTC 24
Finished	Sep 01 06:03:05 AM UTC 24
Peak memory	222916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793534541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.1793534541
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/36.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.17486485
Short name	T260
Test name
Test status
Simulation time	484224167 ps
CPU time	25.24 seconds
Started	Sep 01 06:00:32 AM UTC 24
Finished	Sep 01 06:00:58 AM UTC 24
Peak memory	218876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17486485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.17486485
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/36.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.221894261
Short name	T683
Test name
Test status
Simulation time	7979152586 ps
CPU time	74.81 seconds
Started	Sep 01 06:00:51 AM UTC 24
Finished	Sep 01 06:02:07 AM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221894261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.221894261
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/37.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.2700172798
Short name	T226
Test name
Test status
Simulation time	69934981206 ps
CPU time	299.78 seconds
Started	Sep 01 06:00:55 AM UTC 24
Finished	Sep 01 06:05:59 AM UTC 24
Peak memory	219144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700172798 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.2700172798
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/37.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.918650280
Short name	T666
Test name
Test status
Simulation time	110667921 ps
CPU time	17.84 seconds
Started	Sep 01 06:01:00 AM UTC 24
Finished	Sep 01 06:01:19 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918650280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.918650280
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/37.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.1301475343
Short name	T672
Test name
Test status
Simulation time	1195161569 ps
CPU time	26.76 seconds
Started	Sep 01 06:01:00 AM UTC 24
Finished	Sep 01 06:01:28 AM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301475343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1301475343
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/37.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random.808471237
Short name	T658
Test name
Test status
Simulation time	1527978018 ps
CPU time	17.15 seconds
Started	Sep 01 06:00:41 AM UTC 24
Finished	Sep 01 06:01:00 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808471237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.808471237
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/37.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.1824375384
Short name	T684
Test name
Test status
Simulation time	21093311886 ps
CPU time	82.88 seconds
Started	Sep 01 06:00:43 AM UTC 24
Finished	Sep 01 06:02:08 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824375384 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.1824375384
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/37.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2288707314
Short name	T811
Test name
Test status
Simulation time	35469903446 ps
CPU time	307.43 seconds
Started	Sep 01 06:00:46 AM UTC 24
Finished	Sep 01 06:05:57 AM UTC 24
Peak memory	217156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288707314 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2288707314
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/37.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.1592878582
Short name	T67
Test name
Test status
Simulation time	180424157 ps
CPU time	32.94 seconds
Started	Sep 01 06:00:43 AM UTC 24
Finished	Sep 01 06:01:17 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592878582 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.1592878582
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/37.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.3922331623
Short name	T673
Test name
Test status
Simulation time	9452001734 ps
CPU time	41.08 seconds
Started	Sep 01 06:00:56 AM UTC 24
Finished	Sep 01 06:01:39 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922331623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3922331623
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/37.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.513540955
Short name	T652
Test name
Test status
Simulation time	111716230 ps
CPU time	4.55 seconds
Started	Sep 01 06:00:36 AM UTC 24
Finished	Sep 01 06:00:42 AM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513540955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.513540955
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/37.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2910242495
Short name	T677
Test name
Test status
Simulation time	7652060505 ps
CPU time	71.54 seconds
Started	Sep 01 06:00:39 AM UTC 24
Finished	Sep 01 06:01:52 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910242495 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2910242495
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/37.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.1431204830
Short name	T660
Test name
Test status
Simulation time	3521137671 ps
CPU time	25.09 seconds
Started	Sep 01 06:00:40 AM UTC 24
Finished	Sep 01 06:01:06 AM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431204830 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1431204830
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/37.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3998088355
Short name	T650
Test name
Test status
Simulation time	27040914 ps
CPU time	3.08 seconds
Started	Sep 01 06:00:36 AM UTC 24
Finished	Sep 01 06:00:41 AM UTC 24
Peak memory	217128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998088355 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3998088355
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/37.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.547004995
Short name	T719
Test name
Test status
Simulation time	3275388283 ps
CPU time	121.68 seconds
Started	Sep 01 06:01:02 AM UTC 24
Finished	Sep 01 06:03:06 AM UTC 24
Peak memory	220856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547004995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.547004995
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/37.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.3431556853
Short name	T730
Test name
Test status
Simulation time	3505070708 ps
CPU time	140.95 seconds
Started	Sep 01 06:01:06 AM UTC 24
Finished	Sep 01 06:03:30 AM UTC 24
Peak memory	220932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431556853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3431556853
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/37.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.2847040693
Short name	T735
Test name
Test status
Simulation time	2104434085 ps
CPU time	152.93 seconds
Started	Sep 01 06:01:08 AM UTC 24
Finished	Sep 01 06:03:43 AM UTC 24
Peak memory	222980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847040693 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.2847040693
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/37.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.102966566
Short name	T669
Test name
Test status
Simulation time	503477131 ps
CPU time	22.65 seconds
Started	Sep 01 06:01:00 AM UTC 24
Finished	Sep 01 06:01:24 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102966566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.102966566
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/37.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.1142461374
Short name	T689
Test name
Test status
Simulation time	350821173 ps
CPU time	44.69 seconds
Started	Sep 01 06:01:26 AM UTC 24
Finished	Sep 01 06:02:12 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142461374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1142461374
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/38.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3053991789
Short name	T852
Test name
Test status
Simulation time	62125423546 ps
CPU time	331.17 seconds
Started	Sep 01 06:01:27 AM UTC 24
Finished	Sep 01 06:07:03 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053991789 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.3053991789
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/38.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.709598675
Short name	T687
Test name
Test status
Simulation time	973584284 ps
CPU time	19.21 seconds
Started	Sep 01 06:01:49 AM UTC 24
Finished	Sep 01 06:02:10 AM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709598675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.709598675
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/38.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.1607476619
Short name	T678
Test name
Test status
Simulation time	194575676 ps
CPU time	20.95 seconds
Started	Sep 01 06:01:30 AM UTC 24
Finished	Sep 01 06:01:52 AM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607476619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1607476619
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/38.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random.2439506195
Short name	T676
Test name
Test status
Simulation time	379501430 ps
CPU time	31.03 seconds
Started	Sep 01 06:01:19 AM UTC 24
Finished	Sep 01 06:01:51 AM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439506195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.2439506195
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/38.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.116070866
Short name	T876
Test name
Test status
Simulation time	126135626908 ps
CPU time	424.44 seconds
Started	Sep 01 06:01:21 AM UTC 24
Finished	Sep 01 06:08:30 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116070866 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.116070866
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/38.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.766214069
Short name	T731
Test name
Test status
Simulation time	44954379896 ps
CPU time	127.62 seconds
Started	Sep 01 06:01:24 AM UTC 24
Finished	Sep 01 06:03:34 AM UTC 24
Peak memory	216892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766214069 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.766214069
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/38.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.960597317
Short name	T675
Test name
Test status
Simulation time	191768203 ps
CPU time	26.21 seconds
Started	Sep 01 06:01:20 AM UTC 24
Finished	Sep 01 06:01:48 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960597317 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.960597317
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/38.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.2040722841
Short name	T674
Test name
Test status
Simulation time	634364627 ps
CPU time	18.04 seconds
Started	Sep 01 06:01:29 AM UTC 24
Finished	Sep 01 06:01:48 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040722841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.2040722841
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/38.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.3112088029
Short name	T663
Test name
Test status
Simulation time	112068837 ps
CPU time	4.46 seconds
Started	Sep 01 06:01:11 AM UTC 24
Finished	Sep 01 06:01:16 AM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112088029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3112088029
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/38.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.1545628005
Short name	T691
Test name
Test status
Simulation time	5587493008 ps
CPU time	57.65 seconds
Started	Sep 01 06:01:19 AM UTC 24
Finished	Sep 01 06:02:18 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545628005 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.1545628005
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/38.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2224691550
Short name	T261
Test name
Test status
Simulation time	13658259584 ps
CPU time	54.92 seconds
Started	Sep 01 06:01:19 AM UTC 24
Finished	Sep 01 06:02:15 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224691550 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2224691550
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/38.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.3762316085
Short name	T664
Test name
Test status
Simulation time	35721213 ps
CPU time	3.47 seconds
Started	Sep 01 06:01:13 AM UTC 24
Finished	Sep 01 06:01:17 AM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762316085 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.3762316085
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/38.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.1648058530
Short name	T791
Test name
Test status
Simulation time	8938093234 ps
CPU time	201.61 seconds
Started	Sep 01 06:01:49 AM UTC 24
Finished	Sep 01 06:05:14 AM UTC 24
Peak memory	218880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648058530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1648058530
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/38.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1775496858
Short name	T713
Test name
Test status
Simulation time	1010848632 ps
CPU time	66.58 seconds
Started	Sep 01 06:01:54 AM UTC 24
Finished	Sep 01 06:03:02 AM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775496858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1775496858
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/38.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2766756230
Short name	T288
Test name
Test status
Simulation time	4110634669 ps
CPU time	329.5 seconds
Started	Sep 01 06:01:50 AM UTC 24
Finished	Sep 01 06:07:25 AM UTC 24
Peak memory	221000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766756230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.2766756230
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/38.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1960248965
Short name	T850
Test name
Test status
Simulation time	1990501318 ps
CPU time	300.89 seconds
Started	Sep 01 06:01:54 AM UTC 24
Finished	Sep 01 06:06:59 AM UTC 24
Peak memory	233592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960248965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.1960248965
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/38.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.1553916007
Short name	T68
Test name
Test status
Simulation time	1166642601 ps
CPU time	40.09 seconds
Started	Sep 01 06:01:40 AM UTC 24
Finished	Sep 01 06:02:22 AM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553916007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1553916007
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/38.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.2012236020
Short name	T693
Test name
Test status
Simulation time	300309105 ps
CPU time	12.02 seconds
Started	Sep 01 06:02:09 AM UTC 24
Finished	Sep 01 06:02:22 AM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012236020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2012236020
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/39.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3876538525
Short name	T899
Test name
Test status
Simulation time	126086110292 ps
CPU time	718.99 seconds
Started	Sep 01 06:02:09 AM UTC 24
Finished	Sep 01 06:14:17 AM UTC 24
Peak memory	220568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876538525 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.3876538525
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/39.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.599317193
Short name	T704
Test name
Test status
Simulation time	1191587322 ps
CPU time	33.17 seconds
Started	Sep 01 06:02:12 AM UTC 24
Finished	Sep 01 06:02:46 AM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599317193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.599317193
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/39.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.525395898
Short name	T699
Test name
Test status
Simulation time	479254269 ps
CPU time	16.55 seconds
Started	Sep 01 06:02:12 AM UTC 24
Finished	Sep 01 06:02:29 AM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525395898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.525395898
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/39.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random.1183546820
Short name	T686
Test name
Test status
Simulation time	115393471 ps
CPU time	7.76 seconds
Started	Sep 01 06:02:00 AM UTC 24
Finished	Sep 01 06:02:09 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183546820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1183546820
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/39.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.2241083841
Short name	T752
Test name
Test status
Simulation time	23528474009 ps
CPU time	129.5 seconds
Started	Sep 01 06:02:05 AM UTC 24
Finished	Sep 01 06:04:17 AM UTC 24
Peak memory	217160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241083841 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2241083841
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/39.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1536495107
Short name	T813
Test name
Test status
Simulation time	54995990462 ps
CPU time	228.94 seconds
Started	Sep 01 06:02:09 AM UTC 24
Finished	Sep 01 06:06:01 AM UTC 24
Peak memory	216904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536495107 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1536495107
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/39.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.3635951692
Short name	T688
Test name
Test status
Simulation time	52995834 ps
CPU time	7.58 seconds
Started	Sep 01 06:02:02 AM UTC 24
Finished	Sep 01 06:02:11 AM UTC 24
Peak memory	217080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635951692 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.3635951692
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/39.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.2843340807
Short name	T694
Test name
Test status
Simulation time	116964938 ps
CPU time	9.78 seconds
Started	Sep 01 06:02:11 AM UTC 24
Finished	Sep 01 06:02:22 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843340807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.2843340807
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/39.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.687646715
Short name	T681
Test name
Test status
Simulation time	201297138 ps
CPU time	5.13 seconds
Started	Sep 01 06:01:54 AM UTC 24
Finished	Sep 01 06:02:00 AM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687646715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.687646715
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/39.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3038343993
Short name	T698
Test name
Test status
Simulation time	4573891755 ps
CPU time	31.25 seconds
Started	Sep 01 06:01:55 AM UTC 24
Finished	Sep 01 06:02:28 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038343993 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3038343993
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/39.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.2272436519
Short name	T702
Test name
Test status
Simulation time	2722855489 ps
CPU time	38.99 seconds
Started	Sep 01 06:01:57 AM UTC 24
Finished	Sep 01 06:02:37 AM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272436519 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2272436519
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/39.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1420342999
Short name	T680
Test name
Test status
Simulation time	40668652 ps
CPU time	3.67 seconds
Started	Sep 01 06:01:54 AM UTC 24
Finished	Sep 01 06:01:59 AM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420342999 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1420342999
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/39.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.3178358955
Short name	T749
Test name
Test status
Simulation time	4030521311 ps
CPU time	119.47 seconds
Started	Sep 01 06:02:13 AM UTC 24
Finished	Sep 01 06:04:15 AM UTC 24
Peak memory	221060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178358955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3178358955
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/39.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.816456507
Short name	T744
Test name
Test status
Simulation time	1794743902 ps
CPU time	109.61 seconds
Started	Sep 01 06:02:16 AM UTC 24
Finished	Sep 01 06:04:07 AM UTC 24
Peak memory	218824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816456507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.816456507
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/39.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.2784131926
Short name	T729
Test name
Test status
Simulation time	347292266 ps
CPU time	68.93 seconds
Started	Sep 01 06:02:16 AM UTC 24
Finished	Sep 01 06:03:26 AM UTC 24
Peak memory	220940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784131926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.2784131926
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/39.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2939416382
Short name	T873
Test name
Test status
Simulation time	1873981316 ps
CPU time	335.98 seconds
Started	Sep 01 06:02:20 AM UTC 24
Finished	Sep 01 06:08:01 AM UTC 24
Peak memory	233852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939416382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.2939416382
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/39.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.292941616
Short name	T700
Test name
Test status
Simulation time	153768583 ps
CPU time	23.08 seconds
Started	Sep 01 06:02:12 AM UTC 24
Finished	Sep 01 06:02:36 AM UTC 24
Peak memory	219200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292941616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.292941616
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/39.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.1596774241
Short name	T319
Test name
Test status
Simulation time	19170719 ps
CPU time	4.48 seconds
Started	Sep 01 05:39:55 AM UTC 24
Finished	Sep 01 05:40:00 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596774241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.1596774241
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/4.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3731181556
Short name	T262
Test name
Test status
Simulation time	5806863711 ps
CPU time	94.72 seconds
Started	Sep 01 05:39:57 AM UTC 24
Finished	Sep 01 05:41:34 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731181556 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.3731181556
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/4.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.1058669013
Short name	T322
Test name
Test status
Simulation time	20175509 ps
CPU time	3.56 seconds
Started	Sep 01 05:40:12 AM UTC 24
Finished	Sep 01 05:40:17 AM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058669013 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.1058669013
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/4.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.3066218529
Short name	T321
Test name
Test status
Simulation time	1238529733 ps
CPU time	13.26 seconds
Started	Sep 01 05:40:01 AM UTC 24
Finished	Sep 01 05:40:15 AM UTC 24
Peak memory	216760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066218529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3066218529
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/4.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random.2071920702
Short name	T323
Test name
Test status
Simulation time	296076567 ps
CPU time	32.23 seconds
Started	Sep 01 05:39:43 AM UTC 24
Finished	Sep 01 05:40:17 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071920702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.2071920702
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/4.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.655861892
Short name	T164
Test name
Test status
Simulation time	30808154125 ps
CPU time	211.38 seconds
Started	Sep 01 05:39:47 AM UTC 24
Finished	Sep 01 05:43:22 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655861892 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.655861892
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/4.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1561209417
Short name	T60
Test name
Test status
Simulation time	31279850157 ps
CPU time	360.37 seconds
Started	Sep 01 05:39:49 AM UTC 24
Finished	Sep 01 05:45:54 AM UTC 24
Peak memory	218944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561209417 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1561209417
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/4.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.1332783383
Short name	T320
Test name
Test status
Simulation time	158455188 ps
CPU time	19.85 seconds
Started	Sep 01 05:39:45 AM UTC 24
Finished	Sep 01 05:40:06 AM UTC 24
Peak memory	217084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332783383 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1332783383
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/4.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.3544113667
Short name	T20
Test name
Test status
Simulation time	1572374381 ps
CPU time	35.02 seconds
Started	Sep 01 05:40:00 AM UTC 24
Finished	Sep 01 05:40:36 AM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544113667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3544113667
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/4.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.2451646072
Short name	T181
Test name
Test status
Simulation time	161500430 ps
CPU time	4.67 seconds
Started	Sep 01 05:39:35 AM UTC 24
Finished	Sep 01 05:39:40 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451646072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2451646072
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/4.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2676850269
Short name	T95
Test name
Test status
Simulation time	20188819623 ps
CPU time	86.5 seconds
Started	Sep 01 05:39:39 AM UTC 24
Finished	Sep 01 05:41:07 AM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676850269 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2676850269
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/4.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.3710103608
Short name	T89
Test name
Test status
Simulation time	5461135339 ps
CPU time	49.56 seconds
Started	Sep 01 05:39:41 AM UTC 24
Finished	Sep 01 05:40:32 AM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710103608 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.3710103608
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/4.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.3637686002
Short name	T182
Test name
Test status
Simulation time	30786327 ps
CPU time	3.88 seconds
Started	Sep 01 05:39:38 AM UTC 24
Finished	Sep 01 05:39:43 AM UTC 24
Peak memory	216744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637686002 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.3637686002
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/4.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.1223770292
Short name	T193
Test name
Test status
Simulation time	877293174 ps
CPU time	100.58 seconds
Started	Sep 01 05:40:16 AM UTC 24
Finished	Sep 01 05:41:59 AM UTC 24
Peak memory	221060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223770292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1223770292
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/4.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.857391868
Short name	T93
Test name
Test status
Simulation time	1536954031 ps
CPU time	27.63 seconds
Started	Sep 01 05:40:17 AM UTC 24
Finished	Sep 01 05:40:46 AM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857391868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.857391868
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/4.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.2748251592
Short name	T201
Test name
Test status
Simulation time	12333343612 ps
CPU time	314.72 seconds
Started	Sep 01 05:40:17 AM UTC 24
Finished	Sep 01 05:45:37 AM UTC 24
Peak memory	223048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748251592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.2748251592
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/4.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.1900002950
Short name	T92
Test name
Test status
Simulation time	860547262 ps
CPU time	36.9 seconds
Started	Sep 01 05:40:07 AM UTC 24
Finished	Sep 01 05:40:45 AM UTC 24
Peak memory	219136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900002950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1900002950
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/4.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.890795397
Short name	T732
Test name
Test status
Simulation time	2077754496 ps
CPU time	63.68 seconds
Started	Sep 01 06:02:30 AM UTC 24
Finished	Sep 01 06:03:36 AM UTC 24
Peak memory	218820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890795397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.890795397
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/40.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3501057858
Short name	T134
Test name
Test status
Simulation time	84648998236 ps
CPU time	475.18 seconds
Started	Sep 01 06:02:30 AM UTC 24
Finished	Sep 01 06:10:31 AM UTC 24
Peak memory	219456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501057858 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.3501057858
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/40.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.1103315433
Short name	T709
Test name
Test status
Simulation time	1618362823 ps
CPU time	18.56 seconds
Started	Sep 01 06:02:39 AM UTC 24
Finished	Sep 01 06:02:58 AM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103315433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.1103315433
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/40.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.1448174713
Short name	T706
Test name
Test status
Simulation time	508818722 ps
CPU time	18.29 seconds
Started	Sep 01 06:02:37 AM UTC 24
Finished	Sep 01 06:02:56 AM UTC 24
Peak memory	216948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448174713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1448174713
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/40.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random.820881389
Short name	T716
Test name
Test status
Simulation time	816350168 ps
CPU time	37.26 seconds
Started	Sep 01 06:02:24 AM UTC 24
Finished	Sep 01 06:03:03 AM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820881389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.820881389
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/40.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.4068869044
Short name	T803
Test name
Test status
Simulation time	43319681850 ps
CPU time	200.08 seconds
Started	Sep 01 06:02:26 AM UTC 24
Finished	Sep 01 06:05:50 AM UTC 24
Peak memory	217156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068869044 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.4068869044
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/40.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1089746141
Short name	T801
Test name
Test status
Simulation time	30588198475 ps
CPU time	184.81 seconds
Started	Sep 01 06:02:28 AM UTC 24
Finished	Sep 01 06:05:36 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089746141 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1089746141
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/40.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.3716147113
Short name	T703
Test name
Test status
Simulation time	66344395 ps
CPU time	9.91 seconds
Started	Sep 01 06:02:26 AM UTC 24
Finished	Sep 01 06:02:37 AM UTC 24
Peak memory	216752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716147113 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.3716147113
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/40.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.3948816369
Short name	T707
Test name
Test status
Simulation time	330936693 ps
CPU time	23.42 seconds
Started	Sep 01 06:02:32 AM UTC 24
Finished	Sep 01 06:02:57 AM UTC 24
Peak memory	223596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948816369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3948816369
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/40.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.3134927608
Short name	T697
Test name
Test status
Simulation time	197062610 ps
CPU time	5.21 seconds
Started	Sep 01 06:02:20 AM UTC 24
Finished	Sep 01 06:02:27 AM UTC 24
Peak memory	217132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134927608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3134927608
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/40.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.1868468835
Short name	T141
Test name
Test status
Simulation time	9586330676 ps
CPU time	44.29 seconds
Started	Sep 01 06:02:24 AM UTC 24
Finished	Sep 01 06:03:09 AM UTC 24
Peak memory	217140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868468835 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1868468835
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/40.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.4170288510
Short name	T705
Test name
Test status
Simulation time	5178051434 ps
CPU time	28.44 seconds
Started	Sep 01 06:02:24 AM UTC 24
Finished	Sep 01 06:02:54 AM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170288510 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.4170288510
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/40.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.382502814
Short name	T695
Test name
Test status
Simulation time	60197353 ps
CPU time	3.26 seconds
Started	Sep 01 06:02:20 AM UTC 24
Finished	Sep 01 06:02:25 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382502814 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.382502814
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/40.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.3936956610
Short name	T872
Test name
Test status
Simulation time	15678416262 ps
CPU time	317.05 seconds
Started	Sep 01 06:02:39 AM UTC 24
Finished	Sep 01 06:08:00 AM UTC 24
Peak memory	223408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936956610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3936956610
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/40.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.396446725
Short name	T746
Test name
Test status
Simulation time	3022943618 ps
CPU time	75.58 seconds
Started	Sep 01 06:02:54 AM UTC 24
Finished	Sep 01 06:04:11 AM UTC 24
Peak memory	219212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396446725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.396446725
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/40.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.139415220
Short name	T820
Test name
Test status
Simulation time	601250051 ps
CPU time	202.15 seconds
Started	Sep 01 06:02:47 AM UTC 24
Finished	Sep 01 06:06:13 AM UTC 24
Peak memory	220860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139415220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.139415220
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/40.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3870370647
Short name	T887
Test name
Test status
Simulation time	4869667003 ps
CPU time	416.87 seconds
Started	Sep 01 06:02:56 AM UTC 24
Finished	Sep 01 06:09:58 AM UTC 24
Peak memory	233656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870370647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.3870370647
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/40.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.746785354
Short name	T721
Test name
Test status
Simulation time	2049444281 ps
CPU time	37.2 seconds
Started	Sep 01 06:02:39 AM UTC 24
Finished	Sep 01 06:03:17 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746785354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.746785354
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/40.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.362289102
Short name	T70
Test name
Test status
Simulation time	67774067 ps
CPU time	8.23 seconds
Started	Sep 01 06:03:06 AM UTC 24
Finished	Sep 01 06:03:15 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362289102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.362289102
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/41.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3076222790
Short name	T895
Test name
Test status
Simulation time	51787692189 ps
CPU time	553.33 seconds
Started	Sep 01 06:03:06 AM UTC 24
Finished	Sep 01 06:12:26 AM UTC 24
Peak memory	220888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076222790 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.3076222790
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/41.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.1750205253
Short name	T728
Test name
Test status
Simulation time	390720311 ps
CPU time	15.73 seconds
Started	Sep 01 06:03:08 AM UTC 24
Finished	Sep 01 06:03:25 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750205253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.1750205253
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/41.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.2884840214
Short name	T733
Test name
Test status
Simulation time	804389006 ps
CPU time	30.82 seconds
Started	Sep 01 06:03:06 AM UTC 24
Finished	Sep 01 06:03:38 AM UTC 24
Peak memory	216756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884840214 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2884840214
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/41.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random.2379683082
Short name	T720
Test name
Test status
Simulation time	87716628 ps
CPU time	3.99 seconds
Started	Sep 01 06:03:05 AM UTC 24
Finished	Sep 01 06:03:10 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379683082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.2379683082
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/41.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.2516711145
Short name	T799
Test name
Test status
Simulation time	14862814295 ps
CPU time	143.28 seconds
Started	Sep 01 06:03:06 AM UTC 24
Finished	Sep 01 06:05:32 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516711145 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2516711145
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/41.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.68653581
Short name	T881
Test name
Test status
Simulation time	45703579559 ps
CPU time	329.09 seconds
Started	Sep 01 06:03:06 AM UTC 24
Finished	Sep 01 06:08:39 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68653581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.68653581
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/41.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.1407320944
Short name	T723
Test name
Test status
Simulation time	178727659 ps
CPU time	14.84 seconds
Started	Sep 01 06:03:05 AM UTC 24
Finished	Sep 01 06:03:21 AM UTC 24
Peak memory	216756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407320944 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1407320944
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/41.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.2756247135
Short name	T725
Test name
Test status
Simulation time	855314426 ps
CPU time	17.12 seconds
Started	Sep 01 06:03:06 AM UTC 24
Finished	Sep 01 06:03:24 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756247135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2756247135
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/41.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.3018513596
Short name	T717
Test name
Test status
Simulation time	981592860 ps
CPU time	5.65 seconds
Started	Sep 01 06:02:57 AM UTC 24
Finished	Sep 01 06:03:04 AM UTC 24
Peak memory	217072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018513596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3018513596
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/41.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.3650666978
Short name	T734
Test name
Test status
Simulation time	5366414608 ps
CPU time	41.43 seconds
Started	Sep 01 06:03:00 AM UTC 24
Finished	Sep 01 06:03:43 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650666978 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3650666978
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/41.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2771362195
Short name	T737
Test name
Test status
Simulation time	11641800028 ps
CPU time	47.22 seconds
Started	Sep 01 06:03:00 AM UTC 24
Finished	Sep 01 06:03:49 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771362195 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2771362195
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/41.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.15974580
Short name	T715
Test name
Test status
Simulation time	89891074 ps
CPU time	2.81 seconds
Started	Sep 01 06:02:59 AM UTC 24
Finished	Sep 01 06:03:02 AM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15974580 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.15974580
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/41.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.658371985
Short name	T751
Test name
Test status
Simulation time	555537801 ps
CPU time	66.92 seconds
Started	Sep 01 06:03:08 AM UTC 24
Finished	Sep 01 06:04:17 AM UTC 24
Peak memory	218816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658371985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.658371985
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/41.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.1928548532
Short name	T745
Test name
Test status
Simulation time	6001689443 ps
CPU time	54.24 seconds
Started	Sep 01 06:03:12 AM UTC 24
Finished	Sep 01 06:04:08 AM UTC 24
Peak memory	218944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928548532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1928548532
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/41.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1206183613
Short name	T132
Test name
Test status
Simulation time	5568371171 ps
CPU time	618.77 seconds
Started	Sep 01 06:03:10 AM UTC 24
Finished	Sep 01 06:13:37 AM UTC 24
Peak memory	224924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206183613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.1206183613
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/41.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1976492066
Short name	T736
Test name
Test status
Simulation time	42810315 ps
CPU time	27.93 seconds
Started	Sep 01 06:03:16 AM UTC 24
Finished	Sep 01 06:03:46 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976492066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.1976492066
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/41.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.2784286543
Short name	T722
Test name
Test status
Simulation time	665339784 ps
CPU time	12.45 seconds
Started	Sep 01 06:03:06 AM UTC 24
Finished	Sep 01 06:03:19 AM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784286543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2784286543
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/41.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.3958577804
Short name	T756
Test name
Test status
Simulation time	385194066 ps
CPU time	56.77 seconds
Started	Sep 01 06:03:29 AM UTC 24
Finished	Sep 01 06:04:28 AM UTC 24
Peak memory	217100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958577804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3958577804
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/42.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1330906884
Short name	T894
Test name
Test status
Simulation time	77620888610 ps
CPU time	527.77 seconds
Started	Sep 01 06:03:31 AM UTC 24
Finished	Sep 01 06:12:25 AM UTC 24
Peak memory	221000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330906884 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.1330906884
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/42.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.4174034335
Short name	T738
Test name
Test status
Simulation time	99823234 ps
CPU time	10.41 seconds
Started	Sep 01 06:03:39 AM UTC 24
Finished	Sep 01 06:03:51 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174034335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.4174034335
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/42.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.3137342161
Short name	T742
Test name
Test status
Simulation time	429899305 ps
CPU time	23.39 seconds
Started	Sep 01 06:03:36 AM UTC 24
Finished	Sep 01 06:04:01 AM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137342161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3137342161
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/42.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random.240159578
Short name	T750
Test name
Test status
Simulation time	953333709 ps
CPU time	47.22 seconds
Started	Sep 01 06:03:27 AM UTC 24
Finished	Sep 01 06:04:16 AM UTC 24
Peak memory	219136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240159578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.240159578
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/42.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.1985799006
Short name	T878
Test name
Test status
Simulation time	79961185295 ps
CPU time	300.28 seconds
Started	Sep 01 06:03:27 AM UTC 24
Finished	Sep 01 06:08:32 AM UTC 24
Peak memory	216904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985799006 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1985799006
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/42.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1129214831
Short name	T758
Test name
Test status
Simulation time	7364019118 ps
CPU time	59.66 seconds
Started	Sep 01 06:03:29 AM UTC 24
Finished	Sep 01 06:04:30 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129214831 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1129214831
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/42.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.1398456876
Short name	T743
Test name
Test status
Simulation time	254934784 ps
CPU time	34.57 seconds
Started	Sep 01 06:03:27 AM UTC 24
Finished	Sep 01 06:04:03 AM UTC 24
Peak memory	217148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398456876 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.1398456876
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/42.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.1099950225
Short name	T739
Test name
Test status
Simulation time	1379430435 ps
CPU time	15.85 seconds
Started	Sep 01 06:03:34 AM UTC 24
Finished	Sep 01 06:03:51 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099950225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1099950225
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/42.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.772359819
Short name	T724
Test name
Test status
Simulation time	28259161 ps
CPU time	3.01 seconds
Started	Sep 01 06:03:19 AM UTC 24
Finished	Sep 01 06:03:24 AM UTC 24
Peak memory	217068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772359819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.772359819
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/42.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.87015681
Short name	T748
Test name
Test status
Simulation time	12075414933 ps
CPU time	50 seconds
Started	Sep 01 06:03:23 AM UTC 24
Finished	Sep 01 06:04:15 AM UTC 24
Peak memory	216884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87015681 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.87015681
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/42.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3562680294
Short name	T142
Test name
Test status
Simulation time	4882347395 ps
CPU time	47.38 seconds
Started	Sep 01 06:03:27 AM UTC 24
Finished	Sep 01 06:04:16 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562680294 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3562680294
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/42.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.2926508072
Short name	T726
Test name
Test status
Simulation time	82121648 ps
CPU time	2.37 seconds
Started	Sep 01 06:03:21 AM UTC 24
Finished	Sep 01 06:03:25 AM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926508072 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.2926508072
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/42.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.860717283
Short name	T838
Test name
Test status
Simulation time	6115359885 ps
CPU time	173.1 seconds
Started	Sep 01 06:03:45 AM UTC 24
Finished	Sep 01 06:06:41 AM UTC 24
Peak memory	220928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860717283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.860717283
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/42.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3711745093
Short name	T763
Test name
Test status
Simulation time	1241186684 ps
CPU time	52.33 seconds
Started	Sep 01 06:03:47 AM UTC 24
Finished	Sep 01 06:04:41 AM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711745093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3711745093
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/42.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3400832407
Short name	T772
Test name
Test status
Simulation time	186920565 ps
CPU time	64.86 seconds
Started	Sep 01 06:03:45 AM UTC 24
Finished	Sep 01 06:04:52 AM UTC 24
Peak memory	218820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400832407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.3400832407
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/42.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.4273534442
Short name	T291
Test name
Test status
Simulation time	4086542862 ps
CPU time	29.12 seconds
Started	Sep 01 06:03:37 AM UTC 24
Finished	Sep 01 06:04:08 AM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273534442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.4273534442
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/42.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.2027225030
Short name	T747
Test name
Test status
Simulation time	102047423 ps
CPU time	3.39 seconds
Started	Sep 01 06:04:10 AM UTC 24
Finished	Sep 01 06:04:14 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027225030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.2027225030
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/43.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3215944958
Short name	T893
Test name
Test status
Simulation time	52175658371 ps
CPU time	472.21 seconds
Started	Sep 01 06:04:13 AM UTC 24
Finished	Sep 01 06:12:11 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215944958 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.3215944958
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/43.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2758563528
Short name	T767
Test name
Test status
Simulation time	1734418694 ps
CPU time	27.51 seconds
Started	Sep 01 06:04:18 AM UTC 24
Finished	Sep 01 06:04:47 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758563528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.2758563528
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/43.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.292394023
Short name	T760
Test name
Test status
Simulation time	290820544 ps
CPU time	18.31 seconds
Started	Sep 01 06:04:18 AM UTC 24
Finished	Sep 01 06:04:38 AM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292394023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.292394023
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/43.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random.3051248972
Short name	T754
Test name
Test status
Simulation time	419118189 ps
CPU time	21.34 seconds
Started	Sep 01 06:04:02 AM UTC 24
Finished	Sep 01 06:04:25 AM UTC 24
Peak memory	216960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051248972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.3051248972
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/43.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.2096098031
Short name	T797
Test name
Test status
Simulation time	34718720843 ps
CPU time	77.5 seconds
Started	Sep 01 06:04:10 AM UTC 24
Finished	Sep 01 06:05:29 AM UTC 24
Peak memory	217140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096098031 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2096098031
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/43.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.2232781318
Short name	T829
Test name
Test status
Simulation time	25760002385 ps
CPU time	131.76 seconds
Started	Sep 01 06:04:10 AM UTC 24
Finished	Sep 01 06:06:24 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232781318 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2232781318
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/43.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.2334477798
Short name	T753
Test name
Test status
Simulation time	77625925 ps
CPU time	12.94 seconds
Started	Sep 01 06:04:05 AM UTC 24
Finished	Sep 01 06:04:19 AM UTC 24
Peak memory	216752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334477798 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.2334477798
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/43.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.1896041128
Short name	T759
Test name
Test status
Simulation time	126833293 ps
CPU time	11.09 seconds
Started	Sep 01 06:04:18 AM UTC 24
Finished	Sep 01 06:04:30 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896041128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1896041128
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/43.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.952238410
Short name	T740
Test name
Test status
Simulation time	41577898 ps
CPU time	3.13 seconds
Started	Sep 01 06:03:52 AM UTC 24
Finished	Sep 01 06:03:56 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952238410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.952238410
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/43.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.679900263
Short name	T771
Test name
Test status
Simulation time	13542298390 ps
CPU time	52.11 seconds
Started	Sep 01 06:03:57 AM UTC 24
Finished	Sep 01 06:04:51 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679900263 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.679900263
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/43.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2703706130
Short name	T768
Test name
Test status
Simulation time	5957613963 ps
CPU time	47.52 seconds
Started	Sep 01 06:03:58 AM UTC 24
Finished	Sep 01 06:04:47 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703706130 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2703706130
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/43.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.2121627530
Short name	T741
Test name
Test status
Simulation time	39357070 ps
CPU time	2.84 seconds
Started	Sep 01 06:03:54 AM UTC 24
Finished	Sep 01 06:03:57 AM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121627530 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.2121627530
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/43.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.2515723297
Short name	T886
Test name
Test status
Simulation time	32984563346 ps
CPU time	302.98 seconds
Started	Sep 01 06:04:18 AM UTC 24
Finished	Sep 01 06:09:26 AM UTC 24
Peak memory	218944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515723297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2515723297
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/43.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1263863951
Short name	T810
Test name
Test status
Simulation time	909164241 ps
CPU time	94.63 seconds
Started	Sep 01 06:04:21 AM UTC 24
Finished	Sep 01 06:05:57 AM UTC 24
Peak memory	218820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263863951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1263863951
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/43.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1719121041
Short name	T891
Test name
Test status
Simulation time	2060280073 ps
CPU time	401.19 seconds
Started	Sep 01 06:04:21 AM UTC 24
Finished	Sep 01 06:11:08 AM UTC 24
Peak memory	233592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719121041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.1719121041
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/43.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2440945756
Short name	T794
Test name
Test status
Simulation time	70789437 ps
CPU time	63.18 seconds
Started	Sep 01 06:04:21 AM UTC 24
Finished	Sep 01 06:05:26 AM UTC 24
Peak memory	220936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440945756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.2440945756
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/43.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.1286657603
Short name	T761
Test name
Test status
Simulation time	147789943 ps
CPU time	18.41 seconds
Started	Sep 01 06:04:18 AM UTC 24
Finished	Sep 01 06:04:38 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286657603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1286657603
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/43.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.1955279967
Short name	T778
Test name
Test status
Simulation time	677460176 ps
CPU time	23.2 seconds
Started	Sep 01 06:04:32 AM UTC 24
Finished	Sep 01 06:04:57 AM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955279967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.1955279967
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/44.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3425190433
Short name	T897
Test name
Test status
Simulation time	86614077101 ps
CPU time	536.56 seconds
Started	Sep 01 06:04:34 AM UTC 24
Finished	Sep 01 06:13:38 AM UTC 24
Peak memory	222548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425190433 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.3425190433
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/44.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.22675610
Short name	T777
Test name
Test status
Simulation time	519322205 ps
CPU time	12.97 seconds
Started	Sep 01 06:04:42 AM UTC 24
Finished	Sep 01 06:04:56 AM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22675610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.22675610
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/44.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.330245492
Short name	T776
Test name
Test status
Simulation time	362678766 ps
CPU time	14.17 seconds
Started	Sep 01 06:04:40 AM UTC 24
Finished	Sep 01 06:04:55 AM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330245492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.330245492
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/44.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.2278101592
Short name	T286
Test name
Test status
Simulation time	2239344826 ps
CPU time	21.48 seconds
Started	Sep 01 06:04:28 AM UTC 24
Finished	Sep 01 06:04:51 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278101592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2278101592
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/44.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.283103041
Short name	T764
Test name
Test status
Simulation time	1567706968 ps
CPU time	10.65 seconds
Started	Sep 01 06:04:30 AM UTC 24
Finished	Sep 01 06:04:42 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283103041 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.283103041
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/44.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.448173525
Short name	T809
Test name
Test status
Simulation time	5590838117 ps
CPU time	82.85 seconds
Started	Sep 01 06:04:32 AM UTC 24
Finished	Sep 01 06:05:57 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448173525 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.448173525
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/44.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.2370601399
Short name	T769
Test name
Test status
Simulation time	526890696 ps
CPU time	17.45 seconds
Started	Sep 01 06:04:30 AM UTC 24
Finished	Sep 01 06:04:49 AM UTC 24
Peak memory	217080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370601399 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.2370601399
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/44.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.3796251065
Short name	T779
Test name
Test status
Simulation time	604034470 ps
CPU time	16.55 seconds
Started	Sep 01 06:04:40 AM UTC 24
Finished	Sep 01 06:04:58 AM UTC 24
Peak memory	217028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796251065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3796251065
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/44.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.2728948278
Short name	T755
Test name
Test status
Simulation time	42928745 ps
CPU time	2.95 seconds
Started	Sep 01 06:04:22 AM UTC 24
Finished	Sep 01 06:04:26 AM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728948278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2728948278
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/44.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.2951582730
Short name	T786
Test name
Test status
Simulation time	5130738854 ps
CPU time	42.46 seconds
Started	Sep 01 06:04:25 AM UTC 24
Finished	Sep 01 06:05:09 AM UTC 24
Peak memory	217140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951582730 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2951582730
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/44.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.939370765
Short name	T785
Test name
Test status
Simulation time	3618230967 ps
CPU time	36.81 seconds
Started	Sep 01 06:04:28 AM UTC 24
Finished	Sep 01 06:05:06 AM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939370765 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.939370765
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/44.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.1566492585
Short name	T757
Test name
Test status
Simulation time	42386070 ps
CPU time	2.8 seconds
Started	Sep 01 06:04:24 AM UTC 24
Finished	Sep 01 06:04:28 AM UTC 24
Peak memory	217064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566492585 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.1566492585
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/44.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.4077718013
Short name	T864
Test name
Test status
Simulation time	2334917590 ps
CPU time	160.25 seconds
Started	Sep 01 06:04:42 AM UTC 24
Finished	Sep 01 06:07:25 AM UTC 24
Peak memory	221316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077718013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.4077718013
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/44.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.554219236
Short name	T798
Test name
Test status
Simulation time	857622831 ps
CPU time	43.1 seconds
Started	Sep 01 06:04:45 AM UTC 24
Finished	Sep 01 06:05:29 AM UTC 24
Peak memory	216672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554219236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.554219236
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/44.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.21364958
Short name	T160
Test name
Test status
Simulation time	2961272287 ps
CPU time	248.17 seconds
Started	Sep 01 06:04:45 AM UTC 24
Finished	Sep 01 06:08:57 AM UTC 24
Peak memory	222804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21364958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.21364958
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/44.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.4178944039
Short name	T890
Test name
Test status
Simulation time	2442665514 ps
CPU time	364.82 seconds
Started	Sep 01 06:04:45 AM UTC 24
Finished	Sep 01 06:10:55 AM UTC 24
Peak memory	233724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178944039 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.4178944039
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/44.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.2197037710
Short name	T781
Test name
Test status
Simulation time	373197361 ps
CPU time	19.64 seconds
Started	Sep 01 06:04:40 AM UTC 24
Finished	Sep 01 06:05:01 AM UTC 24
Peak memory	219140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197037710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2197037710
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/44.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.2774722216
Short name	T806
Test name
Test status
Simulation time	1578264398 ps
CPU time	56.46 seconds
Started	Sep 01 06:04:56 AM UTC 24
Finished	Sep 01 06:05:54 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774722216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.2774722216
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/45.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2485121077
Short name	T252
Test name
Test status
Simulation time	8708999758 ps
CPU time	90.18 seconds
Started	Sep 01 06:04:56 AM UTC 24
Finished	Sep 01 06:06:28 AM UTC 24
Peak memory	217160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485121077 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.2485121077
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/45.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1872311657
Short name	T795
Test name
Test status
Simulation time	1954628702 ps
CPU time	25.5 seconds
Started	Sep 01 06:05:00 AM UTC 24
Finished	Sep 01 06:05:26 AM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872311657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.1872311657
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/45.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3763817264
Short name	T789
Test name
Test status
Simulation time	355986931 ps
CPU time	13.44 seconds
Started	Sep 01 06:04:58 AM UTC 24
Finished	Sep 01 06:05:13 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763817264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3763817264
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/45.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.4230467856
Short name	T783
Test name
Test status
Simulation time	78329732 ps
CPU time	8.87 seconds
Started	Sep 01 06:04:52 AM UTC 24
Finished	Sep 01 06:05:02 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230467856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.4230467856
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/45.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.4119346189
Short name	T866
Test name
Test status
Simulation time	36345269998 ps
CPU time	152.63 seconds
Started	Sep 01 06:04:54 AM UTC 24
Finished	Sep 01 06:07:29 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119346189 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.4119346189
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/45.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2536458337
Short name	T863
Test name
Test status
Simulation time	14638843720 ps
CPU time	146.82 seconds
Started	Sep 01 06:04:54 AM UTC 24
Finished	Sep 01 06:07:24 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536458337 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2536458337
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/45.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.2586832801
Short name	T780
Test name
Test status
Simulation time	68489795 ps
CPU time	7.32 seconds
Started	Sep 01 06:04:52 AM UTC 24
Finished	Sep 01 06:05:01 AM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586832801 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2586832801
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/45.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.1954263988
Short name	T792
Test name
Test status
Simulation time	782340135 ps
CPU time	21.04 seconds
Started	Sep 01 06:04:58 AM UTC 24
Finished	Sep 01 06:05:21 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954263988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1954263988
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/45.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.3797108315
Short name	T775
Test name
Test status
Simulation time	185199763 ps
CPU time	4.6 seconds
Started	Sep 01 06:04:49 AM UTC 24
Finished	Sep 01 06:04:54 AM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797108315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3797108315
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/45.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.4176635129
Short name	T802
Test name
Test status
Simulation time	5546588758 ps
CPU time	53.15 seconds
Started	Sep 01 06:04:50 AM UTC 24
Finished	Sep 01 06:05:45 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176635129 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.4176635129
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/45.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.42840040
Short name	T818
Test name
Test status
Simulation time	11240027253 ps
CPU time	73.91 seconds
Started	Sep 01 06:04:50 AM UTC 24
Finished	Sep 01 06:06:06 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42840040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.42840040
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/45.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2350120616
Short name	T773
Test name
Test status
Simulation time	24378391 ps
CPU time	2.49 seconds
Started	Sep 01 06:04:49 AM UTC 24
Finished	Sep 01 06:04:52 AM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350120616 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.2350120616
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/45.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.1650718976
Short name	T846
Test name
Test status
Simulation time	3763175831 ps
CPU time	108.56 seconds
Started	Sep 01 06:05:03 AM UTC 24
Finished	Sep 01 06:06:54 AM UTC 24
Peak memory	220928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650718976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1650718976
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/45.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3369320175
Short name	T814
Test name
Test status
Simulation time	1759045991 ps
CPU time	57.01 seconds
Started	Sep 01 06:05:03 AM UTC 24
Finished	Sep 01 06:06:02 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369320175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3369320175
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/45.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2054593420
Short name	T274
Test name
Test status
Simulation time	1804253201 ps
CPU time	275.4 seconds
Started	Sep 01 06:05:03 AM UTC 24
Finished	Sep 01 06:09:42 AM UTC 24
Peak memory	222916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054593420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.2054593420
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/45.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1823568875
Short name	T853
Test name
Test status
Simulation time	622501230 ps
CPU time	116.14 seconds
Started	Sep 01 06:05:04 AM UTC 24
Finished	Sep 01 06:07:03 AM UTC 24
Peak memory	223244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823568875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.1823568875
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/45.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.2339292163
Short name	T784
Test name
Test status
Simulation time	92265730 ps
CPU time	6.07 seconds
Started	Sep 01 06:04:58 AM UTC 24
Finished	Sep 01 06:05:05 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339292163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2339292163
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/45.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.3632573374
Short name	T71
Test name
Test status
Simulation time	3890795031 ps
CPU time	45.66 seconds
Started	Sep 01 06:05:21 AM UTC 24
Finished	Sep 01 06:06:09 AM UTC 24
Peak memory	218956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632573374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.3632573374
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/46.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.448506490
Short name	T210
Test name
Test status
Simulation time	9100589314 ps
CPU time	90.53 seconds
Started	Sep 01 06:05:26 AM UTC 24
Finished	Sep 01 06:06:59 AM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448506490 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.448506490
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/46.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.633454833
Short name	T812
Test name
Test status
Simulation time	2289117087 ps
CPU time	26.82 seconds
Started	Sep 01 06:05:31 AM UTC 24
Finished	Sep 01 06:05:59 AM UTC 24
Peak memory	216704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633454833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.633454833
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/46.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.2017650467
Short name	T807
Test name
Test status
Simulation time	257490265 ps
CPU time	24.04 seconds
Started	Sep 01 06:05:29 AM UTC 24
Finished	Sep 01 06:05:55 AM UTC 24
Peak memory	217084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017650467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2017650467
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/46.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.359454664
Short name	T793
Test name
Test status
Simulation time	264744457 ps
CPU time	8.92 seconds
Started	Sep 01 06:05:14 AM UTC 24
Finished	Sep 01 06:05:25 AM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359454664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.359454664
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/46.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.1559717711
Short name	T828
Test name
Test status
Simulation time	16157100190 ps
CPU time	63.44 seconds
Started	Sep 01 06:05:16 AM UTC 24
Finished	Sep 01 06:06:22 AM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559717711 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1559717711
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/46.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1596018910
Short name	T805
Test name
Test status
Simulation time	16510584009 ps
CPU time	156.78 seconds
Started	Sep 01 06:05:16 AM UTC 24
Finished	Sep 01 06:07:56 AM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596018910 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1596018910
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/46.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.3234364356
Short name	T796
Test name
Test status
Simulation time	122414159 ps
CPU time	10 seconds
Started	Sep 01 06:05:16 AM UTC 24
Finished	Sep 01 06:05:27 AM UTC 24
Peak memory	217148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234364356 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.3234364356
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/46.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.4262291503
Short name	T667
Test name
Test status
Simulation time	655939070 ps
CPU time	20.87 seconds
Started	Sep 01 06:05:29 AM UTC 24
Finished	Sep 01 06:05:52 AM UTC 24
Peak memory	217084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262291503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.4262291503
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/46.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.3814861109
Short name	T788
Test name
Test status
Simulation time	118662820 ps
CPU time	4.29 seconds
Started	Sep 01 06:05:07 AM UTC 24
Finished	Sep 01 06:05:12 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814861109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3814861109
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/46.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1890940412
Short name	T826
Test name
Test status
Simulation time	11344178688 ps
CPU time	67.64 seconds
Started	Sep 01 06:05:10 AM UTC 24
Finished	Sep 01 06:06:20 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890940412 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1890940412
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/46.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.657144750
Short name	T815
Test name
Test status
Simulation time	3037682601 ps
CPU time	50.43 seconds
Started	Sep 01 06:05:12 AM UTC 24
Finished	Sep 01 06:06:04 AM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657144750 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.657144750
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/46.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.370577951
Short name	T787
Test name
Test status
Simulation time	27322022 ps
CPU time	3.17 seconds
Started	Sep 01 06:05:07 AM UTC 24
Finished	Sep 01 06:05:11 AM UTC 24
Peak memory	217068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370577951 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.370577951
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/46.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.3120501594
Short name	T830
Test name
Test status
Simulation time	358363811 ps
CPU time	55.15 seconds
Started	Sep 01 06:05:31 AM UTC 24
Finished	Sep 01 06:06:28 AM UTC 24
Peak memory	218760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120501594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3120501594
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/46.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2807021317
Short name	T869
Test name
Test status
Simulation time	4052495184 ps
CPU time	119.08 seconds
Started	Sep 01 06:05:34 AM UTC 24
Finished	Sep 01 06:07:36 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807021317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2807021317
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/46.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1001861363
Short name	T889
Test name
Test status
Simulation time	6172716667 ps
CPU time	295.39 seconds
Started	Sep 01 06:05:32 AM UTC 24
Finished	Sep 01 06:10:32 AM UTC 24
Peak memory	223048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001861363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.1001861363
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/46.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.1142864731
Short name	T849
Test name
Test status
Simulation time	369704611 ps
CPU time	80.97 seconds
Started	Sep 01 06:05:37 AM UTC 24
Finished	Sep 01 06:06:59 AM UTC 24
Peak memory	220868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142864731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.1142864731
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/46.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.1319307207
Short name	T800
Test name
Test status
Simulation time	24100235 ps
CPU time	2.7 seconds
Started	Sep 01 06:05:29 AM UTC 24
Finished	Sep 01 06:05:33 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319307207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1319307207
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/46.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.1764538289
Short name	T822
Test name
Test status
Simulation time	144448285 ps
CPU time	15.21 seconds
Started	Sep 01 06:05:59 AM UTC 24
Finished	Sep 01 06:06:16 AM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764538289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1764538289
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/47.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1474272274
Short name	T871
Test name
Test status
Simulation time	13157687589 ps
CPU time	101 seconds
Started	Sep 01 06:05:59 AM UTC 24
Finished	Sep 01 06:07:42 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474272274 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.1474272274
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/47.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3963232506
Short name	T825
Test name
Test status
Simulation time	273669920 ps
CPU time	14.42 seconds
Started	Sep 01 06:06:04 AM UTC 24
Finished	Sep 01 06:06:19 AM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963232506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.3963232506
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/47.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1450039830
Short name	T816
Test name
Test status
Simulation time	336189757 ps
CPU time	3.43 seconds
Started	Sep 01 06:06:01 AM UTC 24
Finished	Sep 01 06:06:06 AM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450039830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1450039830
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/47.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.4065993241
Short name	T832
Test name
Test status
Simulation time	821756189 ps
CPU time	36.46 seconds
Started	Sep 01 06:05:55 AM UTC 24
Finished	Sep 01 06:06:33 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065993241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.4065993241
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/47.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.248186750
Short name	T143
Test name
Test status
Simulation time	23475705353 ps
CPU time	131.44 seconds
Started	Sep 01 06:05:57 AM UTC 24
Finished	Sep 01 06:08:11 AM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248186750 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.248186750
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/47.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3953619704
Short name	T880
Test name
Test status
Simulation time	24869798594 ps
CPU time	151.95 seconds
Started	Sep 01 06:05:59 AM UTC 24
Finished	Sep 01 06:08:34 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953619704 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3953619704
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/47.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.2901543798
Short name	T834
Test name
Test status
Simulation time	361183553 ps
CPU time	39.76 seconds
Started	Sep 01 06:05:55 AM UTC 24
Finished	Sep 01 06:06:36 AM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901543798 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.2901543798
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/47.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.910680853
Short name	T827
Test name
Test status
Simulation time	1041725113 ps
CPU time	18.96 seconds
Started	Sep 01 06:06:01 AM UTC 24
Finished	Sep 01 06:06:21 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910680853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.910680853
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/47.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.3484665087
Short name	T804
Test name
Test status
Simulation time	27506050 ps
CPU time	3.31 seconds
Started	Sep 01 06:05:46 AM UTC 24
Finished	Sep 01 06:05:50 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484665087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3484665087
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/47.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1124265902
Short name	T835
Test name
Test status
Simulation time	16032483482 ps
CPU time	43.13 seconds
Started	Sep 01 06:05:53 AM UTC 24
Finished	Sep 01 06:06:37 AM UTC 24
Peak memory	217140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124265902 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1124265902
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/47.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2761828046
Short name	T845
Test name
Test status
Simulation time	14142656578 ps
CPU time	57.27 seconds
Started	Sep 01 06:05:54 AM UTC 24
Finished	Sep 01 06:06:53 AM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761828046 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2761828046
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/47.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1718726232
Short name	T808
Test name
Test status
Simulation time	41692984 ps
CPU time	3.8 seconds
Started	Sep 01 06:05:51 AM UTC 24
Finished	Sep 01 06:05:55 AM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718726232 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1718726232
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/47.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.246944278
Short name	T877
Test name
Test status
Simulation time	1740055419 ps
CPU time	142.41 seconds
Started	Sep 01 06:06:05 AM UTC 24
Finished	Sep 01 06:08:30 AM UTC 24
Peak memory	218820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246944278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.246944278
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/47.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.4130547429
Short name	T831
Test name
Test status
Simulation time	770757638 ps
CPU time	18.5 seconds
Started	Sep 01 06:06:09 AM UTC 24
Finished	Sep 01 06:06:28 AM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130547429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.4130547429
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/47.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1028106602
Short name	T847
Test name
Test status
Simulation time	186781158 ps
CPU time	46.57 seconds
Started	Sep 01 06:06:09 AM UTC 24
Finished	Sep 01 06:06:57 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028106602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.1028106602
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/47.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3357558981
Short name	T821
Test name
Test status
Simulation time	7757892 ps
CPU time	1.65 seconds
Started	Sep 01 06:06:11 AM UTC 24
Finished	Sep 01 06:06:13 AM UTC 24
Peak memory	215844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357558981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.3357558981
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/47.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.3090664592
Short name	T819
Test name
Test status
Simulation time	121819538 ps
CPU time	6.36 seconds
Started	Sep 01 06:06:04 AM UTC 24
Finished	Sep 01 06:06:11 AM UTC 24
Peak memory	217028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090664592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3090664592
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/47.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.1255990569
Short name	T848
Test name
Test status
Simulation time	961036834 ps
CPU time	34.32 seconds
Started	Sep 01 06:06:23 AM UTC 24
Finished	Sep 01 06:06:58 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255990569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.1255990569
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/48.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3226166739
Short name	T138
Test name
Test status
Simulation time	4951457056 ps
CPU time	53.08 seconds
Started	Sep 01 06:06:23 AM UTC 24
Finished	Sep 01 06:07:17 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226166739 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.3226166739
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/48.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.877857265
Short name	T843
Test name
Test status
Simulation time	183902472 ps
CPU time	18.63 seconds
Started	Sep 01 06:06:30 AM UTC 24
Finished	Sep 01 06:06:50 AM UTC 24
Peak memory	217032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877857265 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.877857265
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/48.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.1548167124
Short name	T837
Test name
Test status
Simulation time	683084180 ps
CPU time	13.84 seconds
Started	Sep 01 06:06:26 AM UTC 24
Finished	Sep 01 06:06:41 AM UTC 24
Peak memory	217080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548167124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1548167124
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/48.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.3641813425
Short name	T833
Test name
Test status
Simulation time	137884293 ps
CPU time	15.68 seconds
Started	Sep 01 06:06:17 AM UTC 24
Finished	Sep 01 06:06:34 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641813425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.3641813425
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/48.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.1087050387
Short name	T885
Test name
Test status
Simulation time	18964188262 ps
CPU time	177.25 seconds
Started	Sep 01 06:06:19 AM UTC 24
Finished	Sep 01 06:09:19 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087050387 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1087050387
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/48.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3523485357
Short name	T879
Test name
Test status
Simulation time	22630323150 ps
CPU time	130.83 seconds
Started	Sep 01 06:06:20 AM UTC 24
Finished	Sep 01 06:08:34 AM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523485357 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3523485357
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/48.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.1066223191
Short name	T836
Test name
Test status
Simulation time	141978610 ps
CPU time	20.17 seconds
Started	Sep 01 06:06:19 AM UTC 24
Finished	Sep 01 06:06:40 AM UTC 24
Peak memory	217084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066223191 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.1066223191
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/48.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.4083055477
Short name	T844
Test name
Test status
Simulation time	2668722886 ps
CPU time	27.44 seconds
Started	Sep 01 06:06:23 AM UTC 24
Finished	Sep 01 06:06:52 AM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083055477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.4083055477
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/48.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.2828241387
Short name	T824
Test name
Test status
Simulation time	690729981 ps
CPU time	5.83 seconds
Started	Sep 01 06:06:11 AM UTC 24
Finished	Sep 01 06:06:18 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828241387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2828241387
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/48.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2338654749
Short name	T856
Test name
Test status
Simulation time	8477740101 ps
CPU time	53.54 seconds
Started	Sep 01 06:06:14 AM UTC 24
Finished	Sep 01 06:07:09 AM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338654749 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2338654749
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/48.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2468193682
Short name	T841
Test name
Test status
Simulation time	3826719762 ps
CPU time	29.2 seconds
Started	Sep 01 06:06:15 AM UTC 24
Finished	Sep 01 06:06:46 AM UTC 24
Peak memory	217132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468193682 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.2468193682
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/48.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2202867444
Short name	T823
Test name
Test status
Simulation time	34828986 ps
CPU time	3.53 seconds
Started	Sep 01 06:06:12 AM UTC 24
Finished	Sep 01 06:06:17 AM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202867444 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2202867444
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/48.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.237253039
Short name	T870
Test name
Test status
Simulation time	488877470 ps
CPU time	64.04 seconds
Started	Sep 01 06:06:30 AM UTC 24
Finished	Sep 01 06:07:36 AM UTC 24
Peak memory	218880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237253039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.237253039
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/48.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.3127447722
Short name	T861
Test name
Test status
Simulation time	916624660 ps
CPU time	40.34 seconds
Started	Sep 01 06:06:35 AM UTC 24
Finished	Sep 01 06:07:17 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127447722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3127447722
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/48.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2786293358
Short name	T883
Test name
Test status
Simulation time	121988200 ps
CPU time	129.44 seconds
Started	Sep 01 06:06:35 AM UTC 24
Finished	Sep 01 06:08:47 AM UTC 24
Peak memory	221260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786293358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.2786293358
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/48.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.602595918
Short name	T874
Test name
Test status
Simulation time	241807553 ps
CPU time	93.19 seconds
Started	Sep 01 06:06:38 AM UTC 24
Finished	Sep 01 06:08:13 AM UTC 24
Peak memory	221184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602595918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.602595918
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/48.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.2658172390
Short name	T840
Test name
Test status
Simulation time	437307744 ps
CPU time	13.6 seconds
Started	Sep 01 06:06:30 AM UTC 24
Finished	Sep 01 06:06:45 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658172390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2658172390
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/48.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.3440145106
Short name	T855
Test name
Test status
Simulation time	82801085 ps
CPU time	17.31 seconds
Started	Sep 01 06:06:48 AM UTC 24
Finished	Sep 01 06:07:06 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440145106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.3440145106
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/49.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3716530647
Short name	T898
Test name
Test status
Simulation time	83374226151 ps
CPU time	430.04 seconds
Started	Sep 01 06:06:51 AM UTC 24
Finished	Sep 01 06:14:07 AM UTC 24
Peak memory	219336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716530647 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.3716530647
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/49.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2071160450
Short name	T854
Test name
Test status
Simulation time	71882889 ps
CPU time	9.76 seconds
Started	Sep 01 06:06:55 AM UTC 24
Finished	Sep 01 06:07:06 AM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071160450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.2071160450
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/49.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.4186189500
Short name	T851
Test name
Test status
Simulation time	73324195 ps
CPU time	5.61 seconds
Started	Sep 01 06:06:53 AM UTC 24
Finished	Sep 01 06:07:00 AM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186189500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.4186189500
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/49.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2967498821
Short name	T860
Test name
Test status
Simulation time	2606284975 ps
CPU time	28.68 seconds
Started	Sep 01 06:06:46 AM UTC 24
Finished	Sep 01 06:07:16 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967498821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.2967498821
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/49.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.2455125171
Short name	T888
Test name
Test status
Simulation time	28502364211 ps
CPU time	188.12 seconds
Started	Sep 01 06:06:48 AM UTC 24
Finished	Sep 01 06:09:59 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455125171 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2455125171
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/49.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.1131142138
Short name	T602
Test name
Test status
Simulation time	23818304324 ps
CPU time	68.23 seconds
Started	Sep 01 06:06:48 AM UTC 24
Finished	Sep 01 06:07:57 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131142138 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1131142138
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/49.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.3101802816
Short name	T859
Test name
Test status
Simulation time	197699502 ps
CPU time	27.48 seconds
Started	Sep 01 06:06:46 AM UTC 24
Finished	Sep 01 06:07:14 AM UTC 24
Peak memory	216752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101802816 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.3101802816
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/49.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.860884782
Short name	T858
Test name
Test status
Simulation time	153894193 ps
CPU time	18.07 seconds
Started	Sep 01 06:06:53 AM UTC 24
Finished	Sep 01 06:07:13 AM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860884782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.860884782
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/49.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.2017036281
Short name	T839
Test name
Test status
Simulation time	28233529 ps
CPU time	3.18 seconds
Started	Sep 01 06:06:39 AM UTC 24
Finished	Sep 01 06:06:43 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017036281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2017036281
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/49.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1406022440
Short name	T867
Test name
Test status
Simulation time	5837277030 ps
CPU time	47.51 seconds
Started	Sep 01 06:06:42 AM UTC 24
Finished	Sep 01 06:07:31 AM UTC 24
Peak memory	216884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406022440 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1406022440
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/49.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.624824976
Short name	T868
Test name
Test status
Simulation time	4122295408 ps
CPU time	47.45 seconds
Started	Sep 01 06:06:42 AM UTC 24
Finished	Sep 01 06:07:32 AM UTC 24
Peak memory	217200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624824976 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.624824976
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/49.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.445433184
Short name	T842
Test name
Test status
Simulation time	42838172 ps
CPU time	2.88 seconds
Started	Sep 01 06:06:42 AM UTC 24
Finished	Sep 01 06:06:46 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445433184 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.445433184
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/49.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.1493903621
Short name	T135
Test name
Test status
Simulation time	5999478972 ps
CPU time	223.48 seconds
Started	Sep 01 06:06:59 AM UTC 24
Finished	Sep 01 06:10:46 AM UTC 24
Peak memory	220996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493903621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1493903621
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/49.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.1403254223
Short name	T875
Test name
Test status
Simulation time	811779706 ps
CPU time	85.75 seconds
Started	Sep 01 06:07:02 AM UTC 24
Finished	Sep 01 06:08:30 AM UTC 24
Peak memory	219128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403254223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1403254223
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/49.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.4064302895
Short name	T882
Test name
Test status
Simulation time	131543046 ps
CPU time	99.08 seconds
Started	Sep 01 06:06:59 AM UTC 24
Finished	Sep 01 06:08:41 AM UTC 24
Peak memory	220932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064302895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.4064302895
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/49.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1964787075
Short name	T896
Test name
Test status
Simulation time	2673243935 ps
CPU time	367.49 seconds
Started	Sep 01 06:07:02 AM UTC 24
Finished	Sep 01 06:13:15 AM UTC 24
Peak memory	233832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964787075 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.1964787075
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/49.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.3681533077
Short name	T862
Test name
Test status
Simulation time	128729506 ps
CPU time	23.2 seconds
Started	Sep 01 06:06:55 AM UTC 24
Finished	Sep 01 06:07:20 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681533077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3681533077
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/49.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.1707075493
Short name	T296
Test name
Test status
Simulation time	60335024410 ps
CPU time	685.53 seconds
Started	Sep 01 05:41:08 AM UTC 24
Finished	Sep 01 05:52:42 AM UTC 24
Peak memory	220500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707075493 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.1707075493
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/5.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.223767447
Short name	T188
Test name
Test status
Simulation time	19093604 ps
CPU time	2.38 seconds
Started	Sep 01 05:41:34 AM UTC 24
Finished	Sep 01 05:41:38 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223767447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.223767447
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/5.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.78869752
Short name	T190
Test name
Test status
Simulation time	2096863984 ps
CPU time	31.66 seconds
Started	Sep 01 05:41:22 AM UTC 24
Finished	Sep 01 05:41:55 AM UTC 24
Peak memory	216756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78869752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.78869752
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/5.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random.388196881
Short name	T144
Test name
Test status
Simulation time	2332671754 ps
CPU time	43.13 seconds
Started	Sep 01 05:40:36 AM UTC 24
Finished	Sep 01 05:41:21 AM UTC 24
Peak memory	217152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388196881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.388196881
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/5.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.3069921640
Short name	T189
Test name
Test status
Simulation time	17047013739 ps
CPU time	58.3 seconds
Started	Sep 01 05:40:46 AM UTC 24
Finished	Sep 01 05:41:46 AM UTC 24
Peak memory	217156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069921640 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3069921640
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/5.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1120326604
Short name	T263
Test name
Test status
Simulation time	23143215448 ps
CPU time	204.79 seconds
Started	Sep 01 05:40:48 AM UTC 24
Finished	Sep 01 05:44:15 AM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120326604 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1120326604
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/5.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.3336347092
Short name	T94
Test name
Test status
Simulation time	231271659 ps
CPU time	24.91 seconds
Started	Sep 01 05:40:37 AM UTC 24
Finished	Sep 01 05:41:03 AM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336347092 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3336347092
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/5.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.2826179478
Short name	T265
Test name
Test status
Simulation time	166388569 ps
CPU time	17.08 seconds
Started	Sep 01 05:41:15 AM UTC 24
Finished	Sep 01 05:41:33 AM UTC 24
Peak memory	216960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826179478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2826179478
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/5.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.346479373
Short name	T90
Test name
Test status
Simulation time	165790727 ps
CPU time	3.42 seconds
Started	Sep 01 05:40:30 AM UTC 24
Finished	Sep 01 05:40:34 AM UTC 24
Peak memory	216752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346479373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.346479373
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/5.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.1596992720
Short name	T96
Test name
Test status
Simulation time	17077673222 ps
CPU time	39.37 seconds
Started	Sep 01 05:40:33 AM UTC 24
Finished	Sep 01 05:41:14 AM UTC 24
Peak memory	217204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596992720 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.1596992720
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/5.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.338243366
Short name	T192
Test name
Test status
Simulation time	11468871636 ps
CPU time	79.16 seconds
Started	Sep 01 05:40:35 AM UTC 24
Finished	Sep 01 05:41:56 AM UTC 24
Peak memory	216872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338243366 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.338243366
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/5.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.871865248
Short name	T91
Test name
Test status
Simulation time	31984453 ps
CPU time	3.1 seconds
Started	Sep 01 05:40:31 AM UTC 24
Finished	Sep 01 05:40:35 AM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871865248 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.871865248
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/5.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.1537588595
Short name	T185
Test name
Test status
Simulation time	1738630674 ps
CPU time	124.6 seconds
Started	Sep 01 05:41:34 AM UTC 24
Finished	Sep 01 05:43:41 AM UTC 24
Peak memory	220864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537588595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1537588595
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/5.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.4036553062
Short name	T307
Test name
Test status
Simulation time	7068984819 ps
CPU time	175.46 seconds
Started	Sep 01 05:41:39 AM UTC 24
Finished	Sep 01 05:44:37 AM UTC 24
Peak memory	219268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036553062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.4036553062
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/5.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.2270804882
Short name	T32
Test name
Test status
Simulation time	1139100563 ps
CPU time	206.79 seconds
Started	Sep 01 05:41:35 AM UTC 24
Finished	Sep 01 05:45:05 AM UTC 24
Peak memory	220936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270804882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.2270804882
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/5.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1582879633
Short name	T301
Test name
Test status
Simulation time	6310922163 ps
CPU time	222.21 seconds
Started	Sep 01 05:41:47 AM UTC 24
Finished	Sep 01 05:45:33 AM UTC 24
Peak memory	223160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582879633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.1582879633
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/5.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.50646103
Short name	T110
Test name
Test status
Simulation time	699919587 ps
CPU time	38.35 seconds
Started	Sep 01 05:41:30 AM UTC 24
Finished	Sep 01 05:42:10 AM UTC 24
Peak memory	218812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50646103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.50646103
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/5.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.3533048928
Short name	T5
Test name
Test status
Simulation time	759421078 ps
CPU time	38.97 seconds
Started	Sep 01 05:42:04 AM UTC 24
Finished	Sep 01 05:42:44 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533048928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.3533048928
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/6.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1848587820
Short name	T103
Test name
Test status
Simulation time	33295882008 ps
CPU time	231.17 seconds
Started	Sep 01 05:42:07 AM UTC 24
Finished	Sep 01 05:46:02 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848587820 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.1848587820
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/6.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3367648325
Short name	T115
Test name
Test status
Simulation time	651966127 ps
CPU time	15.82 seconds
Started	Sep 01 05:42:13 AM UTC 24
Finished	Sep 01 05:42:31 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367648325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3367648325
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/6.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.698256698
Short name	T324
Test name
Test status
Simulation time	1756600374 ps
CPU time	26.67 seconds
Started	Sep 01 05:42:11 AM UTC 24
Finished	Sep 01 05:42:39 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698256698 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.698256698
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/6.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random.2962716201
Short name	T81
Test name
Test status
Simulation time	5547793352 ps
CPU time	48.34 seconds
Started	Sep 01 05:41:57 AM UTC 24
Finished	Sep 01 05:42:47 AM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962716201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.2962716201
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/6.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.3726259698
Short name	T239
Test name
Test status
Simulation time	31999159133 ps
CPU time	121.34 seconds
Started	Sep 01 05:42:00 AM UTC 24
Finished	Sep 01 05:44:03 AM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726259698 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3726259698
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/6.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.4575437
Short name	T327
Test name
Test status
Simulation time	3969864078 ps
CPU time	46.47 seconds
Started	Sep 01 05:42:02 AM UTC 24
Finished	Sep 01 05:42:50 AM UTC 24
Peak memory	217156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4575437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.4575437
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/6.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.323087599
Short name	T112
Test name
Test status
Simulation time	69951509 ps
CPU time	14.49 seconds
Started	Sep 01 05:41:57 AM UTC 24
Finished	Sep 01 05:42:13 AM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323087599 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.323087599
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/6.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.2195390233
Short name	T114
Test name
Test status
Simulation time	179374026 ps
CPU time	10.16 seconds
Started	Sep 01 05:42:09 AM UTC 24
Finished	Sep 01 05:42:20 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195390233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2195390233
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/6.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.1123213835
Short name	T191
Test name
Test status
Simulation time	496412461 ps
CPU time	6.56 seconds
Started	Sep 01 05:41:48 AM UTC 24
Finished	Sep 01 05:41:55 AM UTC 24
Peak memory	217068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123213835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1123213835
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/6.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3732508060
Short name	T331
Test name
Test status
Simulation time	10631101271 ps
CPU time	66.65 seconds
Started	Sep 01 05:41:56 AM UTC 24
Finished	Sep 01 05:43:05 AM UTC 24
Peak memory	217076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732508060 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3732508060
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/6.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.1905299230
Short name	T329
Test name
Test status
Simulation time	4310701719 ps
CPU time	60.7 seconds
Started	Sep 01 05:41:56 AM UTC 24
Finished	Sep 01 05:42:59 AM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905299230 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1905299230
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/6.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2278572884
Short name	T194
Test name
Test status
Simulation time	34936683 ps
CPU time	3.57 seconds
Started	Sep 01 05:41:56 AM UTC 24
Finished	Sep 01 05:42:01 AM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278572884 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2278572884
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/6.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.434139198
Short name	T82
Test name
Test status
Simulation time	3438003645 ps
CPU time	59.21 seconds
Started	Sep 01 05:42:18 AM UTC 24
Finished	Sep 01 05:43:19 AM UTC 24
Peak memory	219204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434139198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.434139198
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/6.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.845413907
Short name	T302
Test name
Test status
Simulation time	11595429446 ps
CPU time	102.24 seconds
Started	Sep 01 05:42:29 AM UTC 24
Finished	Sep 01 05:44:13 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845413907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.845413907
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/6.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.2772600543
Short name	T326
Test name
Test status
Simulation time	97310683 ps
CPU time	22.66 seconds
Started	Sep 01 05:42:21 AM UTC 24
Finished	Sep 01 05:42:45 AM UTC 24
Peak memory	218888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772600543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.2772600543
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/6.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.3994781048
Short name	T317
Test name
Test status
Simulation time	7337539542 ps
CPU time	542.75 seconds
Started	Sep 01 05:42:30 AM UTC 24
Finished	Sep 01 05:51:41 AM UTC 24
Peak memory	235208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994781048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.3994781048
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/6.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.3827635985
Short name	T116
Test name
Test status
Simulation time	148026216 ps
CPU time	20.9 seconds
Started	Sep 01 05:42:11 AM UTC 24
Finished	Sep 01 05:42:34 AM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827635985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3827635985
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/6.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.872197689
Short name	T57
Test name
Test status
Simulation time	679000653 ps
CPU time	24.05 seconds
Started	Sep 01 05:42:45 AM UTC 24
Finished	Sep 01 05:43:11 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872197689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.872197689
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/7.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.3611567239
Short name	T333
Test name
Test status
Simulation time	362227585 ps
CPU time	14.76 seconds
Started	Sep 01 05:42:56 AM UTC 24
Finished	Sep 01 05:43:12 AM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611567239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3611567239
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/7.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.769431081
Short name	T330
Test name
Test status
Simulation time	156662013 ps
CPU time	7.89 seconds
Started	Sep 01 05:42:51 AM UTC 24
Finished	Sep 01 05:43:00 AM UTC 24
Peak memory	216760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769431081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.769431081
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/7.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random.2394464339
Short name	T328
Test name
Test status
Simulation time	113719472 ps
CPU time	13.47 seconds
Started	Sep 01 05:42:41 AM UTC 24
Finished	Sep 01 05:42:56 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394464339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.2394464339
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/7.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.629868626
Short name	T352
Test name
Test status
Simulation time	20930341178 ps
CPU time	162.74 seconds
Started	Sep 01 05:42:45 AM UTC 24
Finished	Sep 01 05:45:31 AM UTC 24
Peak memory	216892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629868626 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.629868626
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/7.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.584450253
Short name	T106
Test name
Test status
Simulation time	23903956024 ps
CPU time	330.87 seconds
Started	Sep 01 05:42:45 AM UTC 24
Finished	Sep 01 05:48:21 AM UTC 24
Peak memory	217188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584450253 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.584450253
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/7.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.4220939585
Short name	T247
Test name
Test status
Simulation time	478323313 ps
CPU time	39.48 seconds
Started	Sep 01 05:42:41 AM UTC 24
Finished	Sep 01 05:43:22 AM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220939585 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.4220939585
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/7.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.3328832107
Short name	T211
Test name
Test status
Simulation time	1128004740 ps
CPU time	10.08 seconds
Started	Sep 01 05:42:50 AM UTC 24
Finished	Sep 01 05:43:01 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328832107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3328832107
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/7.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.2186147292
Short name	T117
Test name
Test status
Simulation time	143989969 ps
CPU time	5.32 seconds
Started	Sep 01 05:42:31 AM UTC 24
Finished	Sep 01 05:42:38 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186147292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2186147292
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/7.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.1842904647
Short name	T335
Test name
Test status
Simulation time	34736653361 ps
CPU time	73.22 seconds
Started	Sep 01 05:42:39 AM UTC 24
Finished	Sep 01 05:43:54 AM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842904647 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.1842904647
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/7.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.454187423
Short name	T334
Test name
Test status
Simulation time	12562252749 ps
CPU time	36.88 seconds
Started	Sep 01 05:42:40 AM UTC 24
Finished	Sep 01 05:43:18 AM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454187423 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.454187423
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/7.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.166159069
Short name	T325
Test name
Test status
Simulation time	126148043 ps
CPU time	3.93 seconds
Started	Sep 01 05:42:35 AM UTC 24
Finished	Sep 01 05:42:40 AM UTC 24
Peak memory	216744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166159069 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.166159069
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/7.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.2331438393
Short name	T146
Test name
Test status
Simulation time	12451790584 ps
CPU time	216.7 seconds
Started	Sep 01 05:42:57 AM UTC 24
Finished	Sep 01 05:46:37 AM UTC 24
Peak memory	223040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331438393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2331438393
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/7.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2695946698
Short name	T306
Test name
Test status
Simulation time	11270643569 ps
CPU time	296.22 seconds
Started	Sep 01 05:43:00 AM UTC 24
Finished	Sep 01 05:48:01 AM UTC 24
Peak memory	218940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695946698 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2695946698
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/7.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.3559273543
Short name	T168
Test name
Test status
Simulation time	348757195 ps
CPU time	123.68 seconds
Started	Sep 01 05:42:59 AM UTC 24
Finished	Sep 01 05:45:05 AM UTC 24
Peak memory	220940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559273543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.3559273543
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/7.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3539022284
Short name	T276
Test name
Test status
Simulation time	142421052 ps
CPU time	49.33 seconds
Started	Sep 01 05:43:00 AM UTC 24
Finished	Sep 01 05:43:51 AM UTC 24
Peak memory	220932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539022284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.3539022284
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/7.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.2373494305
Short name	T163
Test name
Test status
Simulation time	72058110 ps
CPU time	5.66 seconds
Started	Sep 01 05:42:53 AM UTC 24
Finished	Sep 01 05:43:00 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373494305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2373494305
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/7.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.1797450999
Short name	T249
Test name
Test status
Simulation time	205361749 ps
CPU time	19.64 seconds
Started	Sep 01 05:43:20 AM UTC 24
Finished	Sep 01 05:43:40 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797450999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1797450999
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/8.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.2687236802
Short name	T521
Test name
Test status
Simulation time	60060630220 ps
CPU time	663.82 seconds
Started	Sep 01 05:43:23 AM UTC 24
Finished	Sep 01 05:54:35 AM UTC 24
Peak memory	220500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687236802 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.2687236802
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/8.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.2439055060
Short name	T338
Test name
Test status
Simulation time	772653438 ps
CPU time	35.48 seconds
Started	Sep 01 05:43:37 AM UTC 24
Finished	Sep 01 05:44:14 AM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439055060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.2439055060
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/8.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.3339586410
Short name	T275
Test name
Test status
Simulation time	1204065181 ps
CPU time	15.17 seconds
Started	Sep 01 05:43:32 AM UTC 24
Finished	Sep 01 05:43:48 AM UTC 24
Peak memory	216756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339586410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3339586410
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/8.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random.1964937953
Short name	T212
Test name
Test status
Simulation time	143169393 ps
CPU time	27.36 seconds
Started	Sep 01 05:43:12 AM UTC 24
Finished	Sep 01 05:43:41 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964937953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1964937953
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/8.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.1978974089
Short name	T381
Test name
Test status
Simulation time	91685052932 ps
CPU time	253.48 seconds
Started	Sep 01 05:43:17 AM UTC 24
Finished	Sep 01 05:47:35 AM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978974089 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1978974089
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/8.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.1411937064
Short name	T100
Test name
Test status
Simulation time	12295023191 ps
CPU time	103.18 seconds
Started	Sep 01 05:43:20 AM UTC 24
Finished	Sep 01 05:45:05 AM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411937064 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1411937064
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/8.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.352174280
Short name	T248
Test name
Test status
Simulation time	185685356 ps
CPU time	18.32 seconds
Started	Sep 01 05:43:13 AM UTC 24
Finished	Sep 01 05:43:33 AM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352174280 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.352174280
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/8.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.193394977
Short name	T271
Test name
Test status
Simulation time	6497935222 ps
CPU time	42.93 seconds
Started	Sep 01 05:43:23 AM UTC 24
Finished	Sep 01 05:44:07 AM UTC 24
Peak memory	217152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193394977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.193394977
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/8.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.1460850311
Short name	T56
Test name
Test status
Simulation time	124846182 ps
CPU time	5.32 seconds
Started	Sep 01 05:43:02 AM UTC 24
Finished	Sep 01 05:43:08 AM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460850311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1460850311
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/8.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.1575771630
Short name	T250
Test name
Test status
Simulation time	6630483645 ps
CPU time	35.83 seconds
Started	Sep 01 05:43:09 AM UTC 24
Finished	Sep 01 05:43:46 AM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575771630 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1575771630
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/8.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2995436371
Short name	T337
Test name
Test status
Simulation time	4755026788 ps
CPU time	59.04 seconds
Started	Sep 01 05:43:12 AM UTC 24
Finished	Sep 01 05:44:13 AM UTC 24
Peak memory	216944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995436371 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2995436371
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/8.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.4113881538
Short name	T332
Test name
Test status
Simulation time	36460669 ps
CPU time	3.86 seconds
Started	Sep 01 05:43:06 AM UTC 24
Finished	Sep 01 05:43:11 AM UTC 24
Peak memory	216744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113881538 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.4113881538
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/8.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.1862614733
Short name	T171
Test name
Test status
Simulation time	1258869593 ps
CPU time	91.01 seconds
Started	Sep 01 05:43:37 AM UTC 24
Finished	Sep 01 05:45:10 AM UTC 24
Peak memory	218816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862614733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1862614733
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/8.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.316636178
Short name	T251
Test name
Test status
Simulation time	219401667 ps
CPU time	4.81 seconds
Started	Sep 01 05:43:42 AM UTC 24
Finished	Sep 01 05:43:48 AM UTC 24
Peak memory	217076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316636178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.316636178
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/8.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.898703790
Short name	T40
Test name
Test status
Simulation time	367507326 ps
CPU time	134.63 seconds
Started	Sep 01 05:43:41 AM UTC 24
Finished	Sep 01 05:45:58 AM UTC 24
Peak memory	220920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898703790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.898703790
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/8.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2726770868
Short name	T312
Test name
Test status
Simulation time	4398953780 ps
CPU time	255.86 seconds
Started	Sep 01 05:43:42 AM UTC 24
Finished	Sep 01 05:48:02 AM UTC 24
Peak memory	223400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726770868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.2726770868
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/8.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.2469011392
Short name	T84
Test name
Test status
Simulation time	841487927 ps
CPU time	43.63 seconds
Started	Sep 01 05:43:33 AM UTC 24
Finished	Sep 01 05:44:18 AM UTC 24
Peak memory	218812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469011392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2469011392
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/8.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.2993276409
Short name	T99
Test name
Test status
Simulation time	905344894 ps
CPU time	37.42 seconds
Started	Sep 01 05:43:55 AM UTC 24
Finished	Sep 01 05:44:34 AM UTC 24
Peak memory	218824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993276409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.2993276409
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/9.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.1340557372
Short name	T305
Test name
Test status
Simulation time	524792873200 ps
CPU time	906.63 seconds
Started	Sep 01 05:44:03 AM UTC 24
Finished	Sep 01 05:59:20 AM UTC 24
Peak memory	222612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340557372 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.1340557372
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/9.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.354032242
Short name	T343
Test name
Test status
Simulation time	110078296 ps
CPU time	17.1 seconds
Started	Sep 01 05:44:11 AM UTC 24
Finished	Sep 01 05:44:29 AM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354032242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.354032242
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/9.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.3964551028
Short name	T344
Test name
Test status
Simulation time	586206902 ps
CPU time	27.33 seconds
Started	Sep 01 05:44:08 AM UTC 24
Finished	Sep 01 05:44:37 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964551028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3964551028
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/9.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random.2904889200
Short name	T273
Test name
Test status
Simulation time	1239425626 ps
CPU time	38.13 seconds
Started	Sep 01 05:43:51 AM UTC 24
Finished	Sep 01 05:44:31 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904889200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.2904889200
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/9.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.682090042
Short name	T378
Test name
Test status
Simulation time	31340561535 ps
CPU time	212.94 seconds
Started	Sep 01 05:43:53 AM UTC 24
Finished	Sep 01 05:47:29 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682090042 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.682090042
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/9.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.964908072
Short name	T145
Test name
Test status
Simulation time	12555138137 ps
CPU time	91.89 seconds
Started	Sep 01 05:43:54 AM UTC 24
Finished	Sep 01 05:45:28 AM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964908072 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.964908072
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/9.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.3744330203
Short name	T339
Test name
Test status
Simulation time	294286253 ps
CPU time	28.24 seconds
Started	Sep 01 05:43:53 AM UTC 24
Finished	Sep 01 05:44:22 AM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744330203 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.3744330203
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/9.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.3442369260
Short name	T341
Test name
Test status
Simulation time	169818277 ps
CPU time	16.6 seconds
Started	Sep 01 05:44:04 AM UTC 24
Finished	Sep 01 05:44:23 AM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442369260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3442369260
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/9.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.3904665439
Short name	T238
Test name
Test status
Simulation time	773106644 ps
CPU time	7.46 seconds
Started	Sep 01 05:43:42 AM UTC 24
Finished	Sep 01 05:43:51 AM UTC 24
Peak memory	216752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904665439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3904665439
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/9.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.2958141906
Short name	T58
Test name
Test status
Simulation time	13468270800 ps
CPU time	61.8 seconds
Started	Sep 01 05:43:48 AM UTC 24
Finished	Sep 01 05:44:52 AM UTC 24
Peak memory	217196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958141906 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2958141906
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/9.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.979003089
Short name	T350
Test name
Test status
Simulation time	11049206851 ps
CPU time	73.54 seconds
Started	Sep 01 05:43:49 AM UTC 24
Finished	Sep 01 05:45:05 AM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979003089 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.979003089
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/9.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.2243785518
Short name	T277
Test name
Test status
Simulation time	41135710 ps
CPU time	3.9 seconds
Started	Sep 01 05:43:47 AM UTC 24
Finished	Sep 01 05:43:52 AM UTC 24
Peak memory	216744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243785518 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2243785518
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/9.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.4129435728
Short name	T87
Test name
Test status
Simulation time	2667785229 ps
CPU time	97.15 seconds
Started	Sep 01 05:44:14 AM UTC 24
Finished	Sep 01 05:45:53 AM UTC 24
Peak memory	221124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129435728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.4129435728
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/9.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.560439301
Short name	T242
Test name
Test status
Simulation time	4882080984 ps
CPU time	131.95 seconds
Started	Sep 01 05:44:15 AM UTC 24
Finished	Sep 01 05:46:30 AM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560439301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.560439301
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/9.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.3163443225
Short name	T437
Test name
Test status
Simulation time	1651158782 ps
CPU time	341.76 seconds
Started	Sep 01 05:44:14 AM UTC 24
Finished	Sep 01 05:50:01 AM UTC 24
Peak memory	223416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163443225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.3163443225
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/9.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.1588601605
Short name	T316
Test name
Test status
Simulation time	247830739 ps
CPU time	85.47 seconds
Started	Sep 01 05:44:17 AM UTC 24
Finished	Sep 01 05:45:44 AM UTC 24
Peak memory	220932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588601605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.1588601605
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/9.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.1489482970
Short name	T85
Test name
Test status
Simulation time	688779306 ps
CPU time	18.26 seconds
Started	Sep 01 05:44:11 AM UTC 24
Finished	Sep 01 05:44:30 AM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489482970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1489482970
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/9.xbar_unmapped_addr/latest