Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1837	1			T13	1		T17	1		T79	4
all_values[1]	1872	1			T17	1		T79	3		T304	1
all_values[2]	1821	1			T13	1		T17	5		T79	4
all_values[3]	1754	1			T17	1		T79	9		T304	5
all_values[4]	1829	1			T17	2		T304	4		T149	2
all_values[5]	1841	1			T17	2		T79	2		T304	1
all_values[6]	1856	1			T13	1		T17	5		T79	2
all_values[7]	1788	1			T13	2		T17	6		T79	1
all_values[8]	1873	1			T17	2		T79	4		T243	1
all_values[9]	1736	1			T17	4		T79	3		T304	2
all_values[10]	1831	1			T13	1		T17	2		T79	4
all_values[11]	1900	1			T17	3		T79	3		T304	2
all_values[12]	1870	1			T13	1		T17	1		T79	1
all_values[13]	1851	1			T17	2		T79	1		T304	3
all_values[14]	1812	1			T17	4		T79	1		T243	1
all_values[15]	1859	1			T13	2		T17	2		T79	2
all_values[16]	1833	1			T13	1		T79	2		T304	3
all_values[17]	1785	1			T79	2		T304	1		T33	11
all_values[18]	1798	1			T13	1		T17	3		T79	5
all_values[19]	1837	1			T13	1		T17	1		T79	1
all_values[20]	1858	1			T17	2		T79	3		T304	2
all_values[21]	1806	1			T17	4		T79	1		T304	2
all_values[22]	1858	1			T79	3		T304	3		T149	2
all_values[23]	1812	1			T17	1		T79	1		T304	2
all_values[24]	1798	1			T13	1		T17	3		T79	5
all_values[25]	1815	1			T13	1		T17	2		T79	4
all_values[26]	1769	1			T13	1		T17	4		T79	6
all_values[27]	1791	1			T13	1		T17	1		T79	1
all_values[28]	1875	1			T17	2		T79	3		T304	2
all_values[29]	1818	1			T17	1		T79	2		T304	3
all_values[30]	1810	1			T13	1		T17	3		T79	2
all_values[31]	1891	1			T17	3		T79	4		T149	2
all_values[32]	1844	1			T17	2		T79	3		T149	3
all_values[33]	1861	1			T79	6		T304	2		T243	1
all_values[34]	1791	1			T17	2		T79	2		T304	2
all_values[35]	1869	1			T13	1		T17	2		T79	3
all_values[36]	1894	1			T17	2		T79	2		T304	2
all_values[37]	1826	1			T17	2		T79	2		T304	2
all_values[38]	1775	1			T17	1		T266	1		T33	10
all_values[39]	1841	1			T17	5		T79	3		T304	2
all_values[40]	1735	1			T17	2		T79	1		T304	4
all_values[41]	1748	1			T13	2		T17	3		T79	1
all_values[42]	1914	1			T17	2		T79	1		T243	1
all_values[43]	1819	1			T13	4		T17	1		T79	2
all_values[44]	1873	1			T17	3		T79	3		T304	1
all_values[45]	1812	1			T17	2		T79	3		T304	2
all_values[46]	1800	1			T17	3		T79	2		T304	3
all_values[47]	1817	1			T17	2		T79	1		T304	2
all_values[48]	1872	1			T17	4		T79	1		T304	2
all_values[49]	1863	1			T17	1		T79	1		T266	1
all_values[50]	1793	1			T13	2		T17	4		T79	3
all_values[51]	1764	1			T13	2		T17	3		T79	1
all_values[52]	1795	1			T17	1		T79	1		T304	1
all_values[53]	1860	1			T17	5		T79	1		T304	4
all_values[54]	1858	1			T13	1		T17	1		T79	2
all_values[55]	1765	1			T13	2		T17	2		T79	2
all_values[56]	1786	1			T13	2		T79	1		T304	1
all_values[57]	1881	1			T13	1		T17	1		T79	1
all_values[58]	1857	1			T17	3		T79	2		T304	4
all_values[59]	1783	1			T13	2		T79	6		T304	2
all_values[60]	1859	1			T13	3		T17	2		T304	4
all_values[61]	1802	1			T13	3		T17	3		T79	4
all_values[62]	1782	1			T13	1		T17	3		T79	4
all_values[63]	1813	1			T17	5		T79	1		T149	1