Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.03	99.26	88.97	98.80		95.88	99.26	100.00

Total test records in report: 900

T772	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.296531400	Sep 03 11:52:00 PM UTC 24	Sep 03 11:54:55 PM UTC 24	10636987836 ps
T773	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.739169039	Sep 03 11:48:45 PM UTC 24	Sep 03 11:54:55 PM UTC 24	740344419 ps
T774	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.2344841517	Sep 03 11:54:33 PM UTC 24	Sep 03 11:54:56 PM UTC 24	216490803 ps
T775	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.879844736	Sep 03 11:49:42 PM UTC 24	Sep 03 11:54:56 PM UTC 24	4708646489 ps
T776	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.3238518237	Sep 03 11:54:53 PM UTC 24	Sep 03 11:54:58 PM UTC 24	71585838 ps
T777	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2051536465	Sep 03 11:54:53 PM UTC 24	Sep 03 11:54:58 PM UTC 24	30654762 ps
T778	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.1208565954	Sep 03 11:54:45 PM UTC 24	Sep 03 11:55:00 PM UTC 24	782920049 ps
T779	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.2447500309	Sep 03 11:54:41 PM UTC 24	Sep 03 11:55:01 PM UTC 24	200669864 ps
T780	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.3429852406	Sep 03 11:54:57 PM UTC 24	Sep 03 11:55:03 PM UTC 24	89927609 ps
T781	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.4095745689	Sep 03 11:54:57 PM UTC 24	Sep 03 11:55:07 PM UTC 24	155686088 ps
T303	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3248696031	Sep 03 11:50:50 PM UTC 24	Sep 03 11:55:08 PM UTC 24	65512318899 ps
T782	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.1932612317	Sep 03 11:51:39 PM UTC 24	Sep 03 11:55:08 PM UTC 24	26479781634 ps
T52	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1934765697	Sep 03 11:53:05 PM UTC 24	Sep 03 11:55:12 PM UTC 24	216534009 ps
T783	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.2822794629	Sep 03 11:54:35 PM UTC 24	Sep 03 11:55:12 PM UTC 24	1857211411 ps
T784	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2185102564	Sep 03 11:55:09 PM UTC 24	Sep 03 11:55:15 PM UTC 24	47708658 ps
T785	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.1504927691	Sep 03 11:54:45 PM UTC 24	Sep 03 11:55:15 PM UTC 24	1708441587 ps
T786	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1814983754	Sep 03 11:54:59 PM UTC 24	Sep 03 11:55:15 PM UTC 24	891758048 ps
T289	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1828569351	Sep 03 11:51:31 PM UTC 24	Sep 03 11:55:15 PM UTC 24	3021420136 ps
T138	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.616674225	Sep 03 11:52:06 PM UTC 24	Sep 03 11:55:16 PM UTC 24	60678324503 ps
T787	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3118653094	Sep 03 11:54:31 PM UTC 24	Sep 03 11:55:16 PM UTC 24	6000572016 ps
T788	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.1665027382	Sep 03 11:51:53 PM UTC 24	Sep 03 11:55:18 PM UTC 24	3512118847 ps
T789	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.3205596584	Sep 03 11:55:17 PM UTC 24	Sep 03 11:55:21 PM UTC 24	167594756 ps
T790	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1339268272	Sep 03 11:55:17 PM UTC 24	Sep 03 11:55:21 PM UTC 24	45901040 ps
T346	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.2952704828	Sep 03 11:49:16 PM UTC 24	Sep 03 11:55:21 PM UTC 24	4617724976 ps
T791	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2497191681	Sep 03 11:54:48 PM UTC 24	Sep 03 11:55:21 PM UTC 24	1339289554 ps
T792	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.3543914605	Sep 03 11:55:03 PM UTC 24	Sep 03 11:55:22 PM UTC 24	2798933138 ps
T793	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2395480099	Sep 03 11:54:33 PM UTC 24	Sep 03 11:55:23 PM UTC 24	6501263505 ps
T794	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.3982445686	Sep 03 11:51:52 PM UTC 24	Sep 03 11:55:24 PM UTC 24	5983229315 ps
T795	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2340775423	Sep 03 11:54:24 PM UTC 24	Sep 03 11:55:25 PM UTC 24	2624567755 ps
T796	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3870404861	Sep 03 11:50:40 PM UTC 24	Sep 03 11:55:26 PM UTC 24	4882796082 ps
T797	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.628659873	Sep 03 11:52:09 PM UTC 24	Sep 03 11:55:29 PM UTC 24	22418275522 ps
T798	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1652452352	Sep 03 11:54:57 PM UTC 24	Sep 03 11:55:29 PM UTC 24	8564430858 ps
T799	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.664400316	Sep 03 11:53:58 PM UTC 24	Sep 03 11:55:31 PM UTC 24	95337232 ps
T800	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.638843019	Sep 03 11:54:59 PM UTC 24	Sep 03 11:55:32 PM UTC 24	690544489 ps
T801	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.3124612263	Sep 03 11:54:21 PM UTC 24	Sep 03 11:55:33 PM UTC 24	625756409 ps
T802	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.2416155852	Sep 03 11:55:25 PM UTC 24	Sep 03 11:55:36 PM UTC 24	201546307 ps
T803	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3861647302	Sep 03 11:55:17 PM UTC 24	Sep 03 11:55:37 PM UTC 24	19914371 ps
T804	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3503451672	Sep 03 11:54:07 PM UTC 24	Sep 03 11:55:37 PM UTC 24	2737320541 ps
T805	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1819442911	Sep 03 11:55:34 PM UTC 24	Sep 03 11:55:38 PM UTC 24	45264023 ps
T806	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.9120785	Sep 03 11:55:34 PM UTC 24	Sep 03 11:55:38 PM UTC 24	54039548 ps
T263	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3626017180	Sep 03 11:44:57 PM UTC 24	Sep 03 11:55:39 PM UTC 24	3024273523 ps
T807	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.608621134	Sep 03 11:55:05 PM UTC 24	Sep 03 11:55:43 PM UTC 24	1489992889 ps
T808	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.306107201	Sep 03 11:55:19 PM UTC 24	Sep 03 11:55:46 PM UTC 24	549865193 ps
T809	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.1105006744	Sep 03 11:55:26 PM UTC 24	Sep 03 11:55:48 PM UTC 24	547355226 ps
T78	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.4227375228	Sep 03 11:52:53 PM UTC 24	Sep 03 11:55:49 PM UTC 24	48754864899 ps
T810	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2286590114	Sep 03 11:55:17 PM UTC 24	Sep 03 11:55:50 PM UTC 24	6310370324 ps
T337	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.2565465093	Sep 03 11:52:42 PM UTC 24	Sep 03 11:55:51 PM UTC 24	668304923 ps
T811	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1571507845	Sep 03 11:55:28 PM UTC 24	Sep 03 11:55:52 PM UTC 24	277533378 ps
T812	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.4215483191	Sep 03 11:55:19 PM UTC 24	Sep 03 11:55:53 PM UTC 24	5714936078 ps
T813	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.614217757	Sep 03 11:55:40 PM UTC 24	Sep 03 11:55:53 PM UTC 24	570909562 ps
T814	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.199539288	Sep 03 11:55:19 PM UTC 24	Sep 03 11:55:55 PM UTC 24	993695468 ps
T815	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1898903002	Sep 03 11:55:49 PM UTC 24	Sep 03 11:55:55 PM UTC 24	41635851 ps
T816	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.549345286	Sep 03 11:55:42 PM UTC 24	Sep 03 11:55:56 PM UTC 24	305397408 ps
T817	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2176714768	Sep 03 11:55:58 PM UTC 24	Sep 03 11:56:01 PM UTC 24	43696433 ps
T818	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.440184864	Sep 03 11:54:57 PM UTC 24	Sep 03 11:56:02 PM UTC 24	32322544552 ps
T819	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2477193602	Sep 03 11:55:34 PM UTC 24	Sep 03 11:56:03 PM UTC 24	11924199143 ps
T820	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3981822058	Sep 03 11:55:37 PM UTC 24	Sep 03 11:56:03 PM UTC 24	7271430516 ps
T821	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.2805588889	Sep 03 11:55:25 PM UTC 24	Sep 03 11:56:04 PM UTC 24	1338087011 ps
T822	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.3521144111	Sep 03 11:55:58 PM UTC 24	Sep 03 11:56:04 PM UTC 24	464082967 ps
T823	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.343106605	Sep 03 11:51:16 PM UTC 24	Sep 03 11:56:06 PM UTC 24	35707882340 ps
T824	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3843298598	Sep 03 11:55:51 PM UTC 24	Sep 03 11:56:07 PM UTC 24	459367995 ps
T825	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.1967431201	Sep 03 11:55:51 PM UTC 24	Sep 03 11:56:09 PM UTC 24	434645419 ps
T175	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.4043084366	Sep 03 11:53:56 PM UTC 24	Sep 03 11:56:09 PM UTC 24	4442860565 ps
T235	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.436244997	Sep 03 11:53:32 PM UTC 24	Sep 03 11:56:11 PM UTC 24	4809297174 ps
T826	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.1188072987	Sep 03 11:54:48 PM UTC 24	Sep 03 11:56:12 PM UTC 24	952530633 ps
T827	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3357577760	Sep 03 11:54:27 PM UTC 24	Sep 03 11:56:13 PM UTC 24	359171196 ps
T828	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.175707941	Sep 03 11:56:07 PM UTC 24	Sep 03 11:56:14 PM UTC 24	166108266 ps
T829	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.242206515	Sep 03 11:55:40 PM UTC 24	Sep 03 11:56:15 PM UTC 24	1094912814 ps
T830	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.3430592178	Sep 03 11:55:47 PM UTC 24	Sep 03 11:56:16 PM UTC 24	1334391566 ps
T831	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.1408682358	Sep 03 11:56:11 PM UTC 24	Sep 03 11:56:19 PM UTC 24	53288492 ps
T832	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.1950784235	Sep 03 11:56:13 PM UTC 24	Sep 03 11:56:19 PM UTC 24	32583667 ps
T833	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.437954061	Sep 03 11:55:30 PM UTC 24	Sep 03 11:56:22 PM UTC 24	1143361002 ps
T834	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3928700537	Sep 03 11:54:15 PM UTC 24	Sep 03 11:56:22 PM UTC 24	27615514295 ps
T835	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.3328258637	Sep 03 11:56:18 PM UTC 24	Sep 03 11:56:23 PM UTC 24	98552834 ps
T836	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.567018303	Sep 03 11:53:34 PM UTC 24	Sep 03 11:56:25 PM UTC 24	409408322 ps
T837	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1410515241	Sep 03 11:56:21 PM UTC 24	Sep 03 11:56:26 PM UTC 24	29801602 ps
T838	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1324443590	Sep 03 11:54:15 PM UTC 24	Sep 03 11:56:26 PM UTC 24	18182794217 ps
T839	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.1558639087	Sep 03 11:56:11 PM UTC 24	Sep 03 11:56:32 PM UTC 24	193975820 ps
T840	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.2116660890	Sep 03 11:55:23 PM UTC 24	Sep 03 11:56:34 PM UTC 24	2059720917 ps
T841	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3473045851	Sep 03 11:56:02 PM UTC 24	Sep 03 11:56:34 PM UTC 24	3095039843 ps
T842	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.1238783622	Sep 03 11:56:07 PM UTC 24	Sep 03 11:56:34 PM UTC 24	228650113 ps
T843	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.3882740975	Sep 03 11:56:07 PM UTC 24	Sep 03 11:56:36 PM UTC 24	733030547 ps
T844	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.3175205945	Sep 03 11:54:57 PM UTC 24	Sep 03 11:56:36 PM UTC 24	12999859443 ps
T845	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.2023079036	Sep 03 11:56:25 PM UTC 24	Sep 03 11:56:39 PM UTC 24	93909328 ps
T846	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2766613536	Sep 03 11:55:55 PM UTC 24	Sep 03 11:56:39 PM UTC 24	1624635474 ps
T847	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.3008369230	Sep 03 11:56:25 PM UTC 24	Sep 03 11:56:41 PM UTC 24	114598490 ps
T848	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.3993747193	Sep 03 11:55:40 PM UTC 24	Sep 03 11:56:42 PM UTC 24	10157558247 ps
T849	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.4159618449	Sep 03 11:56:09 PM UTC 24	Sep 03 11:56:43 PM UTC 24	3848720644 ps
T850	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1218463332	Sep 03 11:56:22 PM UTC 24	Sep 03 11:56:49 PM UTC 24	4526982324 ps
T851	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2446402294	Sep 03 11:51:16 PM UTC 24	Sep 03 11:56:49 PM UTC 24	50906523219 ps
T852	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.1584880111	Sep 03 11:55:53 PM UTC 24	Sep 03 11:56:50 PM UTC 24	962459452 ps
T46	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.867352547	Sep 03 11:51:07 PM UTC 24	Sep 03 11:56:53 PM UTC 24	989063999 ps
T853	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.967709049	Sep 03 11:56:21 PM UTC 24	Sep 03 11:56:53 PM UTC 24	5943604503 ps
T854	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.4078976606	Sep 03 11:56:36 PM UTC 24	Sep 03 11:56:54 PM UTC 24	534305898 ps
T855	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2169550996	Sep 03 11:55:58 PM UTC 24	Sep 03 11:56:55 PM UTC 24	6333809730 ps
T856	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.223973341	Sep 03 11:56:28 PM UTC 24	Sep 03 11:56:56 PM UTC 24	631453168 ps
T358	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.1525351770	Sep 03 11:56:36 PM UTC 24	Sep 03 11:56:56 PM UTC 24	641350408 ps
T857	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1263201367	Sep 03 11:56:38 PM UTC 24	Sep 03 11:56:58 PM UTC 24	202289988 ps
T858	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.2792896250	Sep 03 11:56:36 PM UTC 24	Sep 03 11:57:07 PM UTC 24	1920353741 ps
T147	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.1328731673	Sep 03 11:53:43 PM UTC 24	Sep 03 11:57:08 PM UTC 24	47933320918 ps
T264	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.3537205894	Sep 03 11:56:15 PM UTC 24	Sep 03 11:57:12 PM UTC 24	393164970 ps
T859	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1496306164	Sep 03 11:53:23 PM UTC 24	Sep 03 11:57:13 PM UTC 24	26824417003 ps
T860	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2865870916	Sep 03 11:56:26 PM UTC 24	Sep 03 11:57:21 PM UTC 24	6464064157 ps
T861	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.1693120254	Sep 03 11:55:09 PM UTC 24	Sep 03 11:57:23 PM UTC 24	3928913397 ps
T862	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.3374454257	Sep 03 11:53:01 PM UTC 24	Sep 03 11:57:31 PM UTC 24	8409461227 ps
T863	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3264518514	Sep 03 11:54:35 PM UTC 24	Sep 03 11:57:37 PM UTC 24	18167614408 ps
T864	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.2888060943	Sep 03 11:51:07 PM UTC 24	Sep 03 11:57:47 PM UTC 24	9520686452 ps
T865	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.860010696	Sep 03 11:53:45 PM UTC 24	Sep 03 11:57:47 PM UTC 24	48504652574 ps
T866	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.214680285	Sep 03 11:56:40 PM UTC 24	Sep 03 11:57:53 PM UTC 24	3823491704 ps
T867	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1839196411	Sep 03 11:56:16 PM UTC 24	Sep 03 11:57:53 PM UTC 24	4107896533 ps
T868	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.156413370	Sep 03 11:55:28 PM UTC 24	Sep 03 11:57:54 PM UTC 24	7383365415 ps
T869	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2219066353	Sep 03 11:55:55 PM UTC 24	Sep 03 11:58:07 PM UTC 24	3902266507 ps
T870	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.941914988	Sep 03 11:56:15 PM UTC 24	Sep 03 11:58:12 PM UTC 24	1912151771 ps
T871	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.778113846	Sep 03 11:55:13 PM UTC 24	Sep 03 11:58:16 PM UTC 24	9444766976 ps
T872	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3630351479	Sep 03 11:53:20 PM UTC 24	Sep 03 11:58:19 PM UTC 24	61138002197 ps
T873	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1296773592	Sep 03 11:55:53 PM UTC 24	Sep 03 11:58:39 PM UTC 24	533928625 ps
T874	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1486323220	Sep 03 11:51:41 PM UTC 24	Sep 03 11:58:43 PM UTC 24	95435649713 ps
T47	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3842343838	Sep 03 11:55:32 PM UTC 24	Sep 03 11:58:45 PM UTC 24	21307965362 ps
T875	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2477828131	Sep 03 11:55:30 PM UTC 24	Sep 03 11:58:47 PM UTC 24	600914425 ps
T236	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.121318799	Sep 03 11:52:09 PM UTC 24	Sep 03 11:58:48 PM UTC 24	74798772469 ps
T255	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.1644582444	Sep 03 11:48:35 PM UTC 24	Sep 03 11:58:49 PM UTC 24	124294822760 ps
T876	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.236004359	Sep 03 11:56:38 PM UTC 24	Sep 03 11:59:02 PM UTC 24	3667527743 ps
T877	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.1293124492	Sep 03 11:54:15 PM UTC 24	Sep 03 11:59:03 PM UTC 24	174783805491 ps
T148	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1998827103	Sep 03 11:55:40 PM UTC 24	Sep 03 11:59:04 PM UTC 24	91459936415 ps
T878	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1138923313	Sep 03 11:55:25 PM UTC 24	Sep 03 11:59:08 PM UTC 24	116184171817 ps
T879	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3707022273	Sep 03 11:54:07 PM UTC 24	Sep 03 11:59:08 PM UTC 24	2339621927 ps
T880	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.1798038229	Sep 03 11:54:52 PM UTC 24	Sep 03 11:59:20 PM UTC 24	3724789865 ps
T881	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.687744604	Sep 03 11:55:23 PM UTC 24	Sep 03 11:59:23 PM UTC 24	27446616062 ps
T882	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.2660679377	Sep 03 11:56:07 PM UTC 24	Sep 03 11:59:36 PM UTC 24	50954567097 ps
T883	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.160260818	Sep 03 11:52:14 PM UTC 24	Sep 03 11:59:43 PM UTC 24	3707831283 ps
T884	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.4011250228	Sep 03 11:54:38 PM UTC 24	Sep 03 11:59:48 PM UTC 24	65899887655 ps
T885	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3153958158	Sep 03 11:52:45 PM UTC 24	Sep 03 11:59:58 PM UTC 24	4624486747 ps
T886	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2050129172	Sep 03 11:55:13 PM UTC 24	Sep 04 12:00:14 AM UTC 24	1074584404 ps
T887	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.3602406424	Sep 03 11:54:35 PM UTC 24	Sep 04 12:00:21 AM UTC 24	55796724558 ps
T888	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.1513233922	Sep 03 11:56:07 PM UTC 24	Sep 04 12:00:28 AM UTC 24	67305291300 ps
T889	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.1803449141	Sep 03 11:56:26 PM UTC 24	Sep 04 12:01:00 AM UTC 24	36672493260 ps
T890	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2995886999	Sep 03 11:54:22 PM UTC 24	Sep 04 12:01:02 AM UTC 24	11184933650 ps
T891	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.294707962	Sep 03 11:56:07 PM UTC 24	Sep 04 12:01:06 AM UTC 24	98239252394 ps
T56	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2318634406	Sep 03 11:53:37 PM UTC 24	Sep 04 12:01:17 AM UTC 24	11623015229 ps
T892	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3034609967	Sep 03 11:56:17 PM UTC 24	Sep 04 12:01:28 AM UTC 24	1914107516 ps
T893	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1444264498	Sep 03 11:56:40 PM UTC 24	Sep 04 12:01:53 AM UTC 24	3027977208 ps
T894	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1706746424	Sep 03 11:52:59 PM UTC 24	Sep 04 12:01:55 AM UTC 24	155215503279 ps
T895	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.406492279	Sep 03 11:55:23 PM UTC 24	Sep 04 12:02:40 AM UTC 24	196200455504 ps
T48	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.2876664042	Sep 03 11:56:43 PM UTC 24	Sep 04 12:02:54 AM UTC 24	1900960363 ps
T896	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3259136125	Sep 03 11:54:48 PM UTC 24	Sep 04 12:03:16 AM UTC 24	11657661800 ps
T897	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3824053519	Sep 03 11:50:00 PM UTC 24	Sep 04 12:04:03 AM UTC 24	93965061573 ps
T299	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2846582247	Sep 03 11:48:13 PM UTC 24	Sep 04 12:04:06 AM UTC 24	417633159109 ps
T898	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.788758633	Sep 03 11:55:45 PM UTC 24	Sep 04 12:05:35 AM UTC 24	176220702311 ps
T899	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.638334844	Sep 03 11:56:34 PM UTC 24	Sep 04 12:07:49 AM UTC 24	66481437226 ps
T900	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1383969222	Sep 03 11:55:02 PM UTC 24	Sep 04 12:10:36 AM UTC 24	79408686965 ps

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random.1165047628
Short name	T9
Test name
Test status
Simulation time	589328263 ps
CPU time	12.18 seconds
Started	Sep 03 11:37:48 PM UTC 24
Finished	Sep 03 11:38:02 PM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165047628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.1165047628
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/0.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.3575969968
Short name	T117
Test name
Test status
Simulation time	119488711842 ps
CPU time	592.52 seconds
Started	Sep 03 11:38:19 PM UTC 24
Finished	Sep 03 11:48:18 PM UTC 24
Peak memory	220560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575969968 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.3575969968
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/3.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.1911330916
Short name	T90
Test name
Test status
Simulation time	11788376056 ps
CPU time	66.89 seconds
Started	Sep 03 11:38:30 PM UTC 24
Finished	Sep 03 11:39:38 PM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911330916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.1911330916
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/4.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.988398478
Short name	T347
Test name
Test status
Simulation time	29183482031 ps
CPU time	240.01 seconds
Started	Sep 03 11:39:49 PM UTC 24
Finished	Sep 03 11:43:53 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988398478 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.988398478
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/8.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.323017974
Short name	T4
Test name
Test status
Simulation time	97688521 ps
CPU time	11.73 seconds
Started	Sep 03 11:37:49 PM UTC 24
Finished	Sep 03 11:38:02 PM UTC 24
Peak memory	217152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323017974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.323017974
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/0.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.3520983463
Short name	T39
Test name
Test status
Simulation time	4418153850 ps
CPU time	44.72 seconds
Started	Sep 03 11:38:02 PM UTC 24
Finished	Sep 03 11:38:48 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520983463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.3520983463
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/2.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2662271896
Short name	T301
Test name
Test status
Simulation time	59189240081 ps
CPU time	498.43 seconds
Started	Sep 03 11:40:29 PM UTC 24
Finished	Sep 03 11:48:54 PM UTC 24
Peak memory	221376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662271896 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.2662271896
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/10.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.2741707219
Short name	T481
Test name
Test status
Simulation time	2476167176 ps
CPU time	382.55 seconds
Started	Sep 03 11:38:59 PM UTC 24
Finished	Sep 03 11:45:27 PM UTC 24
Peak memory	233660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741707219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.2741707219
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/5.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.975783109
Short name	T33
Test name
Test status
Simulation time	166768223 ps
CPU time	60.46 seconds
Started	Sep 03 11:38:10 PM UTC 24
Finished	Sep 03 11:39:12 PM UTC 24
Peak memory	220872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975783109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.975783109
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/2.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.766133511
Short name	T24
Test name
Test status
Simulation time	4699137146 ps
CPU time	30.26 seconds
Started	Sep 03 11:38:43 PM UTC 24
Finished	Sep 03 11:39:14 PM UTC 24
Peak memory	216872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766133511 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.766133511
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/5.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.2063633291
Short name	T45
Test name
Test status
Simulation time	895921108 ps
CPU time	218.34 seconds
Started	Sep 03 11:39:01 PM UTC 24
Finished	Sep 03 11:42:43 PM UTC 24
Peak memory	223356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063633291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.2063633291
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/5.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.1424085559
Short name	T109
Test name
Test status
Simulation time	4162968225 ps
CPU time	140.52 seconds
Started	Sep 03 11:42:29 PM UTC 24
Finished	Sep 03 11:44:52 PM UTC 24
Peak memory	221124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424085559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1424085559
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/15.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.3507021621
Short name	T60
Test name
Test status
Simulation time	8592559427 ps
CPU time	61 seconds
Started	Sep 03 11:37:49 PM UTC 24
Finished	Sep 03 11:38:52 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507021621 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3507021621
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/0.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.4287793361
Short name	T106
Test name
Test status
Simulation time	66799023795 ps
CPU time	214.63 seconds
Started	Sep 03 11:38:02 PM UTC 24
Finished	Sep 03 11:41:40 PM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287793361 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.4287793361
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/2.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.320922993
Short name	T26
Test name
Test status
Simulation time	847588851 ps
CPU time	26.36 seconds
Started	Sep 03 11:37:49 PM UTC 24
Finished	Sep 03 11:38:18 PM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320922993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.320922993
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/0.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.2282559860
Short name	T8
Test name
Test status
Simulation time	234469654 ps
CPU time	10.54 seconds
Started	Sep 03 11:37:49 PM UTC 24
Finished	Sep 03 11:38:01 PM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282559860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2282559860
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/0.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.3230461190
Short name	T116
Test name
Test status
Simulation time	1925228928 ps
CPU time	73.43 seconds
Started	Sep 03 11:46:26 PM UTC 24
Finished	Sep 03 11:47:42 PM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230461190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3230461190
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/25.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1625691269
Short name	T102
Test name
Test status
Simulation time	898312269 ps
CPU time	311.49 seconds
Started	Sep 03 11:37:50 PM UTC 24
Finished	Sep 03 11:43:06 PM UTC 24
Peak memory	224524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625691269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.1625691269
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/0.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.2795236073
Short name	T150
Test name
Test status
Simulation time	1257706413 ps
CPU time	37.65 seconds
Started	Sep 03 11:40:08 PM UTC 24
Finished	Sep 03 11:40:47 PM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795236073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.2795236073
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/9.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.44372099
Short name	T49
Test name
Test status
Simulation time	10029331372 ps
CPU time	154.59 seconds
Started	Sep 03 11:50:10 PM UTC 24
Finished	Sep 03 11:52:47 PM UTC 24
Peak memory	220988 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44372099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-si m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.44372099
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/33.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.332401883
Short name	T274
Test name
Test status
Simulation time	346007673 ps
CPU time	86.41 seconds
Started	Sep 03 11:38:39 PM UTC 24
Finished	Sep 03 11:40:08 PM UTC 24
Peak memory	220936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332401883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.332401883
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/4.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.710932536
Short name	T61
Test name
Test status
Simulation time	28422433134 ps
CPU time	130.44 seconds
Started	Sep 03 11:37:49 PM UTC 24
Finished	Sep 03 11:40:02 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710932536 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.710932536
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/0.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.1731030174
Short name	T136
Test name
Test status
Simulation time	124417844793 ps
CPU time	620.22 seconds
Started	Sep 03 11:43:58 PM UTC 24
Finished	Sep 03 11:54:26 PM UTC 24
Peak memory	222872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731030174 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.1731030174
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/19.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2318634406
Short name	T56
Test name
Test status
Simulation time	11623015229 ps
CPU time	453.84 seconds
Started	Sep 03 11:53:37 PM UTC 24
Finished	Sep 04 12:01:17 AM UTC 24
Peak memory	234040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318634406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.2318634406
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/41.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.3272273259
Short name	T36
Test name
Test status
Simulation time	2382205412 ps
CPU time	347.4 seconds
Started	Sep 03 11:38:38 PM UTC 24
Finished	Sep 03 11:44:30 PM UTC 24
Peak memory	233660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272273259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.3272273259
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/4.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3299173321
Short name	T307
Test name
Test status
Simulation time	8038037297 ps
CPU time	215.17 seconds
Started	Sep 03 11:42:56 PM UTC 24
Finished	Sep 03 11:46:35 PM UTC 24
Peak memory	221196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299173321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.3299173321
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/16.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.1940101916
Short name	T34
Test name
Test status
Simulation time	165485754 ps
CPU time	92.58 seconds
Started	Sep 03 11:44:09 PM UTC 24
Finished	Sep 03 11:45:44 PM UTC 24
Peak memory	220872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940101916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.1940101916
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/19.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.867352547
Short name	T46
Test name
Test status
Simulation time	989063999 ps
CPU time	340.33 seconds
Started	Sep 03 11:51:07 PM UTC 24
Finished	Sep 03 11:56:53 PM UTC 24
Peak memory	233524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867352547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.867352547
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/35.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1934765697
Short name	T52
Test name
Test status
Simulation time	216534009 ps
CPU time	124.48 seconds
Started	Sep 03 11:53:05 PM UTC 24
Finished	Sep 03 11:55:12 PM UTC 24
Peak memory	222980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934765697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.1934765697
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/40.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.2458987438
Short name	T79
Test name
Test status
Simulation time	2446739997 ps
CPU time	29.15 seconds
Started	Sep 03 11:37:49 PM UTC 24
Finished	Sep 03 11:38:20 PM UTC 24
Peak memory	216892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458987438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2458987438
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/0.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.1401921596
Short name	T231
Test name
Test status
Simulation time	3326922053 ps
CPU time	442.15 seconds
Started	Sep 03 11:37:52 PM UTC 24
Finished	Sep 03 11:45:19 PM UTC 24
Peak memory	224664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401921596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.1401921596
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/1.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.4166356994
Short name	T32
Test name
Test status
Simulation time	3143296109 ps
CPU time	27.58 seconds
Started	Sep 03 11:37:49 PM UTC 24
Finished	Sep 03 11:38:18 PM UTC 24
Peak memory	217160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166356994 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.4166356994
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/0.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.3394970992
Short name	T15
Test name
Test status
Simulation time	263187981 ps
CPU time	14.61 seconds
Started	Sep 03 11:37:49 PM UTC 24
Finished	Sep 03 11:38:05 PM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394970992 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3394970992
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/0.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.2953243201
Short name	T2
Test name
Test status
Simulation time	34126491 ps
CPU time	2.15 seconds
Started	Sep 03 11:37:48 PM UTC 24
Finished	Sep 03 11:37:51 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953243201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2953243201
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/0.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.886382047
Short name	T247
Test name
Test status
Simulation time	16052811352 ps
CPU time	40.71 seconds
Started	Sep 03 11:37:48 PM UTC 24
Finished	Sep 03 11:38:30 PM UTC 24
Peak memory	216884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886382047 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.886382047
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/0.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.3729205880
Short name	T25
Test name
Test status
Simulation time	4134818771 ps
CPU time	25.29 seconds
Started	Sep 03 11:37:48 PM UTC 24
Finished	Sep 03 11:38:15 PM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729205880 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3729205880
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/0.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.864732735
Short name	T1
Test name
Test status
Simulation time	95512776 ps
CPU time	2.19 seconds
Started	Sep 03 11:37:48 PM UTC 24
Finished	Sep 03 11:37:51 PM UTC 24
Peak memory	216872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864732735 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.864732735
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/0.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.666912884
Short name	T51
Test name
Test status
Simulation time	4407994082 ps
CPU time	121.62 seconds
Started	Sep 03 11:37:50 PM UTC 24
Finished	Sep 03 11:39:54 PM UTC 24
Peak memory	220484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666912884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.666912884
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/0.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1734356329
Short name	T58
Test name
Test status
Simulation time	3519050562 ps
CPU time	82.48 seconds
Started	Sep 03 11:37:50 PM UTC 24
Finished	Sep 03 11:39:14 PM UTC 24
Peak memory	218672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734356329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1734356329
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/0.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.615640830
Short name	T38
Test name
Test status
Simulation time	536222700 ps
CPU time	175.6 seconds
Started	Sep 03 11:37:50 PM UTC 24
Finished	Sep 03 11:40:48 PM UTC 24
Peak memory	223308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615640830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.615640830
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/0.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.3514586146
Short name	T16
Test name
Test status
Simulation time	151158900 ps
CPU time	15.29 seconds
Started	Sep 03 11:37:49 PM UTC 24
Finished	Sep 03 11:38:06 PM UTC 24
Peak memory	216284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514586146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3514586146
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/0.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.517308826
Short name	T19
Test name
Test status
Simulation time	440746811 ps
CPU time	17.16 seconds
Started	Sep 03 11:37:51 PM UTC 24
Finished	Sep 03 11:38:10 PM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517308826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.517308826
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/1.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1384824798
Short name	T105
Test name
Test status
Simulation time	17188309981 ps
CPU time	188.79 seconds
Started	Sep 03 11:37:51 PM UTC 24
Finished	Sep 03 11:41:03 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384824798 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.1384824798
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/1.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.3146809190
Short name	T27
Test name
Test status
Simulation time	2133237995 ps
CPU time	25.48 seconds
Started	Sep 03 11:37:52 PM UTC 24
Finished	Sep 03 11:38:19 PM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146809190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.3146809190
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/1.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.2365917627
Short name	T20
Test name
Test status
Simulation time	612199317 ps
CPU time	17.17 seconds
Started	Sep 03 11:37:52 PM UTC 24
Finished	Sep 03 11:38:10 PM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365917627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2365917627
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/1.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random.2238921140
Short name	T21
Test name
Test status
Simulation time	112198614 ps
CPU time	19.63 seconds
Started	Sep 03 11:37:51 PM UTC 24
Finished	Sep 03 11:38:12 PM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238921140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.2238921140
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/1.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.1674465726
Short name	T103
Test name
Test status
Simulation time	13106274679 ps
CPU time	104.67 seconds
Started	Sep 03 11:37:51 PM UTC 24
Finished	Sep 03 11:39:38 PM UTC 24
Peak memory	217156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674465726 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.1674465726
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/1.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3975470759
Short name	T131
Test name
Test status
Simulation time	24855122160 ps
CPU time	131.46 seconds
Started	Sep 03 11:37:51 PM UTC 24
Finished	Sep 03 11:40:05 PM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975470759 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3975470759
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/1.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.749009054
Short name	T80
Test name
Test status
Simulation time	215062748 ps
CPU time	28.34 seconds
Started	Sep 03 11:37:51 PM UTC 24
Finished	Sep 03 11:38:21 PM UTC 24
Peak memory	218812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749009054 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.749009054
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/1.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.3920354612
Short name	T17
Test name
Test status
Simulation time	320882902 ps
CPU time	14.55 seconds
Started	Sep 03 11:37:51 PM UTC 24
Finished	Sep 03 11:38:07 PM UTC 24
Peak memory	217152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920354612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3920354612
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/1.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.3561833545
Short name	T11
Test name
Test status
Simulation time	43720710 ps
CPU time	2.47 seconds
Started	Sep 03 11:37:50 PM UTC 24
Finished	Sep 03 11:37:53 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561833545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3561833545
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/1.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3085397829
Short name	T30
Test name
Test status
Simulation time	4840600214 ps
CPU time	31.03 seconds
Started	Sep 03 11:37:50 PM UTC 24
Finished	Sep 03 11:38:22 PM UTC 24
Peak memory	217140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085397829 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3085397829
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/1.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.3954636575
Short name	T248
Test name
Test status
Simulation time	18527350820 ps
CPU time	44.91 seconds
Started	Sep 03 11:37:51 PM UTC 24
Finished	Sep 03 11:38:38 PM UTC 24
Peak memory	216520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954636575 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3954636575
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/1.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.2371372223
Short name	T10
Test name
Test status
Simulation time	99587659 ps
CPU time	2.21 seconds
Started	Sep 03 11:37:50 PM UTC 24
Finished	Sep 03 11:37:53 PM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371372223 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.2371372223
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/1.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.267670177
Short name	T13
Test name
Test status
Simulation time	509338797 ps
CPU time	8.96 seconds
Started	Sep 03 11:37:52 PM UTC 24
Finished	Sep 03 11:38:02 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267670177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.267670177
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/1.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.3925155871
Short name	T370
Test name
Test status
Simulation time	1047546318 ps
CPU time	90.74 seconds
Started	Sep 03 11:37:52 PM UTC 24
Finished	Sep 03 11:39:25 PM UTC 24
Peak memory	220932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925155871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.3925155871
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/1.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.1363164780
Short name	T368
Test name
Test status
Simulation time	12478091990 ps
CPU time	484.09 seconds
Started	Sep 03 11:37:53 PM UTC 24
Finished	Sep 03 11:46:03 PM UTC 24
Peak memory	235272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363164780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.1363164780
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/1.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.828942472
Short name	T23
Test name
Test status
Simulation time	218153884 ps
CPU time	24.57 seconds
Started	Sep 03 11:37:52 PM UTC 24
Finished	Sep 03 11:38:17 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828942472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.828942472
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/1.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.279553691
Short name	T93
Test name
Test status
Simulation time	258757622 ps
CPU time	14.22 seconds
Started	Sep 03 11:40:26 PM UTC 24
Finished	Sep 03 11:40:42 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279553691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.279553691
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/10.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.1606734107
Short name	T360
Test name
Test status
Simulation time	71659711 ps
CPU time	6.73 seconds
Started	Sep 03 11:40:37 PM UTC 24
Finished	Sep 03 11:40:45 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606734107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.1606734107
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/10.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.70240996
Short name	T311
Test name
Test status
Simulation time	64507112 ps
CPU time	3.79 seconds
Started	Sep 03 11:40:32 PM UTC 24
Finished	Sep 03 11:40:37 PM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70240996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.70240996
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/10.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random.1151618379
Short name	T213
Test name
Test status
Simulation time	148937931 ps
CPU time	12.52 seconds
Started	Sep 03 11:40:25 PM UTC 24
Finished	Sep 03 11:40:39 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151618379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.1151618379
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/10.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.3422543088
Short name	T407
Test name
Test status
Simulation time	15887197407 ps
CPU time	85.47 seconds
Started	Sep 03 11:40:26 PM UTC 24
Finished	Sep 03 11:41:53 PM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422543088 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3422543088
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/10.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3856841026
Short name	T419
Test name
Test status
Simulation time	8541871635 ps
CPU time	97.01 seconds
Started	Sep 03 11:40:26 PM UTC 24
Finished	Sep 03 11:42:05 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856841026 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3856841026
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/10.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.91153810
Short name	T362
Test name
Test status
Simulation time	172427325 ps
CPU time	25.66 seconds
Started	Sep 03 11:40:26 PM UTC 24
Finished	Sep 03 11:40:53 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91153810 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.91153810
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/10.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.1801593368
Short name	T212
Test name
Test status
Simulation time	69730561 ps
CPU time	6.01 seconds
Started	Sep 03 11:40:30 PM UTC 24
Finished	Sep 03 11:40:37 PM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801593368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1801593368
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/10.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.1274607601
Short name	T400
Test name
Test status
Simulation time	55343763 ps
CPU time	3.53 seconds
Started	Sep 03 11:40:19 PM UTC 24
Finished	Sep 03 11:40:25 PM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274607601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1274607601
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/10.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.2180164095
Short name	T209
Test name
Test status
Simulation time	16463079670 ps
CPU time	53.89 seconds
Started	Sep 03 11:40:20 PM UTC 24
Finished	Sep 03 11:41:15 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180164095 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2180164095
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/10.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3511557987
Short name	T363
Test name
Test status
Simulation time	8220843023 ps
CPU time	31.51 seconds
Started	Sep 03 11:40:25 PM UTC 24
Finished	Sep 03 11:40:58 PM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511557987 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3511557987
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/10.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.455840116
Short name	T398
Test name
Test status
Simulation time	34880096 ps
CPU time	2.99 seconds
Started	Sep 03 11:40:20 PM UTC 24
Finished	Sep 03 11:40:23 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455840116 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.455840116
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/10.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.3346430807
Short name	T96
Test name
Test status
Simulation time	941525882 ps
CPU time	41.63 seconds
Started	Sep 03 11:40:38 PM UTC 24
Finished	Sep 03 11:41:21 PM UTC 24
Peak memory	218876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346430807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3346430807
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/10.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.2747141737
Short name	T378
Test name
Test status
Simulation time	4057826414 ps
CPU time	81.49 seconds
Started	Sep 03 11:40:38 PM UTC 24
Finished	Sep 03 11:42:01 PM UTC 24
Peak memory	219204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747141737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2747141737
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/10.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1730976956
Short name	T462
Test name
Test status
Simulation time	1993095854 ps
CPU time	232.32 seconds
Started	Sep 03 11:40:38 PM UTC 24
Finished	Sep 03 11:44:34 PM UTC 24
Peak memory	222984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730976956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.1730976956
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/10.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.236792440
Short name	T174
Test name
Test status
Simulation time	3117001351 ps
CPU time	367.85 seconds
Started	Sep 03 11:40:38 PM UTC 24
Finished	Sep 03 11:46:51 PM UTC 24
Peak memory	233908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236792440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.236792440
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/10.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.2662222945
Short name	T401
Test name
Test status
Simulation time	17345835 ps
CPU time	2.6 seconds
Started	Sep 03 11:40:36 PM UTC 24
Finished	Sep 03 11:40:40 PM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662222945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2662222945
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/10.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.535592672
Short name	T97
Test name
Test status
Simulation time	1487516759 ps
CPU time	44.58 seconds
Started	Sep 03 11:40:45 PM UTC 24
Finished	Sep 03 11:41:31 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535592672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.535592672
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/11.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.88447048
Short name	T382
Test name
Test status
Simulation time	45848890480 ps
CPU time	500.87 seconds
Started	Sep 03 11:40:47 PM UTC 24
Finished	Sep 03 11:49:14 PM UTC 24
Peak memory	219324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88447048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.88447048
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/11.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.3249579899
Short name	T226
Test name
Test status
Simulation time	517141953 ps
CPU time	24.94 seconds
Started	Sep 03 11:40:58 PM UTC 24
Finished	Sep 03 11:41:25 PM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249579899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.3249579899
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/11.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.1071796472
Short name	T208
Test name
Test status
Simulation time	2151870846 ps
CPU time	21.3 seconds
Started	Sep 03 11:40:50 PM UTC 24
Finished	Sep 03 11:41:12 PM UTC 24
Peak memory	216884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071796472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1071796472
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/11.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random.442439784
Short name	T204
Test name
Test status
Simulation time	429471032 ps
CPU time	24.78 seconds
Started	Sep 03 11:40:43 PM UTC 24
Finished	Sep 03 11:41:09 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442439784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.442439784
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/11.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.3473337065
Short name	T71
Test name
Test status
Simulation time	192524249719 ps
CPU time	354.06 seconds
Started	Sep 03 11:40:44 PM UTC 24
Finished	Sep 03 11:46:43 PM UTC 24
Peak memory	217220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473337065 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3473337065
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/11.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.821115974
Short name	T406
Test name
Test status
Simulation time	14630144848 ps
CPU time	65.94 seconds
Started	Sep 03 11:40:45 PM UTC 24
Finished	Sep 03 11:41:53 PM UTC 24
Peak memory	217156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821115974 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.821115974
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/11.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.3354287094
Short name	T205
Test name
Test status
Simulation time	211567035 ps
CPU time	24.88 seconds
Started	Sep 03 11:40:43 PM UTC 24
Finished	Sep 03 11:41:09 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354287094 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.3354287094
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/11.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.2030250796
Short name	T403
Test name
Test status
Simulation time	208456408 ps
CPU time	10.33 seconds
Started	Sep 03 11:40:50 PM UTC 24
Finished	Sep 03 11:41:01 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030250796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2030250796
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/11.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.178785800
Short name	T259
Test name
Test status
Simulation time	137465917 ps
CPU time	4.99 seconds
Started	Sep 03 11:40:38 PM UTC 24
Finished	Sep 03 11:40:44 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178785800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.178785800
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/11.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.2759335983
Short name	T158
Test name
Test status
Simulation time	30658117185 ps
CPU time	63.29 seconds
Started	Sep 03 11:40:39 PM UTC 24
Finished	Sep 03 11:41:45 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759335983 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2759335983
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/11.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.2267947880
Short name	T214
Test name
Test status
Simulation time	4734775958 ps
CPU time	56.49 seconds
Started	Sep 03 11:40:41 PM UTC 24
Finished	Sep 03 11:41:39 PM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267947880 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.2267947880
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/11.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.4203568618
Short name	T359
Test name
Test status
Simulation time	26511974 ps
CPU time	2.92 seconds
Started	Sep 03 11:40:39 PM UTC 24
Finished	Sep 03 11:40:43 PM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203568618 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.4203568618
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/11.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.1577465200
Short name	T405
Test name
Test status
Simulation time	1742766769 ps
CPU time	49.42 seconds
Started	Sep 03 11:40:59 PM UTC 24
Finished	Sep 03 11:41:51 PM UTC 24
Peak memory	218880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577465200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1577465200
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/11.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.4200782978
Short name	T315
Test name
Test status
Simulation time	4863807812 ps
CPU time	121.55 seconds
Started	Sep 03 11:41:03 PM UTC 24
Finished	Sep 03 11:43:07 PM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200782978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.4200782978
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/11.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.2695665231
Short name	T41
Test name
Test status
Simulation time	178192099 ps
CPU time	49.44 seconds
Started	Sep 03 11:41:02 PM UTC 24
Finished	Sep 03 11:41:54 PM UTC 24
Peak memory	218820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695665231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.2695665231
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/11.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1506082714
Short name	T376
Test name
Test status
Simulation time	13233568733 ps
CPU time	286.01 seconds
Started	Sep 03 11:41:03 PM UTC 24
Finished	Sep 03 11:45:53 PM UTC 24
Peak memory	221000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506082714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.1506082714
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/11.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.1645073075
Short name	T300
Test name
Test status
Simulation time	57475008 ps
CPU time	3.22 seconds
Started	Sep 03 11:40:54 PM UTC 24
Finished	Sep 03 11:40:58 PM UTC 24
Peak memory	216760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645073075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1645073075
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/11.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.3202633378
Short name	T404
Test name
Test status
Simulation time	388830148 ps
CPU time	35.39 seconds
Started	Sep 03 11:41:14 PM UTC 24
Finished	Sep 03 11:41:51 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202633378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.3202633378
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/12.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2989168890
Short name	T239
Test name
Test status
Simulation time	28175160088 ps
CPU time	207.9 seconds
Started	Sep 03 11:41:16 PM UTC 24
Finished	Sep 03 11:44:47 PM UTC 24
Peak memory	218944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989168890 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.2989168890
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/12.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.1072956833
Short name	T157
Test name
Test status
Simulation time	762817688 ps
CPU time	14.41 seconds
Started	Sep 03 11:41:29 PM UTC 24
Finished	Sep 03 11:41:44 PM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072956833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.1072956833
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/12.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.318663141
Short name	T413
Test name
Test status
Simulation time	2014564140 ps
CPU time	34.04 seconds
Started	Sep 03 11:41:22 PM UTC 24
Finished	Sep 03 11:41:58 PM UTC 24
Peak memory	216964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318663141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.318663141
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/12.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random.1509621590
Short name	T161
Test name
Test status
Simulation time	1811346869 ps
CPU time	36.56 seconds
Started	Sep 03 11:41:10 PM UTC 24
Finished	Sep 03 11:41:48 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509621590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.1509621590
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/12.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.3129243747
Short name	T477
Test name
Test status
Simulation time	53221562089 ps
CPU time	244.34 seconds
Started	Sep 03 11:41:13 PM UTC 24
Finished	Sep 03 11:45:21 PM UTC 24
Peak memory	218896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129243747 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3129243747
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/12.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.1775056106
Short name	T155
Test name
Test status
Simulation time	4784660563 ps
CPU time	27.69 seconds
Started	Sep 03 11:41:13 PM UTC 24
Finished	Sep 03 11:41:42 PM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775056106 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.1775056106
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/12.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.2644206870
Short name	T228
Test name
Test status
Simulation time	480558663 ps
CPU time	23.59 seconds
Started	Sep 03 11:41:10 PM UTC 24
Finished	Sep 03 11:41:35 PM UTC 24
Peak memory	216912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644206870 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.2644206870
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/12.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.4096894647
Short name	T230
Test name
Test status
Simulation time	1205112773 ps
CPU time	18.03 seconds
Started	Sep 03 11:41:21 PM UTC 24
Finished	Sep 03 11:41:41 PM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096894647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.4096894647
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/12.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.687574285
Short name	T203
Test name
Test status
Simulation time	27062814 ps
CPU time	3.34 seconds
Started	Sep 03 11:41:04 PM UTC 24
Finished	Sep 03 11:41:08 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687574285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.687574285
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/12.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.2737045559
Short name	T162
Test name
Test status
Simulation time	15788730198 ps
CPU time	38.52 seconds
Started	Sep 03 11:41:09 PM UTC 24
Finished	Sep 03 11:41:49 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737045559 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2737045559
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/12.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.679197655
Short name	T421
Test name
Test status
Simulation time	18762653382 ps
CPU time	58.42 seconds
Started	Sep 03 11:41:10 PM UTC 24
Finished	Sep 03 11:42:11 PM UTC 24
Peak memory	216972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679197655 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.679197655
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/12.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2478780043
Short name	T207
Test name
Test status
Simulation time	38643240 ps
CPU time	2.86 seconds
Started	Sep 03 11:41:08 PM UTC 24
Finished	Sep 03 11:41:12 PM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478780043 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2478780043
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/12.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.2395225162
Short name	T154
Test name
Test status
Simulation time	3809462686 ps
CPU time	128.35 seconds
Started	Sep 03 11:41:33 PM UTC 24
Finished	Sep 03 11:43:43 PM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395225162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2395225162
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/12.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2957725498
Short name	T375
Test name
Test status
Simulation time	6593423112 ps
CPU time	159.73 seconds
Started	Sep 03 11:41:37 PM UTC 24
Finished	Sep 03 11:44:19 PM UTC 24
Peak memory	220996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957725498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2957725498
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/12.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.3999190812
Short name	T386
Test name
Test status
Simulation time	4821257010 ps
CPU time	253.59 seconds
Started	Sep 03 11:41:35 PM UTC 24
Finished	Sep 03 11:45:52 PM UTC 24
Peak memory	223048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999190812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.3999190812
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/12.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.1158422576
Short name	T479
Test name
Test status
Simulation time	1557006273 ps
CPU time	217.8 seconds
Started	Sep 03 11:41:41 PM UTC 24
Finished	Sep 03 11:45:23 PM UTC 24
Peak memory	223284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158422576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.1158422576
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/12.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.2944636408
Short name	T156
Test name
Test status
Simulation time	533471975 ps
CPU time	14.8 seconds
Started	Sep 03 11:41:26 PM UTC 24
Finished	Sep 03 11:41:42 PM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944636408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2944636408
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/12.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.2730308391
Short name	T215
Test name
Test status
Simulation time	236561331 ps
CPU time	25.68 seconds
Started	Sep 03 11:41:46 PM UTC 24
Finished	Sep 03 11:42:13 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730308391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2730308391
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/13.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.1801747504
Short name	T381
Test name
Test status
Simulation time	68157946175 ps
CPU time	330.93 seconds
Started	Sep 03 11:41:48 PM UTC 24
Finished	Sep 03 11:47:24 PM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801747504 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.1801747504
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/13.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.3609615025
Short name	T418
Test name
Test status
Simulation time	228477933 ps
CPU time	9.46 seconds
Started	Sep 03 11:41:53 PM UTC 24
Finished	Sep 03 11:42:03 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609615025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.3609615025
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/13.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.276170820
Short name	T420
Test name
Test status
Simulation time	342678867 ps
CPU time	14.36 seconds
Started	Sep 03 11:41:50 PM UTC 24
Finished	Sep 03 11:42:06 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276170820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.276170820
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/13.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random.853604799
Short name	T408
Test name
Test status
Simulation time	60175722 ps
CPU time	11.41 seconds
Started	Sep 03 11:41:44 PM UTC 24
Finished	Sep 03 11:41:56 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853604799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.853604799
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/13.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.2410828662
Short name	T164
Test name
Test status
Simulation time	24284263371 ps
CPU time	125.39 seconds
Started	Sep 03 11:41:46 PM UTC 24
Finished	Sep 03 11:43:54 PM UTC 24
Peak memory	216892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410828662 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2410828662
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/13.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.4029068481
Short name	T415
Test name
Test status
Simulation time	2532974199 ps
CPU time	14.51 seconds
Started	Sep 03 11:41:46 PM UTC 24
Finished	Sep 03 11:42:02 PM UTC 24
Peak memory	217216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029068481 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.4029068481
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/13.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.3437433781
Short name	T160
Test name
Test status
Simulation time	14149739 ps
CPU time	1.86 seconds
Started	Sep 03 11:41:44 PM UTC 24
Finished	Sep 03 11:41:47 PM UTC 24
Peak memory	215836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437433781 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3437433781
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/13.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.1211445872
Short name	T411
Test name
Test status
Simulation time	269661800 ps
CPU time	6.12 seconds
Started	Sep 03 11:41:50 PM UTC 24
Finished	Sep 03 11:41:57 PM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211445872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1211445872
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/13.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.3526327516
Short name	T163
Test name
Test status
Simulation time	170099467 ps
CPU time	6.67 seconds
Started	Sep 03 11:41:41 PM UTC 24
Finished	Sep 03 11:41:49 PM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526327516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.3526327516
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/13.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.103204513
Short name	T277
Test name
Test status
Simulation time	32788686536 ps
CPU time	66.97 seconds
Started	Sep 03 11:41:42 PM UTC 24
Finished	Sep 03 11:42:50 PM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103204513 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.103204513
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/13.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.3572318072
Short name	T222
Test name
Test status
Simulation time	4173857927 ps
CPU time	33.86 seconds
Started	Sep 03 11:41:42 PM UTC 24
Finished	Sep 03 11:42:17 PM UTC 24
Peak memory	216868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572318072 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3572318072
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/13.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.1628321002
Short name	T159
Test name
Test status
Simulation time	26532017 ps
CPU time	2.7 seconds
Started	Sep 03 11:41:41 PM UTC 24
Finished	Sep 03 11:41:45 PM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628321002 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.1628321002
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/13.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.1605638168
Short name	T443
Test name
Test status
Simulation time	3771985477 ps
CPU time	122.96 seconds
Started	Sep 03 11:41:53 PM UTC 24
Finished	Sep 03 11:43:58 PM UTC 24
Peak memory	219140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605638168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1605638168
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/13.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.4216659289
Short name	T410
Test name
Test status
Simulation time	5598461 ps
CPU time	1.19 seconds
Started	Sep 03 11:41:55 PM UTC 24
Finished	Sep 03 11:41:57 PM UTC 24
Peak memory	204364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216659289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.4216659289
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/13.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.2615653496
Short name	T225
Test name
Test status
Simulation time	1020130512 ps
CPU time	320.89 seconds
Started	Sep 03 11:41:55 PM UTC 24
Finished	Sep 03 11:47:20 PM UTC 24
Peak memory	223288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615653496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.2615653496
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/13.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1593876550
Short name	T384
Test name
Test status
Simulation time	9955555345 ps
CPU time	268.84 seconds
Started	Sep 03 11:41:55 PM UTC 24
Finished	Sep 03 11:46:28 PM UTC 24
Peak memory	233656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593876550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.1593876550
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/13.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.2203531636
Short name	T412
Test name
Test status
Simulation time	50424511 ps
CPU time	6.12 seconds
Started	Sep 03 11:41:50 PM UTC 24
Finished	Sep 03 11:41:58 PM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203531636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2203531636
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/13.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.3464013132
Short name	T221
Test name
Test status
Simulation time	293956090 ps
CPU time	10.7 seconds
Started	Sep 03 11:42:04 PM UTC 24
Finished	Sep 03 11:42:16 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464013132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.3464013132
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/14.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.4109667373
Short name	T124
Test name
Test status
Simulation time	116287495458 ps
CPU time	585.91 seconds
Started	Sep 03 11:42:04 PM UTC 24
Finished	Sep 03 11:51:57 PM UTC 24
Peak memory	222548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109667373 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.4109667373
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/14.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.880147460
Short name	T219
Test name
Test status
Simulation time	100509045 ps
CPU time	9.53 seconds
Started	Sep 03 11:42:05 PM UTC 24
Finished	Sep 03 11:42:15 PM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880147460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.880147460
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/14.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.1472629149
Short name	T217
Test name
Test status
Simulation time	83522820 ps
CPU time	7.58 seconds
Started	Sep 03 11:42:04 PM UTC 24
Finished	Sep 03 11:42:13 PM UTC 24
Peak memory	216760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472629149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1472629149
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/14.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random.1904405386
Short name	T220
Test name
Test status
Simulation time	121055440 ps
CPU time	15.08 seconds
Started	Sep 03 11:41:59 PM UTC 24
Finished	Sep 03 11:42:16 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904405386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1904405386
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/14.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.3360260257
Short name	T195
Test name
Test status
Simulation time	4649980939 ps
CPU time	25.28 seconds
Started	Sep 03 11:42:02 PM UTC 24
Finished	Sep 03 11:42:28 PM UTC 24
Peak memory	217032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360260257 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3360260257
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/14.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2157922494
Short name	T65
Test name
Test status
Simulation time	22263539078 ps
CPU time	86.33 seconds
Started	Sep 03 11:42:02 PM UTC 24
Finished	Sep 03 11:43:30 PM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157922494 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2157922494
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/14.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.326559999
Short name	T218
Test name
Test status
Simulation time	107331501 ps
CPU time	14.15 seconds
Started	Sep 03 11:41:59 PM UTC 24
Finished	Sep 03 11:42:15 PM UTC 24
Peak memory	217140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326559999 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.326559999
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/14.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.4023250533
Short name	T422
Test name
Test status
Simulation time	848254094 ps
CPU time	19.61 seconds
Started	Sep 03 11:42:04 PM UTC 24
Finished	Sep 03 11:42:25 PM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023250533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.4023250533
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/14.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.2326643050
Short name	T416
Test name
Test status
Simulation time	358524954 ps
CPU time	5.02 seconds
Started	Sep 03 11:41:57 PM UTC 24
Finished	Sep 03 11:42:03 PM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326643050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2326643050
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/14.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3025784681
Short name	T425
Test name
Test status
Simulation time	7661662278 ps
CPU time	35.86 seconds
Started	Sep 03 11:41:59 PM UTC 24
Finished	Sep 03 11:42:36 PM UTC 24
Peak memory	217140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025784681 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3025784681
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/14.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.1589031203
Short name	T424
Test name
Test status
Simulation time	2760210169 ps
CPU time	34.41 seconds
Started	Sep 03 11:41:59 PM UTC 24
Finished	Sep 03 11:42:35 PM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589031203 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1589031203
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/14.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.2775327724
Short name	T414
Test name
Test status
Simulation time	27575674 ps
CPU time	2.79 seconds
Started	Sep 03 11:41:57 PM UTC 24
Finished	Sep 03 11:42:01 PM UTC 24
Peak memory	217064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775327724 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.2775327724
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/14.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.3668703671
Short name	T459
Test name
Test status
Simulation time	955076632 ps
CPU time	137.42 seconds
Started	Sep 03 11:42:07 PM UTC 24
Finished	Sep 03 11:44:27 PM UTC 24
Peak memory	218816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668703671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3668703671
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/14.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1795625742
Short name	T366
Test name
Test status
Simulation time	8066993990 ps
CPU time	180.24 seconds
Started	Sep 03 11:42:13 PM UTC 24
Finished	Sep 03 11:45:16 PM UTC 24
Peak memory	219208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795625742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1795625742
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/14.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.1409735063
Short name	T537
Test name
Test status
Simulation time	2960445269 ps
CPU time	354.76 seconds
Started	Sep 03 11:42:07 PM UTC 24
Finished	Sep 03 11:48:06 PM UTC 24
Peak memory	223420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409735063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.1409735063
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/14.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.4128317686
Short name	T352
Test name
Test status
Simulation time	108566850 ps
CPU time	42.4 seconds
Started	Sep 03 11:42:15 PM UTC 24
Finished	Sep 03 11:42:59 PM UTC 24
Peak memory	218824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128317686 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.4128317686
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/14.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.3036259928
Short name	T151
Test name
Test status
Simulation time	358572705 ps
CPU time	15.63 seconds
Started	Sep 03 11:42:04 PM UTC 24
Finished	Sep 03 11:42:21 PM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036259928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3036259928
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/14.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.2591638029
Short name	T329
Test name
Test status
Simulation time	238089080 ps
CPU time	14.59 seconds
Started	Sep 03 11:42:22 PM UTC 24
Finished	Sep 03 11:42:38 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591638029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2591638029
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/15.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.3093081509
Short name	T369
Test name
Test status
Simulation time	16447320510 ps
CPU time	74.64 seconds
Started	Sep 03 11:42:22 PM UTC 24
Finished	Sep 03 11:43:39 PM UTC 24
Peak memory	219204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093081509 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.3093081509
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/15.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.517580597
Short name	T349
Test name
Test status
Simulation time	4179039701 ps
CPU time	25.97 seconds
Started	Sep 03 11:42:29 PM UTC 24
Finished	Sep 03 11:42:56 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517580597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.517580597
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/15.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.318948309
Short name	T350
Test name
Test status
Simulation time	824871128 ps
CPU time	28.68 seconds
Started	Sep 03 11:42:27 PM UTC 24
Finished	Sep 03 11:42:57 PM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318948309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.318948309
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/15.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random.2068563489
Short name	T260
Test name
Test status
Simulation time	804244959 ps
CPU time	21.01 seconds
Started	Sep 03 11:42:18 PM UTC 24
Finished	Sep 03 11:42:40 PM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068563489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2068563489
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/15.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.5568423
Short name	T238
Test name
Test status
Simulation time	31505344553 ps
CPU time	108.63 seconds
Started	Sep 03 11:42:18 PM UTC 24
Finished	Sep 03 11:44:09 PM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5568423 -assert nopostproc +UVM_TESTNAME=xbar_base_t est +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.5568423
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/15.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3540935919
Short name	T470
Test name
Test status
Simulation time	20498777894 ps
CPU time	145.21 seconds
Started	Sep 03 11:42:22 PM UTC 24
Finished	Sep 03 11:44:50 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540935919 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3540935919
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/15.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.241414453
Short name	T426
Test name
Test status
Simulation time	204685877 ps
CPU time	18.22 seconds
Started	Sep 03 11:42:18 PM UTC 24
Finished	Sep 03 11:42:37 PM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241414453 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.241414453
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/15.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.1877982093
Short name	T351
Test name
Test status
Simulation time	3781635448 ps
CPU time	32.41 seconds
Started	Sep 03 11:42:24 PM UTC 24
Finished	Sep 03 11:42:58 PM UTC 24
Peak memory	217156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877982093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1877982093
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/15.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.2145344934
Short name	T223
Test name
Test status
Simulation time	231599519 ps
CPU time	4.74 seconds
Started	Sep 03 11:42:15 PM UTC 24
Finished	Sep 03 11:42:21 PM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145344934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.2145344934
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/15.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2000229763
Short name	T279
Test name
Test status
Simulation time	14082924758 ps
CPU time	35.35 seconds
Started	Sep 03 11:42:18 PM UTC 24
Finished	Sep 03 11:42:54 PM UTC 24
Peak memory	217204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000229763 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2000229763
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/15.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.844922978
Short name	T319
Test name
Test status
Simulation time	8461929774 ps
CPU time	51.43 seconds
Started	Sep 03 11:42:18 PM UTC 24
Finished	Sep 03 11:43:11 PM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844922978 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.844922978
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/15.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.201033253
Short name	T224
Test name
Test status
Simulation time	28772059 ps
CPU time	2.29 seconds
Started	Sep 03 11:42:18 PM UTC 24
Finished	Sep 03 11:42:21 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201033253 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.201033253
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/15.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.2375669675
Short name	T475
Test name
Test status
Simulation time	4875269031 ps
CPU time	154.69 seconds
Started	Sep 03 11:42:36 PM UTC 24
Finished	Sep 03 11:45:14 PM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375669675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2375669675
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/15.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2360821514
Short name	T387
Test name
Test status
Simulation time	98365024 ps
CPU time	67.85 seconds
Started	Sep 03 11:42:36 PM UTC 24
Finished	Sep 03 11:43:46 PM UTC 24
Peak memory	218820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360821514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.2360821514
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/15.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.337082090
Short name	T322
Test name
Test status
Simulation time	60578064 ps
CPU time	35.8 seconds
Started	Sep 03 11:42:39 PM UTC 24
Finished	Sep 03 11:43:16 PM UTC 24
Peak memory	220928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337082090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.337082090
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/15.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.2502125800
Short name	T152
Test name
Test status
Simulation time	1809849653 ps
CPU time	24.89 seconds
Started	Sep 03 11:42:27 PM UTC 24
Finished	Sep 03 11:42:53 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502125800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2502125800
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/15.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.736241964
Short name	T278
Test name
Test status
Simulation time	18435544 ps
CPU time	2.19 seconds
Started	Sep 03 11:42:49 PM UTC 24
Finished	Sep 03 11:42:52 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736241964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.736241964
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/16.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.2925659783
Short name	T647
Test name
Test status
Simulation time	72118143442 ps
CPU time	523.5 seconds
Started	Sep 03 11:42:49 PM UTC 24
Finished	Sep 03 11:51:39 PM UTC 24
Peak memory	220500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925659783 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.2925659783
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/16.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.825812097
Short name	T318
Test name
Test status
Simulation time	312218400 ps
CPU time	12.64 seconds
Started	Sep 03 11:42:56 PM UTC 24
Finished	Sep 03 11:43:10 PM UTC 24
Peak memory	216400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825812097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.825812097
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/16.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.893009780
Short name	T316
Test name
Test status
Simulation time	2584605474 ps
CPU time	13.72 seconds
Started	Sep 03 11:42:53 PM UTC 24
Finished	Sep 03 11:43:08 PM UTC 24
Peak memory	216888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893009780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.893009780
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/16.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random.3881148331
Short name	T257
Test name
Test status
Simulation time	940776178 ps
CPU time	36.15 seconds
Started	Sep 03 11:42:46 PM UTC 24
Finished	Sep 03 11:43:23 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881148331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.3881148331
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/16.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.3694019918
Short name	T67
Test name
Test status
Simulation time	18898138176 ps
CPU time	127.72 seconds
Started	Sep 03 11:42:46 PM UTC 24
Finished	Sep 03 11:44:56 PM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694019918 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3694019918
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/16.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2950807801
Short name	T113
Test name
Test status
Simulation time	45619242549 ps
CPU time	228.29 seconds
Started	Sep 03 11:42:48 PM UTC 24
Finished	Sep 03 11:46:39 PM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950807801 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2950807801
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/16.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.1236561847
Short name	T317
Test name
Test status
Simulation time	169094784 ps
CPU time	22.66 seconds
Started	Sep 03 11:42:46 PM UTC 24
Finished	Sep 03 11:43:09 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236561847 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.1236561847
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/16.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.1616008657
Short name	T429
Test name
Test status
Simulation time	5224059273 ps
CPU time	30.56 seconds
Started	Sep 03 11:42:51 PM UTC 24
Finished	Sep 03 11:43:23 PM UTC 24
Peak memory	217152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616008657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1616008657
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/16.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.3388236746
Short name	T256
Test name
Test status
Simulation time	141806086 ps
CPU time	4.94 seconds
Started	Sep 03 11:42:39 PM UTC 24
Finished	Sep 03 11:42:45 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388236746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3388236746
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/16.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.123599261
Short name	T320
Test name
Test status
Simulation time	6513954238 ps
CPU time	29.59 seconds
Started	Sep 03 11:42:41 PM UTC 24
Finished	Sep 03 11:43:12 PM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123599261 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.123599261
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/16.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.4093366127
Short name	T323
Test name
Test status
Simulation time	7501303247 ps
CPU time	30.33 seconds
Started	Sep 03 11:42:45 PM UTC 24
Finished	Sep 03 11:43:17 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093366127 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.4093366127
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/16.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.120448844
Short name	T427
Test name
Test status
Simulation time	66888017 ps
CPU time	3 seconds
Started	Sep 03 11:42:39 PM UTC 24
Finished	Sep 03 11:42:43 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120448844 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.120448844
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/16.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.306957774
Short name	T431
Test name
Test status
Simulation time	857786079 ps
CPU time	27.22 seconds
Started	Sep 03 11:42:56 PM UTC 24
Finished	Sep 03 11:43:25 PM UTC 24
Peak memory	218308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306957774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.306957774
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/16.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1734760135
Short name	T438
Test name
Test status
Simulation time	1301873965 ps
CPU time	48.66 seconds
Started	Sep 03 11:42:58 PM UTC 24
Finished	Sep 03 11:43:49 PM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734760135 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1734760135
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/16.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.487438850
Short name	T712
Test name
Test status
Simulation time	5220854624 ps
CPU time	610.4 seconds
Started	Sep 03 11:42:58 PM UTC 24
Finished	Sep 03 11:53:16 PM UTC 24
Peak memory	235076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487438850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.487438850
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/16.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.4094431343
Short name	T321
Test name
Test status
Simulation time	176297288 ps
CPU time	17.42 seconds
Started	Sep 03 11:42:54 PM UTC 24
Finished	Sep 03 11:43:13 PM UTC 24
Peak memory	218820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094431343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.4094431343
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/16.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.2414205640
Short name	T64
Test name
Test status
Simulation time	558264002 ps
CPU time	15.41 seconds
Started	Sep 03 11:43:09 PM UTC 24
Finished	Sep 03 11:43:26 PM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414205640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2414205640
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/17.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.2010108400
Short name	T759
Test name
Test status
Simulation time	102015282748 ps
CPU time	673.95 seconds
Started	Sep 03 11:43:11 PM UTC 24
Finished	Sep 03 11:54:33 PM UTC 24
Peak memory	222044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010108400 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.2010108400
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/17.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3404389442
Short name	T428
Test name
Test status
Simulation time	61899550 ps
CPU time	3.62 seconds
Started	Sep 03 11:43:14 PM UTC 24
Finished	Sep 03 11:43:19 PM UTC 24
Peak memory	217156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404389442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3404389442
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/17.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.298697860
Short name	T442
Test name
Test status
Simulation time	884336128 ps
CPU time	40.84 seconds
Started	Sep 03 11:43:12 PM UTC 24
Finished	Sep 03 11:43:55 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298697860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.298697860
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/17.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random.1256950332
Short name	T297
Test name
Test status
Simulation time	507030285 ps
CPU time	14.28 seconds
Started	Sep 03 11:43:04 PM UTC 24
Finished	Sep 03 11:43:19 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256950332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.1256950332
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/17.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.2331687478
Short name	T436
Test name
Test status
Simulation time	8699190744 ps
CPU time	24.96 seconds
Started	Sep 03 11:43:07 PM UTC 24
Finished	Sep 03 11:43:33 PM UTC 24
Peak memory	217148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331687478 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2331687478
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/17.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3435167346
Short name	T451
Test name
Test status
Simulation time	10280010397 ps
CPU time	64.39 seconds
Started	Sep 03 11:43:07 PM UTC 24
Finished	Sep 03 11:44:13 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435167346 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3435167346
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/17.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.2940892494
Short name	T434
Test name
Test status
Simulation time	361099248 ps
CPU time	23.05 seconds
Started	Sep 03 11:43:05 PM UTC 24
Finished	Sep 03 11:43:29 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940892494 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.2940892494
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/17.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.3507127343
Short name	T439
Test name
Test status
Simulation time	2565329423 ps
CPU time	35.97 seconds
Started	Sep 03 11:43:11 PM UTC 24
Finished	Sep 03 11:43:49 PM UTC 24
Peak memory	216160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507127343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3507127343
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/17.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.2910591045
Short name	T353
Test name
Test status
Simulation time	57095268 ps
CPU time	3.54 seconds
Started	Sep 03 11:42:58 PM UTC 24
Finished	Sep 03 11:43:03 PM UTC 24
Peak memory	217008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910591045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2910591045
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/17.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2618224471
Short name	T433
Test name
Test status
Simulation time	11485766095 ps
CPU time	27.75 seconds
Started	Sep 03 11:42:59 PM UTC 24
Finished	Sep 03 11:43:29 PM UTC 24
Peak memory	217140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618224471 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2618224471
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/17.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.2987836121
Short name	T435
Test name
Test status
Simulation time	5404036018 ps
CPU time	28.4 seconds
Started	Sep 03 11:42:59 PM UTC 24
Finished	Sep 03 11:43:29 PM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987836121 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2987836121
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/17.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.2543435273
Short name	T354
Test name
Test status
Simulation time	36207250 ps
CPU time	3.53 seconds
Started	Sep 03 11:42:59 PM UTC 24
Finished	Sep 03 11:43:04 PM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543435273 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.2543435273
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/17.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.2284623888
Short name	T240
Test name
Test status
Simulation time	808451556 ps
CPU time	73.63 seconds
Started	Sep 03 11:43:17 PM UTC 24
Finished	Sep 03 11:44:33 PM UTC 24
Peak memory	218816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284623888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2284623888
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/17.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.184678773
Short name	T365
Test name
Test status
Simulation time	4527677177 ps
CPU time	108.57 seconds
Started	Sep 03 11:43:20 PM UTC 24
Finished	Sep 03 11:45:10 PM UTC 24
Peak memory	218888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184678773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.184678773
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/17.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3588148447
Short name	T112
Test name
Test status
Simulation time	3655273501 ps
CPU time	179.81 seconds
Started	Sep 03 11:43:18 PM UTC 24
Finished	Sep 03 11:46:21 PM UTC 24
Peak memory	220932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588148447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.3588148447
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/17.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.2215344525
Short name	T383
Test name
Test status
Simulation time	2976052127 ps
CPU time	190.24 seconds
Started	Sep 03 11:43:20 PM UTC 24
Finished	Sep 03 11:46:33 PM UTC 24
Peak memory	223368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215344525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.2215344525
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/17.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.570752967
Short name	T430
Test name
Test status
Simulation time	920582214 ps
CPU time	8.99 seconds
Started	Sep 03 11:43:13 PM UTC 24
Finished	Sep 03 11:43:23 PM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570752967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.570752967
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/17.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.3103215912
Short name	T364
Test name
Test status
Simulation time	2557771498 ps
CPU time	44.22 seconds
Started	Sep 03 11:43:30 PM UTC 24
Finished	Sep 03 11:44:16 PM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103215912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3103215912
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/18.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.4212952565
Short name	T642
Test name
Test status
Simulation time	46269589479 ps
CPU time	477.76 seconds
Started	Sep 03 11:43:30 PM UTC 24
Finished	Sep 03 11:51:34 PM UTC 24
Peak memory	219208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212952565 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.4212952565
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/18.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3559553203
Short name	T437
Test name
Test status
Simulation time	398303761 ps
CPU time	10.08 seconds
Started	Sep 03 11:43:35 PM UTC 24
Finished	Sep 03 11:43:46 PM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559553203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3559553203
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/18.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.1589393749
Short name	T446
Test name
Test status
Simulation time	273814475 ps
CPU time	29.85 seconds
Started	Sep 03 11:43:31 PM UTC 24
Finished	Sep 03 11:44:02 PM UTC 24
Peak memory	216756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589393749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1589393749
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/18.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random.13623332
Short name	T298
Test name
Test status
Simulation time	703527767 ps
CPU time	26.47 seconds
Started	Sep 03 11:43:26 PM UTC 24
Finished	Sep 03 11:43:53 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13623332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.13623332
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/18.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.2597156275
Short name	T513
Test name
Test status
Simulation time	48452467082 ps
CPU time	209.83 seconds
Started	Sep 03 11:43:28 PM UTC 24
Finished	Sep 03 11:47:01 PM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597156275 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2597156275
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/18.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3896375764
Short name	T445
Test name
Test status
Simulation time	3145287796 ps
CPU time	29.13 seconds
Started	Sep 03 11:43:30 PM UTC 24
Finished	Sep 03 11:44:01 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896375764 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3896375764
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/18.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.2497884504
Short name	T447
Test name
Test status
Simulation time	185984851 ps
CPU time	33.18 seconds
Started	Sep 03 11:43:28 PM UTC 24
Finished	Sep 03 11:44:02 PM UTC 24
Peak memory	218800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497884504 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.2497884504
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/18.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.1678218833
Short name	T450
Test name
Test status
Simulation time	1939095852 ps
CPU time	37.54 seconds
Started	Sep 03 11:43:31 PM UTC 24
Finished	Sep 03 11:44:10 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678218833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1678218833
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/18.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.4127573714
Short name	T432
Test name
Test status
Simulation time	36980807 ps
CPU time	3.24 seconds
Started	Sep 03 11:43:23 PM UTC 24
Finished	Sep 03 11:43:27 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127573714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.4127573714
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/18.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.2137013790
Short name	T444
Test name
Test status
Simulation time	8638032115 ps
CPU time	34.86 seconds
Started	Sep 03 11:43:24 PM UTC 24
Finished	Sep 03 11:44:01 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137013790 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2137013790
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/18.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.531080464
Short name	T453
Test name
Test status
Simulation time	5265839134 ps
CPU time	48.71 seconds
Started	Sep 03 11:43:24 PM UTC 24
Finished	Sep 03 11:44:15 PM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531080464 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.531080464
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/18.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.651173719
Short name	T144
Test name
Test status
Simulation time	40353150 ps
CPU time	3.39 seconds
Started	Sep 03 11:43:24 PM UTC 24
Finished	Sep 03 11:43:29 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651173719 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.651173719
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/18.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.1809524768
Short name	T165
Test name
Test status
Simulation time	16628888931 ps
CPU time	260.4 seconds
Started	Sep 03 11:43:39 PM UTC 24
Finished	Sep 03 11:48:04 PM UTC 24
Peak memory	222976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809524768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1809524768
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/18.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1837055156
Short name	T339
Test name
Test status
Simulation time	2204410969 ps
CPU time	148.1 seconds
Started	Sep 03 11:43:47 PM UTC 24
Finished	Sep 03 11:46:18 PM UTC 24
Peak memory	223044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837055156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1837055156
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/18.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.1325636418
Short name	T464
Test name
Test status
Simulation time	120172010 ps
CPU time	54.07 seconds
Started	Sep 03 11:43:45 PM UTC 24
Finished	Sep 03 11:44:40 PM UTC 24
Peak memory	219212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325636418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.1325636418
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/18.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.463455939
Short name	T540
Test name
Test status
Simulation time	1122257757 ps
CPU time	259.34 seconds
Started	Sep 03 11:43:47 PM UTC 24
Finished	Sep 03 11:48:10 PM UTC 24
Peak memory	233908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463455939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.463455939
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/18.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.3416941715
Short name	T271
Test name
Test status
Simulation time	997015013 ps
CPU time	19.15 seconds
Started	Sep 03 11:43:35 PM UTC 24
Finished	Sep 03 11:43:55 PM UTC 24
Peak memory	218888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416941715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3416941715
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/18.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.3265066495
Short name	T448
Test name
Test status
Simulation time	38806513 ps
CPU time	6.46 seconds
Started	Sep 03 11:43:56 PM UTC 24
Finished	Sep 03 11:44:04 PM UTC 24
Peak memory	216844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265066495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.3265066495
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/19.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.2518499474
Short name	T458
Test name
Test status
Simulation time	804829959 ps
CPU time	15.66 seconds
Started	Sep 03 11:44:04 PM UTC 24
Finished	Sep 03 11:44:21 PM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518499474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.2518499474
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/19.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.3102068865
Short name	T463
Test name
Test status
Simulation time	873038342 ps
CPU time	37 seconds
Started	Sep 03 11:44:02 PM UTC 24
Finished	Sep 03 11:44:40 PM UTC 24
Peak memory	216760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102068865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.3102068865
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/19.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random.1191480299
Short name	T108
Test name
Test status
Simulation time	1309434045 ps
CPU time	33.26 seconds
Started	Sep 03 11:43:55 PM UTC 24
Finished	Sep 03 11:44:29 PM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191480299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.1191480299
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/19.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.1693806143
Short name	T455
Test name
Test status
Simulation time	4772227096 ps
CPU time	22.68 seconds
Started	Sep 03 11:43:55 PM UTC 24
Finished	Sep 03 11:44:19 PM UTC 24
Peak memory	216888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693806143 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1693806143
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/19.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.414180179
Short name	T461
Test name
Test status
Simulation time	3592339284 ps
CPU time	32.83 seconds
Started	Sep 03 11:43:56 PM UTC 24
Finished	Sep 03 11:44:30 PM UTC 24
Peak memory	216888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414180179 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.414180179
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/19.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.3161499821
Short name	T452
Test name
Test status
Simulation time	393936277 ps
CPU time	18.33 seconds
Started	Sep 03 11:43:55 PM UTC 24
Finished	Sep 03 11:44:14 PM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161499821 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.3161499821
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/19.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.3684580689
Short name	T449
Test name
Test status
Simulation time	190079665 ps
CPU time	6.71 seconds
Started	Sep 03 11:44:02 PM UTC 24
Finished	Sep 03 11:44:09 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684580689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3684580689
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/19.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.2713423040
Short name	T440
Test name
Test status
Simulation time	32392138 ps
CPU time	3.02 seconds
Started	Sep 03 11:43:49 PM UTC 24
Finished	Sep 03 11:43:53 PM UTC 24
Peak memory	217072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713423040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2713423040
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/19.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.360782117
Short name	T460
Test name
Test status
Simulation time	6968180126 ps
CPU time	32.42 seconds
Started	Sep 03 11:43:53 PM UTC 24
Finished	Sep 03 11:44:27 PM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360782117 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.360782117
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/19.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1473782761
Short name	T66
Test name
Test status
Simulation time	6586102118 ps
CPU time	34.09 seconds
Started	Sep 03 11:43:55 PM UTC 24
Finished	Sep 03 11:44:30 PM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473782761 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1473782761
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/19.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.2721655805
Short name	T441
Test name
Test status
Simulation time	28879589 ps
CPU time	3.6 seconds
Started	Sep 03 11:43:49 PM UTC 24
Finished	Sep 03 11:43:54 PM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721655805 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.2721655805
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/19.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.685277798
Short name	T111
Test name
Test status
Simulation time	3121647139 ps
CPU time	126.44 seconds
Started	Sep 03 11:44:04 PM UTC 24
Finished	Sep 03 11:46:13 PM UTC 24
Peak memory	218944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685277798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.685277798
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/19.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.3248443642
Short name	T180
Test name
Test status
Simulation time	17532490329 ps
CPU time	215.17 seconds
Started	Sep 03 11:44:10 PM UTC 24
Finished	Sep 03 11:47:49 PM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248443642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3248443642
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/19.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.2414285673
Short name	T385
Test name
Test status
Simulation time	588883871 ps
CPU time	133.08 seconds
Started	Sep 03 11:44:11 PM UTC 24
Finished	Sep 03 11:46:26 PM UTC 24
Peak memory	222916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414285673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.2414285673
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/19.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.1773242889
Short name	T454
Test name
Test status
Simulation time	161452130 ps
CPU time	13.09 seconds
Started	Sep 03 11:44:03 PM UTC 24
Finished	Sep 03 11:44:17 PM UTC 24
Peak memory	217028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773242889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.1773242889
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/19.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.839725106
Short name	T31
Test name
Test status
Simulation time	595154269 ps
CPU time	14.9 seconds
Started	Sep 03 11:38:06 PM UTC 24
Finished	Sep 03 11:38:22 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839725106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.839725106
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/2.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.4157259624
Short name	T22
Test name
Test status
Simulation time	107066795 ps
CPU time	10.87 seconds
Started	Sep 03 11:38:05 PM UTC 24
Finished	Sep 03 11:38:17 PM UTC 24
Peak memory	216760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157259624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.4157259624
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/2.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random.2824774068
Short name	T18
Test name
Test status
Simulation time	123799651 ps
CPU time	9.76 seconds
Started	Sep 03 11:37:58 PM UTC 24
Finished	Sep 03 11:38:09 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824774068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.2824774068
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/2.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.1978300989
Short name	T377
Test name
Test status
Simulation time	55011544400 ps
CPU time	143.38 seconds
Started	Sep 03 11:37:59 PM UTC 24
Finished	Sep 03 11:40:25 PM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978300989 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1978300989
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/2.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.3670574686
Short name	T193
Test name
Test status
Simulation time	5949769346 ps
CPU time	83.16 seconds
Started	Sep 03 11:38:02 PM UTC 24
Finished	Sep 03 11:39:27 PM UTC 24
Peak memory	216892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670574686 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3670574686
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/2.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.4039764594
Short name	T14
Test name
Test status
Simulation time	39546994 ps
CPU time	4.23 seconds
Started	Sep 03 11:37:59 PM UTC 24
Finished	Sep 03 11:38:04 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039764594 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.4039764594
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/2.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.2097527748
Short name	T304
Test name
Test status
Simulation time	171878554 ps
CPU time	16.56 seconds
Started	Sep 03 11:38:03 PM UTC 24
Finished	Sep 03 11:38:21 PM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097527748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2097527748
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/2.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.4240380489
Short name	T7
Test name
Test status
Simulation time	141290929 ps
CPU time	4.12 seconds
Started	Sep 03 11:37:53 PM UTC 24
Finished	Sep 03 11:37:58 PM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240380489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.4240380489
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/2.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.1925898278
Short name	T59
Test name
Test status
Simulation time	19378078803 ps
CPU time	33.1 seconds
Started	Sep 03 11:37:54 PM UTC 24
Finished	Sep 03 11:38:28 PM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925898278 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1925898278
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/2.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.3456768626
Short name	T324
Test name
Test status
Simulation time	4282604148 ps
CPU time	40.14 seconds
Started	Sep 03 11:37:58 PM UTC 24
Finished	Sep 03 11:38:39 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456768626 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3456768626
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/2.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.309266303
Short name	T12
Test name
Test status
Simulation time	33613167 ps
CPU time	3.26 seconds
Started	Sep 03 11:37:54 PM UTC 24
Finished	Sep 03 11:37:58 PM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309266303 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.309266303
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/2.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.2205618555
Short name	T99
Test name
Test status
Simulation time	26997892771 ps
CPU time	272.28 seconds
Started	Sep 03 11:38:07 PM UTC 24
Finished	Sep 03 11:42:43 PM UTC 24
Peak memory	220928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205618555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2205618555
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/2.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3906030926
Short name	T57
Test name
Test status
Simulation time	220024808 ps
CPU time	27.45 seconds
Started	Sep 03 11:38:09 PM UTC 24
Finished	Sep 03 11:38:38 PM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906030926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3906030926
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/2.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.782436817
Short name	T44
Test name
Test status
Simulation time	706122101 ps
CPU time	244.88 seconds
Started	Sep 03 11:38:08 PM UTC 24
Finished	Sep 03 11:42:17 PM UTC 24
Peak memory	221184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782436817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.782436817
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/2.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.1973470644
Short name	T245
Test name
Test status
Simulation time	149270969 ps
CPU time	22.1 seconds
Started	Sep 03 11:38:06 PM UTC 24
Finished	Sep 03 11:38:29 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973470644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1973470644
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/2.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.3688711985
Short name	T234
Test name
Test status
Simulation time	523714724 ps
CPU time	29.7 seconds
Started	Sep 03 11:44:22 PM UTC 24
Finished	Sep 03 11:44:53 PM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688711985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3688711985
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/20.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3630072268
Short name	T186
Test name
Test status
Simulation time	60077496288 ps
CPU time	240.96 seconds
Started	Sep 03 11:44:22 PM UTC 24
Finished	Sep 03 11:48:26 PM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630072268 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.3630072268
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/20.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.2362622037
Short name	T465
Test name
Test status
Simulation time	43943677 ps
CPU time	7.46 seconds
Started	Sep 03 11:44:32 PM UTC 24
Finished	Sep 03 11:44:41 PM UTC 24
Peak memory	216964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362622037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.2362622037
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/20.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.156500497
Short name	T331
Test name
Test status
Simulation time	524314412 ps
CPU time	26.48 seconds
Started	Sep 03 11:44:28 PM UTC 24
Finished	Sep 03 11:44:56 PM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156500497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.156500497
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/20.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random.3802066658
Short name	T233
Test name
Test status
Simulation time	628861645 ps
CPU time	28.53 seconds
Started	Sep 03 11:44:18 PM UTC 24
Finished	Sep 03 11:44:48 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802066658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.3802066658
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/20.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.2539808329
Short name	T490
Test name
Test status
Simulation time	12749396390 ps
CPU time	82.48 seconds
Started	Sep 03 11:44:21 PM UTC 24
Finished	Sep 03 11:45:45 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539808329 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2539808329
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/20.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1153826106
Short name	T486
Test name
Test status
Simulation time	11700632294 ps
CPU time	70.7 seconds
Started	Sep 03 11:44:21 PM UTC 24
Finished	Sep 03 11:45:33 PM UTC 24
Peak memory	217156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153826106 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1153826106
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/20.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.3028815740
Short name	T276
Test name
Test status
Simulation time	261403738 ps
CPU time	21.29 seconds
Started	Sep 03 11:44:19 PM UTC 24
Finished	Sep 03 11:44:42 PM UTC 24
Peak memory	217084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028815740 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.3028815740
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/20.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.3228784120
Short name	T333
Test name
Test status
Simulation time	3145449160 ps
CPU time	33.44 seconds
Started	Sep 03 11:44:28 PM UTC 24
Finished	Sep 03 11:45:03 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228784120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3228784120
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/20.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.199994056
Short name	T457
Test name
Test status
Simulation time	230122827 ps
CPU time	4.79 seconds
Started	Sep 03 11:44:15 PM UTC 24
Finished	Sep 03 11:44:21 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199994056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.199994056
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/20.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.605818773
Short name	T474
Test name
Test status
Simulation time	23705486524 ps
CPU time	55.88 seconds
Started	Sep 03 11:44:16 PM UTC 24
Finished	Sep 03 11:45:14 PM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605818773 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.605818773
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/20.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.3922825242
Short name	T467
Test name
Test status
Simulation time	4879747592 ps
CPU time	24.04 seconds
Started	Sep 03 11:44:17 PM UTC 24
Finished	Sep 03 11:44:42 PM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922825242 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.3922825242
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/20.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1080021678
Short name	T456
Test name
Test status
Simulation time	47563800 ps
CPU time	3.59 seconds
Started	Sep 03 11:44:15 PM UTC 24
Finished	Sep 03 11:44:19 PM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080021678 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1080021678
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/20.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.412764539
Short name	T379
Test name
Test status
Simulation time	8610352216 ps
CPU time	98.84 seconds
Started	Sep 03 11:44:32 PM UTC 24
Finished	Sep 03 11:46:13 PM UTC 24
Peak memory	220992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412764539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.412764539
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/20.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.1146799281
Short name	T487
Test name
Test status
Simulation time	542141328 ps
CPU time	58.24 seconds
Started	Sep 03 11:44:33 PM UTC 24
Finished	Sep 03 11:45:33 PM UTC 24
Peak memory	218820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146799281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1146799281
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/20.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1716724933
Short name	T305
Test name
Test status
Simulation time	1590372859 ps
CPU time	66.24 seconds
Started	Sep 03 11:44:32 PM UTC 24
Finished	Sep 03 11:45:40 PM UTC 24
Peak memory	220940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716724933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.1716724933
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/20.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.4036224749
Short name	T35
Test name
Test status
Simulation time	8447422467 ps
CPU time	344.52 seconds
Started	Sep 03 11:44:35 PM UTC 24
Finished	Sep 03 11:50:24 PM UTC 24
Peak memory	237688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036224749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.4036224749
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/20.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.387104069
Short name	T466
Test name
Test status
Simulation time	169477960 ps
CPU time	10.42 seconds
Started	Sep 03 11:44:30 PM UTC 24
Finished	Sep 03 11:44:42 PM UTC 24
Peak memory	219200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387104069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.387104069
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/20.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.2476713455
Short name	T334
Test name
Test status
Simulation time	1013847294 ps
CPU time	15.23 seconds
Started	Sep 03 11:44:48 PM UTC 24
Finished	Sep 03 11:45:05 PM UTC 24
Peak memory	216024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476713455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.2476713455
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/21.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1962590106
Short name	T69
Test name
Test status
Simulation time	5962249470 ps
CPU time	44.87 seconds
Started	Sep 03 11:44:49 PM UTC 24
Finished	Sep 03 11:45:36 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962590106 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.1962590106
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/21.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.1518133405
Short name	T335
Test name
Test status
Simulation time	68365925 ps
CPU time	11.82 seconds
Started	Sep 03 11:44:54 PM UTC 24
Finished	Sep 03 11:45:07 PM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518133405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.1518133405
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/21.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.68986379
Short name	T480
Test name
Test status
Simulation time	1502254321 ps
CPU time	29.75 seconds
Started	Sep 03 11:44:53 PM UTC 24
Finished	Sep 03 11:45:24 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68986379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.68986379
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/21.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random.1064020689
Short name	T471
Test name
Test status
Simulation time	731316337 ps
CPU time	6.67 seconds
Started	Sep 03 11:44:44 PM UTC 24
Finished	Sep 03 11:44:52 PM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064020689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.1064020689
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/21.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.2669782854
Short name	T254
Test name
Test status
Simulation time	38227892155 ps
CPU time	149.69 seconds
Started	Sep 03 11:44:46 PM UTC 24
Finished	Sep 03 11:47:18 PM UTC 24
Peak memory	217160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669782854 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2669782854
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/21.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.3144479148
Short name	T73
Test name
Test status
Simulation time	59717024792 ps
CPU time	187.47 seconds
Started	Sep 03 11:44:48 PM UTC 24
Finished	Sep 03 11:47:59 PM UTC 24
Peak memory	216292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144479148 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3144479148
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/21.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.1417296785
Short name	T332
Test name
Test status
Simulation time	129134281 ps
CPU time	16.89 seconds
Started	Sep 03 11:44:44 PM UTC 24
Finished	Sep 03 11:45:02 PM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417296785 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1417296785
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/21.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.2712344633
Short name	T476
Test name
Test status
Simulation time	589270407 ps
CPU time	24.77 seconds
Started	Sep 03 11:44:50 PM UTC 24
Finished	Sep 03 11:45:17 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712344633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2712344633
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/21.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.760900283
Short name	T469
Test name
Test status
Simulation time	462924975 ps
CPU time	5.37 seconds
Started	Sep 03 11:44:41 PM UTC 24
Finished	Sep 03 11:44:47 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760900283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.760900283
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/21.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.840946497
Short name	T482
Test name
Test status
Simulation time	9552956888 ps
CPU time	45.86 seconds
Started	Sep 03 11:44:42 PM UTC 24
Finished	Sep 03 11:45:30 PM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840946497 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.840946497
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/21.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.3924706365
Short name	T68
Test name
Test status
Simulation time	2451518812 ps
CPU time	20.92 seconds
Started	Sep 03 11:44:44 PM UTC 24
Finished	Sep 03 11:45:06 PM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924706365 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3924706365
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/21.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.806620893
Short name	T468
Test name
Test status
Simulation time	24373176 ps
CPU time	3.03 seconds
Started	Sep 03 11:44:41 PM UTC 24
Finished	Sep 03 11:44:45 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806620893 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.806620893
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/21.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.820219528
Short name	T528
Test name
Test status
Simulation time	11919511801 ps
CPU time	150.07 seconds
Started	Sep 03 11:44:57 PM UTC 24
Finished	Sep 03 11:47:30 PM UTC 24
Peak memory	218880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820219528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.820219528
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/21.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.205619344
Short name	T344
Test name
Test status
Simulation time	2267292115 ps
CPU time	77.73 seconds
Started	Sep 03 11:45:03 PM UTC 24
Finished	Sep 03 11:46:23 PM UTC 24
Peak memory	219212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205619344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.205619344
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/21.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3626017180
Short name	T263
Test name
Test status
Simulation time	3024273523 ps
CPU time	632.83 seconds
Started	Sep 03 11:44:57 PM UTC 24
Finished	Sep 03 11:55:39 PM UTC 24
Peak memory	237324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626017180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.3626017180
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/21.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1289015331
Short name	T496
Test name
Test status
Simulation time	179688760 ps
CPU time	51 seconds
Started	Sep 03 11:45:05 PM UTC 24
Finished	Sep 03 11:45:57 PM UTC 24
Peak memory	220932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289015331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.1289015331
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/21.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.1551966962
Short name	T336
Test name
Test status
Simulation time	415790304 ps
CPU time	15.25 seconds
Started	Sep 03 11:44:53 PM UTC 24
Finished	Sep 03 11:45:09 PM UTC 24
Peak memory	219144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551966962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1551966962
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/21.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.3234965902
Short name	T110
Test name
Test status
Simulation time	400369146 ps
CPU time	13.2 seconds
Started	Sep 03 11:45:15 PM UTC 24
Finished	Sep 03 11:45:29 PM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234965902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3234965902
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/22.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2031537790
Short name	T682
Test name
Test status
Simulation time	63842332808 ps
CPU time	427.08 seconds
Started	Sep 03 11:45:17 PM UTC 24
Finished	Sep 03 11:52:29 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031537790 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.2031537790
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/22.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.1345714447
Short name	T494
Test name
Test status
Simulation time	826981385 ps
CPU time	27.54 seconds
Started	Sep 03 11:45:22 PM UTC 24
Finished	Sep 03 11:45:51 PM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345714447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.1345714447
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/22.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.1074343670
Short name	T484
Test name
Test status
Simulation time	244477366 ps
CPU time	9.01 seconds
Started	Sep 03 11:45:21 PM UTC 24
Finished	Sep 03 11:45:31 PM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074343670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1074343670
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/22.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random.3420968926
Short name	T261
Test name
Test status
Simulation time	399722442 ps
CPU time	7.11 seconds
Started	Sep 03 11:45:11 PM UTC 24
Finished	Sep 03 11:45:20 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420968926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.3420968926
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/22.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.2967465904
Short name	T535
Test name
Test status
Simulation time	42951313901 ps
CPU time	167.93 seconds
Started	Sep 03 11:45:11 PM UTC 24
Finished	Sep 03 11:48:02 PM UTC 24
Peak memory	217224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967465904 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2967465904
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/22.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.553204051
Short name	T511
Test name
Test status
Simulation time	20378994900 ps
CPU time	100.46 seconds
Started	Sep 03 11:45:15 PM UTC 24
Finished	Sep 03 11:46:57 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553204051 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.553204051
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/22.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.2701420000
Short name	T478
Test name
Test status
Simulation time	119786592 ps
CPU time	8.5 seconds
Started	Sep 03 11:45:11 PM UTC 24
Finished	Sep 03 11:45:21 PM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701420000 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.2701420000
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/22.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.3798285049
Short name	T488
Test name
Test status
Simulation time	2173154668 ps
CPU time	15.45 seconds
Started	Sep 03 11:45:18 PM UTC 24
Finished	Sep 03 11:45:35 PM UTC 24
Peak memory	216892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798285049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3798285049
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/22.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.2613851123
Short name	T472
Test name
Test status
Simulation time	31558145 ps
CPU time	3.43 seconds
Started	Sep 03 11:45:06 PM UTC 24
Finished	Sep 03 11:45:10 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613851123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2613851123
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/22.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1687353385
Short name	T493
Test name
Test status
Simulation time	7253026410 ps
CPU time	39.91 seconds
Started	Sep 03 11:45:08 PM UTC 24
Finished	Sep 03 11:45:49 PM UTC 24
Peak memory	217140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687353385 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1687353385
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/22.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1406167941
Short name	T314
Test name
Test status
Simulation time	17526346015 ps
CPU time	49.27 seconds
Started	Sep 03 11:45:10 PM UTC 24
Finished	Sep 03 11:46:01 PM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406167941 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1406167941
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/22.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.2557698024
Short name	T473
Test name
Test status
Simulation time	47225310 ps
CPU time	2.91 seconds
Started	Sep 03 11:45:07 PM UTC 24
Finished	Sep 03 11:45:11 PM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557698024 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.2557698024
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/22.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.349041800
Short name	T343
Test name
Test status
Simulation time	525523231 ps
CPU time	56.82 seconds
Started	Sep 03 11:45:22 PM UTC 24
Finished	Sep 03 11:46:21 PM UTC 24
Peak memory	219136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349041800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.349041800
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/22.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.1641195031
Short name	T499
Test name
Test status
Simulation time	2736841989 ps
CPU time	39.42 seconds
Started	Sep 03 11:45:25 PM UTC 24
Finished	Sep 03 11:46:06 PM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641195031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1641195031
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/22.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.4235006068
Short name	T356
Test name
Test status
Simulation time	7157227098 ps
CPU time	420.58 seconds
Started	Sep 03 11:45:23 PM UTC 24
Finished	Sep 03 11:52:30 PM UTC 24
Peak memory	220936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235006068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.4235006068
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/22.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2790369089
Short name	T491
Test name
Test status
Simulation time	117060827 ps
CPU time	19.52 seconds
Started	Sep 03 11:45:25 PM UTC 24
Finished	Sep 03 11:45:45 PM UTC 24
Peak memory	219144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790369089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.2790369089
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/22.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.4235812661
Short name	T483
Test name
Test status
Simulation time	321756967 ps
CPU time	8.56 seconds
Started	Sep 03 11:45:21 PM UTC 24
Finished	Sep 03 11:45:30 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235812661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.4235812661
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/22.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.1461822333
Short name	T338
Test name
Test status
Simulation time	574632157 ps
CPU time	39.75 seconds
Started	Sep 03 11:45:35 PM UTC 24
Finished	Sep 03 11:46:17 PM UTC 24
Peak memory	218820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461822333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1461822333
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/23.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.310577348
Short name	T134
Test name
Test status
Simulation time	84849985088 ps
CPU time	509.48 seconds
Started	Sep 03 11:45:35 PM UTC 24
Finished	Sep 03 11:54:12 PM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310577348 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.310577348
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/23.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1569917346
Short name	T501
Test name
Test status
Simulation time	442266253 ps
CPU time	22.63 seconds
Started	Sep 03 11:45:46 PM UTC 24
Finished	Sep 03 11:46:10 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569917346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1569917346
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/23.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.264297695
Short name	T342
Test name
Test status
Simulation time	2099492438 ps
CPU time	38.45 seconds
Started	Sep 03 11:45:41 PM UTC 24
Finished	Sep 03 11:46:21 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264297695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.264297695
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/23.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random.3433802056
Short name	T262
Test name
Test status
Simulation time	380966335 ps
CPU time	29.41 seconds
Started	Sep 03 11:45:32 PM UTC 24
Finished	Sep 03 11:46:03 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433802056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3433802056
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/23.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.180527673
Short name	T189
Test name
Test status
Simulation time	100243234142 ps
CPU time	173.36 seconds
Started	Sep 03 11:45:34 PM UTC 24
Finished	Sep 03 11:48:30 PM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180527673 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.180527673
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/23.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.2505321006
Short name	T302
Test name
Test status
Simulation time	23429935850 ps
CPU time	234.47 seconds
Started	Sep 03 11:45:34 PM UTC 24
Finished	Sep 03 11:49:32 PM UTC 24
Peak memory	216904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505321006 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2505321006
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/23.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.2793278152
Short name	T492
Test name
Test status
Simulation time	77827157 ps
CPU time	13.28 seconds
Started	Sep 03 11:45:33 PM UTC 24
Finished	Sep 03 11:45:47 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793278152 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.2793278152
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/23.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.1651497464
Short name	T495
Test name
Test status
Simulation time	1337066448 ps
CPU time	17.35 seconds
Started	Sep 03 11:45:36 PM UTC 24
Finished	Sep 03 11:45:55 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651497464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1651497464
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/23.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.144741978
Short name	T485
Test name
Test status
Simulation time	76872488 ps
CPU time	3.06 seconds
Started	Sep 03 11:45:28 PM UTC 24
Finished	Sep 03 11:45:32 PM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144741978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.144741978
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/23.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.1951693415
Short name	T168
Test name
Test status
Simulation time	20109512104 ps
CPU time	71.98 seconds
Started	Sep 03 11:45:30 PM UTC 24
Finished	Sep 03 11:46:44 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951693415 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1951693415
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/23.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.4119519908
Short name	T330
Test name
Test status
Simulation time	6276289382 ps
CPU time	36.73 seconds
Started	Sep 03 11:45:32 PM UTC 24
Finished	Sep 03 11:46:10 PM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119519908 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.4119519908
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/23.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.2103091880
Short name	T489
Test name
Test status
Simulation time	41978375 ps
CPU time	3.11 seconds
Started	Sep 03 11:45:30 PM UTC 24
Finished	Sep 03 11:45:35 PM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103091880 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.2103091880
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/23.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.2904314540
Short name	T172
Test name
Test status
Simulation time	2262321515 ps
CPU time	61.64 seconds
Started	Sep 03 11:45:46 PM UTC 24
Finished	Sep 03 11:46:49 PM UTC 24
Peak memory	219208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904314540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2904314540
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/23.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1473465348
Short name	T505
Test name
Test status
Simulation time	268262141 ps
CPU time	35.56 seconds
Started	Sep 03 11:45:50 PM UTC 24
Finished	Sep 03 11:46:27 PM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473465348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1473465348
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/23.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.1991696800
Short name	T306
Test name
Test status
Simulation time	687327722 ps
CPU time	246.28 seconds
Started	Sep 03 11:45:48 PM UTC 24
Finished	Sep 03 11:49:58 PM UTC 24
Peak memory	221064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991696800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.1991696800
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/23.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.4060383002
Short name	T516
Test name
Test status
Simulation time	1644283989 ps
CPU time	70.72 seconds
Started	Sep 03 11:45:52 PM UTC 24
Finished	Sep 03 11:47:04 PM UTC 24
Peak memory	218888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060383002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.4060383002
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/23.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.2428570391
Short name	T498
Test name
Test status
Simulation time	1463927057 ps
CPU time	14.44 seconds
Started	Sep 03 11:45:45 PM UTC 24
Finished	Sep 03 11:46:00 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428570391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2428570391
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/23.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.1448574825
Short name	T522
Test name
Test status
Simulation time	1882915965 ps
CPU time	67.8 seconds
Started	Sep 03 11:46:04 PM UTC 24
Finished	Sep 03 11:47:13 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448574825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1448574825
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/24.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.398103151
Short name	T555
Test name
Test status
Simulation time	11114046612 ps
CPU time	160.16 seconds
Started	Sep 03 11:46:04 PM UTC 24
Finished	Sep 03 11:48:47 PM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398103151 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.398103151
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/24.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.823634293
Short name	T340
Test name
Test status
Simulation time	42170218 ps
CPU time	6.17 seconds
Started	Sep 03 11:46:11 PM UTC 24
Finished	Sep 03 11:46:18 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823634293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.823634293
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/24.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.1818565427
Short name	T506
Test name
Test status
Simulation time	1748935204 ps
CPU time	22.06 seconds
Started	Sep 03 11:46:08 PM UTC 24
Finished	Sep 03 11:46:32 PM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818565427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1818565427
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/24.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random.3226268333
Short name	T115
Test name
Test status
Simulation time	2818464915 ps
CPU time	41.27 seconds
Started	Sep 03 11:45:59 PM UTC 24
Finished	Sep 03 11:46:42 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226268333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.3226268333
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/24.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.76179641
Short name	T546
Test name
Test status
Simulation time	59061481547 ps
CPU time	131.52 seconds
Started	Sep 03 11:46:01 PM UTC 24
Finished	Sep 03 11:48:15 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76179641 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.76179641
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/24.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.1482105636
Short name	T146
Test name
Test status
Simulation time	5114709164 ps
CPU time	48.93 seconds
Started	Sep 03 11:46:02 PM UTC 24
Finished	Sep 03 11:46:53 PM UTC 24
Peak memory	217220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482105636 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1482105636
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/24.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.3964583658
Short name	T500
Test name
Test status
Simulation time	64664075 ps
CPU time	6.49 seconds
Started	Sep 03 11:46:00 PM UTC 24
Finished	Sep 03 11:46:07 PM UTC 24
Peak memory	216752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964583658 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.3964583658
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/24.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.3617712488
Short name	T504
Test name
Test status
Simulation time	2088309252 ps
CPU time	18.46 seconds
Started	Sep 03 11:46:07 PM UTC 24
Finished	Sep 03 11:46:27 PM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617712488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3617712488
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/24.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.1063517167
Short name	T70
Test name
Test status
Simulation time	104663550 ps
CPU time	3.99 seconds
Started	Sep 03 11:45:53 PM UTC 24
Finished	Sep 03 11:45:58 PM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063517167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1063517167
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/24.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.403237290
Short name	T508
Test name
Test status
Simulation time	9104490194 ps
CPU time	42.35 seconds
Started	Sep 03 11:45:55 PM UTC 24
Finished	Sep 03 11:46:39 PM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403237290 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.403237290
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/24.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.4170118081
Short name	T341
Test name
Test status
Simulation time	3380210068 ps
CPU time	19.18 seconds
Started	Sep 03 11:45:58 PM UTC 24
Finished	Sep 03 11:46:18 PM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170118081 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.4170118081
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/24.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1863017308
Short name	T497
Test name
Test status
Simulation time	49279565 ps
CPU time	3.62 seconds
Started	Sep 03 11:45:54 PM UTC 24
Finished	Sep 03 11:45:59 PM UTC 24
Peak memory	217064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863017308 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1863017308
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/24.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.2801957741
Short name	T563
Test name
Test status
Simulation time	11875628942 ps
CPU time	169.97 seconds
Started	Sep 03 11:46:11 PM UTC 24
Finished	Sep 03 11:49:03 PM UTC 24
Peak memory	223172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801957741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2801957741
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/24.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.799925247
Short name	T544
Test name
Test status
Simulation time	6753426776 ps
CPU time	117.61 seconds
Started	Sep 03 11:46:14 PM UTC 24
Finished	Sep 03 11:48:14 PM UTC 24
Peak memory	220992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799925247 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.799925247
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/24.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.2536325128
Short name	T510
Test name
Test status
Simulation time	113010100 ps
CPU time	39.15 seconds
Started	Sep 03 11:46:14 PM UTC 24
Finished	Sep 03 11:46:55 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536325128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.2536325128
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/24.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.2754240519
Short name	T55
Test name
Test status
Simulation time	7914914896 ps
CPU time	343.9 seconds
Started	Sep 03 11:46:18 PM UTC 24
Finished	Sep 03 11:52:06 PM UTC 24
Peak memory	233592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754240519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.2754240519
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/24.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.693311424
Short name	T502
Test name
Test status
Simulation time	194663049 ps
CPU time	14.22 seconds
Started	Sep 03 11:46:10 PM UTC 24
Finished	Sep 03 11:46:25 PM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693311424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.693311424
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/24.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.234080099
Short name	T348
Test name
Test status
Simulation time	15839615608 ps
CPU time	123.28 seconds
Started	Sep 03 11:46:26 PM UTC 24
Finished	Sep 03 11:48:32 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234080099 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.234080099
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/25.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.213046217
Short name	T171
Test name
Test status
Simulation time	219627527 ps
CPU time	18.21 seconds
Started	Sep 03 11:46:29 PM UTC 24
Finished	Sep 03 11:46:49 PM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213046217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.213046217
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/25.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.1091809564
Short name	T509
Test name
Test status
Simulation time	238253370 ps
CPU time	22.72 seconds
Started	Sep 03 11:46:28 PM UTC 24
Finished	Sep 03 11:46:52 PM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091809564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1091809564
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/25.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random.2493187103
Short name	T145
Test name
Test status
Simulation time	97657937 ps
CPU time	15.2 seconds
Started	Sep 03 11:46:21 PM UTC 24
Finished	Sep 03 11:46:38 PM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493187103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.2493187103
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/25.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.501929332
Short name	T283
Test name
Test status
Simulation time	64383799420 ps
CPU time	198.81 seconds
Started	Sep 03 11:46:24 PM UTC 24
Finished	Sep 03 11:49:46 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501929332 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.501929332
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/25.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.2339065105
Short name	T591
Test name
Test status
Simulation time	34252105572 ps
CPU time	228.86 seconds
Started	Sep 03 11:46:24 PM UTC 24
Finished	Sep 03 11:50:17 PM UTC 24
Peak memory	219160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339065105 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2339065105
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/25.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.3923376419
Short name	T507
Test name
Test status
Simulation time	177982964 ps
CPU time	14.14 seconds
Started	Sep 03 11:46:23 PM UTC 24
Finished	Sep 03 11:46:39 PM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923376419 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.3923376419
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/25.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.2535111452
Short name	T517
Test name
Test status
Simulation time	2095907407 ps
CPU time	35.54 seconds
Started	Sep 03 11:46:28 PM UTC 24
Finished	Sep 03 11:47:05 PM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535111452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2535111452
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/25.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.4239890121
Short name	T503
Test name
Test status
Simulation time	164238758 ps
CPU time	4.95 seconds
Started	Sep 03 11:46:19 PM UTC 24
Finished	Sep 03 11:46:25 PM UTC 24
Peak memory	217072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239890121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.4239890121
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/25.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2778716911
Short name	T173
Test name
Test status
Simulation time	5394394401 ps
CPU time	28.93 seconds
Started	Sep 03 11:46:19 PM UTC 24
Finished	Sep 03 11:46:49 PM UTC 24
Peak memory	217204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778716911 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2778716911
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/25.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.2482614198
Short name	T518
Test name
Test status
Simulation time	3355528729 ps
CPU time	44.05 seconds
Started	Sep 03 11:46:21 PM UTC 24
Finished	Sep 03 11:47:07 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482614198 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2482614198
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/25.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.10348962
Short name	T345
Test name
Test status
Simulation time	62216986 ps
CPU time	2.93 seconds
Started	Sep 03 11:46:19 PM UTC 24
Finished	Sep 03 11:46:23 PM UTC 24
Peak memory	217132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10348962 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.10348962
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/25.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.2602963097
Short name	T166
Test name
Test status
Simulation time	9390402601 ps
CPU time	123.96 seconds
Started	Sep 03 11:46:32 PM UTC 24
Finished	Sep 03 11:48:39 PM UTC 24
Peak memory	220996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602963097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2602963097
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/25.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.4167598840
Short name	T571
Test name
Test status
Simulation time	4531901098 ps
CPU time	161.54 seconds
Started	Sep 03 11:46:36 PM UTC 24
Finished	Sep 03 11:49:21 PM UTC 24
Peak memory	220996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167598840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.4167598840
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/25.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.2358054102
Short name	T53
Test name
Test status
Simulation time	491465875 ps
CPU time	211.3 seconds
Started	Sep 03 11:46:34 PM UTC 24
Finished	Sep 03 11:50:09 PM UTC 24
Peak memory	220940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358054102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.2358054102
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/25.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.2541668779
Short name	T641
Test name
Test status
Simulation time	18828413447 ps
CPU time	290.46 seconds
Started	Sep 03 11:46:39 PM UTC 24
Finished	Sep 03 11:51:33 PM UTC 24
Peak memory	233656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541668779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.2541668779
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/25.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.722655028
Short name	T167
Test name
Test status
Simulation time	280633328 ps
CPU time	13.86 seconds
Started	Sep 03 11:46:28 PM UTC 24
Finished	Sep 03 11:46:43 PM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722655028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.722655028
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/25.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.3284415468
Short name	T72
Test name
Test status
Simulation time	5494300264 ps
CPU time	58.49 seconds
Started	Sep 03 11:46:47 PM UTC 24
Finished	Sep 03 11:47:47 PM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284415468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.3284415468
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/26.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1847948767
Short name	T672
Test name
Test status
Simulation time	41790570084 ps
CPU time	319.78 seconds
Started	Sep 03 11:46:50 PM UTC 24
Finished	Sep 03 11:52:14 PM UTC 24
Peak memory	218924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847948767 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.1847948767
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/26.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1512943436
Short name	T526
Test name
Test status
Simulation time	842108334 ps
CPU time	33.92 seconds
Started	Sep 03 11:46:53 PM UTC 24
Finished	Sep 03 11:47:28 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512943436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1512943436
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/26.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.2292012974
Short name	T524
Test name
Test status
Simulation time	939162115 ps
CPU time	29.33 seconds
Started	Sep 03 11:46:50 PM UTC 24
Finished	Sep 03 11:47:21 PM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292012974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2292012974
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/26.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random.3431253864
Short name	T211
Test name
Test status
Simulation time	1035926338 ps
CPU time	38.91 seconds
Started	Sep 03 11:46:43 PM UTC 24
Finished	Sep 03 11:47:24 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431253864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3431253864
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/26.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.865210567
Short name	T744
Test name
Test status
Simulation time	243032731080 ps
CPU time	440.96 seconds
Started	Sep 03 11:46:46 PM UTC 24
Finished	Sep 03 11:54:12 PM UTC 24
Peak memory	219208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865210567 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.865210567
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/26.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.2361365676
Short name	T514
Test name
Test status
Simulation time	2080473800 ps
CPU time	15 seconds
Started	Sep 03 11:46:46 PM UTC 24
Finished	Sep 03 11:47:02 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361365676 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2361365676
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/26.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.3127608828
Short name	T521
Test name
Test status
Simulation time	404517478 ps
CPU time	26.73 seconds
Started	Sep 03 11:46:45 PM UTC 24
Finished	Sep 03 11:47:13 PM UTC 24
Peak memory	216756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127608828 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3127608828
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/26.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.2883819930
Short name	T512
Test name
Test status
Simulation time	133279296 ps
CPU time	5.93 seconds
Started	Sep 03 11:46:50 PM UTC 24
Finished	Sep 03 11:46:57 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883819930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2883819930
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/26.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.327057220
Short name	T170
Test name
Test status
Simulation time	365134846 ps
CPU time	4.41 seconds
Started	Sep 03 11:46:40 PM UTC 24
Finished	Sep 03 11:46:46 PM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327057220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.327057220
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/26.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.1612072260
Short name	T530
Test name
Test status
Simulation time	14304172182 ps
CPU time	48.3 seconds
Started	Sep 03 11:46:41 PM UTC 24
Finished	Sep 03 11:47:31 PM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612072260 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1612072260
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/26.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.2758409204
Short name	T523
Test name
Test status
Simulation time	11604369040 ps
CPU time	33.4 seconds
Started	Sep 03 11:46:42 PM UTC 24
Finished	Sep 03 11:47:17 PM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758409204 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.2758409204
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/26.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1703891002
Short name	T169
Test name
Test status
Simulation time	35946837 ps
CPU time	3.35 seconds
Started	Sep 03 11:46:40 PM UTC 24
Finished	Sep 03 11:46:45 PM UTC 24
Peak memory	217064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703891002 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1703891002
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/26.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.3636773760
Short name	T602
Test name
Test status
Simulation time	6916931729 ps
CPU time	213.71 seconds
Started	Sep 03 11:46:54 PM UTC 24
Finished	Sep 03 11:50:31 PM UTC 24
Peak memory	223304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636773760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3636773760
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/26.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1684812189
Short name	T585
Test name
Test status
Simulation time	8560547943 ps
CPU time	185.33 seconds
Started	Sep 03 11:46:58 PM UTC 24
Finished	Sep 03 11:50:06 PM UTC 24
Peak memory	219272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684812189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1684812189
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/26.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.3403844473
Short name	T620
Test name
Test status
Simulation time	1934445901 ps
CPU time	246.62 seconds
Started	Sep 03 11:46:56 PM UTC 24
Finished	Sep 03 11:51:06 PM UTC 24
Peak memory	221196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403844473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.3403844473
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/26.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2315872672
Short name	T185
Test name
Test status
Simulation time	368301987 ps
CPU time	83.52 seconds
Started	Sep 03 11:46:58 PM UTC 24
Finished	Sep 03 11:48:23 PM UTC 24
Peak memory	221132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315872672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.2315872672
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/26.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.4245297539
Short name	T515
Test name
Test status
Simulation time	238590448 ps
CPU time	9.51 seconds
Started	Sep 03 11:46:53 PM UTC 24
Finished	Sep 03 11:47:04 PM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245297539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.4245297539
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/26.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.3828121394
Short name	T176
Test name
Test status
Simulation time	1558945507 ps
CPU time	26.86 seconds
Started	Sep 03 11:47:14 PM UTC 24
Finished	Sep 03 11:47:42 PM UTC 24
Peak memory	218892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828121394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.3828121394
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/27.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.3326418030
Short name	T373
Test name
Test status
Simulation time	13642006499 ps
CPU time	114.76 seconds
Started	Sep 03 11:47:15 PM UTC 24
Finished	Sep 03 11:49:12 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326418030 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.3326418030
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/27.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.1348645322
Short name	T533
Test name
Test status
Simulation time	632543164 ps
CPU time	16.36 seconds
Started	Sep 03 11:47:22 PM UTC 24
Finished	Sep 03 11:47:39 PM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348645322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.1348645322
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/27.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.2964072568
Short name	T181
Test name
Test status
Simulation time	859072326 ps
CPU time	33.25 seconds
Started	Sep 03 11:47:19 PM UTC 24
Finished	Sep 03 11:47:54 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964072568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2964072568
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/27.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random.2197159508
Short name	T114
Test name
Test status
Simulation time	1053217314 ps
CPU time	14.26 seconds
Started	Sep 03 11:47:06 PM UTC 24
Finished	Sep 03 11:47:21 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197159508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.2197159508
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/27.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.3344729216
Short name	T643
Test name
Test status
Simulation time	59277982664 ps
CPU time	262.09 seconds
Started	Sep 03 11:47:08 PM UTC 24
Finished	Sep 03 11:51:35 PM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344729216 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3344729216
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/27.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.1741272975
Short name	T529
Test name
Test status
Simulation time	8601693152 ps
CPU time	20.35 seconds
Started	Sep 03 11:47:09 PM UTC 24
Finished	Sep 03 11:47:31 PM UTC 24
Peak memory	217152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741272975 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1741272975
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/27.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.2688782995
Short name	T525
Test name
Test status
Simulation time	93119358 ps
CPU time	13.79 seconds
Started	Sep 03 11:47:08 PM UTC 24
Finished	Sep 03 11:47:23 PM UTC 24
Peak memory	216756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688782995 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2688782995
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/27.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.2003358832
Short name	T178
Test name
Test status
Simulation time	1432521569 ps
CPU time	27.14 seconds
Started	Sep 03 11:47:18 PM UTC 24
Finished	Sep 03 11:47:47 PM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003358832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2003358832
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/27.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.1548466114
Short name	T520
Test name
Test status
Simulation time	187678652 ps
CPU time	4.6 seconds
Started	Sep 03 11:47:02 PM UTC 24
Finished	Sep 03 11:47:08 PM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548466114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1548466114
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/27.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.432279563
Short name	T177
Test name
Test status
Simulation time	4814593868 ps
CPU time	38.85 seconds
Started	Sep 03 11:47:04 PM UTC 24
Finished	Sep 03 11:47:45 PM UTC 24
Peak memory	217200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432279563 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.432279563
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/27.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3944642916
Short name	T527
Test name
Test status
Simulation time	3007308974 ps
CPU time	21.71 seconds
Started	Sep 03 11:47:06 PM UTC 24
Finished	Sep 03 11:47:29 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944642916 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3944642916
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/27.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1239521698
Short name	T519
Test name
Test status
Simulation time	79845585 ps
CPU time	3.27 seconds
Started	Sep 03 11:47:03 PM UTC 24
Finished	Sep 03 11:47:07 PM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239521698 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.1239521698
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/27.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.4014881401
Short name	T558
Test name
Test status
Simulation time	559829661 ps
CPU time	88.67 seconds
Started	Sep 03 11:47:22 PM UTC 24
Finished	Sep 03 11:48:53 PM UTC 24
Peak memory	220928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014881401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.4014881401
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/27.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3220200619
Short name	T545
Test name
Test status
Simulation time	4964559896 ps
CPU time	48.91 seconds
Started	Sep 03 11:47:24 PM UTC 24
Finished	Sep 03 11:48:15 PM UTC 24
Peak memory	217032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220200619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3220200619
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/27.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3810607401
Short name	T241
Test name
Test status
Simulation time	385595387 ps
CPU time	161.99 seconds
Started	Sep 03 11:47:24 PM UTC 24
Finished	Sep 03 11:50:09 PM UTC 24
Peak memory	220936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810607401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.3810607401
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/27.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.4059591629
Short name	T622
Test name
Test status
Simulation time	654472969 ps
CPU time	219.14 seconds
Started	Sep 03 11:47:25 PM UTC 24
Finished	Sep 03 11:51:08 PM UTC 24
Peak memory	233528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059591629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.4059591629
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/27.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.3610992225
Short name	T179
Test name
Test status
Simulation time	162308143 ps
CPU time	25.88 seconds
Started	Sep 03 11:47:22 PM UTC 24
Finished	Sep 03 11:47:49 PM UTC 24
Peak memory	218820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610992225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3610992225
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/27.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.1880321245
Short name	T118
Test name
Test status
Simulation time	956680201 ps
CPU time	37.06 seconds
Started	Sep 03 11:47:42 PM UTC 24
Finished	Sep 03 11:48:21 PM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880321245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1880321245
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/28.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.3414759878
Short name	T656
Test name
Test status
Simulation time	44412308062 ps
CPU time	252.25 seconds
Started	Sep 03 11:47:42 PM UTC 24
Finished	Sep 03 11:51:58 PM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414759878 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.3414759878
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/28.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.781405873
Short name	T536
Test name
Test status
Simulation time	695792615 ps
CPU time	11.9 seconds
Started	Sep 03 11:47:50 PM UTC 24
Finished	Sep 03 11:48:04 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781405873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.781405873
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/28.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.3185467316
Short name	T547
Test name
Test status
Simulation time	572981863 ps
CPU time	27.67 seconds
Started	Sep 03 11:47:48 PM UTC 24
Finished	Sep 03 11:48:17 PM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185467316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3185467316
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/28.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random.871664091
Short name	T187
Test name
Test status
Simulation time	2054681476 ps
CPU time	54.25 seconds
Started	Sep 03 11:47:33 PM UTC 24
Finished	Sep 03 11:48:29 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871664091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.871664091
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/28.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.2791331152
Short name	T617
Test name
Test status
Simulation time	40482101072 ps
CPU time	200.59 seconds
Started	Sep 03 11:47:35 PM UTC 24
Finished	Sep 03 11:50:59 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791331152 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2791331152
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/28.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.1882304629
Short name	T615
Test name
Test status
Simulation time	24489490871 ps
CPU time	188.68 seconds
Started	Sep 03 11:47:40 PM UTC 24
Finished	Sep 03 11:50:52 PM UTC 24
Peak memory	217160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882304629 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.1882304629
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/28.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.284669111
Short name	T182
Test name
Test status
Simulation time	188222869 ps
CPU time	24.3 seconds
Started	Sep 03 11:47:35 PM UTC 24
Finished	Sep 03 11:48:00 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284669111 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.284669111
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/28.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.607427480
Short name	T542
Test name
Test status
Simulation time	1409319993 ps
CPU time	22.99 seconds
Started	Sep 03 11:47:46 PM UTC 24
Finished	Sep 03 11:48:10 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607427480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.607427480
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/28.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.401409864
Short name	T531
Test name
Test status
Simulation time	46852694 ps
CPU time	3.16 seconds
Started	Sep 03 11:47:30 PM UTC 24
Finished	Sep 03 11:47:34 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401409864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.401409864
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/28.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.1467186551
Short name	T561
Test name
Test status
Simulation time	33974080257 ps
CPU time	84.96 seconds
Started	Sep 03 11:47:31 PM UTC 24
Finished	Sep 03 11:48:58 PM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467186551 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1467186551
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/28.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.480230486
Short name	T538
Test name
Test status
Simulation time	11504246951 ps
CPU time	35.56 seconds
Started	Sep 03 11:47:31 PM UTC 24
Finished	Sep 03 11:48:08 PM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480230486 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.480230486
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/28.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.3935982852
Short name	T532
Test name
Test status
Simulation time	30830064 ps
CPU time	3.31 seconds
Started	Sep 03 11:47:30 PM UTC 24
Finished	Sep 03 11:47:34 PM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935982852 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3935982852
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/28.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.343671271
Short name	T125
Test name
Test status
Simulation time	7243849850 ps
CPU time	257.66 seconds
Started	Sep 03 11:47:50 PM UTC 24
Finished	Sep 03 11:52:12 PM UTC 24
Peak memory	220928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343671271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.343671271
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/28.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.2514373170
Short name	T584
Test name
Test status
Simulation time	14198525713 ps
CPU time	122.06 seconds
Started	Sep 03 11:48:00 PM UTC 24
Finished	Sep 03 11:50:04 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514373170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2514373170
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/28.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.3073659892
Short name	T43
Test name
Test status
Simulation time	1160467265 ps
CPU time	240.82 seconds
Started	Sep 03 11:47:55 PM UTC 24
Finished	Sep 03 11:51:59 PM UTC 24
Peak memory	223244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073659892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.3073659892
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/28.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.328321773
Short name	T665
Test name
Test status
Simulation time	2056415267 ps
CPU time	242.07 seconds
Started	Sep 03 11:48:01 PM UTC 24
Finished	Sep 03 11:52:07 PM UTC 24
Peak memory	233588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328321773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.328321773
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/28.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.1986690213
Short name	T543
Test name
Test status
Simulation time	193994381 ps
CPU time	22.69 seconds
Started	Sep 03 11:47:48 PM UTC 24
Finished	Sep 03 11:48:12 PM UTC 24
Peak memory	218880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986690213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1986690213
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/28.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.2709773667
Short name	T120
Test name
Test status
Simulation time	939694014 ps
CPU time	41.16 seconds
Started	Sep 03 11:48:12 PM UTC 24
Finished	Sep 03 11:48:55 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709773667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.2709773667
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/29.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2846582247
Short name	T299
Test name
Test status
Simulation time	417633159109 ps
CPU time	942.98 seconds
Started	Sep 03 11:48:13 PM UTC 24
Finished	Sep 04 12:04:06 AM UTC 24
Peak memory	220564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846582247 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.2846582247
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/29.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.3552808664
Short name	T548
Test name
Test status
Simulation time	362041375 ps
CPU time	12.38 seconds
Started	Sep 03 11:48:18 PM UTC 24
Finished	Sep 03 11:48:31 PM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552808664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.3552808664
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/29.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.3693007756
Short name	T549
Test name
Test status
Simulation time	1365018265 ps
CPU time	16.85 seconds
Started	Sep 03 11:48:16 PM UTC 24
Finished	Sep 03 11:48:34 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693007756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3693007756
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/29.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random.1675991793
Short name	T188
Test name
Test status
Simulation time	107168466 ps
CPU time	19.54 seconds
Started	Sep 03 11:48:09 PM UTC 24
Finished	Sep 03 11:48:30 PM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675991793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.1675991793
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/29.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.4046374722
Short name	T710
Test name
Test status
Simulation time	43011633563 ps
CPU time	297.93 seconds
Started	Sep 03 11:48:12 PM UTC 24
Finished	Sep 03 11:53:14 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046374722 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.4046374722
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/29.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1638906693
Short name	T668
Test name
Test status
Simulation time	66422743205 ps
CPU time	234.72 seconds
Started	Sep 03 11:48:12 PM UTC 24
Finished	Sep 03 11:52:10 PM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638906693 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1638906693
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/29.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.296835157
Short name	T184
Test name
Test status
Simulation time	71422065 ps
CPU time	11.26 seconds
Started	Sep 03 11:48:10 PM UTC 24
Finished	Sep 03 11:48:23 PM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296835157 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.296835157
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/29.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.570683228
Short name	T183
Test name
Test status
Simulation time	153133398 ps
CPU time	5.77 seconds
Started	Sep 03 11:48:16 PM UTC 24
Finished	Sep 03 11:48:23 PM UTC 24
Peak memory	217080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570683228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.570683228
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/29.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.75709627
Short name	T541
Test name
Test status
Simulation time	245945078 ps
CPU time	5.61 seconds
Started	Sep 03 11:48:03 PM UTC 24
Finished	Sep 03 11:48:10 PM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75709627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.75709627
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/29.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.1202989755
Short name	T556
Test name
Test status
Simulation time	10918848473 ps
CPU time	40.01 seconds
Started	Sep 03 11:48:05 PM UTC 24
Finished	Sep 03 11:48:47 PM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202989755 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1202989755
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/29.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.3944248711
Short name	T550
Test name
Test status
Simulation time	4216065713 ps
CPU time	25.68 seconds
Started	Sep 03 11:48:08 PM UTC 24
Finished	Sep 03 11:48:35 PM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944248711 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3944248711
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/29.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.1917119974
Short name	T539
Test name
Test status
Simulation time	27123692 ps
CPU time	2.67 seconds
Started	Sep 03 11:48:05 PM UTC 24
Finished	Sep 03 11:48:09 PM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917119974 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.1917119974
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/29.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.388257593
Short name	T599
Test name
Test status
Simulation time	1056955804 ps
CPU time	121.5 seconds
Started	Sep 03 11:48:19 PM UTC 24
Finished	Sep 03 11:50:23 PM UTC 24
Peak memory	220928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388257593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.388257593
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/29.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.2404444498
Short name	T553
Test name
Test status
Simulation time	2003923652 ps
CPU time	17.68 seconds
Started	Sep 03 11:48:24 PM UTC 24
Finished	Sep 03 11:48:43 PM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404444498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2404444498
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/29.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.3277335263
Short name	T576
Test name
Test status
Simulation time	68051373 ps
CPU time	63.15 seconds
Started	Sep 03 11:48:21 PM UTC 24
Finished	Sep 03 11:49:26 PM UTC 24
Peak memory	220936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277335263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.3277335263
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/29.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.138196513
Short name	T566
Test name
Test status
Simulation time	130479043 ps
CPU time	49.79 seconds
Started	Sep 03 11:48:24 PM UTC 24
Finished	Sep 03 11:49:15 PM UTC 24
Peak memory	219204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138196513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.138196513
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/29.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.248803561
Short name	T552
Test name
Test status
Simulation time	1739852127 ps
CPU time	24.82 seconds
Started	Sep 03 11:48:16 PM UTC 24
Finished	Sep 03 11:48:42 PM UTC 24
Peak memory	218880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248803561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.248803561
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/29.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.3028821568
Short name	T269
Test name
Test status
Simulation time	1877390083 ps
CPU time	48.85 seconds
Started	Sep 03 11:38:19 PM UTC 24
Finished	Sep 03 11:39:09 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028821568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.3028821568
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/3.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.920888602
Short name	T246
Test name
Test status
Simulation time	252797920 ps
CPU time	7.55 seconds
Started	Sep 03 11:38:21 PM UTC 24
Finished	Sep 03 11:38:29 PM UTC 24
Peak memory	216904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920888602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.920888602
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/3.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.4170809811
Short name	T82
Test name
Test status
Simulation time	1196236322 ps
CPU time	33.94 seconds
Started	Sep 03 11:38:19 PM UTC 24
Finished	Sep 03 11:38:54 PM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170809811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.4170809811
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/3.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random.2525897882
Short name	T29
Test name
Test status
Simulation time	309787601 ps
CPU time	6.86 seconds
Started	Sep 03 11:38:15 PM UTC 24
Finished	Sep 03 11:38:23 PM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525897882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.2525897882
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/3.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.303622728
Short name	T196
Test name
Test status
Simulation time	61489424763 ps
CPU time	275.86 seconds
Started	Sep 03 11:38:15 PM UTC 24
Finished	Sep 03 11:42:55 PM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303622728 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.303622728
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/3.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.4059804541
Short name	T104
Test name
Test status
Simulation time	17121900041 ps
CPU time	126 seconds
Started	Sep 03 11:38:17 PM UTC 24
Finished	Sep 03 11:40:26 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059804541 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.4059804541
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/3.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.2723178451
Short name	T325
Test name
Test status
Simulation time	198118766 ps
CPU time	22.14 seconds
Started	Sep 03 11:38:15 PM UTC 24
Finished	Sep 03 11:38:39 PM UTC 24
Peak memory	217080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723178451 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2723178451
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/3.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.1189288066
Short name	T243
Test name
Test status
Simulation time	64650202 ps
CPU time	4.02 seconds
Started	Sep 03 11:38:19 PM UTC 24
Finished	Sep 03 11:38:24 PM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189288066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1189288066
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/3.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.2067320714
Short name	T390
Test name
Test status
Simulation time	30591042 ps
CPU time	3.05 seconds
Started	Sep 03 11:38:11 PM UTC 24
Finished	Sep 03 11:38:15 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067320714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2067320714
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/3.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3272001517
Short name	T327
Test name
Test status
Simulation time	4896520586 ps
CPU time	27.45 seconds
Started	Sep 03 11:38:13 PM UTC 24
Finished	Sep 03 11:38:42 PM UTC 24
Peak memory	216948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272001517 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3272001517
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/3.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.881589215
Short name	T85
Test name
Test status
Simulation time	10704078082 ps
CPU time	45.92 seconds
Started	Sep 03 11:38:13 PM UTC 24
Finished	Sep 03 11:39:01 PM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881589215 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.881589215
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/3.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1398686294
Short name	T389
Test name
Test status
Simulation time	26252618 ps
CPU time	2.87 seconds
Started	Sep 03 11:38:11 PM UTC 24
Finished	Sep 03 11:38:15 PM UTC 24
Peak memory	216744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398686294 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1398686294
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/3.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.2995009097
Short name	T355
Test name
Test status
Simulation time	1403691608 ps
CPU time	112.36 seconds
Started	Sep 03 11:38:21 PM UTC 24
Finished	Sep 03 11:40:15 PM UTC 24
Peak memory	221252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995009097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2995009097
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/3.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.2771644336
Short name	T54
Test name
Test status
Simulation time	3049971979 ps
CPU time	54.21 seconds
Started	Sep 03 11:38:22 PM UTC 24
Finished	Sep 03 11:39:18 PM UTC 24
Peak memory	218876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771644336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2771644336
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/3.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.1590886496
Short name	T216
Test name
Test status
Simulation time	718228568 ps
CPU time	250.39 seconds
Started	Sep 03 11:38:21 PM UTC 24
Finished	Sep 03 11:42:35 PM UTC 24
Peak memory	222984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590886496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.1590886496
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/3.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.2655778127
Short name	T42
Test name
Test status
Simulation time	3300698881 ps
CPU time	213.47 seconds
Started	Sep 03 11:38:22 PM UTC 24
Finished	Sep 03 11:41:59 PM UTC 24
Peak memory	223480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655778127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.2655778127
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/3.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.2045094299
Short name	T326
Test name
Test status
Simulation time	203651971 ps
CPU time	20.43 seconds
Started	Sep 03 11:38:19 PM UTC 24
Finished	Sep 03 11:38:41 PM UTC 24
Peak memory	218816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045094299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2045094299
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/3.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.2276475096
Short name	T567
Test name
Test status
Simulation time	504070266 ps
CPU time	41.86 seconds
Started	Sep 03 11:48:33 PM UTC 24
Finished	Sep 03 11:49:17 PM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276475096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.2276475096
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/30.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.1644582444
Short name	T255
Test name
Test status
Simulation time	124294822760 ps
CPU time	606.71 seconds
Started	Sep 03 11:48:35 PM UTC 24
Finished	Sep 03 11:58:49 PM UTC 24
Peak memory	222616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644582444 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.1644582444
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/30.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3301292565
Short name	T562
Test name
Test status
Simulation time	286232795 ps
CPU time	15.33 seconds
Started	Sep 03 11:48:43 PM UTC 24
Finished	Sep 03 11:48:59 PM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301292565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3301292565
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/30.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.1942258977
Short name	T557
Test name
Test status
Simulation time	742919585 ps
CPU time	8.25 seconds
Started	Sep 03 11:48:38 PM UTC 24
Finished	Sep 03 11:48:47 PM UTC 24
Peak memory	216888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942258977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1942258977
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/30.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random.152380990
Short name	T74
Test name
Test status
Simulation time	965551747 ps
CPU time	36.75 seconds
Started	Sep 03 11:48:31 PM UTC 24
Finished	Sep 03 11:49:09 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152380990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.152380990
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/30.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.3108848886
Short name	T698
Test name
Test status
Simulation time	31416609969 ps
CPU time	257.85 seconds
Started	Sep 03 11:48:32 PM UTC 24
Finished	Sep 03 11:52:54 PM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108848886 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.3108848886
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/30.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1477688168
Short name	T718
Test name
Test status
Simulation time	152512722402 ps
CPU time	290.07 seconds
Started	Sep 03 11:48:32 PM UTC 24
Finished	Sep 03 11:53:26 PM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477688168 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1477688168
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/30.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.1355336256
Short name	T551
Test name
Test status
Simulation time	25047681 ps
CPU time	4.96 seconds
Started	Sep 03 11:48:31 PM UTC 24
Finished	Sep 03 11:48:37 PM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355336256 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.1355336256
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/30.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.3452716053
Short name	T564
Test name
Test status
Simulation time	2608991386 ps
CPU time	34.49 seconds
Started	Sep 03 11:48:36 PM UTC 24
Finished	Sep 03 11:49:12 PM UTC 24
Peak memory	217152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452716053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3452716053
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/30.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.716695054
Short name	T534
Test name
Test status
Simulation time	34280099 ps
CPU time	2.15 seconds
Started	Sep 03 11:48:25 PM UTC 24
Finished	Sep 03 11:48:28 PM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716695054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.716695054
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/30.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.3508572134
Short name	T568
Test name
Test status
Simulation time	18497930010 ps
CPU time	46.48 seconds
Started	Sep 03 11:48:30 PM UTC 24
Finished	Sep 03 11:49:18 PM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508572134 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3508572134
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/30.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2757792014
Short name	T569
Test name
Test status
Simulation time	5365721499 ps
CPU time	46.51 seconds
Started	Sep 03 11:48:30 PM UTC 24
Finished	Sep 03 11:49:18 PM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757792014 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2757792014
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/30.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.56740732
Short name	T190
Test name
Test status
Simulation time	42614711 ps
CPU time	2.46 seconds
Started	Sep 03 11:48:27 PM UTC 24
Finished	Sep 03 11:48:31 PM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56740732 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.56740732
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/30.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.976678833
Short name	T122
Test name
Test status
Simulation time	4216896325 ps
CPU time	110.26 seconds
Started	Sep 03 11:48:43 PM UTC 24
Finished	Sep 03 11:50:35 PM UTC 24
Peak memory	218944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976678833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.976678833
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/30.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2627190115
Short name	T565
Test name
Test status
Simulation time	346656558 ps
CPU time	26.63 seconds
Started	Sep 03 11:48:45 PM UTC 24
Finished	Sep 03 11:49:13 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627190115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2627190115
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/30.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.739169039
Short name	T773
Test name
Test status
Simulation time	740344419 ps
CPU time	364.66 seconds
Started	Sep 03 11:48:45 PM UTC 24
Finished	Sep 03 11:54:55 PM UTC 24
Peak memory	222912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739169039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.739169039
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/30.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.4030148593
Short name	T287
Test name
Test status
Simulation time	227062231 ps
CPU time	67.42 seconds
Started	Sep 03 11:48:47 PM UTC 24
Finished	Sep 03 11:49:56 PM UTC 24
Peak memory	220936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030148593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.4030148593
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/30.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.167504338
Short name	T554
Test name
Test status
Simulation time	49775161 ps
CPU time	2.88 seconds
Started	Sep 03 11:48:39 PM UTC 24
Finished	Sep 03 11:48:43 PM UTC 24
Peak memory	217148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167504338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.167504338
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/30.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.3845322556
Short name	T121
Test name
Test status
Simulation time	1921504483 ps
CPU time	36.1 seconds
Started	Sep 03 11:49:01 PM UTC 24
Finished	Sep 03 11:49:38 PM UTC 24
Peak memory	216844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845322556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3845322556
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/31.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1230553745
Short name	T139
Test name
Test status
Simulation time	11542956269 ps
CPU time	119.8 seconds
Started	Sep 03 11:49:04 PM UTC 24
Finished	Sep 03 11:51:06 PM UTC 24
Peak memory	219208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230553745 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.1230553745
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/31.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.331581576
Short name	T570
Test name
Test status
Simulation time	61297672 ps
CPU time	5.63 seconds
Started	Sep 03 11:49:14 PM UTC 24
Finished	Sep 03 11:49:20 PM UTC 24
Peak memory	216968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331581576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.331581576
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/31.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.3608031644
Short name	T579
Test name
Test status
Simulation time	540591724 ps
CPU time	16.84 seconds
Started	Sep 03 11:49:14 PM UTC 24
Finished	Sep 03 11:49:32 PM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608031644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3608031644
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/31.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random.3711921639
Short name	T281
Test name
Test status
Simulation time	1172451071 ps
CPU time	45.19 seconds
Started	Sep 03 11:48:55 PM UTC 24
Finished	Sep 03 11:49:42 PM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711921639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.3711921639
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/31.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.3871806102
Short name	T580
Test name
Test status
Simulation time	5598073608 ps
CPU time	36.9 seconds
Started	Sep 03 11:48:56 PM UTC 24
Finished	Sep 03 11:49:35 PM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871806102 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3871806102
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/31.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1301596113
Short name	T666
Test name
Test status
Simulation time	49067155820 ps
CPU time	186.42 seconds
Started	Sep 03 11:49:00 PM UTC 24
Finished	Sep 03 11:52:09 PM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301596113 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1301596113
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/31.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.3038892651
Short name	T242
Test name
Test status
Simulation time	168107445 ps
CPU time	25.51 seconds
Started	Sep 03 11:48:55 PM UTC 24
Finished	Sep 03 11:49:22 PM UTC 24
Peak memory	216752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038892651 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3038892651
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/31.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.55206021
Short name	T573
Test name
Test status
Simulation time	355436312 ps
CPU time	13.31 seconds
Started	Sep 03 11:49:10 PM UTC 24
Finished	Sep 03 11:49:25 PM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55206021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.55206021
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/31.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.2096948754
Short name	T560
Test name
Test status
Simulation time	758591413 ps
CPU time	6.24 seconds
Started	Sep 03 11:48:49 PM UTC 24
Finished	Sep 03 11:48:56 PM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096948754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2096948754
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/31.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.696432218
Short name	T280
Test name
Test status
Simulation time	9163416017 ps
CPU time	45.35 seconds
Started	Sep 03 11:48:54 PM UTC 24
Finished	Sep 03 11:49:41 PM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696432218 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.696432218
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/31.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.2191009359
Short name	T577
Test name
Test status
Simulation time	4298789422 ps
CPU time	33.59 seconds
Started	Sep 03 11:48:54 PM UTC 24
Finished	Sep 03 11:49:29 PM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191009359 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2191009359
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/31.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3422878533
Short name	T559
Test name
Test status
Simulation time	35381623 ps
CPU time	3.29 seconds
Started	Sep 03 11:48:49 PM UTC 24
Finished	Sep 03 11:48:53 PM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422878533 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3422878533
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/31.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.3887077921
Short name	T598
Test name
Test status
Simulation time	2828381778 ps
CPU time	65.75 seconds
Started	Sep 03 11:49:15 PM UTC 24
Finished	Sep 03 11:50:23 PM UTC 24
Peak memory	218940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887077921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3887077921
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/31.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.1757082830
Short name	T632
Test name
Test status
Simulation time	5776556623 ps
CPU time	120.58 seconds
Started	Sep 03 11:49:17 PM UTC 24
Finished	Sep 03 11:51:20 PM UTC 24
Peak memory	220932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757082830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1757082830
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/31.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.2952704828
Short name	T346
Test name
Test status
Simulation time	4617724976 ps
CPU time	359.54 seconds
Started	Sep 03 11:49:16 PM UTC 24
Finished	Sep 03 11:55:21 PM UTC 24
Peak memory	220936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952704828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.2952704828
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/31.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3586717213
Short name	T578
Test name
Test status
Simulation time	7357134 ps
CPU time	9.75 seconds
Started	Sep 03 11:49:19 PM UTC 24
Finished	Sep 03 11:49:30 PM UTC 24
Peak memory	216760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586717213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.3586717213
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/31.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.2632747841
Short name	T574
Test name
Test status
Simulation time	47475899 ps
CPU time	10.32 seconds
Started	Sep 03 11:49:14 PM UTC 24
Finished	Sep 03 11:49:25 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632747841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.2632747841
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/31.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.239687753
Short name	T594
Test name
Test status
Simulation time	3209980737 ps
CPU time	52.49 seconds
Started	Sep 03 11:49:27 PM UTC 24
Finished	Sep 03 11:50:21 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239687753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.239687753
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/32.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.218398207
Short name	T628
Test name
Test status
Simulation time	11701560418 ps
CPU time	102.95 seconds
Started	Sep 03 11:49:29 PM UTC 24
Finished	Sep 03 11:51:15 PM UTC 24
Peak memory	216904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218398207 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.218398207
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/32.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.962255287
Short name	T583
Test name
Test status
Simulation time	214533189 ps
CPU time	21.7 seconds
Started	Sep 03 11:49:36 PM UTC 24
Finished	Sep 03 11:50:00 PM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962255287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.962255287
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/32.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.864545792
Short name	T582
Test name
Test status
Simulation time	237924392 ps
CPU time	4.06 seconds
Started	Sep 03 11:49:33 PM UTC 24
Finished	Sep 03 11:49:38 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864545792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.864545792
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/32.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random.2872387654
Short name	T282
Test name
Test status
Simulation time	860806956 ps
CPU time	18.81 seconds
Started	Sep 03 11:49:25 PM UTC 24
Finished	Sep 03 11:49:45 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872387654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.2872387654
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/32.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.1755162829
Short name	T727
Test name
Test status
Simulation time	41583260287 ps
CPU time	250.7 seconds
Started	Sep 03 11:49:26 PM UTC 24
Finished	Sep 03 11:53:40 PM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755162829 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1755162829
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/32.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.2729623826
Short name	T721
Test name
Test status
Simulation time	26485156850 ps
CPU time	242.2 seconds
Started	Sep 03 11:49:27 PM UTC 24
Finished	Sep 03 11:53:33 PM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729623826 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2729623826
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/32.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.479825295
Short name	T286
Test name
Test status
Simulation time	211581302 ps
CPU time	28.67 seconds
Started	Sep 03 11:49:26 PM UTC 24
Finished	Sep 03 11:49:56 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479825295 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.479825295
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/32.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.3257522409
Short name	T288
Test name
Test status
Simulation time	2089912038 ps
CPU time	25.35 seconds
Started	Sep 03 11:49:32 PM UTC 24
Finished	Sep 03 11:49:58 PM UTC 24
Peak memory	217152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257522409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3257522409
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/32.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.526553946
Short name	T572
Test name
Test status
Simulation time	26233321 ps
CPU time	2.45 seconds
Started	Sep 03 11:49:19 PM UTC 24
Finished	Sep 03 11:49:23 PM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526553946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.526553946
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/32.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.3525483458
Short name	T75
Test name
Test status
Simulation time	4187221423 ps
CPU time	34.39 seconds
Started	Sep 03 11:49:23 PM UTC 24
Finished	Sep 03 11:49:59 PM UTC 24
Peak memory	216884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525483458 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3525483458
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/32.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2189949975
Short name	T586
Test name
Test status
Simulation time	12093300513 ps
CPU time	48.05 seconds
Started	Sep 03 11:49:23 PM UTC 24
Finished	Sep 03 11:50:13 PM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189949975 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2189949975
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/32.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.197797318
Short name	T575
Test name
Test status
Simulation time	30209931 ps
CPU time	3.26 seconds
Started	Sep 03 11:49:21 PM UTC 24
Finished	Sep 03 11:49:26 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197797318 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.197797318
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/32.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.437377775
Short name	T644
Test name
Test status
Simulation time	906704628 ps
CPU time	115.72 seconds
Started	Sep 03 11:49:38 PM UTC 24
Finished	Sep 03 11:51:36 PM UTC 24
Peak memory	220864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437377775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.437377775
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/32.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1397331604
Short name	T621
Test name
Test status
Simulation time	893059444 ps
CPU time	84.47 seconds
Started	Sep 03 11:49:40 PM UTC 24
Finished	Sep 03 11:51:06 PM UTC 24
Peak memory	220936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397331604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1397331604
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/32.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.1622042150
Short name	T739
Test name
Test status
Simulation time	1779001295 ps
CPU time	265.33 seconds
Started	Sep 03 11:49:40 PM UTC 24
Finished	Sep 03 11:54:09 PM UTC 24
Peak memory	221132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622042150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.1622042150
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/32.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.879844736
Short name	T775
Test name
Test status
Simulation time	4708646489 ps
CPU time	309.7 seconds
Started	Sep 03 11:49:42 PM UTC 24
Finished	Sep 03 11:54:56 PM UTC 24
Peak memory	233588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879844736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.879844736
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/32.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.2309319399
Short name	T581
Test name
Test status
Simulation time	162402784 ps
CPU time	3.48 seconds
Started	Sep 03 11:49:33 PM UTC 24
Finished	Sep 03 11:49:38 PM UTC 24
Peak memory	217068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309319399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2309319399
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/32.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.156094258
Short name	T600
Test name
Test status
Simulation time	517563988 ps
CPU time	22.61 seconds
Started	Sep 03 11:50:00 PM UTC 24
Finished	Sep 03 11:50:24 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156094258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.156094258
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/33.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3824053519
Short name	T897
Test name
Test status
Simulation time	93965061573 ps
CPU time	833.63 seconds
Started	Sep 03 11:50:00 PM UTC 24
Finished	Sep 04 12:04:03 AM UTC 24
Peak memory	222612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824053519 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.3824053519
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/33.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.1861387068
Short name	T588
Test name
Test status
Simulation time	112514611 ps
CPU time	4.64 seconds
Started	Sep 03 11:50:10 PM UTC 24
Finished	Sep 03 11:50:16 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861387068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.1861387068
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/33.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.2005397132
Short name	T592
Test name
Test status
Simulation time	629016573 ps
CPU time	12.61 seconds
Started	Sep 03 11:50:06 PM UTC 24
Finished	Sep 03 11:50:19 PM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005397132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.2005397132
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/33.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random.1731475199
Short name	T587
Test name
Test status
Simulation time	136107677 ps
CPU time	24.49 seconds
Started	Sep 03 11:49:50 PM UTC 24
Finished	Sep 03 11:50:16 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731475199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.1731475199
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/33.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.1121090021
Short name	T607
Test name
Test status
Simulation time	9382338689 ps
CPU time	43.35 seconds
Started	Sep 03 11:49:58 PM UTC 24
Finished	Sep 03 11:50:42 PM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121090021 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.1121090021
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/33.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.121172265
Short name	T679
Test name
Test status
Simulation time	16823937240 ps
CPU time	140.88 seconds
Started	Sep 03 11:49:59 PM UTC 24
Finished	Sep 03 11:52:22 PM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121172265 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.121172265
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/33.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.3109956137
Short name	T589
Test name
Test status
Simulation time	152474621 ps
CPU time	17.58 seconds
Started	Sep 03 11:49:58 PM UTC 24
Finished	Sep 03 11:50:16 PM UTC 24
Peak memory	216756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109956137 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.3109956137
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/33.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.1880777709
Short name	T596
Test name
Test status
Simulation time	351249940 ps
CPU time	20.8 seconds
Started	Sep 03 11:50:00 PM UTC 24
Finished	Sep 03 11:50:22 PM UTC 24
Peak memory	217152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880777709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1880777709
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/33.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.1663222381
Short name	T284
Test name
Test status
Simulation time	112001291 ps
CPU time	4.42 seconds
Started	Sep 03 11:49:43 PM UTC 24
Finished	Sep 03 11:49:49 PM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663222381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1663222381
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/33.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.212896101
Short name	T590
Test name
Test status
Simulation time	4466166220 ps
CPU time	27.25 seconds
Started	Sep 03 11:49:48 PM UTC 24
Finished	Sep 03 11:50:16 PM UTC 24
Peak memory	217200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212896101 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.212896101
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/33.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.3755472661
Short name	T593
Test name
Test status
Simulation time	3317042605 ps
CPU time	27.87 seconds
Started	Sep 03 11:49:50 PM UTC 24
Finished	Sep 03 11:50:19 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755472661 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3755472661
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/33.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.2852656731
Short name	T285
Test name
Test status
Simulation time	47052822 ps
CPU time	3.22 seconds
Started	Sep 03 11:49:45 PM UTC 24
Finished	Sep 03 11:49:50 PM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852656731 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.2852656731
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/33.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3126050199
Short name	T606
Test name
Test status
Simulation time	958050824 ps
CPU time	20.65 seconds
Started	Sep 03 11:50:17 PM UTC 24
Finished	Sep 03 11:50:39 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126050199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3126050199
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/33.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3506625789
Short name	T738
Test name
Test status
Simulation time	656745201 ps
CPU time	228.92 seconds
Started	Sep 03 11:50:15 PM UTC 24
Finished	Sep 03 11:54:07 PM UTC 24
Peak memory	220932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506625789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.3506625789
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/33.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.4290698154
Short name	T604
Test name
Test status
Simulation time	54154686 ps
CPU time	20.35 seconds
Started	Sep 03 11:50:17 PM UTC 24
Finished	Sep 03 11:50:39 PM UTC 24
Peak memory	218888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290698154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.4290698154
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/33.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.573220098
Short name	T601
Test name
Test status
Simulation time	2102883707 ps
CPU time	21.59 seconds
Started	Sep 03 11:50:07 PM UTC 24
Finished	Sep 03 11:50:30 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573220098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.573220098
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/33.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.1206580237
Short name	T616
Test name
Test status
Simulation time	1060834386 ps
CPU time	29.48 seconds
Started	Sep 03 11:50:24 PM UTC 24
Finished	Sep 03 11:50:55 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206580237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1206580237
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/34.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.2243409696
Short name	T634
Test name
Test status
Simulation time	16109789873 ps
CPU time	55.68 seconds
Started	Sep 03 11:50:24 PM UTC 24
Finished	Sep 03 11:51:22 PM UTC 24
Peak memory	216892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243409696 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.2243409696
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/34.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1943700028
Short name	T603
Test name
Test status
Simulation time	20557182 ps
CPU time	2.38 seconds
Started	Sep 03 11:50:31 PM UTC 24
Finished	Sep 03 11:50:34 PM UTC 24
Peak memory	216964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943700028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.1943700028
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/34.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.3309252621
Short name	T611
Test name
Test status
Simulation time	2939160682 ps
CPU time	21.72 seconds
Started	Sep 03 11:50:26 PM UTC 24
Finished	Sep 03 11:50:49 PM UTC 24
Peak memory	216888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309252621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3309252621
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/34.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random.1875803625
Short name	T612
Test name
Test status
Simulation time	236805114 ps
CPU time	27.75 seconds
Started	Sep 03 11:50:20 PM UTC 24
Finished	Sep 03 11:50:49 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875803625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.1875803625
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/34.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.1369895679
Short name	T624
Test name
Test status
Simulation time	23465769135 ps
CPU time	47.67 seconds
Started	Sep 03 11:50:22 PM UTC 24
Finished	Sep 03 11:51:11 PM UTC 24
Peak memory	217220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369895679 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1369895679
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/34.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.2583623181
Short name	T648
Test name
Test status
Simulation time	10296900235 ps
CPU time	74.16 seconds
Started	Sep 03 11:50:24 PM UTC 24
Finished	Sep 03 11:51:40 PM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583623181 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2583623181
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/34.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.4162590855
Short name	T610
Test name
Test status
Simulation time	232015444 ps
CPU time	22.92 seconds
Started	Sep 03 11:50:22 PM UTC 24
Finished	Sep 03 11:50:46 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162590855 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.4162590855
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/34.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.1806266041
Short name	T605
Test name
Test status
Simulation time	3572643800 ps
CPU time	13.72 seconds
Started	Sep 03 11:50:24 PM UTC 24
Finished	Sep 03 11:50:39 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806266041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1806266041
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/34.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.862594705
Short name	T597
Test name
Test status
Simulation time	146865665 ps
CPU time	4.52 seconds
Started	Sep 03 11:50:17 PM UTC 24
Finished	Sep 03 11:50:23 PM UTC 24
Peak memory	217068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862594705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.862594705
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/34.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.3534328431
Short name	T635
Test name
Test status
Simulation time	8151899538 ps
CPU time	62.54 seconds
Started	Sep 03 11:50:19 PM UTC 24
Finished	Sep 03 11:51:23 PM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534328431 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3534328431
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/34.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1501718259
Short name	T613
Test name
Test status
Simulation time	4098376560 ps
CPU time	29.82 seconds
Started	Sep 03 11:50:20 PM UTC 24
Finished	Sep 03 11:50:51 PM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501718259 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1501718259
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/34.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3151645383
Short name	T595
Test name
Test status
Simulation time	59499837 ps
CPU time	3.05 seconds
Started	Sep 03 11:50:17 PM UTC 24
Finished	Sep 03 11:50:21 PM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151645383 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3151645383
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/34.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.2833023649
Short name	T135
Test name
Test status
Simulation time	4895345139 ps
CPU time	226.51 seconds
Started	Sep 03 11:50:32 PM UTC 24
Finished	Sep 03 11:54:22 PM UTC 24
Peak memory	222976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833023649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2833023649
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/34.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.637076901
Short name	T693
Test name
Test status
Simulation time	4470713321 ps
CPU time	131.03 seconds
Started	Sep 03 11:50:37 PM UTC 24
Finished	Sep 03 11:52:50 PM UTC 24
Peak memory	220936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637076901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.637076901
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/34.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.562720994
Short name	T764
Test name
Test status
Simulation time	3553557566 ps
CPU time	244 seconds
Started	Sep 03 11:50:35 PM UTC 24
Finished	Sep 03 11:54:43 PM UTC 24
Peak memory	223300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562720994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.562720994
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/34.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3870404861
Short name	T796
Test name
Test status
Simulation time	4882796082 ps
CPU time	281.72 seconds
Started	Sep 03 11:50:40 PM UTC 24
Finished	Sep 03 11:55:26 PM UTC 24
Peak memory	235772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870404861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.3870404861
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/34.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.3965442363
Short name	T618
Test name
Test status
Simulation time	3606676717 ps
CPU time	33.59 seconds
Started	Sep 03 11:50:26 PM UTC 24
Finished	Sep 03 11:51:01 PM UTC 24
Peak memory	218880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965442363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3965442363
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/34.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.817290548
Short name	T625
Test name
Test status
Simulation time	338747664 ps
CPU time	19.92 seconds
Started	Sep 03 11:50:51 PM UTC 24
Finished	Sep 03 11:51:12 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817290548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.817290548
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/35.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3381421567
Short name	T725
Test name
Test status
Simulation time	19348593226 ps
CPU time	163.42 seconds
Started	Sep 03 11:50:53 PM UTC 24
Finished	Sep 03 11:53:39 PM UTC 24
Peak memory	218944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381421567 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.3381421567
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/35.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.2598777042
Short name	T631
Test name
Test status
Simulation time	509048291 ps
CPU time	16.56 seconds
Started	Sep 03 11:51:01 PM UTC 24
Finished	Sep 03 11:51:19 PM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598777042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.2598777042
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/35.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.2922312780
Short name	T619
Test name
Test status
Simulation time	60607051 ps
CPU time	4.71 seconds
Started	Sep 03 11:50:56 PM UTC 24
Finished	Sep 03 11:51:02 PM UTC 24
Peak memory	216948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922312780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2922312780
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/35.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random.3215152286
Short name	T639
Test name
Test status
Simulation time	1466800352 ps
CPU time	44.12 seconds
Started	Sep 03 11:50:46 PM UTC 24
Finished	Sep 03 11:51:32 PM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215152286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.3215152286
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/35.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.532295641
Short name	T671
Test name
Test status
Simulation time	11747772119 ps
CPU time	81.06 seconds
Started	Sep 03 11:50:50 PM UTC 24
Finished	Sep 03 11:52:13 PM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532295641 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.532295641
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/35.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3248696031
Short name	T303
Test name
Test status
Simulation time	65512318899 ps
CPU time	254.61 seconds
Started	Sep 03 11:50:50 PM UTC 24
Finished	Sep 03 11:55:08 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248696031 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3248696031
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/35.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.3957695582
Short name	T626
Test name
Test status
Simulation time	123602158 ps
CPU time	25.22 seconds
Started	Sep 03 11:50:47 PM UTC 24
Finished	Sep 03 11:51:14 PM UTC 24
Peak memory	216752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957695582 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.3957695582
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/35.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.1127761308
Short name	T629
Test name
Test status
Simulation time	1117094384 ps
CPU time	21.45 seconds
Started	Sep 03 11:50:53 PM UTC 24
Finished	Sep 03 11:51:16 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127761308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1127761308
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/35.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.2312759765
Short name	T608
Test name
Test status
Simulation time	35104922 ps
CPU time	2.98 seconds
Started	Sep 03 11:50:40 PM UTC 24
Finished	Sep 03 11:50:44 PM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312759765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2312759765
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/35.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1677366143
Short name	T651
Test name
Test status
Simulation time	10619001709 ps
CPU time	57.19 seconds
Started	Sep 03 11:50:43 PM UTC 24
Finished	Sep 03 11:51:42 PM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677366143 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1677366143
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/35.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.941512459
Short name	T637
Test name
Test status
Simulation time	17701142376 ps
CPU time	43.03 seconds
Started	Sep 03 11:50:45 PM UTC 24
Finished	Sep 03 11:51:29 PM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941512459 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.941512459
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/35.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1287981379
Short name	T609
Test name
Test status
Simulation time	58865968 ps
CPU time	3.27 seconds
Started	Sep 03 11:50:40 PM UTC 24
Finished	Sep 03 11:50:44 PM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287981379 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1287981379
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/35.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.2615285277
Short name	T689
Test name
Test status
Simulation time	7591673656 ps
CPU time	98.34 seconds
Started	Sep 03 11:51:02 PM UTC 24
Finished	Sep 03 11:52:43 PM UTC 24
Peak memory	218944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615285277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2615285277
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/35.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2148679840
Short name	T658
Test name
Test status
Simulation time	1296594208 ps
CPU time	51.89 seconds
Started	Sep 03 11:51:07 PM UTC 24
Finished	Sep 03 11:52:01 PM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148679840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2148679840
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/35.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.2888060943
Short name	T864
Test name
Test status
Simulation time	9520686452 ps
CPU time	394.75 seconds
Started	Sep 03 11:51:07 PM UTC 24
Finished	Sep 03 11:57:47 PM UTC 24
Peak memory	233656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888060943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.2888060943
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/35.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.807355832
Short name	T623
Test name
Test status
Simulation time	811552095 ps
CPU time	6.92 seconds
Started	Sep 03 11:51:00 PM UTC 24
Finished	Sep 03 11:51:08 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807355832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.807355832
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/35.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.1308365057
Short name	T687
Test name
Test status
Simulation time	2233087797 ps
CPU time	80.58 seconds
Started	Sep 03 11:51:18 PM UTC 24
Finished	Sep 03 11:52:40 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308365057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.1308365057
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/36.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2669991866
Short name	T697
Test name
Test status
Simulation time	11107620359 ps
CPU time	89.73 seconds
Started	Sep 03 11:51:20 PM UTC 24
Finished	Sep 03 11:52:52 PM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669991866 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.2669991866
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/36.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2396713522
Short name	T638
Test name
Test status
Simulation time	388728108 ps
CPU time	6.85 seconds
Started	Sep 03 11:51:24 PM UTC 24
Finished	Sep 03 11:51:32 PM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396713522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2396713522
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/36.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.890495286
Short name	T640
Test name
Test status
Simulation time	571445886 ps
CPU time	8.89 seconds
Started	Sep 03 11:51:22 PM UTC 24
Finished	Sep 03 11:51:32 PM UTC 24
Peak memory	216756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890495286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.890495286
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/36.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random.3204403883
Short name	T76
Test name
Test status
Simulation time	1545030589 ps
CPU time	42.39 seconds
Started	Sep 03 11:51:15 PM UTC 24
Finished	Sep 03 11:51:59 PM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204403883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.3204403883
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/36.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.343106605
Short name	T823
Test name
Test status
Simulation time	35707882340 ps
CPU time	284.91 seconds
Started	Sep 03 11:51:16 PM UTC 24
Finished	Sep 03 11:56:06 PM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343106605 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.343106605
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/36.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2446402294
Short name	T851
Test name
Test status
Simulation time	50906523219 ps
CPU time	327.57 seconds
Started	Sep 03 11:51:16 PM UTC 24
Finished	Sep 03 11:56:49 PM UTC 24
Peak memory	219204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446402294 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2446402294
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/36.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.2802699589
Short name	T636
Test name
Test status
Simulation time	307183229 ps
CPU time	12.15 seconds
Started	Sep 03 11:51:15 PM UTC 24
Finished	Sep 03 11:51:29 PM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802699589 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2802699589
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/36.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.2796123080
Short name	T646
Test name
Test status
Simulation time	202699010 ps
CPU time	15.66 seconds
Started	Sep 03 11:51:21 PM UTC 24
Finished	Sep 03 11:51:38 PM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796123080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2796123080
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/36.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.4151306828
Short name	T630
Test name
Test status
Simulation time	498339621 ps
CPU time	5.29 seconds
Started	Sep 03 11:51:10 PM UTC 24
Finished	Sep 03 11:51:17 PM UTC 24
Peak memory	217068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151306828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.4151306828
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/36.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3065289902
Short name	T673
Test name
Test status
Simulation time	10464932068 ps
CPU time	60.61 seconds
Started	Sep 03 11:51:12 PM UTC 24
Finished	Sep 03 11:52:15 PM UTC 24
Peak memory	217204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065289902 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3065289902
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/36.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.3879657083
Short name	T655
Test name
Test status
Simulation time	13177660913 ps
CPU time	36.28 seconds
Started	Sep 03 11:51:14 PM UTC 24
Finished	Sep 03 11:51:51 PM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879657083 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3879657083
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/36.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.471526946
Short name	T627
Test name
Test status
Simulation time	32331219 ps
CPU time	2.92 seconds
Started	Sep 03 11:51:10 PM UTC 24
Finished	Sep 03 11:51:14 PM UTC 24
Peak memory	217068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471526946 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.471526946
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/36.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.3435996281
Short name	T652
Test name
Test status
Simulation time	335353405 ps
CPU time	10.57 seconds
Started	Sep 03 11:51:31 PM UTC 24
Finished	Sep 03 11:51:42 PM UTC 24
Peak memory	218816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435996281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3435996281
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/36.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.3361634439
Short name	T741
Test name
Test status
Simulation time	2741031578 ps
CPU time	155.17 seconds
Started	Sep 03 11:51:33 PM UTC 24
Finished	Sep 03 11:54:11 PM UTC 24
Peak memory	223176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361634439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3361634439
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/36.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1828569351
Short name	T289
Test name
Test status
Simulation time	3021420136 ps
CPU time	221.08 seconds
Started	Sep 03 11:51:31 PM UTC 24
Finished	Sep 03 11:55:15 PM UTC 24
Peak memory	223052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828569351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.1828569351
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/36.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.4030439988
Short name	T743
Test name
Test status
Simulation time	415595635 ps
CPU time	155.75 seconds
Started	Sep 03 11:51:33 PM UTC 24
Finished	Sep 03 11:54:12 PM UTC 24
Peak memory	222984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030439988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.4030439988
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/36.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.2077322358
Short name	T650
Test name
Test status
Simulation time	142156777 ps
CPU time	16.41 seconds
Started	Sep 03 11:51:24 PM UTC 24
Finished	Sep 03 11:51:41 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077322358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2077322358
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/36.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.1903427005
Short name	T670
Test name
Test status
Simulation time	220569715 ps
CPU time	27.98 seconds
Started	Sep 03 11:51:41 PM UTC 24
Finished	Sep 03 11:52:10 PM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903427005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1903427005
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/37.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1486323220
Short name	T874
Test name
Test status
Simulation time	95435649713 ps
CPU time	416.39 seconds
Started	Sep 03 11:51:41 PM UTC 24
Finished	Sep 03 11:58:43 PM UTC 24
Peak memory	219272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486323220 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.1486323220
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/37.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.3140230644
Short name	T661
Test name
Test status
Simulation time	104892216 ps
CPU time	11.47 seconds
Started	Sep 03 11:51:52 PM UTC 24
Finished	Sep 03 11:52:04 PM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140230644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.3140230644
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/37.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.1326362782
Short name	T654
Test name
Test status
Simulation time	321448475 ps
CPU time	5.92 seconds
Started	Sep 03 11:51:44 PM UTC 24
Finished	Sep 03 11:51:51 PM UTC 24
Peak memory	217052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326362782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1326362782
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/37.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random.2890227637
Short name	T657
Test name
Test status
Simulation time	642295857 ps
CPU time	21.49 seconds
Started	Sep 03 11:51:37 PM UTC 24
Finished	Sep 03 11:52:00 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890227637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.2890227637
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/37.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.1932612317
Short name	T782
Test name
Test status
Simulation time	26479781634 ps
CPU time	205.82 seconds
Started	Sep 03 11:51:39 PM UTC 24
Finished	Sep 03 11:55:08 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932612317 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.1932612317
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/37.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.804454084
Short name	T140
Test name
Test status
Simulation time	9729947120 ps
CPU time	74.15 seconds
Started	Sep 03 11:51:41 PM UTC 24
Finished	Sep 03 11:52:57 PM UTC 24
Peak memory	217152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804454084 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.804454084
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/37.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.4187353279
Short name	T653
Test name
Test status
Simulation time	64244641 ps
CPU time	10.02 seconds
Started	Sep 03 11:51:39 PM UTC 24
Finished	Sep 03 11:51:50 PM UTC 24
Peak memory	217080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187353279 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.4187353279
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/37.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.2030678943
Short name	T663
Test name
Test status
Simulation time	950347787 ps
CPU time	22.54 seconds
Started	Sep 03 11:51:42 PM UTC 24
Finished	Sep 03 11:52:06 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030678943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2030678943
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/37.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.2904335694
Short name	T645
Test name
Test status
Simulation time	53208651 ps
CPU time	2.84 seconds
Started	Sep 03 11:51:33 PM UTC 24
Finished	Sep 03 11:51:37 PM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904335694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2904335694
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/37.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3737341253
Short name	T674
Test name
Test status
Simulation time	4393435513 ps
CPU time	37.57 seconds
Started	Sep 03 11:51:36 PM UTC 24
Finished	Sep 03 11:52:15 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737341253 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3737341253
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/37.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.3974247400
Short name	T659
Test name
Test status
Simulation time	3134829344 ps
CPU time	23.37 seconds
Started	Sep 03 11:51:36 PM UTC 24
Finished	Sep 03 11:52:01 PM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974247400 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3974247400
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/37.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.2741150496
Short name	T649
Test name
Test status
Simulation time	21655127 ps
CPU time	3 seconds
Started	Sep 03 11:51:36 PM UTC 24
Finished	Sep 03 11:51:40 PM UTC 24
Peak memory	217064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741150496 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.2741150496
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/37.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.3982445686
Short name	T794
Test name
Test status
Simulation time	5983229315 ps
CPU time	208.84 seconds
Started	Sep 03 11:51:52 PM UTC 24
Finished	Sep 03 11:55:24 PM UTC 24
Peak memory	223040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982445686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3982445686
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/37.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2615829749
Short name	T680
Test name
Test status
Simulation time	247476509 ps
CPU time	23.99 seconds
Started	Sep 03 11:51:58 PM UTC 24
Finished	Sep 03 11:52:23 PM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615829749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2615829749
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/37.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.1665027382
Short name	T788
Test name
Test status
Simulation time	3512118847 ps
CPU time	202.06 seconds
Started	Sep 03 11:51:53 PM UTC 24
Finished	Sep 03 11:55:18 PM UTC 24
Peak memory	220936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665027382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.1665027382
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/37.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.296531400
Short name	T772
Test name
Test status
Simulation time	10636987836 ps
CPU time	171.86 seconds
Started	Sep 03 11:52:00 PM UTC 24
Finished	Sep 03 11:54:55 PM UTC 24
Peak memory	223348 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296531400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.296531400
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/37.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.1083752537
Short name	T667
Test name
Test status
Simulation time	130909749 ps
CPU time	24.14 seconds
Started	Sep 03 11:51:44 PM UTC 24
Finished	Sep 03 11:52:09 PM UTC 24
Peak memory	219116 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083752537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1083752537
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/37.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.1692064483
Short name	T133
Test name
Test status
Simulation time	1837662617 ps
CPU time	45.64 seconds
Started	Sep 03 11:52:09 PM UTC 24
Finished	Sep 03 11:52:56 PM UTC 24
Peak memory	219148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692064483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1692064483
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/38.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.121318799
Short name	T236
Test name
Test status
Simulation time	74798772469 ps
CPU time	394.15 seconds
Started	Sep 03 11:52:09 PM UTC 24
Finished	Sep 03 11:58:48 PM UTC 24
Peak memory	219208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121318799 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.121318799
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/38.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.1675141363
Short name	T675
Test name
Test status
Simulation time	124785776 ps
CPU time	3.01 seconds
Started	Sep 03 11:52:12 PM UTC 24
Finished	Sep 03 11:52:16 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675141363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.1675141363
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/38.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.2564882652
Short name	T691
Test name
Test status
Simulation time	651797057 ps
CPU time	33.25 seconds
Started	Sep 03 11:52:10 PM UTC 24
Finished	Sep 03 11:52:45 PM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564882652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2564882652
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/38.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random.3928974762
Short name	T684
Test name
Test status
Simulation time	1827764903 ps
CPU time	32.41 seconds
Started	Sep 03 11:52:02 PM UTC 24
Finished	Sep 03 11:52:36 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928974762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3928974762
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/38.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.616674225
Short name	T138
Test name
Test status
Simulation time	60678324503 ps
CPU time	187.47 seconds
Started	Sep 03 11:52:06 PM UTC 24
Finished	Sep 03 11:55:16 PM UTC 24
Peak memory	217160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616674225 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.616674225
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/38.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.628659873
Short name	T797
Test name
Test status
Simulation time	22418275522 ps
CPU time	197.35 seconds
Started	Sep 03 11:52:09 PM UTC 24
Finished	Sep 03 11:55:29 PM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628659873 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.628659873
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/38.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.1548486901
Short name	T688
Test name
Test status
Simulation time	349985689 ps
CPU time	34.85 seconds
Started	Sep 03 11:52:04 PM UTC 24
Finished	Sep 03 11:52:41 PM UTC 24
Peak memory	217080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548486901 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1548486901
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/38.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.2147672751
Short name	T676
Test name
Test status
Simulation time	1294593218 ps
CPU time	7.8 seconds
Started	Sep 03 11:52:09 PM UTC 24
Finished	Sep 03 11:52:18 PM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147672751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.2147672751
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/38.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.2774947424
Short name	T664
Test name
Test status
Simulation time	175412028 ps
CPU time	5.28 seconds
Started	Sep 03 11:52:00 PM UTC 24
Finished	Sep 03 11:52:06 PM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774947424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2774947424
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/38.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.2208496562
Short name	T683
Test name
Test status
Simulation time	5192867125 ps
CPU time	32.36 seconds
Started	Sep 03 11:52:02 PM UTC 24
Finished	Sep 03 11:52:36 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208496562 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2208496562
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/38.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.937431254
Short name	T685
Test name
Test status
Simulation time	7204942829 ps
CPU time	33.06 seconds
Started	Sep 03 11:52:02 PM UTC 24
Finished	Sep 03 11:52:36 PM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937431254 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.937431254
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/38.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2275443487
Short name	T660
Test name
Test status
Simulation time	36343410 ps
CPU time	2.59 seconds
Started	Sep 03 11:52:00 PM UTC 24
Finished	Sep 03 11:52:04 PM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275443487 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2275443487
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/38.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.2579934978
Short name	T720
Test name
Test status
Simulation time	1092711717 ps
CPU time	77.24 seconds
Started	Sep 03 11:52:12 PM UTC 24
Finished	Sep 03 11:53:31 PM UTC 24
Peak memory	220928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579934978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2579934978
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/38.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.4218321258
Short name	T735
Test name
Test status
Simulation time	1997588706 ps
CPU time	94.38 seconds
Started	Sep 03 11:52:14 PM UTC 24
Finished	Sep 03 11:53:50 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218321258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.4218321258
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/38.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.160260818
Short name	T883
Test name
Test status
Simulation time	3707831283 ps
CPU time	444.2 seconds
Started	Sep 03 11:52:14 PM UTC 24
Finished	Sep 03 11:59:43 PM UTC 24
Peak memory	235200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160260818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.160260818
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/38.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.996843679
Short name	T692
Test name
Test status
Simulation time	86683120 ps
CPU time	30.81 seconds
Started	Sep 03 11:52:15 PM UTC 24
Finished	Sep 03 11:52:47 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996843679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.996843679
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/38.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.3611172625
Short name	T681
Test name
Test status
Simulation time	77857702 ps
CPU time	12.58 seconds
Started	Sep 03 11:52:11 PM UTC 24
Finished	Sep 03 11:52:24 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611172625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3611172625
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/38.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.3902382369
Short name	T702
Test name
Test status
Simulation time	650019883 ps
CPU time	30.66 seconds
Started	Sep 03 11:52:25 PM UTC 24
Finished	Sep 03 11:52:57 PM UTC 24
Peak memory	218852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902382369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3902382369
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/39.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1337897749
Short name	T754
Test name
Test status
Simulation time	27493682967 ps
CPU time	115.38 seconds
Started	Sep 03 11:52:31 PM UTC 24
Finished	Sep 03 11:54:29 PM UTC 24
Peak memory	219204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337897749 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.1337897749
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/39.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.192972723
Short name	T705
Test name
Test status
Simulation time	928098007 ps
CPU time	23.35 seconds
Started	Sep 03 11:52:39 PM UTC 24
Finished	Sep 03 11:53:04 PM UTC 24
Peak memory	217100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192972723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.192972723
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/39.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.605572671
Short name	T699
Test name
Test status
Simulation time	126935453 ps
CPU time	15.59 seconds
Started	Sep 03 11:52:37 PM UTC 24
Finished	Sep 03 11:52:54 PM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605572671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.605572671
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/39.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random.440174290
Short name	T703
Test name
Test status
Simulation time	888250527 ps
CPU time	38.16 seconds
Started	Sep 03 11:52:22 PM UTC 24
Finished	Sep 03 11:53:01 PM UTC 24
Peak memory	219132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440174290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.440174290
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/39.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.1694539578
Short name	T770
Test name
Test status
Simulation time	29928903003 ps
CPU time	144.6 seconds
Started	Sep 03 11:52:24 PM UTC 24
Finished	Sep 03 11:54:51 PM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694539578 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1694539578
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/39.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.4183659134
Short name	T724
Test name
Test status
Simulation time	17293356475 ps
CPU time	70.33 seconds
Started	Sep 03 11:52:25 PM UTC 24
Finished	Sep 03 11:53:38 PM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183659134 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.4183659134
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/39.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.916555907
Short name	T686
Test name
Test status
Simulation time	71319078 ps
CPU time	14.04 seconds
Started	Sep 03 11:52:23 PM UTC 24
Finished	Sep 03 11:52:39 PM UTC 24
Peak memory	217080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916555907 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.916555907
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/39.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.3031877413
Short name	T690
Test name
Test status
Simulation time	435369081 ps
CPU time	10.97 seconds
Started	Sep 03 11:52:31 PM UTC 24
Finished	Sep 03 11:52:44 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031877413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3031877413
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/39.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.3631977848
Short name	T678
Test name
Test status
Simulation time	196983699 ps
CPU time	4.3 seconds
Started	Sep 03 11:52:16 PM UTC 24
Finished	Sep 03 11:52:22 PM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631977848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3631977848
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/39.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3322349594
Short name	T707
Test name
Test status
Simulation time	9783649189 ps
CPU time	48.84 seconds
Started	Sep 03 11:52:18 PM UTC 24
Finished	Sep 03 11:53:08 PM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322349594 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3322349594
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/39.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3781766639
Short name	T704
Test name
Test status
Simulation time	6579108019 ps
CPU time	42.45 seconds
Started	Sep 03 11:52:19 PM UTC 24
Finished	Sep 03 11:53:03 PM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781766639 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3781766639
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/39.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.643393105
Short name	T677
Test name
Test status
Simulation time	74645151 ps
CPU time	3.19 seconds
Started	Sep 03 11:52:17 PM UTC 24
Finished	Sep 03 11:52:21 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643393105 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.643393105
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/39.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.2387680811
Short name	T265
Test name
Test status
Simulation time	1073020992 ps
CPU time	98.4 seconds
Started	Sep 03 11:52:40 PM UTC 24
Finished	Sep 03 11:54:21 PM UTC 24
Peak memory	220928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387680811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.2387680811
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/39.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.4227890368
Short name	T700
Test name
Test status
Simulation time	402575382 ps
CPU time	12.59 seconds
Started	Sep 03 11:52:42 PM UTC 24
Finished	Sep 03 11:52:56 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227890368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.4227890368
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/39.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.2565465093
Short name	T337
Test name
Test status
Simulation time	668304923 ps
CPU time	185.73 seconds
Started	Sep 03 11:52:42 PM UTC 24
Finished	Sep 03 11:55:51 PM UTC 24
Peak memory	221192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565465093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.2565465093
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/39.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3153958158
Short name	T885
Test name
Test status
Simulation time	4624486747 ps
CPU time	426.77 seconds
Started	Sep 03 11:52:45 PM UTC 24
Finished	Sep 03 11:59:58 PM UTC 24
Peak memory	233596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153958158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.3153958158
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/39.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.1340053502
Short name	T701
Test name
Test status
Simulation time	320558502 ps
CPU time	17.1 seconds
Started	Sep 03 11:52:38 PM UTC 24
Finished	Sep 03 11:52:56 PM UTC 24
Peak memory	216768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340053502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1340053502
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/39.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3117368447
Short name	T367
Test name
Test status
Simulation time	72473278584 ps
CPU time	407.88 seconds
Started	Sep 03 11:38:31 PM UTC 24
Finished	Sep 03 11:45:23 PM UTC 24
Peak memory	219328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117368447 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.3117368447
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/4.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.335554828
Short name	T40
Test name
Test status
Simulation time	649809096 ps
CPU time	22.02 seconds
Started	Sep 03 11:38:38 PM UTC 24
Finished	Sep 03 11:39:01 PM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335554828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.335554828
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/4.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.1968849548
Short name	T28
Test name
Test status
Simulation time	643989627 ps
CPU time	4.59 seconds
Started	Sep 03 11:38:31 PM UTC 24
Finished	Sep 03 11:38:36 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968849548 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1968849548
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/4.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random.903956708
Short name	T5
Test name
Test status
Simulation time	735446178 ps
CPU time	24.81 seconds
Started	Sep 03 11:38:25 PM UTC 24
Finished	Sep 03 11:38:51 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903956708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.903956708
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/4.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.1220795168
Short name	T252
Test name
Test status
Simulation time	23779154352 ps
CPU time	149.86 seconds
Started	Sep 03 11:38:30 PM UTC 24
Finished	Sep 03 11:41:02 PM UTC 24
Peak memory	217160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220795168 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1220795168
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/4.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.129499937
Short name	T227
Test name
Test status
Simulation time	39515073500 ps
CPU time	181.3 seconds
Started	Sep 03 11:38:30 PM UTC 24
Finished	Sep 03 11:41:34 PM UTC 24
Peak memory	218940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129499937 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.129499937
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/4.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.4142989877
Short name	T83
Test name
Test status
Simulation time	975394126 ps
CPU time	27.41 seconds
Started	Sep 03 11:38:28 PM UTC 24
Finished	Sep 03 11:38:57 PM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142989877 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.4142989877
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/4.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.1029845351
Short name	T149
Test name
Test status
Simulation time	1323862228 ps
CPU time	14.45 seconds
Started	Sep 03 11:38:31 PM UTC 24
Finished	Sep 03 11:38:46 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029845351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1029845351
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/4.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.3173044983
Short name	T88
Test name
Test status
Simulation time	683741334 ps
CPU time	5.59 seconds
Started	Sep 03 11:38:24 PM UTC 24
Finished	Sep 03 11:38:30 PM UTC 24
Peak memory	217068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173044983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3173044983
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/4.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.346180499
Short name	T81
Test name
Test status
Simulation time	9519472576 ps
CPU time	29.03 seconds
Started	Sep 03 11:38:24 PM UTC 24
Finished	Sep 03 11:38:54 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346180499 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.346180499
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/4.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.588132899
Short name	T84
Test name
Test status
Simulation time	4256832875 ps
CPU time	35.13 seconds
Started	Sep 03 11:38:24 PM UTC 24
Finished	Sep 03 11:39:00 PM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588132899 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.588132899
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/4.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.1387782379
Short name	T244
Test name
Test status
Simulation time	90980558 ps
CPU time	2.95 seconds
Started	Sep 03 11:38:24 PM UTC 24
Finished	Sep 03 11:38:28 PM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387782379 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.1387782379
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/4.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.767499974
Short name	T250
Test name
Test status
Simulation time	2517462567 ps
CPU time	166.23 seconds
Started	Sep 03 11:38:38 PM UTC 24
Finished	Sep 03 11:41:27 PM UTC 24
Peak memory	220996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767499974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.767499974
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/4.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1040910608
Short name	T380
Test name
Test status
Simulation time	1155433521 ps
CPU time	96.32 seconds
Started	Sep 03 11:38:39 PM UTC 24
Finished	Sep 03 11:40:18 PM UTC 24
Peak memory	220860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040910608 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1040910608
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/4.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.3673024817
Short name	T86
Test name
Test status
Simulation time	2172313903 ps
CPU time	24.08 seconds
Started	Sep 03 11:38:35 PM UTC 24
Finished	Sep 03 11:39:01 PM UTC 24
Peak memory	218876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673024817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3673024817
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/4.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.3100194968
Short name	T706
Test name
Test status
Simulation time	322418230 ps
CPU time	9.61 seconds
Started	Sep 03 11:52:55 PM UTC 24
Finished	Sep 03 11:53:06 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100194968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3100194968
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/40.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1706746424
Short name	T894
Test name
Test status
Simulation time	155215503279 ps
CPU time	529.39 seconds
Started	Sep 03 11:52:59 PM UTC 24
Finished	Sep 04 12:01:55 AM UTC 24
Peak memory	220564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706746424 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.1706746424
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/40.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.2990598745
Short name	T716
Test name
Test status
Simulation time	435595176 ps
CPU time	20.1 seconds
Started	Sep 03 11:52:59 PM UTC 24
Finished	Sep 03 11:53:20 PM UTC 24
Peak memory	217160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990598745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.2990598745
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/40.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.2778512315
Short name	T717
Test name
Test status
Simulation time	1083175377 ps
CPU time	20.41 seconds
Started	Sep 03 11:52:59 PM UTC 24
Finished	Sep 03 11:53:21 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778512315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2778512315
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/40.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random.4241971425
Short name	T715
Test name
Test status
Simulation time	750014286 ps
CPU time	25.51 seconds
Started	Sep 03 11:52:53 PM UTC 24
Finished	Sep 03 11:53:20 PM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241971425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.4241971425
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/40.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.4227375228
Short name	T78
Test name
Test status
Simulation time	48754864899 ps
CPU time	172.94 seconds
Started	Sep 03 11:52:53 PM UTC 24
Finished	Sep 03 11:55:49 PM UTC 24
Peak memory	216928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227375228 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.4227375228
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/40.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.142782280
Short name	T752
Test name
Test status
Simulation time	12303668637 ps
CPU time	89.53 seconds
Started	Sep 03 11:52:53 PM UTC 24
Finished	Sep 03 11:54:25 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142782280 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.142782280
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/40.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.2066619319
Short name	T714
Test name
Test status
Simulation time	136143491 ps
CPU time	22.32 seconds
Started	Sep 03 11:52:53 PM UTC 24
Finished	Sep 03 11:53:17 PM UTC 24
Peak memory	216756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066619319 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.2066619319
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/40.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.2614670265
Short name	T713
Test name
Test status
Simulation time	2238465293 ps
CPU time	16.47 seconds
Started	Sep 03 11:52:59 PM UTC 24
Finished	Sep 03 11:53:17 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614670265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2614670265
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/40.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.2360215822
Short name	T695
Test name
Test status
Simulation time	292850523 ps
CPU time	4.71 seconds
Started	Sep 03 11:52:45 PM UTC 24
Finished	Sep 03 11:52:51 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360215822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2360215822
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/40.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.47418972
Short name	T722
Test name
Test status
Simulation time	17422736012 ps
CPU time	45.95 seconds
Started	Sep 03 11:52:48 PM UTC 24
Finished	Sep 03 11:53:35 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47418972 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.47418972
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/40.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.3701466127
Short name	T719
Test name
Test status
Simulation time	3621476542 ps
CPU time	37.84 seconds
Started	Sep 03 11:52:49 PM UTC 24
Finished	Sep 03 11:53:29 PM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701466127 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3701466127
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/40.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.486876842
Short name	T694
Test name
Test status
Simulation time	27940025 ps
CPU time	2.55 seconds
Started	Sep 03 11:52:46 PM UTC 24
Finished	Sep 03 11:52:50 PM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486876842 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.486876842
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/40.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.3374454257
Short name	T862
Test name
Test status
Simulation time	8409461227 ps
CPU time	266.88 seconds
Started	Sep 03 11:53:01 PM UTC 24
Finished	Sep 03 11:57:31 PM UTC 24
Peak memory	223040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374454257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3374454257
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/40.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.4222029590
Short name	T734
Test name
Test status
Simulation time	842377359 ps
CPU time	43.63 seconds
Started	Sep 03 11:53:05 PM UTC 24
Finished	Sep 03 11:53:50 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222029590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.4222029590
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/40.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1253051574
Short name	T755
Test name
Test status
Simulation time	262649543 ps
CPU time	85.73 seconds
Started	Sep 03 11:53:03 PM UTC 24
Finished	Sep 03 11:54:31 PM UTC 24
Peak memory	220932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253051574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.1253051574
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/40.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.1246134635
Short name	T708
Test name
Test status
Simulation time	54563027 ps
CPU time	9.7 seconds
Started	Sep 03 11:52:59 PM UTC 24
Finished	Sep 03 11:53:10 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246134635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1246134635
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/40.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.915431088
Short name	T723
Test name
Test status
Simulation time	101543232 ps
CPU time	13.68 seconds
Started	Sep 03 11:53:21 PM UTC 24
Finished	Sep 03 11:53:35 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915431088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.915431088
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/41.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1496306164
Short name	T859
Test name
Test status
Simulation time	26824417003 ps
CPU time	227.43 seconds
Started	Sep 03 11:53:23 PM UTC 24
Finished	Sep 03 11:57:13 PM UTC 24
Peak memory	219208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496306164 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.1496306164
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/41.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.4030012848
Short name	T733
Test name
Test status
Simulation time	1343259678 ps
CPU time	15.27 seconds
Started	Sep 03 11:53:32 PM UTC 24
Finished	Sep 03 11:53:48 PM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030012848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.4030012848
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/41.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.1602405170
Short name	T669
Test name
Test status
Simulation time	978556689 ps
CPU time	30.69 seconds
Started	Sep 03 11:53:23 PM UTC 24
Finished	Sep 03 11:53:55 PM UTC 24
Peak memory	216756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602405170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1602405170
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/41.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random.1514845384
Short name	T77
Test name
Test status
Simulation time	304635839 ps
CPU time	11.89 seconds
Started	Sep 03 11:53:17 PM UTC 24
Finished	Sep 03 11:53:30 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514845384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.1514845384
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/41.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.3712996013
Short name	T732
Test name
Test status
Simulation time	6168666740 ps
CPU time	26.22 seconds
Started	Sep 03 11:53:20 PM UTC 24
Finished	Sep 03 11:53:48 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712996013 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3712996013
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/41.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3630351479
Short name	T872
Test name
Test status
Simulation time	61138002197 ps
CPU time	294.37 seconds
Started	Sep 03 11:53:20 PM UTC 24
Finished	Sep 03 11:58:19 PM UTC 24
Peak memory	218888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630351479 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3630351479
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/41.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.1403192771
Short name	T730
Test name
Test status
Simulation time	399905456 ps
CPU time	25.8 seconds
Started	Sep 03 11:53:17 PM UTC 24
Finished	Sep 03 11:53:44 PM UTC 24
Peak memory	217080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403192771 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1403192771
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/41.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.28747591
Short name	T731
Test name
Test status
Simulation time	1304162461 ps
CPU time	22.65 seconds
Started	Sep 03 11:53:23 PM UTC 24
Finished	Sep 03 11:53:47 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28747591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.28747591
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/41.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.3794389812
Short name	T709
Test name
Test status
Simulation time	62348396 ps
CPU time	3.08 seconds
Started	Sep 03 11:53:07 PM UTC 24
Finished	Sep 03 11:53:11 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794389812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3794389812
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/41.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.481921519
Short name	T746
Test name
Test status
Simulation time	6701224363 ps
CPU time	60.5 seconds
Started	Sep 03 11:53:11 PM UTC 24
Finished	Sep 03 11:54:13 PM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481921519 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.481921519
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/41.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2635666956
Short name	T726
Test name
Test status
Simulation time	3728297663 ps
CPU time	26.04 seconds
Started	Sep 03 11:53:13 PM UTC 24
Finished	Sep 03 11:53:40 PM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635666956 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2635666956
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/41.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.3500652648
Short name	T711
Test name
Test status
Simulation time	91949320 ps
CPU time	3.48 seconds
Started	Sep 03 11:53:09 PM UTC 24
Finished	Sep 03 11:53:14 PM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500652648 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.3500652648
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/41.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.436244997
Short name	T235
Test name
Test status
Simulation time	4809297174 ps
CPU time	156.51 seconds
Started	Sep 03 11:53:32 PM UTC 24
Finished	Sep 03 11:56:11 PM UTC 24
Peak memory	220992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436244997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.436244997
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/41.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.48783210
Short name	T737
Test name
Test status
Simulation time	2240764066 ps
CPU time	31.19 seconds
Started	Sep 03 11:53:34 PM UTC 24
Finished	Sep 03 11:54:07 PM UTC 24
Peak memory	216892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48783210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.48783210
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/41.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.567018303
Short name	T836
Test name
Test status
Simulation time	409408322 ps
CPU time	167.89 seconds
Started	Sep 03 11:53:34 PM UTC 24
Finished	Sep 03 11:56:25 PM UTC 24
Peak memory	220932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567018303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.567018303
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/41.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.4103777256
Short name	T696
Test name
Test status
Simulation time	718766161 ps
CPU time	37.11 seconds
Started	Sep 03 11:53:27 PM UTC 24
Finished	Sep 03 11:54:06 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103777256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.4103777256
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/41.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.2991614411
Short name	T137
Test name
Test status
Simulation time	3107544503 ps
CPU time	64.32 seconds
Started	Sep 03 11:53:48 PM UTC 24
Finished	Sep 03 11:54:54 PM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991614411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2991614411
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/42.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.302177526
Short name	T747
Test name
Test status
Simulation time	4184950900 ps
CPU time	25.08 seconds
Started	Sep 03 11:53:49 PM UTC 24
Finished	Sep 03 11:54:15 PM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302177526 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.302177526
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/42.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.1349673631
Short name	T662
Test name
Test status
Simulation time	202177782 ps
CPU time	3.4 seconds
Started	Sep 03 11:53:52 PM UTC 24
Finished	Sep 03 11:53:56 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349673631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.1349673631
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/42.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.3098540536
Short name	T751
Test name
Test status
Simulation time	1393295214 ps
CPU time	26.6 seconds
Started	Sep 03 11:53:52 PM UTC 24
Finished	Sep 03 11:54:20 PM UTC 24
Peak memory	217080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098540536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3098540536
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/42.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random.2640369609
Short name	T736
Test name
Test status
Simulation time	70441653 ps
CPU time	7.9 seconds
Started	Sep 03 11:53:42 PM UTC 24
Finished	Sep 03 11:53:51 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640369609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2640369609
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/42.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.1328731673
Short name	T147
Test name
Test status
Simulation time	47933320918 ps
CPU time	201.16 seconds
Started	Sep 03 11:53:43 PM UTC 24
Finished	Sep 03 11:57:08 PM UTC 24
Peak memory	217224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328731673 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1328731673
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/42.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.860010696
Short name	T865
Test name
Test status
Simulation time	48504652574 ps
CPU time	239.19 seconds
Started	Sep 03 11:53:45 PM UTC 24
Finished	Sep 03 11:57:47 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860010696 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.860010696
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/42.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.3695714692
Short name	T745
Test name
Test status
Simulation time	149056251 ps
CPU time	27.82 seconds
Started	Sep 03 11:53:43 PM UTC 24
Finished	Sep 03 11:54:12 PM UTC 24
Peak memory	217080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695714692 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.3695714692
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/42.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.2254929830
Short name	T740
Test name
Test status
Simulation time	1812127320 ps
CPU time	18.71 seconds
Started	Sep 03 11:53:50 PM UTC 24
Finished	Sep 03 11:54:10 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254929830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2254929830
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/42.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.3475779725
Short name	T728
Test name
Test status
Simulation time	193811383 ps
CPU time	3.9 seconds
Started	Sep 03 11:53:37 PM UTC 24
Finished	Sep 03 11:53:42 PM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475779725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3475779725
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/42.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.3333253696
Short name	T771
Test name
Test status
Simulation time	44776563108 ps
CPU time	70.82 seconds
Started	Sep 03 11:53:40 PM UTC 24
Finished	Sep 03 11:54:52 PM UTC 24
Peak memory	217140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333253696 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.3333253696
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/42.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1466347333
Short name	T742
Test name
Test status
Simulation time	5202271688 ps
CPU time	28.59 seconds
Started	Sep 03 11:53:42 PM UTC 24
Finished	Sep 03 11:54:12 PM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466347333 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1466347333
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/42.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.2512860866
Short name	T729
Test name
Test status
Simulation time	84618469 ps
CPU time	3.07 seconds
Started	Sep 03 11:53:38 PM UTC 24
Finished	Sep 03 11:53:43 PM UTC 24
Peak memory	216872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512860866 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.2512860866
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/42.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.4043084366
Short name	T175
Test name
Test status
Simulation time	4442860565 ps
CPU time	130.44 seconds
Started	Sep 03 11:53:56 PM UTC 24
Finished	Sep 03 11:56:09 PM UTC 24
Peak memory	221252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043084366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.4043084366
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/42.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3503451672
Short name	T804
Test name
Test status
Simulation time	2737320541 ps
CPU time	88.03 seconds
Started	Sep 03 11:54:07 PM UTC 24
Finished	Sep 03 11:55:37 PM UTC 24
Peak memory	219208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503451672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3503451672
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/42.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.664400316
Short name	T799
Test name
Test status
Simulation time	95337232 ps
CPU time	91.38 seconds
Started	Sep 03 11:53:58 PM UTC 24
Finished	Sep 03 11:55:31 PM UTC 24
Peak memory	218876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664400316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.664400316
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/42.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3707022273
Short name	T879
Test name
Test status
Simulation time	2339621927 ps
CPU time	296.21 seconds
Started	Sep 03 11:54:07 PM UTC 24
Finished	Sep 03 11:59:08 PM UTC 24
Peak memory	233592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707022273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.3707022273
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/42.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.3607184130
Short name	T750
Test name
Test status
Simulation time	778379091 ps
CPU time	25.78 seconds
Started	Sep 03 11:53:52 PM UTC 24
Finished	Sep 03 11:54:19 PM UTC 24
Peak memory	217084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607184130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3607184130
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/42.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.3933227905
Short name	T760
Test name
Test status
Simulation time	121016713 ps
CPU time	16.91 seconds
Started	Sep 03 11:54:15 PM UTC 24
Finished	Sep 03 11:54:33 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933227905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.3933227905
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/43.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3928700537
Short name	T834
Test name
Test status
Simulation time	27615514295 ps
CPU time	124.69 seconds
Started	Sep 03 11:54:15 PM UTC 24
Finished	Sep 03 11:56:22 PM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928700537 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.3928700537
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/43.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2005268599
Short name	T753
Test name
Test status
Simulation time	144193912 ps
CPU time	7.27 seconds
Started	Sep 03 11:54:19 PM UTC 24
Finished	Sep 03 11:54:28 PM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005268599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.2005268599
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/43.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.4277481905
Short name	T761
Test name
Test status
Simulation time	162386064 ps
CPU time	16.62 seconds
Started	Sep 03 11:54:18 PM UTC 24
Finished	Sep 03 11:54:36 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277481905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.4277481905
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/43.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random.402002504
Short name	T762
Test name
Test status
Simulation time	123633838 ps
CPU time	20.2 seconds
Started	Sep 03 11:54:15 PM UTC 24
Finished	Sep 03 11:54:36 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402002504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.402002504
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/43.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.1293124492
Short name	T877
Test name
Test status
Simulation time	174783805491 ps
CPU time	284.89 seconds
Started	Sep 03 11:54:15 PM UTC 24
Finished	Sep 03 11:59:03 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293124492 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1293124492
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/43.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1324443590
Short name	T838
Test name
Test status
Simulation time	18182794217 ps
CPU time	128.8 seconds
Started	Sep 03 11:54:15 PM UTC 24
Finished	Sep 03 11:56:26 PM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324443590 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1324443590
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/43.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.4103500883
Short name	T769
Test name
Test status
Simulation time	329927091 ps
CPU time	33.93 seconds
Started	Sep 03 11:54:15 PM UTC 24
Finished	Sep 03 11:54:50 PM UTC 24
Peak memory	218868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103500883 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.4103500883
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/43.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.2437805287
Short name	T768
Test name
Test status
Simulation time	1710956651 ps
CPU time	28.41 seconds
Started	Sep 03 11:54:16 PM UTC 24
Finished	Sep 03 11:54:46 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437805287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2437805287
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/43.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.86452445
Short name	T748
Test name
Test status
Simulation time	144854102 ps
CPU time	5.57 seconds
Started	Sep 03 11:54:10 PM UTC 24
Finished	Sep 03 11:54:16 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86452445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.86452445
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/43.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2948011000
Short name	T765
Test name
Test status
Simulation time	4337092908 ps
CPU time	29.78 seconds
Started	Sep 03 11:54:12 PM UTC 24
Finished	Sep 03 11:54:43 PM UTC 24
Peak memory	216884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948011000 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2948011000
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/43.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.657762852
Short name	T766
Test name
Test status
Simulation time	5320495180 ps
CPU time	29.95 seconds
Started	Sep 03 11:54:12 PM UTC 24
Finished	Sep 03 11:54:44 PM UTC 24
Peak memory	216944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657762852 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.657762852
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/43.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.1698295174
Short name	T749
Test name
Test status
Simulation time	35788909 ps
CPU time	3.43 seconds
Started	Sep 03 11:54:12 PM UTC 24
Finished	Sep 03 11:54:17 PM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698295174 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.1698295174
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/43.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.3124612263
Short name	T801
Test name
Test status
Simulation time	625756409 ps
CPU time	70.03 seconds
Started	Sep 03 11:54:21 PM UTC 24
Finished	Sep 03 11:55:33 PM UTC 24
Peak memory	218880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124612263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3124612263
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/43.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2340775423
Short name	T795
Test name
Test status
Simulation time	2624567755 ps
CPU time	59.49 seconds
Started	Sep 03 11:54:24 PM UTC 24
Finished	Sep 03 11:55:25 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340775423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2340775423
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/43.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2995886999
Short name	T890
Test name
Test status
Simulation time	11184933650 ps
CPU time	394.03 seconds
Started	Sep 03 11:54:22 PM UTC 24
Finished	Sep 04 12:01:02 AM UTC 24
Peak memory	223048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995886999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.2995886999
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/43.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3357577760
Short name	T827
Test name
Test status
Simulation time	359171196 ps
CPU time	104.36 seconds
Started	Sep 03 11:54:27 PM UTC 24
Finished	Sep 03 11:56:13 PM UTC 24
Peak memory	222920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357577760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.3357577760
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/43.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.3113793577
Short name	T757
Test name
Test status
Simulation time	243931183 ps
CPU time	12.69 seconds
Started	Sep 03 11:54:18 PM UTC 24
Finished	Sep 03 11:54:32 PM UTC 24
Peak memory	216760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113793577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3113793577
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/43.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.2822794629
Short name	T783
Test name
Test status
Simulation time	1857211411 ps
CPU time	35.96 seconds
Started	Sep 03 11:54:35 PM UTC 24
Finished	Sep 03 11:55:12 PM UTC 24
Peak memory	216968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822794629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.2822794629
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/44.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.4011250228
Short name	T884
Test name
Test status
Simulation time	65899887655 ps
CPU time	305.89 seconds
Started	Sep 03 11:54:38 PM UTC 24
Finished	Sep 03 11:59:48 PM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011250228 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.4011250228
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/44.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.1504927691
Short name	T785
Test name
Test status
Simulation time	1708441587 ps
CPU time	28.47 seconds
Started	Sep 03 11:54:45 PM UTC 24
Finished	Sep 03 11:55:15 PM UTC 24
Peak memory	216844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504927691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.1504927691
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/44.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.2447500309
Short name	T779
Test name
Test status
Simulation time	200669864 ps
CPU time	18.34 seconds
Started	Sep 03 11:54:41 PM UTC 24
Finished	Sep 03 11:55:01 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447500309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2447500309
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/44.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.2633925744
Short name	T763
Test name
Test status
Simulation time	39949875 ps
CPU time	6.18 seconds
Started	Sep 03 11:54:33 PM UTC 24
Finished	Sep 03 11:54:40 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633925744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2633925744
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/44.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.3602406424
Short name	T887
Test name
Test status
Simulation time	55796724558 ps
CPU time	341.62 seconds
Started	Sep 03 11:54:35 PM UTC 24
Finished	Sep 04 12:00:21 AM UTC 24
Peak memory	219272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602406424 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3602406424
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/44.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3264518514
Short name	T863
Test name
Test status
Simulation time	18167614408 ps
CPU time	179.3 seconds
Started	Sep 03 11:54:35 PM UTC 24
Finished	Sep 03 11:57:37 PM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264518514 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3264518514
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/44.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.2344841517
Short name	T774
Test name
Test status
Simulation time	216490803 ps
CPU time	21.17 seconds
Started	Sep 03 11:54:33 PM UTC 24
Finished	Sep 03 11:54:56 PM UTC 24
Peak memory	216752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344841517 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.2344841517
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/44.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.645049004
Short name	T767
Test name
Test status
Simulation time	111815668 ps
CPU time	4.33 seconds
Started	Sep 03 11:54:38 PM UTC 24
Finished	Sep 03 11:54:44 PM UTC 24
Peak memory	217084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645049004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.645049004
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/44.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.627858906
Short name	T756
Test name
Test status
Simulation time	37817174 ps
CPU time	3.09 seconds
Started	Sep 03 11:54:27 PM UTC 24
Finished	Sep 03 11:54:31 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627858906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.627858906
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/44.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3118653094
Short name	T787
Test name
Test status
Simulation time	6000572016 ps
CPU time	44.08 seconds
Started	Sep 03 11:54:31 PM UTC 24
Finished	Sep 03 11:55:16 PM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118653094 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3118653094
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/44.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2395480099
Short name	T793
Test name
Test status
Simulation time	6501263505 ps
CPU time	48.79 seconds
Started	Sep 03 11:54:33 PM UTC 24
Finished	Sep 03 11:55:23 PM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395480099 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2395480099
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/44.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2352447511
Short name	T758
Test name
Test status
Simulation time	28988598 ps
CPU time	2.57 seconds
Started	Sep 03 11:54:29 PM UTC 24
Finished	Sep 03 11:54:33 PM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352447511 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2352447511
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/44.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.1188072987
Short name	T826
Test name
Test status
Simulation time	952530633 ps
CPU time	82.64 seconds
Started	Sep 03 11:54:48 PM UTC 24
Finished	Sep 03 11:56:12 PM UTC 24
Peak memory	220928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188072987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1188072987
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/44.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2497191681
Short name	T791
Test name
Test status
Simulation time	1339289554 ps
CPU time	32.18 seconds
Started	Sep 03 11:54:48 PM UTC 24
Finished	Sep 03 11:55:21 PM UTC 24
Peak memory	218888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497191681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2497191681
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/44.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3259136125
Short name	T896
Test name
Test status
Simulation time	11657661800 ps
CPU time	502.07 seconds
Started	Sep 03 11:54:48 PM UTC 24
Finished	Sep 04 12:03:16 AM UTC 24
Peak memory	224668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259136125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.3259136125
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/44.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.1798038229
Short name	T880
Test name
Test status
Simulation time	3724789865 ps
CPU time	263.91 seconds
Started	Sep 03 11:54:52 PM UTC 24
Finished	Sep 03 11:59:20 PM UTC 24
Peak memory	223740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798038229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.1798038229
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/44.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.1208565954
Short name	T778
Test name
Test status
Simulation time	782920049 ps
CPU time	14.37 seconds
Started	Sep 03 11:54:45 PM UTC 24
Finished	Sep 03 11:55:00 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208565954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1208565954
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/44.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.638843019
Short name	T800
Test name
Test status
Simulation time	690544489 ps
CPU time	31.92 seconds
Started	Sep 03 11:54:59 PM UTC 24
Finished	Sep 03 11:55:32 PM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638843019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.638843019
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/45.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1383969222
Short name	T900
Test name
Test status
Simulation time	79408686965 ps
CPU time	924.05 seconds
Started	Sep 03 11:55:02 PM UTC 24
Finished	Sep 04 12:10:36 AM UTC 24
Peak memory	220500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383969222 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.1383969222
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/45.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2185102564
Short name	T784
Test name
Test status
Simulation time	47708658 ps
CPU time	4.53 seconds
Started	Sep 03 11:55:09 PM UTC 24
Finished	Sep 03 11:55:15 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185102564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.2185102564
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/45.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.608621134
Short name	T807
Test name
Test status
Simulation time	1489992889 ps
CPU time	36.92 seconds
Started	Sep 03 11:55:05 PM UTC 24
Finished	Sep 03 11:55:43 PM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608621134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.608621134
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/45.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.4095745689
Short name	T781
Test name
Test status
Simulation time	155686088 ps
CPU time	8.66 seconds
Started	Sep 03 11:54:57 PM UTC 24
Finished	Sep 03 11:55:07 PM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095745689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.4095745689
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/45.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.3175205945
Short name	T844
Test name
Test status
Simulation time	12999859443 ps
CPU time	97.17 seconds
Started	Sep 03 11:54:57 PM UTC 24
Finished	Sep 03 11:56:36 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175205945 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3175205945
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/45.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1814983754
Short name	T786
Test name
Test status
Simulation time	891758048 ps
CPU time	14.71 seconds
Started	Sep 03 11:54:59 PM UTC 24
Finished	Sep 03 11:55:15 PM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814983754 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1814983754
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/45.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.3429852406
Short name	T780
Test name
Test status
Simulation time	89927609 ps
CPU time	5.07 seconds
Started	Sep 03 11:54:57 PM UTC 24
Finished	Sep 03 11:55:03 PM UTC 24
Peak memory	216752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429852406 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.3429852406
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/45.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.3543914605
Short name	T792
Test name
Test status
Simulation time	2798933138 ps
CPU time	17.29 seconds
Started	Sep 03 11:55:03 PM UTC 24
Finished	Sep 03 11:55:22 PM UTC 24
Peak memory	216892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543914605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3543914605
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/45.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.3238518237
Short name	T776
Test name
Test status
Simulation time	71585838 ps
CPU time	3.42 seconds
Started	Sep 03 11:54:53 PM UTC 24
Finished	Sep 03 11:54:58 PM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238518237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3238518237
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/45.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.440184864
Short name	T818
Test name
Test status
Simulation time	32322544552 ps
CPU time	63.03 seconds
Started	Sep 03 11:54:57 PM UTC 24
Finished	Sep 03 11:56:02 PM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440184864 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.440184864
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/45.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1652452352
Short name	T798
Test name
Test status
Simulation time	8564430858 ps
CPU time	30.94 seconds
Started	Sep 03 11:54:57 PM UTC 24
Finished	Sep 03 11:55:29 PM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652452352 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1652452352
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/45.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2051536465
Short name	T777
Test name
Test status
Simulation time	30654762 ps
CPU time	3.59 seconds
Started	Sep 03 11:54:53 PM UTC 24
Finished	Sep 03 11:54:58 PM UTC 24
Peak memory	217128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051536465 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.2051536465
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/45.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.1693120254
Short name	T861
Test name
Test status
Simulation time	3928913397 ps
CPU time	131.53 seconds
Started	Sep 03 11:55:09 PM UTC 24
Finished	Sep 03 11:57:23 PM UTC 24
Peak memory	219208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693120254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1693120254
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/45.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.778113846
Short name	T871
Test name
Test status
Simulation time	9444766976 ps
CPU time	179.62 seconds
Started	Sep 03 11:55:13 PM UTC 24
Finished	Sep 03 11:58:16 PM UTC 24
Peak memory	221000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778113846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.778113846
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/45.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2050129172
Short name	T886
Test name
Test status
Simulation time	1074584404 ps
CPU time	296.5 seconds
Started	Sep 03 11:55:13 PM UTC 24
Finished	Sep 04 12:00:14 AM UTC 24
Peak memory	223312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050129172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.2050129172
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/45.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3861647302
Short name	T803
Test name
Test status
Simulation time	19914371 ps
CPU time	18.66 seconds
Started	Sep 03 11:55:17 PM UTC 24
Finished	Sep 03 11:55:37 PM UTC 24
Peak memory	217100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861647302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.3861647302
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/45.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.2337375906
Short name	T614
Test name
Test status
Simulation time	661490598 ps
CPU time	22.36 seconds
Started	Sep 03 11:55:09 PM UTC 24
Finished	Sep 03 11:55:33 PM UTC 24
Peak memory	218880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337375906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2337375906
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/45.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.2116660890
Short name	T840
Test name
Test status
Simulation time	2059720917 ps
CPU time	68.94 seconds
Started	Sep 03 11:55:23 PM UTC 24
Finished	Sep 03 11:56:34 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116660890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2116660890
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/46.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1138923313
Short name	T878
Test name
Test status
Simulation time	116184171817 ps
CPU time	218.88 seconds
Started	Sep 03 11:55:25 PM UTC 24
Finished	Sep 03 11:59:08 PM UTC 24
Peak memory	219208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138923313 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.1138923313
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/46.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1571507845
Short name	T811
Test name
Test status
Simulation time	277533378 ps
CPU time	23.02 seconds
Started	Sep 03 11:55:28 PM UTC 24
Finished	Sep 03 11:55:52 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571507845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.1571507845
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/46.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.2416155852
Short name	T802
Test name
Test status
Simulation time	201546307 ps
CPU time	9.01 seconds
Started	Sep 03 11:55:25 PM UTC 24
Finished	Sep 03 11:55:36 PM UTC 24
Peak memory	216752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416155852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2416155852
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/46.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.306107201
Short name	T808
Test name
Test status
Simulation time	549865193 ps
CPU time	25.56 seconds
Started	Sep 03 11:55:19 PM UTC 24
Finished	Sep 03 11:55:46 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306107201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.306107201
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/46.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.406492279
Short name	T895
Test name
Test status
Simulation time	196200455504 ps
CPU time	432.06 seconds
Started	Sep 03 11:55:23 PM UTC 24
Finished	Sep 04 12:02:40 AM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406492279 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.406492279
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/46.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.687744604
Short name	T881
Test name
Test status
Simulation time	27446616062 ps
CPU time	236.29 seconds
Started	Sep 03 11:55:23 PM UTC 24
Finished	Sep 03 11:59:23 PM UTC 24
Peak memory	218944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687744604 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.687744604
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/46.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.199539288
Short name	T814
Test name
Test status
Simulation time	993695468 ps
CPU time	34.04 seconds
Started	Sep 03 11:55:19 PM UTC 24
Finished	Sep 03 11:55:55 PM UTC 24
Peak memory	216756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199539288 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.199539288
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/46.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.2805588889
Short name	T821
Test name
Test status
Simulation time	1338087011 ps
CPU time	36.7 seconds
Started	Sep 03 11:55:25 PM UTC 24
Finished	Sep 03 11:56:04 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805588889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2805588889
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/46.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.3205596584
Short name	T789
Test name
Test status
Simulation time	167594756 ps
CPU time	2.97 seconds
Started	Sep 03 11:55:17 PM UTC 24
Finished	Sep 03 11:55:21 PM UTC 24
Peak memory	216748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205596584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3205596584
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/46.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2286590114
Short name	T810
Test name
Test status
Simulation time	6310370324 ps
CPU time	32.1 seconds
Started	Sep 03 11:55:17 PM UTC 24
Finished	Sep 03 11:55:50 PM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286590114 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2286590114
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/46.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.4215483191
Short name	T812
Test name
Test status
Simulation time	5714936078 ps
CPU time	32.14 seconds
Started	Sep 03 11:55:19 PM UTC 24
Finished	Sep 03 11:55:53 PM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215483191 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.4215483191
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/46.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1339268272
Short name	T790
Test name
Test status
Simulation time	45901040 ps
CPU time	3.17 seconds
Started	Sep 03 11:55:17 PM UTC 24
Finished	Sep 03 11:55:21 PM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339268272 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1339268272
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/46.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.156413370
Short name	T868
Test name
Test status
Simulation time	7383365415 ps
CPU time	143.84 seconds
Started	Sep 03 11:55:28 PM UTC 24
Finished	Sep 03 11:57:54 PM UTC 24
Peak memory	223040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156413370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.156413370
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/46.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.437954061
Short name	T833
Test name
Test status
Simulation time	1143361002 ps
CPU time	49.73 seconds
Started	Sep 03 11:55:30 PM UTC 24
Finished	Sep 03 11:56:22 PM UTC 24
Peak memory	216776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437954061 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.437954061
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/46.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2477828131
Short name	T875
Test name
Test status
Simulation time	600914425 ps
CPU time	193.94 seconds
Started	Sep 03 11:55:30 PM UTC 24
Finished	Sep 03 11:58:47 PM UTC 24
Peak memory	220944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477828131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.2477828131
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/46.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3842343838
Short name	T47
Test name
Test status
Simulation time	21307965362 ps
CPU time	189.89 seconds
Started	Sep 03 11:55:32 PM UTC 24
Finished	Sep 03 11:58:45 PM UTC 24
Peak memory	223048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842343838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.3842343838
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/46.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.1105006744
Short name	T809
Test name
Test status
Simulation time	547355226 ps
CPU time	21.08 seconds
Started	Sep 03 11:55:26 PM UTC 24
Finished	Sep 03 11:55:48 PM UTC 24
Peak memory	219204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105006744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1105006744
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/46.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.549345286
Short name	T816
Test name
Test status
Simulation time	305397408 ps
CPU time	12.62 seconds
Started	Sep 03 11:55:42 PM UTC 24
Finished	Sep 03 11:55:56 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549345286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.549345286
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/47.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.788758633
Short name	T898
Test name
Test status
Simulation time	176220702311 ps
CPU time	583.65 seconds
Started	Sep 03 11:55:45 PM UTC 24
Finished	Sep 04 12:05:35 AM UTC 24
Peak memory	222612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788758633 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.788758633
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/47.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3843298598
Short name	T824
Test name
Test status
Simulation time	459367995 ps
CPU time	14.75 seconds
Started	Sep 03 11:55:51 PM UTC 24
Finished	Sep 03 11:56:07 PM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843298598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.3843298598
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/47.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1898903002
Short name	T815
Test name
Test status
Simulation time	41635851 ps
CPU time	5.01 seconds
Started	Sep 03 11:55:49 PM UTC 24
Finished	Sep 03 11:55:55 PM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898903002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1898903002
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/47.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.614217757
Short name	T813
Test name
Test status
Simulation time	570909562 ps
CPU time	12.15 seconds
Started	Sep 03 11:55:40 PM UTC 24
Finished	Sep 03 11:55:53 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614217757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.614217757
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/47.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.3993747193
Short name	T848
Test name
Test status
Simulation time	10157558247 ps
CPU time	60.47 seconds
Started	Sep 03 11:55:40 PM UTC 24
Finished	Sep 03 11:56:42 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993747193 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3993747193
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/47.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1998827103
Short name	T148
Test name
Test status
Simulation time	91459936415 ps
CPU time	201.04 seconds
Started	Sep 03 11:55:40 PM UTC 24
Finished	Sep 03 11:59:04 PM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998827103 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1998827103
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/47.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.242206515
Short name	T829
Test name
Test status
Simulation time	1094912814 ps
CPU time	34.05 seconds
Started	Sep 03 11:55:40 PM UTC 24
Finished	Sep 03 11:56:15 PM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242206515 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.242206515
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/47.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.3430592178
Short name	T830
Test name
Test status
Simulation time	1334391566 ps
CPU time	26.88 seconds
Started	Sep 03 11:55:47 PM UTC 24
Finished	Sep 03 11:56:16 PM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430592178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3430592178
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/47.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.9120785
Short name	T806
Test name
Test status
Simulation time	54039548 ps
CPU time	3.4 seconds
Started	Sep 03 11:55:34 PM UTC 24
Finished	Sep 03 11:55:38 PM UTC 24
Peak memory	217132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9120785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T EST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.9120785
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/47.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2477193602
Short name	T819
Test name
Test status
Simulation time	11924199143 ps
CPU time	27.32 seconds
Started	Sep 03 11:55:34 PM UTC 24
Finished	Sep 03 11:56:03 PM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477193602 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2477193602
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/47.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3981822058
Short name	T820
Test name
Test status
Simulation time	7271430516 ps
CPU time	25.33 seconds
Started	Sep 03 11:55:37 PM UTC 24
Finished	Sep 03 11:56:03 PM UTC 24
Peak memory	217200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981822058 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3981822058
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/47.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1819442911
Short name	T805
Test name
Test status
Simulation time	45264023 ps
CPU time	2.8 seconds
Started	Sep 03 11:55:34 PM UTC 24
Finished	Sep 03 11:55:38 PM UTC 24
Peak memory	216936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819442911 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1819442911
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/47.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.1584880111
Short name	T852
Test name
Test status
Simulation time	962459452 ps
CPU time	55.19 seconds
Started	Sep 03 11:55:53 PM UTC 24
Finished	Sep 03 11:56:50 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584880111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1584880111
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/47.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2766613536
Short name	T846
Test name
Test status
Simulation time	1624635474 ps
CPU time	41.92 seconds
Started	Sep 03 11:55:55 PM UTC 24
Finished	Sep 03 11:56:39 PM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766613536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2766613536
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/47.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1296773592
Short name	T873
Test name
Test status
Simulation time	533928625 ps
CPU time	163.23 seconds
Started	Sep 03 11:55:53 PM UTC 24
Finished	Sep 03 11:58:39 PM UTC 24
Peak memory	221196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296773592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.1296773592
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/47.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2219066353
Short name	T869
Test name
Test status
Simulation time	3902266507 ps
CPU time	129.18 seconds
Started	Sep 03 11:55:55 PM UTC 24
Finished	Sep 03 11:58:07 PM UTC 24
Peak memory	222984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219066353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.2219066353
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/47.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.1967431201
Short name	T825
Test name
Test status
Simulation time	434645419 ps
CPU time	16.67 seconds
Started	Sep 03 11:55:51 PM UTC 24
Finished	Sep 03 11:56:09 PM UTC 24
Peak memory	218808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967431201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1967431201
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/47.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.3882740975
Short name	T843
Test name
Test status
Simulation time	733030547 ps
CPU time	26.93 seconds
Started	Sep 03 11:56:07 PM UTC 24
Finished	Sep 03 11:56:36 PM UTC 24
Peak memory	219144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882740975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3882740975
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/48.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.294707962
Short name	T891
Test name
Test status
Simulation time	98239252394 ps
CPU time	294.03 seconds
Started	Sep 03 11:56:07 PM UTC 24
Finished	Sep 04 12:01:06 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294707962 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.294707962
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/48.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.1950784235
Short name	T832
Test name
Test status
Simulation time	32583667 ps
CPU time	4.65 seconds
Started	Sep 03 11:56:13 PM UTC 24
Finished	Sep 03 11:56:19 PM UTC 24
Peak memory	216968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950784235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.1950784235
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/48.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.1408682358
Short name	T831
Test name
Test status
Simulation time	53288492 ps
CPU time	6.67 seconds
Started	Sep 03 11:56:11 PM UTC 24
Finished	Sep 03 11:56:19 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408682358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1408682358
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/48.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.175707941
Short name	T828
Test name
Test status
Simulation time	166108266 ps
CPU time	5.76 seconds
Started	Sep 03 11:56:07 PM UTC 24
Finished	Sep 03 11:56:14 PM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175707941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.175707941
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/48.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.2660679377
Short name	T882
Test name
Test status
Simulation time	50954567097 ps
CPU time	205.2 seconds
Started	Sep 03 11:56:07 PM UTC 24
Finished	Sep 03 11:59:36 PM UTC 24
Peak memory	219196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660679377 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2660679377
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/48.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.1513233922
Short name	T888
Test name
Test status
Simulation time	67305291300 ps
CPU time	256.59 seconds
Started	Sep 03 11:56:07 PM UTC 24
Finished	Sep 04 12:00:28 AM UTC 24
Peak memory	218948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513233922 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.1513233922
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/48.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.1238783622
Short name	T842
Test name
Test status
Simulation time	228650113 ps
CPU time	25.25 seconds
Started	Sep 03 11:56:07 PM UTC 24
Finished	Sep 03 11:56:34 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238783622 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.1238783622
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/48.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.4159618449
Short name	T849
Test name
Test status
Simulation time	3848720644 ps
CPU time	32.03 seconds
Started	Sep 03 11:56:09 PM UTC 24
Finished	Sep 03 11:56:43 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159618449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.4159618449
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/48.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.3521144111
Short name	T822
Test name
Test status
Simulation time	464082967 ps
CPU time	5.39 seconds
Started	Sep 03 11:55:58 PM UTC 24
Finished	Sep 03 11:56:04 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521144111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3521144111
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/48.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2169550996
Short name	T855
Test name
Test status
Simulation time	6333809730 ps
CPU time	55.56 seconds
Started	Sep 03 11:55:58 PM UTC 24
Finished	Sep 03 11:56:55 PM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169550996 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2169550996
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/48.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3473045851
Short name	T841
Test name
Test status
Simulation time	3095039843 ps
CPU time	30.57 seconds
Started	Sep 03 11:56:02 PM UTC 24
Finished	Sep 03 11:56:34 PM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473045851 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3473045851
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/48.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2176714768
Short name	T817
Test name
Test status
Simulation time	43696433 ps
CPU time	2.73 seconds
Started	Sep 03 11:55:58 PM UTC 24
Finished	Sep 03 11:56:01 PM UTC 24
Peak memory	216804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176714768 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2176714768
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/48.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.3537205894
Short name	T264
Test name
Test status
Simulation time	393164970 ps
CPU time	54.97 seconds
Started	Sep 03 11:56:15 PM UTC 24
Finished	Sep 03 11:57:12 PM UTC 24
Peak memory	218816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537205894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3537205894
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/48.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1839196411
Short name	T867
Test name
Test status
Simulation time	4107896533 ps
CPU time	95.17 seconds
Started	Sep 03 11:56:16 PM UTC 24
Finished	Sep 03 11:57:53 PM UTC 24
Peak memory	219272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839196411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1839196411
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/48.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.941914988
Short name	T870
Test name
Test status
Simulation time	1912151771 ps
CPU time	114.13 seconds
Started	Sep 03 11:56:15 PM UTC 24
Finished	Sep 03 11:58:12 PM UTC 24
Peak memory	220924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941914988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.941914988
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/48.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3034609967
Short name	T892
Test name
Test status
Simulation time	1914107516 ps
CPU time	306.15 seconds
Started	Sep 03 11:56:17 PM UTC 24
Finished	Sep 04 12:01:28 AM UTC 24
Peak memory	233596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034609967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.3034609967
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/48.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.1558639087
Short name	T839
Test name
Test status
Simulation time	193975820 ps
CPU time	19.55 seconds
Started	Sep 03 11:56:11 PM UTC 24
Finished	Sep 03 11:56:32 PM UTC 24
Peak memory	218888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558639087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.1558639087
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/48.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.223973341
Short name	T856
Test name
Test status
Simulation time	631453168 ps
CPU time	26.33 seconds
Started	Sep 03 11:56:28 PM UTC 24
Finished	Sep 03 11:56:56 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223973341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.223973341
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/49.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.638334844
Short name	T899
Test name
Test status
Simulation time	66481437226 ps
CPU time	667.29 seconds
Started	Sep 03 11:56:34 PM UTC 24
Finished	Sep 04 12:07:49 AM UTC 24
Peak memory	220568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638334844 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.638334844
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/49.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1263201367
Short name	T857
Test name
Test status
Simulation time	202289988 ps
CPU time	18.54 seconds
Started	Sep 03 11:56:38 PM UTC 24
Finished	Sep 03 11:56:58 PM UTC 24
Peak memory	216968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263201367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.1263201367
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/49.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.4078976606
Short name	T854
Test name
Test status
Simulation time	534305898 ps
CPU time	16.8 seconds
Started	Sep 03 11:56:36 PM UTC 24
Finished	Sep 03 11:56:54 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078976606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.4078976606
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/49.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.3008369230
Short name	T847
Test name
Test status
Simulation time	114598490 ps
CPU time	15.17 seconds
Started	Sep 03 11:56:25 PM UTC 24
Finished	Sep 03 11:56:41 PM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008369230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.3008369230
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/49.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.1803449141
Short name	T889
Test name
Test status
Simulation time	36672493260 ps
CPU time	269.5 seconds
Started	Sep 03 11:56:26 PM UTC 24
Finished	Sep 04 12:01:00 AM UTC 24
Peak memory	216852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803449141 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1803449141
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/49.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2865870916
Short name	T860
Test name
Test status
Simulation time	6464064157 ps
CPU time	53.31 seconds
Started	Sep 03 11:56:26 PM UTC 24
Finished	Sep 03 11:57:21 PM UTC 24
Peak memory	216792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865870916 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2865870916
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/49.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.2023079036
Short name	T845
Test name
Test status
Simulation time	93909328 ps
CPU time	12.72 seconds
Started	Sep 03 11:56:25 PM UTC 24
Finished	Sep 03 11:56:39 PM UTC 24
Peak memory	217144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023079036 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.2023079036
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/49.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.2792896250
Short name	T858
Test name
Test status
Simulation time	1920353741 ps
CPU time	29.41 seconds
Started	Sep 03 11:56:36 PM UTC 24
Finished	Sep 03 11:57:07 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792896250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2792896250
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/49.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.3328258637
Short name	T835
Test name
Test status
Simulation time	98552834 ps
CPU time	4.36 seconds
Started	Sep 03 11:56:18 PM UTC 24
Finished	Sep 03 11:56:23 PM UTC 24
Peak memory	217136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328258637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.3328258637
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/49.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.967709049
Short name	T853
Test name
Test status
Simulation time	5943604503 ps
CPU time	30.06 seconds
Started	Sep 03 11:56:21 PM UTC 24
Finished	Sep 03 11:56:53 PM UTC 24
Peak memory	216816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967709049 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.967709049
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/49.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1218463332
Short name	T850
Test name
Test status
Simulation time	4526982324 ps
CPU time	24.62 seconds
Started	Sep 03 11:56:22 PM UTC 24
Finished	Sep 03 11:56:49 PM UTC 24
Peak memory	216876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218463332 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1218463332
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/49.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1410515241
Short name	T837
Test name
Test status
Simulation time	29801602 ps
CPU time	3.33 seconds
Started	Sep 03 11:56:21 PM UTC 24
Finished	Sep 03 11:56:26 PM UTC 24
Peak memory	216740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410515241 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1410515241
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/49.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.236004359
Short name	T876
Test name
Test status
Simulation time	3667527743 ps
CPU time	141.76 seconds
Started	Sep 03 11:56:38 PM UTC 24
Finished	Sep 03 11:59:02 PM UTC 24
Peak memory	220928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236004359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.236004359
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/49.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.214680285
Short name	T866
Test name
Test status
Simulation time	3823491704 ps
CPU time	70.7 seconds
Started	Sep 03 11:56:40 PM UTC 24
Finished	Sep 03 11:57:53 PM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214680285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.214680285
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/49.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1444264498
Short name	T893
Test name
Test status
Simulation time	3027977208 ps
CPU time	308.33 seconds
Started	Sep 03 11:56:40 PM UTC 24
Finished	Sep 04 12:01:53 AM UTC 24
Peak memory	223676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444264498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.1444264498
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/49.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.2876664042
Short name	T48
Test name
Test status
Simulation time	1900960363 ps
CPU time	365.83 seconds
Started	Sep 03 11:56:43 PM UTC 24
Finished	Sep 04 12:02:54 AM UTC 24
Peak memory	233596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876664042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.2876664042
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/49.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.1525351770
Short name	T358
Test name
Test status
Simulation time	641350408 ps
CPU time	18.58 seconds
Started	Sep 03 11:56:36 PM UTC 24
Finished	Sep 03 11:56:56 PM UTC 24
Peak memory	218816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525351770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1525351770
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/49.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.1931291616
Short name	T197
Test name
Test status
Simulation time	290020015 ps
CPU time	37.35 seconds
Started	Sep 03 11:38:49 PM UTC 24
Finished	Sep 03 11:39:28 PM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931291616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1931291616
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/5.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.4052712052
Short name	T249
Test name
Test status
Simulation time	17234152154 ps
CPU time	87.12 seconds
Started	Sep 03 11:38:49 PM UTC 24
Finished	Sep 03 11:40:18 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052712052 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.4052712052
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/5.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1447879609
Short name	T392
Test name
Test status
Simulation time	161906136 ps
CPU time	21.25 seconds
Started	Sep 03 11:38:55 PM UTC 24
Finished	Sep 03 11:39:18 PM UTC 24
Peak memory	216704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447879609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1447879609
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/5.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.1962618740
Short name	T393
Test name
Test status
Simulation time	1136086333 ps
CPU time	26.35 seconds
Started	Sep 03 11:38:53 PM UTC 24
Finished	Sep 03 11:39:21 PM UTC 24
Peak memory	216760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962618740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1962618740
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/5.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random.2887069643
Short name	T87
Test name
Test status
Simulation time	338557691 ps
CPU time	16.75 seconds
Started	Sep 03 11:38:46 PM UTC 24
Finished	Sep 03 11:39:04 PM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887069643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2887069643
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/5.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.610263363
Short name	T237
Test name
Test status
Simulation time	18113529938 ps
CPU time	107.92 seconds
Started	Sep 03 11:38:47 PM UTC 24
Finished	Sep 03 11:40:37 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610263363 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.610263363
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/5.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.2351066290
Short name	T253
Test name
Test status
Simulation time	30119909521 ps
CPU time	243.48 seconds
Started	Sep 03 11:38:47 PM UTC 24
Finished	Sep 03 11:42:54 PM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351066290 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2351066290
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/5.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.192936875
Short name	T270
Test name
Test status
Simulation time	238551397 ps
CPU time	22.27 seconds
Started	Sep 03 11:38:47 PM UTC 24
Finished	Sep 03 11:39:11 PM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192936875 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.192936875
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/5.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.4128144265
Short name	T266
Test name
Test status
Simulation time	564728716 ps
CPU time	13.05 seconds
Started	Sep 03 11:38:52 PM UTC 24
Finished	Sep 03 11:39:06 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128144265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.4128144265
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/5.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.910755248
Short name	T251
Test name
Test status
Simulation time	224652852 ps
CPU time	3.89 seconds
Started	Sep 03 11:38:40 PM UTC 24
Finished	Sep 03 11:38:45 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910755248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.910755248
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/5.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.1501481973
Short name	T258
Test name
Test status
Simulation time	6408251259 ps
CPU time	26.73 seconds
Started	Sep 03 11:38:42 PM UTC 24
Finished	Sep 03 11:39:10 PM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501481973 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.1501481973
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/5.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.1908533020
Short name	T328
Test name
Test status
Simulation time	49089006 ps
CPU time	3.15 seconds
Started	Sep 03 11:38:42 PM UTC 24
Finished	Sep 03 11:38:46 PM UTC 24
Peak memory	216744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908533020 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.1908533020
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/5.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.1481400265
Short name	T95
Test name
Test status
Simulation time	5496838559 ps
CPU time	130.11 seconds
Started	Sep 03 11:38:59 PM UTC 24
Finished	Sep 03 11:41:11 PM UTC 24
Peak memory	219204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481400265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1481400265
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/5.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.407611536
Short name	T202
Test name
Test status
Simulation time	276237612 ps
CPU time	31.45 seconds
Started	Sep 03 11:39:01 PM UTC 24
Finished	Sep 03 11:39:34 PM UTC 24
Peak memory	216772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407611536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.407611536
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/5.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.961344721
Short name	T198
Test name
Test status
Simulation time	873762582 ps
CPU time	31.47 seconds
Started	Sep 03 11:38:55 PM UTC 24
Finished	Sep 03 11:39:28 PM UTC 24
Peak memory	218752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961344721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.961344721
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/5.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.2127344628
Short name	T91
Test name
Test status
Simulation time	3461584884 ps
CPU time	26.77 seconds
Started	Sep 03 11:39:11 PM UTC 24
Finished	Sep 03 11:39:39 PM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127344628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2127344628
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/6.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.634873280
Short name	T107
Test name
Test status
Simulation time	56799742061 ps
CPU time	245.72 seconds
Started	Sep 03 11:39:13 PM UTC 24
Finished	Sep 03 11:43:22 PM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634873280 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.634873280
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/6.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.4050729164
Short name	T201
Test name
Test status
Simulation time	913309421 ps
CPU time	17.55 seconds
Started	Sep 03 11:39:14 PM UTC 24
Finished	Sep 03 11:39:33 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050729164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.4050729164
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/6.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.2050448925
Short name	T357
Test name
Test status
Simulation time	1424059345 ps
CPU time	38.46 seconds
Started	Sep 03 11:39:13 PM UTC 24
Finished	Sep 03 11:39:53 PM UTC 24
Peak memory	216760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050448925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2050448925
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/6.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random.1770414484
Short name	T89
Test name
Test status
Simulation time	750313922 ps
CPU time	25.76 seconds
Started	Sep 03 11:39:08 PM UTC 24
Finished	Sep 03 11:39:35 PM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770414484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1770414484
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/6.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.3556177574
Short name	T194
Test name
Test status
Simulation time	2202761221 ps
CPU time	16.6 seconds
Started	Sep 03 11:39:08 PM UTC 24
Finished	Sep 03 11:39:26 PM UTC 24
Peak memory	216828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556177574 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3556177574
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/6.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.573690660
Short name	T409
Test name
Test status
Simulation time	26251254661 ps
CPU time	163.87 seconds
Started	Sep 03 11:39:10 PM UTC 24
Finished	Sep 03 11:41:56 PM UTC 24
Peak memory	217156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573690660 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.573690660
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/6.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.2145876894
Short name	T391
Test name
Test status
Simulation time	14629758 ps
CPU time	3.31 seconds
Started	Sep 03 11:39:08 PM UTC 24
Finished	Sep 03 11:39:12 PM UTC 24
Peak memory	217076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145876894 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.2145876894
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/6.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.3245771425
Short name	T50
Test name
Test status
Simulation time	2165013402 ps
CPU time	35.93 seconds
Started	Sep 03 11:39:13 PM UTC 24
Finished	Sep 03 11:39:51 PM UTC 24
Peak memory	216892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245771425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3245771425
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/6.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.1095715703
Short name	T268
Test name
Test status
Simulation time	196612721 ps
CPU time	3.59 seconds
Started	Sep 03 11:39:02 PM UTC 24
Finished	Sep 03 11:39:07 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095715703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1095715703
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/6.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.1054199546
Short name	T126
Test name
Test status
Simulation time	5923131836 ps
CPU time	49.22 seconds
Started	Sep 03 11:39:04 PM UTC 24
Finished	Sep 03 11:39:55 PM UTC 24
Peak memory	217204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054199546 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1054199546
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/6.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3605392447
Short name	T291
Test name
Test status
Simulation time	4936376181 ps
CPU time	32.18 seconds
Started	Sep 03 11:39:08 PM UTC 24
Finished	Sep 03 11:39:41 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605392447 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3605392447
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/6.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.3205473481
Short name	T267
Test name
Test status
Simulation time	43770301 ps
CPU time	3.18 seconds
Started	Sep 03 11:39:02 PM UTC 24
Finished	Sep 03 11:39:06 PM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205473481 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.3205473481
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/6.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.2869822757
Short name	T101
Test name
Test status
Simulation time	18482466581 ps
CPU time	218.57 seconds
Started	Sep 03 11:39:15 PM UTC 24
Finished	Sep 03 11:42:57 PM UTC 24
Peak memory	222976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869822757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2869822757
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/6.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.2941919559
Short name	T199
Test name
Test status
Simulation time	187024612 ps
CPU time	8.61 seconds
Started	Sep 03 11:39:19 PM UTC 24
Finished	Sep 03 11:39:29 PM UTC 24
Peak memory	216824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941919559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.2941919559
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/6.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.2042864095
Short name	T119
Test name
Test status
Simulation time	15470076418 ps
CPU time	558.81 seconds
Started	Sep 03 11:39:15 PM UTC 24
Finished	Sep 03 11:48:41 PM UTC 24
Peak memory	225356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042864095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.2042864095
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/6.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1815313177
Short name	T388
Test name
Test status
Simulation time	1283436303 ps
CPU time	183.99 seconds
Started	Sep 03 11:39:19 PM UTC 24
Finished	Sep 03 11:42:26 PM UTC 24
Peak memory	220872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815313177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.1815313177
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/6.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.2261245850
Short name	T191
Test name
Test status
Simulation time	172043463 ps
CPU time	12.17 seconds
Started	Sep 03 11:39:13 PM UTC 24
Finished	Sep 03 11:39:27 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261245850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2261245850
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/6.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.1134004474
Short name	T200
Test name
Test status
Simulation time	45715406 ps
CPU time	3.68 seconds
Started	Sep 03 11:39:29 PM UTC 24
Finished	Sep 03 11:39:34 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134004474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1134004474
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/7.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.1399170998
Short name	T633
Test name
Test status
Simulation time	114340729957 ps
CPU time	703.25 seconds
Started	Sep 03 11:39:30 PM UTC 24
Finished	Sep 03 11:51:22 PM UTC 24
Peak memory	222616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399170998 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.1399170998
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/7.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.1728872465
Short name	T296
Test name
Test status
Simulation time	77905813 ps
CPU time	10.75 seconds
Started	Sep 03 11:39:35 PM UTC 24
Finished	Sep 03 11:39:48 PM UTC 24
Peak memory	217096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728872465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.1728872465
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/7.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.3026372265
Short name	T295
Test name
Test status
Simulation time	132807006 ps
CPU time	11.41 seconds
Started	Sep 03 11:39:32 PM UTC 24
Finished	Sep 03 11:39:45 PM UTC 24
Peak memory	217080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026372265 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3026372265
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/7.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random.2313698853
Short name	T290
Test name
Test status
Simulation time	101274664 ps
CPU time	10.91 seconds
Started	Sep 03 11:39:28 PM UTC 24
Finished	Sep 03 11:39:40 PM UTC 24
Peak memory	216840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313698853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.2313698853
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/7.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.4276001984
Short name	T63
Test name
Test status
Simulation time	35838217672 ps
CPU time	204.65 seconds
Started	Sep 03 11:39:29 PM UTC 24
Finished	Sep 03 11:42:57 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276001984 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.4276001984
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/7.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.388325465
Short name	T62
Test name
Test status
Simulation time	19018251220 ps
CPU time	170.84 seconds
Started	Sep 03 11:39:29 PM UTC 24
Finished	Sep 03 11:42:22 PM UTC 24
Peak memory	218940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388325465 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.388325465
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/7.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.4100574770
Short name	T292
Test name
Test status
Simulation time	135418523 ps
CPU time	13.44 seconds
Started	Sep 03 11:39:28 PM UTC 24
Finished	Sep 03 11:39:42 PM UTC 24
Peak memory	217084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100574770 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.4100574770
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/7.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.2481140496
Short name	T130
Test name
Test status
Simulation time	3051095048 ps
CPU time	28.01 seconds
Started	Sep 03 11:39:32 PM UTC 24
Finished	Sep 03 11:40:02 PM UTC 24
Peak memory	217216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481140496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2481140496
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/7.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.981495505
Short name	T192
Test name
Test status
Simulation time	130025366 ps
CPU time	4.36 seconds
Started	Sep 03 11:39:22 PM UTC 24
Finished	Sep 03 11:39:27 PM UTC 24
Peak memory	216752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981495505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.981495505
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/7.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.858935153
Short name	T127
Test name
Test status
Simulation time	4056935022 ps
CPU time	29.97 seconds
Started	Sep 03 11:39:28 PM UTC 24
Finished	Sep 03 11:39:59 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858935153 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.858935153
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/7.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.2312014903
Short name	T142
Test name
Test status
Simulation time	18400514562 ps
CPU time	41.3 seconds
Started	Sep 03 11:39:28 PM UTC 24
Finished	Sep 03 11:40:10 PM UTC 24
Peak memory	216944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312014903 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2312014903
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/7.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3168888963
Short name	T3
Test name
Test status
Simulation time	116744712 ps
CPU time	3.52 seconds
Started	Sep 03 11:39:26 PM UTC 24
Finished	Sep 03 11:39:30 PM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168888963 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3168888963
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/7.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.3678352592
Short name	T98
Test name
Test status
Simulation time	9324103381 ps
CPU time	122.48 seconds
Started	Sep 03 11:39:35 PM UTC 24
Finished	Sep 03 11:41:41 PM UTC 24
Peak memory	220992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678352592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3678352592
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/7.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1125435062
Short name	T206
Test name
Test status
Simulation time	766949696 ps
CPU time	87.87 seconds
Started	Sep 03 11:39:39 PM UTC 24
Finished	Sep 03 11:41:09 PM UTC 24
Peak memory	219140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125435062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1125435062
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/7.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1872246962
Short name	T153
Test name
Test status
Simulation time	5328719527 ps
CPU time	234.14 seconds
Started	Sep 03 11:39:35 PM UTC 24
Finished	Sep 03 11:43:34 PM UTC 24
Peak memory	222984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872246962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.1872246962
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/7.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.160489079
Short name	T374
Test name
Test status
Simulation time	305573246 ps
CPU time	44.21 seconds
Started	Sep 03 11:39:39 PM UTC 24
Finished	Sep 03 11:40:25 PM UTC 24
Peak memory	221264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160489079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.160489079
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/7.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.3046226694
Short name	T394
Test name
Test status
Simulation time	90835060 ps
CPU time	17.85 seconds
Started	Sep 03 11:39:34 PM UTC 24
Finished	Sep 03 11:39:53 PM UTC 24
Peak memory	218880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046226694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3046226694
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/7.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.2787450572
Short name	T129
Test name
Test status
Simulation time	269385097 ps
CPU time	10.65 seconds
Started	Sep 03 11:39:49 PM UTC 24
Finished	Sep 03 11:40:01 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787450572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.2787450572
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/8.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.3536641424
Short name	T396
Test name
Test status
Simulation time	1545742612 ps
CPU time	20.47 seconds
Started	Sep 03 11:39:55 PM UTC 24
Finished	Sep 03 11:40:17 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536641424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.3536641424
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/8.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.1439653379
Short name	T309
Test name
Test status
Simulation time	3004792963 ps
CPU time	36.18 seconds
Started	Sep 03 11:39:54 PM UTC 24
Finished	Sep 03 11:40:31 PM UTC 24
Peak memory	217140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439653379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1439653379
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/8.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random.1962091942
Short name	T275
Test name
Test status
Simulation time	177201669 ps
CPU time	23.3 seconds
Started	Sep 03 11:39:44 PM UTC 24
Finished	Sep 03 11:40:08 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962091942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1962091942
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/8.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.2050652402
Short name	T143
Test name
Test status
Simulation time	51551035824 ps
CPU time	176.21 seconds
Started	Sep 03 11:39:46 PM UTC 24
Finished	Sep 03 11:42:45 PM UTC 24
Peak memory	216836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050652402 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2050652402
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/8.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.4075155843
Short name	T423
Test name
Test status
Simulation time	26091680595 ps
CPU time	159.82 seconds
Started	Sep 03 11:39:46 PM UTC 24
Finished	Sep 03 11:42:28 PM UTC 24
Peak memory	217216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075155843 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.4075155843
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/8.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.1559340945
Short name	T132
Test name
Test status
Simulation time	209952147 ps
CPU time	20.76 seconds
Started	Sep 03 11:39:44 PM UTC 24
Finished	Sep 03 11:40:06 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559340945 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.1559340945
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/8.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.705303208
Short name	T128
Test name
Test status
Simulation time	110518301 ps
CPU time	6.72 seconds
Started	Sep 03 11:39:52 PM UTC 24
Finished	Sep 03 11:39:59 PM UTC 24
Peak memory	217092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705303208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.705303208
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/8.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.262764340
Short name	T293
Test name
Test status
Simulation time	34933288 ps
CPU time	2.25 seconds
Started	Sep 03 11:39:40 PM UTC 24
Finished	Sep 03 11:39:43 PM UTC 24
Peak memory	217140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262764340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.262764340
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/8.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.1342342610
Short name	T6
Test name
Test status
Simulation time	7434854410 ps
CPU time	50.86 seconds
Started	Sep 03 11:39:42 PM UTC 24
Finished	Sep 03 11:40:35 PM UTC 24
Peak memory	217140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342342610 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1342342610
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/8.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.4122826741
Short name	T141
Test name
Test status
Simulation time	4872282804 ps
CPU time	23.68 seconds
Started	Sep 03 11:39:42 PM UTC 24
Finished	Sep 03 11:40:07 PM UTC 24
Peak memory	216880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122826741 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.4122826741
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/8.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.249407946
Short name	T294
Test name
Test status
Simulation time	87969369 ps
CPU time	3.04 seconds
Started	Sep 03 11:39:41 PM UTC 24
Finished	Sep 03 11:39:45 PM UTC 24
Peak memory	216940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249407946 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.249407946
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/8.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.1366309221
Short name	T210
Test name
Test status
Simulation time	985446338 ps
CPU time	80.35 seconds
Started	Sep 03 11:39:56 PM UTC 24
Finished	Sep 03 11:41:18 PM UTC 24
Peak memory	219204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366309221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1366309221
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/8.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.2228284082
Short name	T312
Test name
Test status
Simulation time	1288719558 ps
CPU time	36.02 seconds
Started	Sep 03 11:40:00 PM UTC 24
Finished	Sep 03 11:40:37 PM UTC 24
Peak memory	216760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228284082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2228284082
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/8.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.1136077531
Short name	T123
Test name
Test status
Simulation time	12994731277 ps
CPU time	643.9 seconds
Started	Sep 03 11:39:59 PM UTC 24
Finished	Sep 03 11:50:51 PM UTC 24
Peak memory	224664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136077531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.1136077531
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/8.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2567110353
Short name	T308
Test name
Test status
Simulation time	13841002 ps
CPU time	27.08 seconds
Started	Sep 03 11:40:00 PM UTC 24
Finished	Sep 03 11:40:28 PM UTC 24
Peak memory	216904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567110353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.2567110353
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/8.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.2702492113
Short name	T37
Test name
Test status
Simulation time	52324620 ps
CPU time	4.93 seconds
Started	Sep 03 11:39:55 PM UTC 24
Finished	Sep 03 11:40:01 PM UTC 24
Peak memory	216764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702492113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2702492113
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/8.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2097068129
Short name	T372
Test name
Test status
Simulation time	78692743699 ps
CPU time	356.89 seconds
Started	Sep 03 11:40:08 PM UTC 24
Finished	Sep 03 11:46:09 PM UTC 24
Peak memory	219272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097068129 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.2097068129
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/9.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.662488009
Short name	T313
Test name
Test status
Simulation time	808932982 ps
CPU time	24.8 seconds
Started	Sep 03 11:40:11 PM UTC 24
Finished	Sep 03 11:40:37 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662488009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.662488009
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/9.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.3228189643
Short name	T397
Test name
Test status
Simulation time	204368674 ps
CPU time	7.25 seconds
Started	Sep 03 11:40:09 PM UTC 24
Finished	Sep 03 11:40:17 PM UTC 24
Peak memory	217012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228189643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3228189643
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/9.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random.365694919
Short name	T232
Test name
Test status
Simulation time	705782991 ps
CPU time	20.85 seconds
Started	Sep 03 11:40:06 PM UTC 24
Finished	Sep 03 11:40:28 PM UTC 24
Peak memory	216832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365694919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.365694919
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/9.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.1275691636
Short name	T417
Test name
Test status
Simulation time	19391418079 ps
CPU time	114.74 seconds
Started	Sep 03 11:40:06 PM UTC 24
Finished	Sep 03 11:42:03 PM UTC 24
Peak memory	216900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275691636 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1275691636
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/9.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1479062728
Short name	T402
Test name
Test status
Simulation time	3815005350 ps
CPU time	33.95 seconds
Started	Sep 03 11:40:06 PM UTC 24
Finished	Sep 03 11:40:42 PM UTC 24
Peak memory	216896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479062728 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1479062728
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/9.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.3310511398
Short name	T395
Test name
Test status
Simulation time	102631308 ps
CPU time	8.55 seconds
Started	Sep 03 11:40:06 PM UTC 24
Finished	Sep 03 11:40:16 PM UTC 24
Peak memory	216820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310511398 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.3310511398
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/9.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.2170817529
Short name	T399
Test name
Test status
Simulation time	655539663 ps
CPU time	13.99 seconds
Started	Sep 03 11:40:09 PM UTC 24
Finished	Sep 03 11:40:24 PM UTC 24
Peak memory	217088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170817529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2170817529
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/9.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.2839640404
Short name	T273
Test name
Test status
Simulation time	62616997 ps
CPU time	3.12 seconds
Started	Sep 03 11:40:02 PM UTC 24
Finished	Sep 03 11:40:06 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839640404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2839640404
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/9.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3639261725
Short name	T310
Test name
Test status
Simulation time	8902214694 ps
CPU time	31.5 seconds
Started	Sep 03 11:40:03 PM UTC 24
Finished	Sep 03 11:40:36 PM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639261725 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3639261725
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/9.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.1745687091
Short name	T361
Test name
Test status
Simulation time	12314314507 ps
CPU time	44.25 seconds
Started	Sep 03 11:40:03 PM UTC 24
Finished	Sep 03 11:40:49 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745687091 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1745687091
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/9.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.2224434090
Short name	T272
Test name
Test status
Simulation time	36498431 ps
CPU time	3.09 seconds
Started	Sep 03 11:40:02 PM UTC 24
Finished	Sep 03 11:40:06 PM UTC 24
Peak memory	216808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224434090 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2224434090
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/9.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.1252333588
Short name	T94
Test name
Test status
Simulation time	4946690548 ps
CPU time	43.48 seconds
Started	Sep 03 11:40:16 PM UTC 24
Finished	Sep 03 11:41:01 PM UTC 24
Peak memory	218940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252333588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1252333588
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/9.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.1667207909
Short name	T371
Test name
Test status
Simulation time	974119890 ps
CPU time	102.26 seconds
Started	Sep 03 11:40:17 PM UTC 24
Finished	Sep 03 11:42:02 PM UTC 24
Peak memory	219076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667207909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1667207909
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/9.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.2048046763
Short name	T100
Test name
Test status
Simulation time	2428399485 ps
CPU time	147.56 seconds
Started	Sep 03 11:40:17 PM UTC 24
Finished	Sep 03 11:42:48 PM UTC 24
Peak memory	223048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048046763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.2048046763
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/9.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2036414186
Short name	T229
Test name
Test status
Simulation time	347091277 ps
CPU time	79.06 seconds
Started	Sep 03 11:40:19 PM UTC 24
Finished	Sep 03 11:41:40 PM UTC 24
Peak memory	222988 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036414186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.2036414186
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/9.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.4047626007
Short name	T92
Test name
Test status
Simulation time	1340539823 ps
CPU time	28.06 seconds
Started	Sep 03 11:40:09 PM UTC 24
Finished	Sep 03 11:40:38 PM UTC 24
Peak memory	218876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047626007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.4047626007
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/9.xbar_unmapped_addr/latest